An output voltage ripple super-audio frequency control circuit

Abstract

The application discloses an output voltage ripple super-audio frequency control circuit, which comprises an error amplifier EA1, a voltage-to-current module V2I, an NMOS tube NM7, a pull-down clamping current source Iclamplow, a valley value comparator VY, a resistor R1, a resistor R2, an NMOS tube NM2, an NMOS tube NM1, an inductor L1, a peak value comparator PEAK, an offset current source ios, a resistor Rlsd_sns, a switch S2, a hysteresis current source i_hys, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PFM mode control module PFM TIMER, a USNC mode control module USNC TIMER, an AND gate AND1, an AND gate AND2 and an RS flip-flop RS1. The application solves the problem that the switching frequency decreases when the load is light, actively controls the frequency to be out of the audio frequency range, improves the output voltage precision of the mode through a loop, and improves the performance of the system.

Description

Technical Field

[0001] This invention relates to an ultrasonic audio control circuit, and more particularly to an ultrasonic audio control circuit with output voltage ripple, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] The bypass boost chip, serving as the power supply front-end in a mobile phone, is a crucial component connecting the phone's battery to subsequent chips such as the processor, camera, and power amplifier (PA). To achieve high efficiency under light loads, pulse frequency modulation (PFM) is employed. This mode continuously reduces the switching frequency of the boost chip as the load decreases. When the frequency drops below audio audibility (below 20kHz) and the output voltage ripple becomes significant, the output capacitor will exhibit a whistling sound. This negatively impacts both the user experience and system reliability.

[0003] Traditional boost chips typically clamp the output of the error amplifier EA to a fixed value, causing the PFM-style spread spectrum to remain at a fixed value. This spread spectrum varies with temperature, voltage, and process angle. To cover these variations, trimming is required, necessitating a large margin to prevent the frequency from entering the audio frequency range under certain conditions. However, this large margin can lead to frequencies significantly above the audio frequency range, resulting in high power consumption. Another approach is to add a clock oscillator (OSC), which ensures accurate frequency entry into the ultra-high frequency range. However, this increases system complexity and introduces additional noise. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an output voltage ripple ultrasonic audio control circuit, thereby realizing a simplified, high-performance, high-efficiency, and high-precision output voltage ultrasonic audio control circuit.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] An output voltage ripple ultrasonic audio control circuit includes an error amplifier EA1, a voltage-to-current module V2I, an NMOS transistor NM7, a pull-down clamping current source Iclamplow, a valley comparator VY, resistors R1 and R2, NMOS transistors NM2 and NM1, an inductor L1, a peak comparator PEAK, an offset current source ios, a resistor Rlsd_sns, a switch S2, a hysteresis current source i_hys, PMOS transistors PM1, PM2, and PM3, a PFM mode control module PFM TIMER, a USNC mode control module USNCTIMER, AND gates AND1 and AND gates AND2, and an RS flip-flop RS1. The output voltage of the error amplifier EA1 is converted into current by the voltage-to-current module V2I and conducted to the peak comparator PEAK and the valley comparator VY to generate the upper transistor control signal HG and the lower transistor control signal LG.

[0007] Furthermore, the non-inverting input of the error amplifier EA1 is connected to the reference voltage vref, and the inverting input is connected to the voltage divider signal fb. The output of the error amplifier EA1 is connected to the first input of the voltage-to-current module V2I and the source of the NMOS transistor NM7 to generate the signal Vcomp. The gate of the NMOS transistor NM7 is connected to one end of the pull-down clamp current source Iclamplow and the second input of the voltage-to-current module V2I. The drain of the NMOS transistor NM7 and the other end of the pull-down clamp current source Iclamplow are connected to the power supply VIN. The first output of the voltage-to-current module V2I is connected to the gates of PMOS transistors PM1, PM2, PM2, and PM3. The second output of the voltage-to-current module V2I is connected to the inverting input of the valley comparator VY and one end of the resistor R1. The third output of the voltage-to-current module V2I is connected to the non-inverting input of the valley comparator VY and... One end of resistor R2 is connected to the ground, and the other end of resistor R2 is connected to the drain of NMOS transistor NM2 to generate signal VOUT. The other end of resistor R1 is connected to the source of NMOS transistor NM2, one end of inductor L1, the drain of NMOS transistor NM1, and the non-inverting input of peak comparator PEAK to generate signal SW. The other end of inductor L1 is connected to signal VIN. The source of NMOS transistor NM1 is grounded. The inverting input of peak comparator PEAK is connected to one end of resistor Rlsd_sns, one end of offset current source ios, and one end of switch S2. The other end of resistor Rlsd_sns and the other end of offset current source ios are grounded. The other end of switch S2 is connected to one end of hysteresis current source i_hys and the drain of PMOS transistor PM3. The other end of hysteresis current source i_hys, the source of PMOS transistor PM3, the source of PMOS transistor PM2, and the source of PMOS transistor PM1 are connected to signal VIN. The drain of PMOS transistor PM1 is connected to the PFM mode control module PFM. The input of the TIMER is connected to the first input of the AND gate AND1, the output of the PFM mode control module PFM TIMER is connected to the second input of the AND gate AND1, the output of the AND gate AND1 generates the signal PFM_END, the output of the peak comparator PEAK is connected to the R terminal of the RS flip-flop RS1 and generates the upper transistor control signal HG, the output of the valley comparator VY is connected to the second input of the AND gate AND2, the first input of the AND gate AND2 is connected to the signal PFM_END, the output of the AND gate AND2 is connected to the S terminal of the RS flip-flop RS1 and generates the lower transistor control signal LG, the Q terminal of the RS flip-flop RS1 generates the signal LSD_ON, and the control terminal of the switch S2 is connected to the signal LSD_ON.

[0008] Furthermore, the voltage divider signal fb is generated by a voltage divider circuit. The voltage divider current includes resistors R3 and R4. One end of resistor R3 is connected to signal VOUT, and the other end of resistor R3 is connected to one end of resistor R4 to generate the voltage divider signal fb. The other end of resistor R4 is grounded.

[0009] Furthermore, it also includes a loop compensation network, which includes a resistor Rcomp and a capacitor Ccomp. One end of the resistor Rcomp is connected to the signal Vcomp, and the other end of the resistor Rcomp is connected to one end of the capacitor Ccomp, while the other end of the capacitor Ccomp is grounded.

[0010] Furthermore, the voltage-to-current module V2I includes NMOS transistors NM3, NM4, NM5, and NM6. The gate of NMOS transistor NM3 is connected to the gates of NMOS transistors NM4, NM5, and NM6 and serves as the first input terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM3 serves as the second input terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM4 serves as the first output terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM5 serves as the second output terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM6 serves as the third output terminal of the voltage-to-current module V2I. The sources of NMOS transistors NM3, NM4, NM5, and NM6 are grounded.

[0011] Furthermore, it also includes an error amplifier EA2, an NMOS transistor NM8, and a reverse current source ineg, with the non-inverting input of the error amplifier EA2 connected to a 102% reference voltage Vref. 102%, the inverting input of error amplifier EA2 is connected to the voltage divider signal fb, the output of error amplifier EA2 is connected to the gate of NMOS transistor NM8 and generates signal Vcomp_usnc, the drain of NMOS transistor NM8 is connected to one end of the reverse current source ineg and the non-inverting input of valley comparator VY, and the source of NMOS transistor NM8 and the other end of the reverse current source ineg are grounded.

[0012] Furthermore, the PFM mode control module PFM TIMER includes an error amplifier EA3, a capacitor C1, and a switch S1. One end of the switch S1 is connected to one end of the capacitor C1 and the non-inverting input of the error amplifier EA3, serving as the input of the PFM mode control module PFM TIMER to input the current Iea_pfm. The other end of the switch S1 and the other end of the capacitor C1 are grounded. The inverting input of the error amplifier EA3 is connected to the reference voltage vref. The output of the error amplifier EA3 serves as the output of the PFM mode control module PFM TIMER. The control terminal of the switch S2 is connected to the signal LSD_ON.

[0013] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a simplified, high-performance, high-efficiency, and high-precision output voltage ripple ultrasonic audio control circuit, which solves the problem that the switching frequency drops when the load becomes lighter, actively controls the frequency to outside the audio frequency (i.e., greater than 20KHz), and improves the output voltage accuracy of this mode through the loop, thereby improving the system performance. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of an output voltage ripple ultrasonic audio control circuit according to the present invention.

[0015] Figure 2 This is a waveform diagram of the output voltage ripple ultrasonic audio control circuit of the present invention. Detailed Implementation

[0016] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0017] like Figure 1As shown, the present invention discloses an output voltage ripple ultrasonic audio control circuit, comprising an error amplifier EA1, a voltage-to-current module V2I, an NMOS transistor NM7, a pull-down clamping current source Iclamplow, a valley comparator VY, resistors R1 and R2, NMOS transistors NM2 and NM1, an inductor L1, a peak comparator PEAK, an offset current source ios, a resistor Rlsd_sns, a switch S2, a hysteresis current source i_hys, PMOS transistors PM1, PM2, and PM3, a PFM mode control module PFM TIMER, a USNC mode control module USNC TIMER, AND gates AND1 and AND gates AND2, and an RS flip-flop RS1. The output voltage of the error amplifier EA1 is converted into current by the voltage-to-current module V2I and conducted to the peak comparator PEAK and the valley comparator VY to generate the upper transistor control signal HG and the lower transistor control signal LG.

[0018] The non-inverting input of error amplifier EA1 is connected to the reference voltage vref, and the inverting input is connected to the voltage divider signal fb. The output of error amplifier EA1 is connected to the first input of voltage-to-current module V2I and the source of NMOS transistor NM7 to generate signal Vcomp. The gate of NMOS transistor NM7 is connected to one end of the pull-down clamp current source Iclamplow and the second input of voltage-to-current module V2I. The drain of NMOS transistor NM7 and the other end of the pull-down clamp current source Iclamplow are connected to power supply VIN. The first output of voltage-to-current module V2I is connected to the gates of PMOS transistors PM1, PM2, PM2, and PM3. The second output of voltage-to-current module V2I is connected to the inverting input of valley comparator VY and one end of resistor R1. The third output of voltage-to-current module V2I is connected to the non-inverting input of valley comparator VY and resistor R1. One end of resistor R2 is connected to the drain of NMOS transistor NM2, generating signal VOUT. The other end of resistor R1 is connected to the source of NMOS transistor NM2, one end of inductor L1, the drain of NMOS transistor NM1, and the non-inverting input of peak comparator PEAK, generating signal SW. The other end of inductor L1 is connected to signal VIN. The source of NMOS transistor NM1 is grounded. The inverting input of peak comparator PEAK is connected to one end of resistor Rlsd_sns, one end of offset current source ios, and one end of switch S2. The other end of resistor Rlsd_sns and the other end of offset current source ios are grounded. The other end of switch S2 is connected to one end of hysteresis current source i_hys and the drain of PMOS transistor PM3. The other end of hysteresis current source i_hys, the source of PMOS transistor PM3, the source of PMOS transistor PM2, and the source of PMOS transistor PM1 are connected to signal VIN. The drain of PMOS transistor PM1 is connected to the PFM mode control module PFM. The input of the TIMER is connected to the first input of the AND gate AND1, the output of the PFM mode control module PFM TIMER is connected to the second input of the AND gate AND1, the output of the AND gate AND1 generates the signal PFM_END, the output of the peak comparator PEAK is connected to the R terminal of the RS flip-flop RS1 and generates the upper transistor control signal HG, the output of the valley comparator VY is connected to the second input of the AND gate AND2, the first input of the AND gate AND2 is connected to the signal PFM_END, the output of the AND gate AND2 is connected to the S terminal of the RS flip-flop RS1 and generates the lower transistor control signal LG, the Q terminal of the RS flip-flop RS1 generates the signal LSD_ON, and the control terminal of the switch S2 is connected to the signal LSD_ON.

[0019] The voltage divider signal fb is generated by the voltage divider circuit. The voltage divider current includes resistors R3 and R4. One end of resistor R3 is connected to the signal VOUT, and the other end of resistor R3 is connected to one end of resistor R4 to generate the voltage divider signal fb. The other end of resistor R4 is grounded.

[0020] The output voltage ripple ultrasonic audio control circuit of the present invention further includes a loop compensation network, which includes a resistor Rcomp and a capacitor Ccomp. One end of the resistor Rcomp is connected to the signal Vcomp, and the other end of the resistor Rcomp is connected to one end of the capacitor Ccomp. The other end of the capacitor Ccomp is grounded.

[0021] The voltage-to-current module V2I includes NMOS transistors NM3, NM4, NM5, and NM6. The gate of NMOS transistor NM3 is connected to the gates of NMOS transistors NM4, NM5, and NM6 and serves as the first input terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM3 serves as the second input terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM4 serves as the first output terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM5 serves as the second output terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM6 serves as the third output terminal of the voltage-to-current module V2I. The sources of NMOS transistors NM3, NM4, NM5, and NM6 are grounded.

[0022] The output voltage ripple ultrasonic audio control circuit of the present invention further includes an error amplifier EA2, an NMOS transistor NM8, and a reverse current source ineg. The non-inverting input terminal of the error amplifier EA2 is connected to a 102% reference voltage Vref. 102%, the inverting input of error amplifier EA2 is connected to the voltage divider signal fb, the output of error amplifier EA2 is connected to the gate of NMOS transistor NM8 and generates signal Vcomp_usnc, the drain of NMOS transistor NM8 is connected to one end of the reverse current source ineg and the non-inverting input of valley comparator VY, and the source of NMOS transistor NM8 and the other end of the reverse current source ineg are grounded.

[0023] The PFM mode control module PFM TIMER includes an error amplifier EA3, a capacitor C1, and a switch S1. One end of switch S1 is connected to one end of capacitor C1 and the non-inverting input of error amplifier EA3, serving as the input of the PFM mode control module PFM TIMER to input the current Iea_pfm. The other end of switch S1 and the other end of capacitor C1 are grounded. The inverting input of error amplifier EA3 is connected to the reference voltage vref. The output of error amplifier EA3 serves as the output of the PFM mode control module PFM TIMER. The control terminal of switch S2 is connected to the signal LSD_ON.

[0024] This invention is based on a current hysteresis control architecture. The feedback voltage FB and the reference voltage generate a control signal Vcomp through the error amplifier EA1. The resistor Rcomp and capacitor Ccomp form a loop compensation network. In continuous conduction mode (CCM), the error of the output voltage collected by the error amplifier EA1 is directly converted into current through the voltage-to-current module V2I, and then conducted to the peak comparator PEAK and the valley comparator VY. These two comparators generate control signals HG and LG for the upper and lower transistors. By adding the inductor current hysteresis window current i_hys, the ripple of the inductor current IL can be controlled, thereby controlling the ripple of the output voltage VOUT. Due to the current loop sampling, the current generated by the V2I module has a fixed proportional relationship with the inductor current. When the load current decreases continuously, the system enters discontinuous conduction mode (DCM). The fixed-proportion scaled current generated by V2I charges the capacitor C1 of the timer in PFM mode. At this time, the pause time of DCM is controlled by this timer. The lighter the load, the longer the pause time, which is reflected in the system continuously reducing the frequency. The method to achieve ultrasonic frequencies involves adding a timer, usnc_timer. In PFM mode, if the frequency generated by PFM_timer falls below usnc_timer, the timer is reset, thus fixing the frequency at the ultrasonic level. After frequency fixing, if the load continues to decrease, excessive energy supplied through the switching transistors can lead to energy non-conservation, necessitating energy recovery. To ensure accurate recovery, another error amplifier, EA2, is added. When the VOUT voltage rises to 102% of the set value, error amplifier EA2 generates a control voltage, Vcomp_usnc. This voltage generates a current, i_neg, through the MOSFET, affecting the comparison point of the VY comparator. This causes the upper transistor to remain on for a slightly longer period, allowing the inductor to continue demagnetizing and the inductor current to drop to a negative current, thus achieving energy conservation. This loop also requires loop compensation to stabilize the output voltage at 102% of the set value.

[0025] like Figure 2As shown, this invention operates in PWM mode under heavy load, with the inductor current continuously conducting. When the load falls below a certain set value, it enters PFM mode. A PFM_timer controls the pause time of the DCM, thereby continuously spreading the frequency until it reaches 50kHz (an arbitrary ultrasonic frequency setting). The frequency is locked by the USNC_timer, and the demagnetization depth is adjusted by a multiplexed USNC loop, ensuring system accuracy and improving system performance.

[0026] This invention provides a simplified, high-performance, high-efficiency, and high-precision output voltage ripple ultrasonic audio control circuit. It solves the problem that the switching frequency decreases when the load becomes lighter, actively controls the frequency to be outside the audio frequency range (i.e., greater than 20KHz), and improves the output voltage accuracy in this mode through a loop, thereby improving the system performance.

[0027] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. An output voltage ripple ultrasonic audio control circuit, characterized in that: It includes an error amplifier EA1, a voltage-to-current converter V2I, an NMOS transistor NM7, a pull-down clamp current source Iclamplow, a valley comparator VY, resistors R1 and R2, NMOS transistors NM2 and NM1, an inductor L1, a peak comparator PEAK, an offset current source ios, a resistor Rlsd_sns, a switch S2, a hysteresis current source i_hys, PMOS transistors PM1, PM2, and PM3, a PFM mode control module PFM TIMER, a USNC mode control module USNC TIMER, AND gates AND1 and AND gates AND2, and an RS flip-flop RS1. The output voltage of the error amplifier EA1 is converted into current by the voltage-to-current converter V2I and conducted to the peak comparator PEAK and the valley comparator VY to generate the upper transistor control signal HG and the lower transistor control signal LG.

2. The output voltage ripple ultrasonic audio control circuit according to claim 1, characterized in that: The non-inverting input of error amplifier EA1 is connected to the reference voltage vref, and the inverting input is connected to the voltage divider signal fb. The output of error amplifier EA1 is connected to the first input of voltage-to-current module V2I and the source of NMOS transistor NM7 to generate signal Vcomp. The gate of NMOS transistor NM7 is connected to one end of the pull-down clamp current source Iclamplow and the second input of voltage-to-current module V2I. The drain of NMOS transistor NM7 and the other end of the pull-down clamp current source Iclamplow are connected to power supply VIN. The first output of voltage-to-current module V2I is connected to the gates of PMOS transistors PM1, PM2, PM2, and PM3. The second output of voltage-to-current module V2I is connected to the inverting input of valley comparator VY and one end of resistor R1. The third output of voltage-to-current module V2I is connected to the non-inverting input of valley comparator VY and resistor R1. One end of resistor R2 is connected, and the other end of resistor R2 is connected to the drain of NMOS transistor NM2 to generate signal VOUT. The other end of resistor R1 is connected to the source of NMOS transistor NM2, one end of inductor L1, the drain of NMOS transistor NM1, and the non-inverting input of peak comparator PEAK to generate signal SW. The other end of inductor L1 is connected to signal VIN. The source of NMOS transistor NM1 is grounded. The inverting input of peak comparator PEAK is connected to one end of resistor Rlsd_sns, one end of offset current source ios, and one end of switch S2. The other end of resistor Rlsd_sns and the other end of offset current source ios are grounded. The other end of switch S2 is connected to one end of hysteresis current source i_hys and the drain of PMOS transistor PM3. The other end of hysteresis current source i_hys, the source of PMOS transistor PM3, the source of PMOS transistor PM2, and the source of PMOS transistor PM1 are connected to signal VIN. The drain of PMOS transistor PM1 is connected to the PFM mode control module PFM. The input of the TIMER is connected to the first input of the AND gate AND1, the output of the PFM mode control module PFM TIMER is connected to the second input of the AND gate AND1, the output of the AND gate AND1 generates the signal PFM_END, the output of the peak comparator PEAK is connected to the R terminal of the RS flip-flop RS1 and generates the upper transistor control signal HG, the output of the valley comparator VY is connected to the second input of the AND gate AND2, the first input of the AND gate AND2 is connected to the signal PFM_END, the output of the AND gate AND2 is connected to the S terminal of the RS flip-flop RS1 and generates the lower transistor control signal LG, the Q terminal of the RS flip-flop RS1 generates the signal LSD_ON, and the control terminal of the switch S2 is connected to the signal LSD_ON.

3. The output voltage ripple ultrasonic audio control circuit according to claim 2, characterized in that: The voltage divider signal fb is generated by the voltage divider circuit. The voltage divider current includes resistors R3 and R4. One end of resistor R3 is connected to signal VOUT, and the other end of resistor R3 is connected to one end of resistor R4 to generate the voltage divider signal fb. The other end of resistor R4 is grounded.

4. The output voltage ripple ultrasonic audio control circuit according to claim 2, characterized in that: It also includes a loop compensation network, which consists of a resistor Rcomp and a capacitor Ccomp. One end of the resistor Rcomp is connected to the signal Vcomp, and the other end of the resistor Rcomp is connected to one end of the capacitor Ccomp. The other end of the capacitor Ccomp is grounded.

5. The output voltage ripple ultrasonic audio control circuit according to claim 2, characterized in that: The voltage-to-current module V2I includes NMOS transistors NM3, NM4, NM5, and NM6. The gate of NMOS transistor NM3 is connected to the gates of NMOS transistors NM4, NM5, and NM6 and serves as the first input terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM3 serves as the second input terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM4 serves as the first output terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM5 serves as the second output terminal of the voltage-to-current module V2I. The drain of NMOS transistor NM6 serves as the third output terminal of the voltage-to-current module V2I. The sources of NMOS transistors NM3, NM4, NM5, and NM6 are grounded.

6. The output voltage ripple ultrasonic audio control circuit according to claim 5, characterized in that: It also includes an error amplifier EA2, an NMOS transistor NM8, and a reverse current source ineg. The non-inverting input of the error amplifier EA2 is connected to a 102% reference voltage Vref. 102%, the inverting input of error amplifier EA2 is connected to the voltage divider signal fb, the output of error amplifier EA2 is connected to the gate of NMOS transistor NM8 and generates signal Vcomp_usnc, the drain of NMOS transistor NM8 is connected to one end of the reverse current source ineg and the non-inverting input of valley comparator VY, and the source of NMOS transistor NM8 and the other end of the reverse current source ineg are grounded.

7. The output voltage ripple ultrasonic audio control circuit according to claim 2, characterized in that: The PFM mode control module PFM TIMER includes an error amplifier EA3, a capacitor C1, and a switch S1. One end of the switch S1 is connected to one end of the capacitor C1 and the non-inverting input of the error amplifier EA3, serving as the input of the PFM mode control module PFM TIMER with an input current Iea_pfm. The other end of the switch S1 and the other end of the capacitor C1 are grounded. The inverting input of the error amplifier EA3 is connected to a reference voltage vref. The output of the error amplifier EA3 serves as the output of the PFM mode control module PFM TIMER. The control terminal of the switch S2 is connected to the signal LSD_ON.

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