A baseband signal processing method for an airborne ship automatic identification receiver

Abstract

The application discloses a kind of baseband signal processing methods for airborne ship automatic identification receiver, it is related to aviation communication field, including: receiving digital intermediate frequency signal conversion into baseband sampling signal;Frame synchronization processing is carried out to baseband sampling signal, after detecting frame header, first, the cache data containing message ID content length of preset, carrier frequency offset estimation and correction, timing synchronization, Viterbi decoding and message length analysis are executed, and message length signal is output, then carrier frequency offset estimation and correction, timing synchronization and Viterbi decoding are executed to a frame data, to symbol data difference decoding, frame flag detection, zero processing and cyclic redundancy check, and byte data and check end flag signal are output, check end flag signal is fed back to frame synchronization processing link, the above process is looped, and the whole process of baseband signal processing is completed.The application makes AIS receiver can receive AIS message of arbitrary time slot length, and improves the sensitivity and practicality of AIS receiver.

Description

Technical Field

[0001] This invention relates to the field of aviation communications, and more specifically, to a baseband signal processing method for an airborne ship automatic identification receiver. Background Technology

[0002] Airborne AIS receivers are typically mounted on aircraft platforms such as patrol aircraft, search and rescue helicopters, and early warning aircraft, which can greatly expand the monitoring range of shore-based base stations. At the same time, due to the flexibility of airborne platforms, continuous tracking of specific ships and areas can be achieved, improving the continuity and integrity of maritime surveillance.

[0003] Based on the demodulation method of the baseband signal, AIS receivers are generally divided into two main categories: those using coherent demodulation and those using non-coherent demodulation. Compared with receivers based on coherent demodulation, receivers based on non-coherent demodulation have slightly lower performance under the same bit error rate. However, because non-coherent demodulation does not require phase synchronization, its hardware design complexity is lower, and it is widely used.

[0004] This invention relates to an airborne AIS receiver based on noncoherent demodulation, which needs to receive various AIS message types, including short messages (occupying only one time slot) and long messages (occupying 2-3 time slots). Since the reception timing of long and short messages is random, the receiver cannot predict the actual length of the received signal. This causes synchronization problems, making it difficult to correctly detect the frame header of each data packet, leading to synchronization errors and reducing the system's accuracy. Ensuring that the receiver can correctly parse AIS messages of different lengths (1-5 time slots) while maintaining a high accuracy rate is a problem that needs to be solved.

[0005] Currently, AIS receivers capable of simultaneously receiving 1-2 timeslot messages handle this by using dual buffers, each with a buffer depth equal to the sampled length of the two timeslot messages. The buffers employ a ping-pong access mechanism to address the coexistence of receiving single-timeslot and dual-timeslot messages. However, this solution has the following drawbacks:

[0006] 1) This method leads to a waste of FPGA resources. The ping-pong read mechanism of the buffer can result in duplicate data or only partially valid data being read, which must be discarded, thus wasting a significant amount of processing resources. If the correct length of data cannot be read from the buffer, subsequent correct data demodulation cannot be guaranteed.

[0007] 2) This method can only receive and process AIS message messages with a length of 1 to 2 time slots, and cannot receive and process AIS messages that occupy longer time slots (3 or more time slots).

[0008] 3) When the message contains a data segment that is the same as the training sequence, it will cause the local reference sequence to produce a false correlation peak with the data segment, resulting in a synchronization header detection error and synchronization chaos, which will greatly reduce the correct data reception rate.

[0009] There is currently no effective solution to the above problems. Summary of the Invention

[0010] To address the problems in related technologies, this invention proposes a baseband signal processing method for an airborne ship automatic identification receiver, thereby overcoming the aforementioned technical problems in existing related technologies.

[0011] Therefore, the specific technical solution adopted by the present invention is as follows:

[0012] This invention provides a baseband signal processing method for an airborne ship automatic identification receiver, comprising:

[0013] It receives digital intermediate frequency (IF) signals and converts them into baseband sampling signals through digital quadrature downconversion.

[0014] The baseband sampling signal is processed for frame synchronization. After the frame header is detected, a frame synchronization detection flag signal is output, and the frame synchronization detection flag signal is used to control the timing of data writing to the data buffer.

[0015] After receiving the frame synchronization detection flag signal, the data buffer begins writing the baseband sampling signal. When the buffer depth of the data buffer reaches the preset depth threshold, it first reads out the buffer data of the preset length for carrier frequency offset estimation of the baseband sampling signal. After the carrier frequency offset estimation is completed, it reads out the buffer data of the preset length containing the message ID content from the data buffer. Carrier frequency offset correction is performed first, followed by timing synchronization and Viterbi decoding, and demodulation of the output code metadata.

[0016] The message ID and the message length corresponding to the message ID are parsed from the decoded code data, and the message length signal is output. The message length signal is used to control the length of data written to the data buffer and the timing of data reading. The buffered data with the length corresponding to the message length signal is read out, and carrier frequency offset estimation and correction, timing synchronization and Viterbi decoding are performed again to demodulate and output code data.

[0017] Differential decoding, frame flag detection, zero removal, and cyclic redundancy check are performed on the code data. The demodulated byte data and the check end flag signal are output to complete the baseband signal processing of one frame of data.

[0018] Further, the step of receiving the digital intermediate frequency signal and converting it into a baseband sampling signal via digital quadrature downconversion includes:

[0019] Receives the digital intermediate frequency signal generated by the AD converter;

[0020] By using the built-in numerically controlled oscillator in the digital mixer, the value of the frequency control word is set to generate an orthogonal waveform of the corresponding frequency. The orthogonal waveform is then multiplied by the complex input signal through the built-in complex multiplier in the digital mixer to generate the baseband sampling signal after orthogonal downconversion.

[0021] The baseband sampling signal is sequentially input to the first-stage 25x CIC decimation filter, the second-stage 5x CIC decimation filter, and the third-stage 5x CIC decimation filter for decimation filtering, and finally outputs the baseband sampling signal with reduced sampling rate.

[0022] Furthermore, the step of performing frame synchronization processing on the baseband sampling signal, outputting a frame synchronization detection flag signal after detecting the frame header, and using the frame synchronization detection flag signal to control the timing of data writing to the data buffer includes:

[0023] Perform differential cross-correlation calculation between the baseband sampled signal and the local reference sequence, and output the cross-correlation result;

[0024] Perform maximum value detection on the cross-correlation results and output the position of the cross-correlation peak;

[0025] The frame header position is determined based on the position of the cross-correlation peaks;

[0026] After detecting the frame header position, the frame synchronization state machine transitions from the idle state to the detection state and outputs a frame synchronization detection flag signal;

[0027] The error prevention mechanism triggers the frame synchronization state machine to enter a waiting state, waiting for the synchronization detection of the next frame signal to begin.

[0028] After the frame synchronization detects the frame header, the output frame synchronization detection flag signal is sent to the data buffer to control the timing of data writing to the data buffer. When the data buffer receives the frame synchronization detection flag signal, it begins to write the baseband sampling signal into the buffer.

[0029] Furthermore, after receiving the frame synchronization detection flag signal, the data buffer begins writing the baseband sampling signal. When the buffer depth of the data buffer reaches a preset depth threshold, it first reads out a preset length of buffered data for carrier frequency offset estimation of the baseband sampling signal. After the carrier frequency offset estimation is completed, it reads out a preset length of buffered data containing the message ID content from the data buffer. Carrier frequency offset correction is performed first, followed by timing synchronization and Viterbi decoding. The demodulated output code metadata includes:

[0030] Once the data buffer receives the frame synchronization detection flag signal, it begins writing the baseband sampling signal into the data buffer.

[0031] During the process of writing the baseband sampling signal into the data buffer, when the buffer depth of the data buffer reaches the preset depth threshold, the corresponding length of the baseband sampling signal is read from the data buffer.

[0032] First, read the cached data of a preset length to perform frequency offset estimation. After the frequency offset estimation is completed, output the frequency offset estimation value and the frequency offset estimation detection end signal. After the data buffer receives the frequency offset estimation detection end signal, read the cached data of a preset length containing the message ID content from the data buffer. Use the frequency offset estimation value to perform frequency offset correction on the subsequently read baseband sampling signal and output the frequency offset corrected baseband sampling signal.

[0033] The timing error of the baseband sampling signal after frequency offset correction is estimated, and the timing error is corrected by a polynomial interpolation filter to obtain the baseband sampling signal after timing error correction.

[0034] The baseband sampling signal after timing error correction is noncoherently decoded using Viterbi decoding to complete the Viterbi decoding and demodulate the output code data.

[0035] Further, the process involves first reading out a preset length of cached data for frequency offset estimation. After the frequency offset estimation is completed, the frequency offset estimation value and a frequency offset estimation detection end signal are output. Upon receiving the frequency offset estimation detection end signal, the data buffer reads out a preset length of cached data containing the message ID content. The frequency offset estimation value is then used to correct the frequency offset of the subsequently read baseband sampling signal. The output frequency offset corrected baseband sampling signal includes:

[0036] Using a carrier frequency offset estimation mechanism based on second-order cyclic cumulant, frequency offset estimation is performed on the baseband sampled signal of a preset length read from the data buffer. After the frequency offset estimation is completed, the frequency offset estimation value and the frequency offset estimation detection end signal are output, and the frequency offset estimation detection end signal is fed back to the data buffer.

[0037] After receiving the frequency offset estimation detection end signal, the data buffer reads the preset buffer data containing the message ID content length from the data buffer, performs an exponential operation on the frequency offset estimation value and the subsequently read baseband sampling signal to complete the frequency offset correction, and outputs the frequency offset corrected baseband sampling signal.

[0038] Furthermore, the step of correcting the timing error of the frequency offset-corrected baseband sampling signal and compensating for the timing error using a polynomial interpolation filter to obtain the timing error-corrected baseband sampling signal includes:

[0039] The baseband sampling signal after frequency offset correction is matched and filtered by a Gaussian matched filter, and the timing error is estimated based on the filtering result, and the estimated timing error value is output.

[0040] A polynomial interpolation filter is used to correct the timing error estimate, and the corrected baseband sampling signal is output.

[0041] Furthermore, the step of performing noncoherent Viterbi decoding on the baseband sampling signal after timing error correction to complete Viterbi decoding, and demodulating the output code data includes:

[0042] The baseband sampling signal after timing error correction is Viterbi decoded through a preset state, and a state transition table is constructed to calculate the path metric value of each branch.

[0043] The path with the largest path metric among all branches is selected as the surviving path and backtracked to demodulate the output code metadata.

[0044] Furthermore, the step of parsing the message ID and the message length corresponding to the message ID using the decoded code data, and outputting the message length signal includes:

[0045] The start flag of the detection code metadata is used by the shift register to start the counter and extract the message ID signal;

[0046] Based on the correspondence between message ID and message length, the corresponding message length signal is parsed and fed back to the data buffer to control the length of data written to the data buffer and the timing of data reading.

[0047] Furthermore, the process of using the message length signal to control the data length written to the buffer and the data readout timing, and reading out the buffered data of the length corresponding to the message length signal, and then performing carrier frequency offset estimation and correction, timing synchronization and Viterbi decoding again, demodulated output code metadata includes:

[0048] After receiving the message length signal, the data buffer waits for the cached data written into the buffer to reach the data length corresponding to the message length signal. Then, it reads out the cached data of the preset length from the data buffer and uses the cached data of the preset length to perform frequency offset estimation. After the frequency offset estimation is completed, it outputs the frequency offset estimation value and the frequency offset estimation detection end signal.

[0049] After receiving the frequency offset estimation detection end signal, the data buffer reads out the buffer data of the length corresponding to the message length signal, performs an exponential operation with the frequency offset estimation value, completes the frequency offset correction, and outputs the frequency offset corrected baseband sampling signal.

[0050] The timing error of the baseband sampling signal after frequency offset correction is estimated, and the timing error is compensated by a polynomial interpolation filter to generate the baseband sampling signal after timing error correction.

[0051] The baseband sampling signal after timing error correction is subjected to Viterbi decoding of the complete frame data, and the output code data is demodulated.

[0052] Furthermore, the baseband signal processing for one frame of data includes differential decoding, frame flag detection, zero removal, and cyclic redundancy check (CRC) of the code data, outputting demodulated byte data and a check completion flag signal.

[0053] Perform differential decoding on the code metadata and output the differentially decoded code metadata;

[0054] Detect the start and end markers in the bit metadata after differential decoding, and output bit metadata with frame boundary indication;

[0055] Remove the padding bits inserted after a continuous sequence of numbers in the code metadata with frame boundary indicators, and output the zero-removed code metadata.

[0056] The cyclic redundancy checker is used to check the zero-removed code data, outputting the cyclic redundancy check end flag and the cyclic redundancy check pass flag, and restoring the data between the start flag and the end flag to byte data output.

[0057] The beneficial effects of this invention are as follows:

[0058] This invention ensures that the AIS receiver can receive message messages of any time slot length (1 to 5 time slots), effectively improving the frame synchronization detection probability, and enabling the AIS receiver to have a higher data reception accuracy (≥95%), higher reception sensitivity, and wider applicability. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a data processing flowchart of a baseband signal processing method for an airborne ship automatic identification receiver according to an embodiment of the present invention;

[0061] Figure 2 This is a block diagram illustrating the baseband signal processing principle of a baseband signal processing method for an airborne ship automatic identification receiver according to an embodiment of the present invention.

[0062] Figure 3 This is a diagram illustrating the composition of a digital quadrature downconverter module according to an embodiment of the present invention.

[0063] Figure 4 This is a frame synchronization state machine diagram according to an embodiment of the present invention;

[0064] Figure 5 This is a read state transition diagram of the data caching module according to an embodiment of the present invention;

[0065] Figure 6 This is a diagram illustrating the composition of a timing synchronization module according to an embodiment of the present invention;

[0066] Figure 7 This is a diagram showing the composition of a data frame processing module according to an embodiment of the present invention;

[0067] Figure 8 This is a schematic diagram of an airborne AIS receiver according to an embodiment of the present invention;

[0068] Figure 9 This is a data frame structure diagram of AIS short messages according to an embodiment of the present invention;

[0069] Figure 10 This is a probability diagram of successful frame header detection according to an embodiment of the present invention;

[0070] Figure 11 This is a bit error rate diagram of 8-state Viterbi decoding according to an embodiment of the present invention;

[0071] Figure 12 This is a packet error rate diagram for 8-state Viterbi decoding according to an embodiment of the present invention. Detailed Implementation

[0072] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention.

[0073] The Automatic Identification System (AIS) uses Time Division Multiple Access (TDMA) for network access. The system divides time into several time slots, with 2250 time slots per minute, each corresponding to 26.67 ms. Each time slot can transmit 256 bits of data, including a power rise sequence, training sequence, start flag, message data, frame check data, end flag, and buffer data. The first 6 bits of the message data are the message ID. The message ID identifies the message type. Different message types may have different message lengths. The data structure of an AIS short message is as follows: Figure 9 As shown.

[0074] The ITU-R M.1371-5 protocol, issued by the International Telecommunication Union (ITU), defines 27 AIS message types. Short messages have a 168-bit data portion and occupy only one time slot; long messages can occupy 2 to 5 time slots depending on their data length, with the protocol stipulating a maximum of 5 time slots for a long message. Because the transmission of short and long messages is random, it's impossible to determine when a long message or a short message will be received. This can cause synchronization problems, making it difficult to correctly capture the frame header of each data packet, leading to synchronization errors and ultimately reducing the system's correct reception rate.

[0075] like Figure 8 As shown, the airborne AIS receiver of the present invention mainly includes: a radio frequency front-end module, a frequency conversion receiving channel module, an AD converter module, a baseband sampling signal processing module (i.e., steps S1-S5 of the technical solution of the present invention), and a data frame processing module.

[0076] The AIS signal received by the antenna first enters the RF front-end module, which performs amplitude limiting, filtering, and low-noise amplification on the signal in sequence. Then, the signal is split into two paths by the power divider and sent to the two frequency conversion receiving channels respectively.

[0077] Two frequency conversion receiving channels are used to process AIS signals of 161.975MHz and 162.025MHz respectively. The two channels have similar compositions, each including an automatic AGC controller, a low-noise amplifier, a two-stage mixer, and a filter. The automatic AGC controller is used to control the gain of large signals. The mixers of the two channels are set with different local oscillator frequencies to ensure that both channels output a 70MHz intermediate frequency (IF) signal. The IF signals generated by the two channels are then output to an analog-to-digital converter (ADC).

[0078] The AD converter digitally samples the intermediate frequency signal, completing the digital-to-analog conversion. The sampling frequency is 48MHz. The digital intermediate frequency signal generated by the AD converter is sent to the baseband signal processing module for baseband signal processing.

[0079] The baseband signal processing module mainly includes modules for digital quadrature downconversion, frame synchronization, data buffering, carrier synchronization, timing synchronization, incoherent Viterbi decoding, and data frame processing. Its primary function is to demodulate the baseband signal. Since this invention uses incoherent demodulation, phase synchronization is unnecessary. The signal after carrier synchronization can be directly demodulated through timing synchronization and incoherent Viterbi decoding.

[0080] The signal output from the baseband signal processing module is then sent to the data reporting module, which mainly performs data parsing and reporting. The reported data will be displayed on the user interface.

[0081] like Figure 2 As shown in the figure, according to an embodiment of the present invention, a baseband signal processing method for an airborne ship automatic identification receiver is proposed, and a detailed block diagram of the baseband signal processing module is provided. The baseband signal processing module mainly includes: a digital quadrature downconversion module, a frame synchronization module, a data buffer module, a carrier synchronization module, a timing synchronization module, a noncoherent Viterbi decoding module, and a data frame processing module. The working mechanism of the baseband signal processing modules for the two paths of this receiver is exactly the same; therefore, only the baseband signal processing module for one channel will be described below.

[0082] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figure 1 As shown, a baseband signal processing method for an airborne ship automatic identification receiver according to an embodiment of the present invention includes:

[0083] Step S1: Receive the digital intermediate frequency signal and convert it into a baseband sampling signal through digital quadrature downconversion;

[0084] Step S2: Perform frame synchronization processing on the baseband sampling signal. After detecting the frame header, output the frame synchronization detection flag signal (frame_syn) and use the frame synchronization detection flag signal (frame_syn) to control the timing of data writing to the data buffer.

[0085] Step S3: After receiving the frame synchronization detection flag signal (frame_syn), the data buffer starts writing the baseband sampling signal. When the buffer depth of the data buffer reaches the preset depth threshold (1500 sampling points), it first reads out the buffer data of the preset length for carrier frequency offset estimation of the baseband sampling signal. After the carrier frequency offset estimation is completed, it reads out the buffer data of the preset length containing the message ID content (768 sampling points) from the data buffer. Carrier frequency offset correction is performed first, and then timing synchronization and Viterbi decoding processing are performed in sequence to demodulate the output code metadata.

[0086] Step S4: Parse the message ID and the message length corresponding to the message ID using the decoded code data, and output the message length signal (message_len); use the message length signal (message_len) to control the length of data written to the data buffer and the timing of data reading, and read out the buffered data of the length corresponding to the message length signal (message_len), and perform carrier frequency offset estimation and correction, timing synchronization and Viterbi decoding again, and demodulate the output code data.

[0087] Step S5: Differential decoding, frame flag detection, zero removal and cyclic redundancy check (CRC check) are performed on the code data. The demodulated byte data and the check end flag signal (CheckFinish) are output to complete the baseband signal processing of one frame of data.

[0088] Specifically, such as Figure 1 As shown, the baseband signal processing method flow is as follows:

[0089] 1) The digital mixer in the digital quadrature downconverter module first performs quadrature downconversion on the digital intermediate frequency signal to generate a baseband sampling signal. Then, through multiple stages of low-pass filtering and decimation filtering, the sampling rate of the baseband sampling signal is reduced from 48MHz to 76.8kHz. The output baseband sampling signal is simultaneously sent to the frame synchronization module and the data buffer module.

[0090] 2) The frame synchronization module performs differential cross-correlation between the received baseband sampled signal and the local reference sequence (24 bits "0101...0101"), and determines the frame header position based on the position of the cross-correlation peak. After detecting the frame header position, the module outputs a frame synchronization detection flag signal (frame_sync) to the data buffer module.

[0091] 3) When the data buffer module receives the frame synchronization detection flag (frame_sync) signal output by the frame synchronization module, it writes the baseband sampling signal into the data buffer. When the data depth written to the data buffer reaches 1500 sampling points, these 1500 sampling points are read out and sent to the frequency offset estimation module in the carrier synchronization module for carrier frequency offset estimation during the message ID parsing stage. The carrier synchronization module uses a carrier frequency offset estimation method based on second-order cyclic cumulant to complete the carrier frequency offset estimation and outputs the frequency offset estimation value. The frequency offset estimation value is sent to the frequency offset correction module in the carrier synchronization module for frequency offset correction. At the same time, the frequency offset estimation detection end signal (afc_finish) is fed back to the data buffer module. After receiving the frequency offset estimation detection end signal (afc_finish), the data buffer module reads out the first 768 sampling points in the buffer (the first 96 bits of a frame of data, which includes message ID information) and sends them to the frequency offset correction module in the carrier synchronization module for frequency offset correction. The frequency offset corrected signal is sent to the timing synchronization module. First, the timing error estimation module within the timing synchronization module estimates the timing error, and then a polynomial interpolation filter compensates for the timing error. The synchronized signal is then sent to the non-coherent Viterbi decoding module for decoding. The decoding result is sent to the message ID detection module for message ID and message length parsing. After message ID parsing is complete, the message ID detection module feeds back the message length signal (message_len) corresponding to the message ID to the data buffer module.

[0092] 4) After receiving the message length signal (message_len), the data buffer module begins the formal message frame parsing process. First, it waits until the length of data written to the data buffer reaches the length corresponding to the message length signal, then stops writing data to the data buffer and reads out the first 2000 sampling points, sending them to the carrier synchronization module for carrier frequency offset estimation during the formal message frame parsing phase. After carrier frequency offset estimation is completed, the carrier synchronization module outputs a carrier frequency offset estimation completion signal to the data buffer module. Upon receiving the carrier frequency offset estimation completion signal, the data buffer module reads out all data from the data buffer and sends it to the carrier synchronization module for frequency offset correction. The frequency offset corrected data is then sent to the timing synchronization module, where the timing error estimation module first performs timing error estimation, and then a polynomial interpolation filter compensates for the timing error. After timing synchronization is complete, the signal is sent to the non-coherent Viterbi decoding module to decode a complete frame of data. The decoded data is then output to the data frame processing module.

[0093] 5) The data frame processing module performs differential decoding, start and end flag detection, zero-removal, and CRC check on the decoded data, ultimately restoring the data between the start and end flags into byte data for output. Simultaneously, it feeds back the CRC check end flag signal (CheckFinish) to the frame synchronization module. Upon receiving this signal, the frame synchronization module begins frame header detection for the next frame.

[0094] In this optional embodiment, receiving the digital intermediate frequency (IF) signal and converting it into a baseband sampling signal via digital quadrature downconversion includes:

[0095] Receives the digital intermediate frequency signal generated by the AD converter, which is a digital sampling signal;

[0096] By using the built-in numerically controlled oscillator in the digital mixer, the value of the frequency control word is set to generate an orthogonal waveform of the corresponding frequency. The orthogonal waveform is then multiplied by the complex input signal through the built-in complex multiplier in the digital mixer to generate the baseband sampling signal after orthogonal downconversion.

[0097] The baseband sampling signal is sequentially input to the first-stage 25x CIC decimation filter, the second-stage 5x CIC decimation filter, and the third-stage 5x CIC decimation filter for decimation filtering, and finally outputs the baseband sampling signal with reduced sampling rate.

[0098] Specifically, the digital quadrature downconverter module mainly downconverts the digital intermediate frequency signal to the baseband sampling signal and reduces the sampling rate of the signal from 48MHz to 76.8kHz.

[0099] like Figure 3As shown, the digital quadrature downconverter module includes sub-modules such as a digital mixer, an FIR low-pass filter, a CIC decimation filter, a first-stage decimation low-pass filter, a 5x decimator, a second-stage low-pass filter, and a third-stage low-pass filter.

[0100] A digital mixer mainly consists of a numerically controlled oscillator (CNC) and a complex multiplier. The CNC generates orthogonal waveforms of corresponding frequencies based on the value of the frequency control word. The complex multiplier performs multiplication operations between the orthogonal output waveform of the CNC and the complex input signal, thereby down-converting the digital intermediate frequency signal into a baseband sampling signal.

[0101] The digital quadrature downconverter module contains three stages of decimation filtering with a total decimation factor of D=625, which is decomposed into D1×D2×D3=25×5×5 for each stage. The first stage of decimation filtering uses a D1=25 times CIC decimation filter, while the second and third stages are both D2=D3=5 times decimation filters.

[0102] After three stages of decimation filtering and low-pass filtering, the signal sampling rate is reduced from 48MHz to 76.8kHz (48MHz / 625=76.8kHz). The baseband sampling signal output from the digital quadrature downconverter module is sent to the frame synchronization module and the data buffer module, respectively.

[0103] In this optional embodiment, the step of performing frame synchronization processing on the baseband sampling signal, outputting a frame synchronization detection flag signal (frame_syn) after detecting the frame header, and using the frame synchronization detection flag signal (frame_syn) to control the timing of data writing to the data buffer includes:

[0104] Perform differential cross-correlation calculation between the baseband sampled signal and the local reference sequence, and output the cross-correlation result;

[0105] Perform maximum value detection on the cross-correlation results and output the position of the cross-correlation peak;

[0106] The frame header position is determined based on the position of the cross-correlation peaks; after the frame header position is detected, the frame synchronization state machine changes from the idle state to the detection state and outputs the frame synchronization detection flag signal.

[0107] The error prevention mechanism triggers the frame synchronization state machine to enter a waiting state, waiting for the synchronization detection of the next frame signal to begin.

[0108] After the frame synchronization detects the frame header, the output frame synchronization detection flag signal is sent to the data buffer to control the timing of data writing to the data buffer. When the data buffer receives the frame synchronization detection flag signal, it begins to write the baseband sampling signal into the buffer.

[0109] Specifically, the frame synchronization module mainly completes the frame header capture of the AIS signal. The training sequence of the AIS signal frame is 24 bits of "0101……0101". The frame synchronization detection module needs to reliably detect the above 24-bit training sequence to provide a signal start position indication for subsequent signal demodulation.

[0110] The frame synchronization module mainly includes a complex convolution module, a maximum value detection module, and a frame synchronization state machine module. The complex convolution module performs differential cross-correlation between the local signal and the received signal. The maximum value detection module reliably detects the correlation peak value from the differential cross-correlation operation; the position of this peak value is the signal frame header position. The frame synchronization state machine module uses a 4-state state machine to ensure the reliability of frame synchronization detection and provides a frame synchronization detection flag signal (frame_syn) to the data buffer module.

[0111] like Figure 4 As shown, the state machine for frame synchronization has the following state transition steps:

[0112] 1) The state machine starts in the idle state. In the idle state, the state machine will continuously detect whether there is a differential cross-correlation peak flag signal. When a differential cross-correlation peak is detected, the state machine jumps to the detection state and outputs the frame synchronization detection flag signal (frame_syn).

[0113] 2) After one clock cycle, the state machine jumps to the waiting state, which will last for 2000 clock cycles, which is slightly less than the number of sampling points in one AIS time slot (256*8=2048, where 8 is the oversampling factor). The purpose is to avoid other frame synchronization detection errors occurring in a time slot after the training sequence.

[0114] 3) After waiting for 2000 clock cycles, or after the subsequent data frame processing module gives the CRC check end flag signal, it means that frame synchronization can start the next signal frame detection, and the state machine adjusts to the return state.

[0115] 4) After one clock cycle, it returns to the idle state and begins the next frame synchronization detection.

[0116] In this optional embodiment, after receiving the frame synchronization detection flag signal (frame_syn), the data buffer begins writing the baseband sampling signal. When the buffer depth of the data buffer reaches a preset depth threshold, a preset length of buffered data is first read out for carrier frequency offset estimation of the baseband sampling signal. After the carrier frequency offset estimation is completed, a preset length of buffered data containing the message ID content is read out from the data buffer. Carrier frequency offset correction is performed first, followed by timing synchronization and Viterbi decoding in sequence. The demodulated output code metadata includes:

[0117] Once the data buffer receives the frame synchronization detection flag signal (frame_syn), it begins writing the baseband sampling signal into the data buffer.

[0118] During the process of writing the baseband sampling signal into the data buffer, when the buffer depth of the data buffer reaches the preset depth threshold (1500 sampling points), the baseband sampling signal of the preset length (1500 sampling points) is read from the data buffer.

[0119] First, frequency offset estimation is performed on the read cached data (1500 sampling points). After the frequency offset estimation is completed, the frequency offset estimation value and the frequency offset estimation detection end signal (afc_finish) are output. After the data buffer receives the frequency offset estimation detection end signal (afc_finish), it reads the cached data (768 sampling points) of the preset length including the message ID content length from the data buffer. The frequency offset estimation value is used to correct the frequency offset of the subsequently read baseband sampling signal, and the frequency offset corrected baseband sampling signal is output.

[0120] The timing error of the baseband sampling signal after frequency offset correction is estimated, and the timing error is corrected by a polynomial interpolation filter to obtain the baseband sampling signal after timing error correction.

[0121] The baseband sampling signal after timing error correction is noncoherently decoded using Viterbi decoding to complete the Viterbi decoding and demodulate the output code data.

[0122] Specifically, in order to improve the processing speed of signal demodulation, the low sampling rate signal is first written to the data buffer module at a low processing rate (76.8kHz), and then the buffer data is read out from the buffer at a high processing rate (48MHz) to improve the speed of subsequent signal demodulation processing and ensure that message ID parsing can be completed before the buffer depth of the data buffer reaches the message length.

[0123] The timing of data writing by the data buffer module is controlled by the frame synchronization detection flag signal (frame_syn) output by the frame synchronization module, and the timing of stopping data writing by the data buffer module is controlled by the message length signal fed back by the message ID detection module. The data reading state of the data buffer module is controlled by the frequency offset estimation detection end signal (afc_finish) output by the carrier synchronization module and the message length signal fed back by the message ID detection module.

[0124] The data caching module employs an 8-state state machine to ensure reliable data retrieval, and reads the state transition diagram, such as... Figure 5 As shown.

[0125] The data reading steps of the data buffer are as follows:

[0126] 1) When the depth of data written to the cache reaches 1500 sampling points, the data cache transitions from the idle state to state 1;

[0127] 2) In state 1, the 1500 sampling points in the buffer are read out and sent to the frequency offset estimation module in the carrier synchronization module for carrier frequency offset estimation in the message ID parsing stage. At this time, the state jumps to state 2.

[0128] 3) In state 2, wait for the carrier frequency offset estimation to finish. After receiving the frequency offset estimation detection end signal (afc_finish), the state machine jumps to state 3.

[0129] 4) In state 3, the first 768 sampling points in the buffer are read out and sent to the frequency offset correction module in the carrier synchronization module for frequency offset correction in the message ID parsing stage. Then the state machine jumps to state 4.

[0130] 5) In state 4, the data caching module receives the message length signal from the message ID detection module and waits for the cache depth to reach the message length corresponding to the message ID. When the cache depth reaches the message length, the state machine transitions to state 5.

[0131] 6) In state 5, the first 2000 sampling points in the buffer are read out and sent to the frequency offset estimation module in the carrier synchronization module, and then the process jumps to state 6.

[0132] 7) In state 6, wait for the carrier frequency offset estimation to finish. After receiving the frequency offset estimation detection end signal (afc_finish), the state machine jumps to state 7.

[0133] 8) In state 7, all data in the buffer is read out and sent to the frequency offset correction module in the carrier synchronization module for frequency offset correction of one frame of data. After all data has been read out, the system jumps to the idle state.

[0134] The carrier synchronization module mainly includes a frequency offset estimation module and a frequency offset correction module, which primarily perform frequency offset estimation and correction functions for the data. The frequency offset estimation module uses a carrier frequency offset estimation method based on second-order cyclic cumulants to estimate the frequency offset of the data. The estimated carrier frequency offset value output by the frequency offset estimation module is shown below. The signal is sent to the frequency offset correction module, where it undergoes an exponential operation with the input signal to eliminate the frequency offset and complete the frequency offset correction. After the carrier frequency offset estimation is completed, a frequency offset estimation detection end signal (afc_finish) is fed back to the data buffer module.

[0135] The timing synchronization module mainly includes a Gaussian matched filter, timing error estimation, and a polynomial interpolation filter, which complete the timing error estimation and timing error correction functions.

[0136] The noncoherent Viterbi decoding module mainly includes an 8-state Viterbi decoding module and a message ID detection module, which mainly completes the Viterbi decoding of the signal, message ID and message length parsing.

[0137] In this optional embodiment, the process involves first reading out a preset length of cached data for frequency offset estimation. After the frequency offset estimation is completed, the frequency offset estimation value and a frequency offset estimation detection end signal (afc_finish) are output. After receiving the frequency offset estimation detection end signal (afc_finish), the data buffer reads out a preset length of cached data containing the message ID from the data buffer. The frequency offset estimation value is then used to correct the frequency offset of the subsequently read baseband sampling signal. The output frequency offset corrected baseband sampling signal includes:

[0138] Using a carrier frequency offset estimation mechanism based on second-order cyclic cumulant, frequency offset estimation is performed on the baseband sampled signal of a preset length read from the data buffer. After the frequency offset estimation is completed, the frequency offset estimation value and the frequency offset estimation detection end signal are output, and the frequency offset estimation detection end signal is fed back to the data buffer.

[0139] After receiving the frequency offset estimation detection end signal, the data buffer reads the preset buffer data containing the message ID content length from the buffer, performs an exponential operation on the frequency offset estimation value and the subsequently read baseband sampling signal to complete the frequency offset correction, and outputs the frequency offset corrected baseband sampling signal.

[0140] Specifically, such as Figure 6 As shown, the carrier synchronization module mainly includes a frequency offset estimation module and a frequency offset correction module, which primarily perform the functions of frequency offset estimation and correction for the data. The frequency offset estimation module uses a carrier frequency offset estimation method based on second-order cyclic cumulants to estimate the frequency offset of the data. The carrier frequency offset estimate value output by the frequency offset estimation module is shown in the figure. The signal is sent to the frequency offset correction module, where it undergoes an exponential operation with the input signal to eliminate the frequency offset and complete the frequency offset correction. After the carrier frequency offset estimation is completed, a frequency offset estimation detection end signal (afc_finish) is fed back to the data buffer module.

[0141] Assume the input signal formula for the carrier synchronization module is:

[0142] ;

[0143] In the formula, Input signal The range, Input signal Frequency offset, Input signal phase, is the exponentiation operator, and j is the imaginary indicator.

[0144] Signal after frequency offset correction The calculation formula is as follows:

[0145] ;

[0146] Signal after frequency offset correction Send to the timed synchronization module.

[0147] In this optional embodiment, the step of correcting the timing error of the frequency offset-corrected baseband sampling signal and compensating for the timing error using a polynomial interpolation filter to obtain the timing error-corrected baseband sampling signal includes:

[0148] The baseband sampling signal after frequency offset correction is matched and filtered by a Gaussian matched filter, and the timing error is estimated based on the filtering result, and the estimated timing error value is output.

[0149] A polynomial interpolation filter is used to correct the timing error estimate, and the corrected baseband sampling signal is output.

[0150] Specifically, the timing synchronization module mainly includes a Gaussian matched filter, timing error estimation, and a polynomial interpolation filter, which complete the timing error estimation and timing error correction functions.

[0151] The timing error is estimated by the timing error estimation module in the timing synchronization module, and then the timing error is compensated by the polynomial interpolation filter.

[0152] like Figure 7 The diagram shows the components of the timed synchronization module.

[0153] Let the sampling period of the signal be... ,remember After sampling n = 1, 2, 3, ..., n is the index of the sampling point. After passing through a Gaussian matched filter, The sampled signal output at time t is denoted as N is the oversampling factor of the signal, here N=8. The timing error estimation module performs the following calculations and outputs the timing error estimate. .

[0154] First, calculate the timing error accumulation function according to the following formula. value:

[0155] ;

[0156] In the formula, This is the cumulative length of the timing error. .

[0157] Calculate the timing error value again. Timing error value The calculation formula is as follows:

[0158] ;

[0159] In the formula, Let N be the symbol period, and N be the oversampling factor of the signal (N=8 here). The arg function calculates the amplitude of the signal. The timing error estimate is then used. The decimal part is denoted as .

[0160] Timing error estimate The signal is sent to a polynomial interpolation filter to correct timing errors. The calculation formula is as follows:

[0161] ;

[0162] In the formula, The interpolation period is m; m is the index of the interpolated value. is the sampling period of the signal; n is the index of the sampling point; h is the transfer function of the polynomial interpolation filter; Estimated timing error The decimal part; This is the output signal after timing error correction, which is then sent to the non-coherent Viterbi decoding module for decoding.

[0163] In this optional embodiment, the step of performing noncoherent Viterbi decoding on the baseband sampling signal after timing error correction to complete Viterbi decoding and demodulate the output code data includes:

[0164] The baseband sampling signal after timing error correction is Viterbi decoded through preset states (8 states), and a state transition table (trellis table) is constructed to calculate the path metric value of each branch.

[0165] The path with the largest path metric among all branches is selected as the surviving path and backtracked to demodulate the output code metadata.

[0166] Specifically, the message ID detection module only parses the message ID and its corresponding message length during the message ID parsing process. The 8-state Viterbi decoding module needs to decode the corresponding message during both the message ID parsing process and the formal message frame parsing process.

[0167] In the message ID parsing process, the 8-state Viterbi decoding module first decodes a portion of the data in a frame (768 sampling points, including the message ID content), sends the decoded data to the message ID detection module, and then the message ID detection module parses out the message ID and the corresponding message length, and feeds back the message length signal to the data cache module to control the data reading of the data cache module.

[0168] In the formal message frame parsing process, the 8-state Viterbi decoding module completes the decoding of a complete frame of data and sends the decoded data to the data frame processing module.

[0169] The Viterbi decoding module first needs to construct a trellis table. Based on this table, it calculates the path metric value of each possible path transitioning from the previous state to the current state, compares the path metric values ​​of each branch in the current state, and selects the path corresponding to the largest path metric as the surviving path. The path information of the surviving path is saved, and so on, until a frame of data is reached, at which point it backtracks to demodulate and output a frame of symbol information. The trellis table for 8-state Viterbi decoding is shown in Table 1.

[0170] Table 1. Trellis state transition table for Viterbi decoding

[0171] In this optional embodiment, the step of parsing the message ID and the message length corresponding to the message ID using the decoded code data, and outputting the message length signal (message_len) includes:

[0172] The start flag of the detection code metadata is used by the shift register to start the counter and extract the message ID signal;

[0173] Based on the correspondence between message ID and message length, the corresponding message length signal (message_len) is parsed and fed back to the data buffer to control the length of data written to the data buffer and the timing of data reading.

[0174] Specifically, the message ID detection module includes a shift register, a counter, and a message ID parsing and message length parsing module. This module parses the message ID and message length of the data decoded by the 8-state Viterbi decoding module. Its workflow includes:

[0175] 1) The message ID detection module only starts working when the data buffer read status is state 4. The data buffer module sends the buffer read status indication signal (st_rd) to the message ID detection module, and the message ID detection module starts working if and only if st_rd=4.

[0176] 2) First, use an 8-bit shift register to detect the start flag "0x7E" of the data frame.

[0177] 3) Once the shift register finds "0x7E", the counter is started, and the 6 bits of data following 0x7E are stored bit by bit into the message ID signal. Once 6 bits are stored, the message ID signal is output.

[0178] 4) Finally, based on the correspondence between message ID and message length, the corresponding message length is parsed out, and the message length (message_len) signal is fed back to the data cache module. This signal is used to control the data reading of the data cache module.

[0179] In this optional embodiment, the data length written to the buffer and the data readout timing are controlled by the message length signal (message_len), and the buffered data of the length corresponding to the message length signal (message_len) is read out. Carrier frequency offset estimation and correction, timing synchronization, and Viterbi decoding are then performed again. The demodulated output code metadata includes:

[0180] After receiving the message length signal (message_len), the data buffer waits for the buffered data written to the buffer to reach the data length corresponding to the message length signal (message_len). Then, it reads out the buffered data of the preset length (the first 2000 sampling points) from the data buffer and uses the buffered data of the preset length to perform frequency offset estimation. After the frequency offset estimation is completed, it outputs the frequency offset estimation value and the frequency offset estimation detection end signal (afc_finish).

[0181] After receiving the frequency offset estimation detection end signal (afc_finish), the data buffer reads out the buffer data of the length corresponding to the message length signal (message_len), performs an exponential operation with the frequency offset estimation value, completes the frequency offset correction, and outputs the frequency offset corrected baseband sampling signal.

[0182] The timing error of the baseband sampling signal after frequency offset correction is estimated, and the timing error is compensated by a polynomial interpolation filter to generate the baseband sampling signal after timing error correction.

[0183] The baseband sampling signal after timing error correction is subjected to Viterbi decoding of the complete frame data, and the output code data is demodulated.

[0184] Specifically, after receiving the message length signal (message_len), the data buffer module begins the formal message frame parsing process. First, the first 2000 sampling points in the data buffer are read out and sent to the carrier synchronization module for carrier frequency offset estimation during the formal message frame parsing phase. When the buffer depth reaches the message length, all data in the data buffer is read out and sent to the carrier synchronization module for frequency offset correction. The frequency offset corrected data is then sent to the timing synchronization module. First, the timing error estimation module in the timing synchronization module performs timing error estimation, and then a polynomial interpolation filter compensates for the timing error. After timing synchronization is complete, the signal is sent to the non-coherent Viterbi decoding module to decode a complete frame of data. This data is then output to the data frame processing module.

[0185] In this optional embodiment, the baseband signal processing for one frame of data includes differential decoding of the code data, frame flag detection, zero removal, and cyclic redundancy check (CRC check), outputting demodulated byte data and a check-finish flag signal (CheckFinish).

[0186] Perform differential decoding on the code metadata and output the differentially decoded code metadata;

[0187] Detect the start and end markers in the bit metadata after differential decoding, and output bit metadata with frame boundary indication;

[0188] Remove the padding bits inserted after a continuous sequence of numbers in the code metadata with frame boundary indicators, and output the zero-removed code metadata.

[0189] The cyclic redundancy checker is used to check the zero-removed code data, outputting the cyclic redundancy check end flag and the cyclic redundancy check pass flag, and restoring the data between the start flag and the end flag to byte data output.

[0190] Specifically, such as Figure 7 The diagram shows the block structure of the data frame processing module. This module parses the Viterbi-decoded data according to the AIS data format. First, differential decoding is performed on the decoded data. Then, the start and end flags (0x7E) are detected. Next, the "0" bits following every five consecutive "1"s are removed. The data after removing the "0" bits is then processed by a CRC checksum reader, which outputs a CRC check completion flag and a CRC pass flag. Finally, the data between the start and end flags is restored to byte data and output.

[0191] According to another embodiment of the present invention, a baseband signal processing system for an airborne ship automatic identification receiver is also provided, the system comprising:

[0192] The digital quadrature downconverter module is used to receive digital intermediate frequency signals and convert them into baseband sampling signals through digital quadrature downconversion.

[0193] The frame synchronization module is used to perform frame synchronization processing on the baseband sampling signal. After detecting the frame header, it outputs a frame synchronization detection flag signal and uses the frame synchronization detection flag signal to control the timing of data writing to the data buffer.

[0194] The data buffer, carrier synchronization, timing synchronization, and non-coherent Viterbi decoding modules are used to write baseband sampling signals after the data buffer receives the frame synchronization detection flag signal. When the buffer depth of the data buffer reaches a preset depth threshold, a preset length of buffered data is first read out for carrier frequency offset estimation of the baseband sampling signal. After the carrier frequency offset estimation is completed, a preset length of buffered data containing the message ID content is read out from the data buffer. Carrier frequency offset correction is performed first, followed by timing synchronization and Viterbi decoding, demodulating the output code metadata.

[0195] The carrier synchronization, timing synchronization, and non-coherent Viterbi decoding module is used to parse the message ID and the message length corresponding to the message ID from the decoded code data, and output the message length signal; the message length signal is used to control the length of data written to the data buffer and the timing of data reading, and the buffered data of the length corresponding to the message length signal is read out, and the carrier frequency offset estimation and correction, timing synchronization and Viterbi decoding are performed again to demodulate and output code data.

[0196] The data frame processing module is used to perform differential decoding, frame flag detection, zero removal and cyclic redundancy check on the code data, and output the demodulated byte data and the check end flag signal to complete the baseband signal processing of one frame of data.

[0197] In summary, the technical solution of the present invention includes the following design:

[0198] First, a message ID detection module was designed to parse the message ID of each data frame before formal parsing. This method effectively and quickly identifies the message type received by the receiver, thereby determining the message length. This effectively solves the problem of chaotic data frame reading caused by uncertain data buffer length, and significantly improves the probability of the system correctly demodulating the received data.

[0199] Second, an error prevention mechanism was designed for the frame synchronization module. After detecting a cross-correlation peak, the frame synchronization module must wait for 2000 clock cycles or receive a verification end flag signal from the incoherent Viterbi decoding module before starting the next frame header detection. This effectively avoids false frame header detection caused by parts of the data segment being identical to the training sequence content, thus improving the correct probability of frame synchronization.

[0200] Third, a data buffer read / write mechanism was designed. The timing of data writing to the data buffer module is controlled by the frame synchronization detection flag signal (frame_syn) output by the frame synchronization module, and the timing of stopping data writing is controlled by the message length signal fed back by the message ID detection module. The data reading state of the data buffer module is controlled by the frequency offset estimation detection end signal (afc_finish) output by the carrier synchronization module and the message length signal fed back by the message ID detection module. This mechanism effectively ensures that message length parsing is completed before the formal parsing of the data frame, providing a guarantee for reading the correct length data frame before Viterbi decoding.

[0201] This invention effectively solves the problem of chaotic data frame reading caused by the uncertain length of the data buffer by using message ID parsing technology, frame synchronization error prevention mechanism, and data buffer read / write mechanism design. This reduces the probability of frame synchronization error detection and significantly improves the system's data reception accuracy. Furthermore, the use of a non-coherent demodulation mechanism greatly reduces the complexity of system implementation.

[0202] The ITU-R M.1371-5 protocol, issued by the International Telecommunication Union, requires that AIS receivers maintain a correct packet reception rate of at least 80% even with a 1kHz frequency offset. The receiver sensitivity requirement is -107dBm. This receiver's performance significantly exceeds these specifications.

[0203] To demonstrate the effectiveness of the frame synchronization error prevention mechanism, simulation verification of the frame synchronization detection success rate is presented. Simulations were performed at different signal-to-noise ratios (SNRs) for carrier frequency offsets of 0Hz, 1kHz, and 2kHz. The simulation results are as follows: Figure 10 As shown.

[0204] like Figure 10 As shown, when the carrier frequency offset is 0Hz, i.e., there is no carrier frequency offset, When the value is greater than 12dB, the success rate of the synchronization head detection can exceed 95%. Among these, The energy of a symbol signal; This represents the power spectral density of white noise.

[0205] When the carrier frequency offset is 1kHz and 2kHz, When the value is greater than 12.5dB, the success rate of the synchronization head detection can be greater than 95%.

[0206] The simulation results show that the frame synchronization design scheme of the present invention has a very high success rate in frame header detection, which lays the foundation for the correct demodulation of subsequent signals.

[0207] In addition, to verify the demodulation performance of 8-state Viterbi decoding based on message ID parsing, simulation results of bit error rate and packet error rate under a 1kHz frequency offset are given.

[0208] like Figure 11 , Figure 12 As shown, when At that time, the bit error rate of 8-state Viterbi decoding can reach 10. -4 The error rate can reach 10%. -2 This meets the system's performance requirements.

[0209] Based on the simulation data above, the receiver sensitivity is calculated, ensuring a frame synchronization success detection probability of 95% and a packet error rate of no less than 10%. -2 time Perform calculations and take .

[0210] According to the receiver sensitivity calculation formula:

[0211] ;

[0212] In the formula, This represents the noise figure of the receiver. For symbol rate, here , =9.6kbps

[0213] The receiver sensitivity is 6 dB higher than the ITU-R M.1371-5 requirement (-107 dB). This performance demonstrates the superior processing performance of this baseband sampling signal processing method.

[0214] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A baseband signal processing method for an airborne automatic identification receiver for ships, characterized in that, include: It receives digital intermediate frequency (IF) signals and converts them into baseband sampling signals through digital quadrature downconversion. The baseband sampling signal is processed for frame synchronization. After the frame header is detected, a frame synchronization detection flag signal is output, and the frame synchronization detection flag signal is used to control the timing of data writing to the data buffer. After receiving the frame synchronization detection flag signal, the data buffer begins writing the baseband sampling signal. When the buffer depth of the data buffer reaches the preset depth threshold, it first reads out the buffer data of the preset length for carrier frequency offset estimation of the baseband sampling signal. After the carrier frequency offset estimation is completed, it reads out the buffer data of the preset length containing the message ID content from the data buffer. Carrier frequency offset correction is performed first, followed by timing synchronization and Viterbi decoding, and demodulation of the output code metadata. The message ID and the message length corresponding to the message ID are parsed from the decoded code data, and the message length signal is output. The message length signal is used to control the length of data written to the data buffer and the timing of data reading. The buffered data with the length corresponding to the message length signal is read out, and carrier frequency offset estimation and correction, timing synchronization and Viterbi decoding are performed again to demodulate and output code data. Differential decoding, frame flag detection, zero removal, and cyclic redundancy check are performed on the code data. The demodulated byte data and the check end flag signal are output to complete the baseband signal processing of one frame of data.

2. The baseband signal processing method for an airborne ship automatic identification receiver according to claim 1, characterized in that, The process of receiving a digital intermediate frequency (IF) signal and converting it into a baseband sampling signal via digital quadrature downconversion includes: Receives the digital intermediate frequency signal generated by the AD converter; By using the built-in numerically controlled oscillator in the digital mixer, the value of the frequency control word is set to generate an orthogonal waveform of the corresponding frequency. The orthogonal waveform is then multiplied by the complex input signal through the built-in complex multiplier in the digital mixer to generate the baseband sampling signal after orthogonal downconversion. The baseband sampling signal is sequentially input to the first-stage 25x CIC decimation filter, the second-stage 5x CIC decimation filter, and the third-stage 5x CIC decimation filter for decimation filtering, and finally outputs the baseband sampling signal with reduced sampling rate.

3. The baseband signal processing method for an airborne ship automatic identification receiver according to claim 1, characterized in that, The step of performing frame synchronization processing on the baseband sampling signal, outputting a frame synchronization detection flag signal after detecting the frame header, and using the frame synchronization detection flag signal to control the timing of data writing to the data buffer includes: Perform differential cross-correlation calculation between the baseband sampled signal and the local reference sequence, and output the cross-correlation result; Perform maximum value detection on the cross-correlation results and output the position of the cross-correlation peak; The frame header position is determined based on the position of the cross-correlation peaks; After detecting the frame header position, the frame synchronization state machine transitions from the idle state to the detection state and outputs a frame synchronization detection flag signal; The error prevention mechanism triggers the frame synchronization state machine to enter a waiting state, waiting for the synchronization detection of the next frame signal to begin. After the frame synchronization detects the frame header, the output frame synchronization detection flag signal is sent to the data buffer to control the timing of data writing to the data buffer. When the data buffer receives the frame synchronization detection flag signal, it begins to write the baseband sampling signal into the buffer.

4. The baseband signal processing method for an airborne ship automatic identification receiver according to claim 1, characterized in that, After receiving the frame synchronization detection flag signal, the data buffer starts writing the baseband sampling signal. When the buffer depth of the data buffer reaches the preset depth threshold, it first reads out the buffer data of the preset length for carrier frequency offset estimation of the baseband sampling signal. After the carrier frequency offset estimation is completed, it reads out the buffer data of the preset length containing the message ID content from the data buffer. First, carrier frequency offset correction is performed, followed by timing synchronization and Viterbi decoding. The demodulated output code metadata includes: Once the data buffer receives the frame synchronization detection flag signal, it begins writing the baseband sampling signal into the data buffer. During the process of writing the baseband sampling signal into the data buffer, when the buffer depth of the data buffer reaches the preset depth threshold, the corresponding length of the baseband sampling signal is read from the data buffer. First, read the cached data of a preset length to perform frequency offset estimation. After the frequency offset estimation is completed, output the frequency offset estimation value and the frequency offset estimation detection end signal. After the data buffer receives the frequency offset estimation detection end signal, read the cached data of a preset length containing the message ID content from the data buffer. Use the frequency offset estimation value to perform frequency offset correction on the subsequently read baseband sampling signal and output the frequency offset corrected baseband sampling signal. The timing error of the baseband sampling signal after frequency offset correction is estimated, and the timing error is corrected by a polynomial interpolation filter to obtain the baseband sampling signal after timing error correction. The baseband sampling signal after timing error correction is noncoherently decoded using Viterbi decoding to complete the Viterbi decoding and demodulate the output code data.

5. A baseband signal processing method for an airborne ship automatic identification receiver according to claim 4, characterized in that, First, a preset length of cached data is read out for frequency offset estimation. After the frequency offset estimation is completed, the frequency offset estimation value and a frequency offset estimation detection end signal are output. After the data buffer receives the frequency offset estimation detection end signal, it reads out a preset length of cached data containing the message ID content from the data buffer. The frequency offset estimation value is used to correct the frequency offset of the subsequently read baseband sampling signal. The output frequency offset corrected baseband sampling signal includes: Using a carrier frequency offset estimation mechanism based on second-order cyclic cumulant, frequency offset estimation is performed on the baseband sampled signal of a preset length read from the data buffer. After the frequency offset estimation is completed, the frequency offset estimation value and the frequency offset estimation detection end signal are output, and the frequency offset estimation detection end signal is fed back to the data buffer. After receiving the frequency offset estimation detection end signal, the data buffer reads the preset buffer data containing the message ID content length from the data buffer, performs an exponential operation on the frequency offset estimation value and the subsequently read baseband sampling signal to complete the frequency offset correction, and outputs the frequency offset corrected baseband sampling signal.

6. A baseband signal processing method for an airborne ship automatic identification receiver according to claim 4, characterized in that, The step of correcting the timing error of the baseband sampling signal after frequency offset correction and compensating for the timing error using a polynomial interpolation filter to obtain the baseband sampling signal after timing error correction includes: The baseband sampling signal after frequency offset correction is matched and filtered by a Gaussian matched filter, and the timing error is estimated based on the filtering result, and the estimated timing error value is output. A polynomial interpolation filter is used to correct the timing error estimate, and the corrected baseband sampling signal is output.

7. A baseband signal processing method for an airborne ship automatic identification receiver according to claim 4, characterized in that, The step of performing non-coherent Viterbi decoding on the baseband sampling signal after timing error correction to complete Viterbi decoding, and demodulating the output code data includes: The baseband sampling signal after timing error correction is Viterbi decoded through a preset state, and a state transition table is constructed to calculate the path metric value of each branch. The path with the largest path metric among all branches is selected as the surviving path and backtracked to demodulate the output code metadata.

8. A baseband signal processing method for an airborne ship automatic identification receiver according to claim 1, characterized in that, The process of parsing the message ID and the message length corresponding to the message ID using the decoded code data and outputting the message length signal includes: The start flag of the detection code metadata is used by the shift register to start the counter and extract the message ID signal; Based on the correspondence between message ID and message length, the corresponding message length signal is parsed and fed back to the data buffer to control the length of data written to the data buffer and the timing of data reading.

9. A baseband signal processing method for an airborne ship automatic identification receiver according to claim 1, characterized in that, The process involves using a message length signal to control the length of data written to the buffer and the timing of data readout, then reading out the buffered data of the length corresponding to the message length signal, and performing carrier frequency offset estimation and correction, timing synchronization, and Viterbi decoding again. The demodulated output code metadata includes: After receiving the message length signal, the data buffer waits for the cached data written into the buffer to reach the data length corresponding to the message length signal. Then, it reads out the cached data of the preset length from the data buffer and uses the cached data of the preset length to perform frequency offset estimation. After the frequency offset estimation is completed, it outputs the frequency offset estimation value and the frequency offset estimation detection end signal. After receiving the frequency offset estimation detection end signal, the data buffer reads out the buffer data of the length corresponding to the message length signal, performs an exponential operation with the frequency offset estimation value, completes the frequency offset correction, and outputs the frequency offset corrected baseband sampling signal. The timing error of the baseband sampling signal after frequency offset correction is estimated, and the timing error is compensated by a polynomial interpolation filter to generate the baseband sampling signal after timing error correction. The baseband sampling signal after timing error correction is subjected to Viterbi decoding of the complete frame data, and the output code data is demodulated.

10. A baseband signal processing method for an airborne ship automatic identification receiver according to claim 1, characterized in that, The process of differentially decoding, detecting frame flags, removing zeros, and performing cyclic redundancy check on the code data, outputting demodulated byte data and a check completion flag signal, to complete the baseband sampling signal processing for one frame of data includes: Perform differential decoding on the code metadata and output the differentially decoded code metadata; Detect the start and end markers in the bit metadata after differential decoding, and output bit metadata with frame boundary indication; Remove the padding bits inserted after a continuous sequence of numbers in the code metadata with frame boundary indicators, and output the zero-removed code metadata. The cyclic redundancy checker is used to check the zero-removed code data, outputting the cyclic redundancy check end flag and the cyclic redundancy check pass flag, and restoring the data between the start flag and the end flag to byte data output.

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