MIPI-based FPGA display subsystem and display method

Abstract

The application discloses a MIPI-based FPGA display subsystem and a display method, provides only four bus interfaces, constructs an FPGA display system with a MIPI controller as a core, realizes synchronous processing of RGB / YUV multi-format 2K-level high-definition video and MIPI DSI-v1.2 protocol output at an FPGA end through integration of DC8000 display control and MIPI DSI / DPHY transmission functions, adopts parameterizable clock reset management and AMBA bus interface design, supports seamless docking with an SOC and register-level flexible configuration, and ensures high stability of video transmission, strong flexibility of interface adaptation and high efficiency of system integration and debugging on the FPGA platform through ASIC / FPGA code compatibility and hierarchical verification mechanism, and meanwhile, low-power consumption design requirements of an embedded scene are considered.

Description

Technical Field

[0001] This invention relates to FPGA display systems, specifically a MIPI-based FPGA display subsystem and display method. Background Technology

[0002] As display technology rapidly advances towards higher resolution, higher refresh rates, and lower power consumption, consumer electronics, industrial control, and automotive displays are placing increasing demands on the transmission rate, interface compatibility, and hardware adaptation flexibility of display subsystems. MIPI DSI, a serial display interface standard developed by the Mobile Processor Interface Consortium, has become the mainstream interface solution in the current display field due to its advantages of high bandwidth, low pin count, and support for differential signal transmission. It supports multi-lane data transmission (up to 4 lanes) and a high-speed transmission rate of 2.5Gbps / lane, meeting the data transmission needs of 2K and higher resolution images. It is also compatible with various video input formats such as RGB and YUV, adapting to the image data processing requirements of different display scenarios.

[0003] In the design and verification of display subsystems, FPGAs, with their characteristics of hardware programmability, short development cycle, and flexible function tailoring, have become the core hardware carrier for display interface development, chip prototype verification, and small-batch application scenarios. Traditional FPGA display designs suffer from several issues, including low integration between the display controller and MIPI interface, inconsistent clock and reset system designs, and poor code reusability between ASIC and FPGA versions. On one hand, most solutions design the display controller, MIPI DSI controller, and DPHY physical layer independently. Interface adaptation between modules requires additional development of adaptation logic, increasing the complexity of FPGA design and timing convergence difficulties, and hindering unified compatibility across multiple protocols (DSI-v1.2, DCS-v1.3, DPI-v2.0, etc.). On the other hand, traditional clock systems lack layered design for high-frequency core clocks, pixel clocks, and bus clocks. The reset system lacks refined asynchronous reset and synchronous release design for different modules such as AXI, APB, and core logic, leading to timing errors and data transmission loss. Furthermore, the ASIC and FPGA versions are typically written independently, making rapid portability of designs difficult and increasing development costs from prototype verification to mass production.

[0004] Meanwhile, existing FPGA display solutions suffer from problems in MIPI interface configuration and control, including cumbersome register configuration, non-standard PHY layer initialization procedures, and imperfect interrupt management mechanisms. This makes it difficult to flexibly configure display resolution, pixel format, and transmission rate. Furthermore, in high-bandwidth data transmission scenarios, issues such as signal skew and clock asynchrony can easily occur, affecting display quality. Additionally, in the SOC top-level integration stage, traditional solutions lack standardized interface definitions, resulting in low interface efficiency between the display subsystem and the AMBA bus (AXI, APB), and difficulty in performing hardware design checks such as CDC (cross-clock domain) and nlint, reducing system stability and verifiability.

[0005] To address the aforementioned issues, there is an urgent need for a highly integrated, highly compatible, and highly reusable MIPI-based FPGA display design solution. This solution would integrate the display controller, MIPI DSI controller, and DPHY physical layer into a unified design, unify the clock and reset system architecture, enable one-click switching between ASIC and FPGA code versions, standardize the configuration process and timing design of the MIPI interface, improve the transmission stability, hardware adaptation flexibility, and development efficiency of the display subsystem, and meet the needs of FPGA prototyping and practical applications in high-resolution display scenarios. Summary of the Invention

[0006] To address the shortcomings of the existing technologies, this invention provides a MIPI-based FPGA display subsystem and display method. This invention is a subsystem-level integrated design, rather than a functional improvement of a single IP. By integrating, unifying, and standardizing the management and control of the three major IPs—the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface—it solves the technical problems of low integration, asynchronous clock reset, and poor interface compatibility in existing solutions.

[0007] To achieve the above technical objectives, the present invention adopts the following technical solution: a MIPI-based FPGA display subsystem, wherein the subsystem is a monolithically integrated hardware module, including a DC8000 display controller, a MIPI DSI host controller, and a MIPI D-PHY physical layer interface; The DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface are interconnected within the hardware module via a bus. The hardware module provides four bus interfaces, namely: One AXI3 Master interface is configured to enable the hardware module to access and interact with DDR storage data; wherein, the AXI3 Master interface is directly brought out from the AXI3 Master interface of the DC8000 display controller to the top level of the subsystem; One APB3 Slave interface is configured to independently configure the registers of the DC8000 display controller; wherein, the APB3 Slave interface is directly brought out from the APB3 Slave interface of the DC8000 display controller to the top level of the subsystem; The first APB2 Slave interface is configured to independently configure the registers of the MIPI DSI host controller; wherein, the first APB2 Slave interface is directly brought out from the APB2 Slave interface of the MIPI DSI host controller to the top level of the subsystem; The second APB2 Slave interface is connected to a top-level register control module and is configured to uniformly configure the top-level control signals of the MIPI DSI host controller and the MIPI D-PHY physical layer interface.

[0008] The hardware module also provides 6 system clock interfaces, which are configured to receive 6 standard input clocks provided by the SOC, and allocate independent clock domains for the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface and realize asynchronous and synchronous processing.

[0009] The hardware module also provides three reset interfaces, which are configured to receive three independent reset signals from the SOC, thereby enabling independent reset control of the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface.

[0010] The hardware module is also provided externally. The interrupt interface is configured to interface with the SOC's interrupt management module; The DPHY differential link interface is configured to directly connect to the MIPI display terminal; The test interface is configured to support mass production testing, online debugging, and hardware fault location for subsystems.

[0011] A MIPI-based FPGA display method includes the following steps: The configuration signals from the CPU are received through one APB3 Slave interface and two APB2 Slave interfaces, and the internal registers of the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface are configured independently respectively. The rendered video data is read from DDR storage via the AXI3 Master interface, and after being stored and managed by the internal MMU of the DC8000 display controller and decompressed by the DEC400, the format conversion and image processing are completed to generate a standard DPI interface video data stream. The standard DPI interface video data stream is sent to the MIPI DSI host controller through the standardized DPI interface. Inside the MIPI DSI host controller, the data is buffered and packetized through FIFO and converted into MIPI DSI protocol data packets. The MIPI DSI protocol data packet is sent to the MIPI D-PHY physical layer interface, converted into a high-speed serial differential signal, and the video signal is output to the MIPI display terminal.

[0012] It also includes the following steps, It receives 6 standard input clocks provided by the SOC and allocates independent clock domains for the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface, and implements asynchronous and synchronous processing. At the hardware level, the pixel clock of the DC8000 display controller is synchronized and bound with the DPI interface clock of the MIPI DSI host controller.

[0013] It also includes the following steps, The reset signal is bound one by one to the core logic / interface of the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface, so as to realize the independent reset of the core logic and bus interface of the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface.

[0014] The reset control within the subsystem follows the following sequence rules: The AXI3 Master interface of the DC8000 display controller enters the reset state first and exits the reset state last.

[0015] It also includes the following steps: unifying the effective duration of the reset signal and the waiting time after cancellation.

[0016] In summary, the present invention has achieved the following technical effects: Integrated Structure: This invention proposes a DC+MIPI integrated packaging structure based on DM_WRAPPER, which encapsulates three independent IPs—DC8000, DWC_mipi_dsi_host, and DWC_mipi_dphy—into a single DM subsystem. Externally, it only exposes standardized AMBA bus interfaces (1 AXI3 Master, 3 APB Slave) and MIPI standard differential link interfaces, which can be directly connected to a SoC without additional adapter circuits, greatly improving system integration and reducing the difficulty of SoC docking and FPGA hardware resource usage. End-to-end standardized video data link: This invention designs an end-to-end standardized video data link from DDR storage to the MIPI display terminal. Through seamless integration with the MIPI DSI host controller via the DC8000DPI interface, it achieves formatless transmission of video data. Simultaneously, through high-speed serial conversion between the MIPI DSI host controller's packet assembly and the MIPI D-PHY physical layer interface, it completes standardized output of the video signal. This hardware-level design ensures the integrity, real-time performance, and synchronization of video data transmission, solving the problems of complex format conversion circuits, data transmission interruptions, and image tearing in existing solutions. System workflow control: This invention upgrades the native workflow of the MIPI DSI host controller to a five-stage workflow at the subsystem level: Boot→PowerDown→Initialization→PowerUp→Running, realizing the status linkage and coordinated start and stop of the three IPs. For example, after the DC video data is prepared, the high-speed transmission mode of the MIPI controller is triggered. When the MIPI transmission is abnormal, the frame buffer of the DC is paused. This invention solves the problems of system instability and state asynchrony caused by the independent operation of a single module through unified management of the top-level DM_WRAPPER. Multi-clock domain collaborative management: This invention designs a parameterizable multi-clock domain collaborative management mechanism, which receives a unified clock source provided by the SOC, allocates independent clock domains to the three IPs, and achieves precise synchronization between the pixel clock and the MIPI transmission clock through dynamic frequency division and phase synchronization mechanisms. At the same time, it supports dynamic adaptation of the pixel clock according to the resolution / frame rate, which solves the problems of display screen distortion and frame rate jump caused by clock domain conflict and large synchronization error in the existing solution. Priority-based reset control: This invention designs a reset priority rule with priority reset of AXI interface and latest cancellation. The reset signal is bound to the core logic / interface of each IP module, and strict timing constraints are imposed on the effective duration of the reset signal and the cancellation waiting duration. At the same time, the external reset signal is synchronized to the local clock domain of each IP, which solves the problems of asynchronous reset, unstable system startup, and data transmission errors caused by metastability of cross-clock domain reset in the existing solution. ASIC / FPGA code compatibility: This invention achieves compatibility of a single RTL code on ASIC and FPGA platforms through macro definition switching. At the same time, the memory is standardized and packaged to support memory replacement on FPGA platforms and tape-out implementation on ASIC platforms. This enables seamless migration from FPGA verification to ASIC tape-out, reduces development costs and tape-out risks, improves the portability of the solution, and can be adapted to both FPGA prototype verification and chip mass production scenarios. Attached Figure Description

[0017] Figure 1 This is a block diagram of the integrated structure of the DM subsystem of this invention; Figure 2 This is a block diagram of the implementation structure of the DM subsystem of the present invention. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to the accompanying drawings.

[0019] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

[0020] Example: like Figure 1 and Figure 2 As shown, a MIPI-based FPGA display subsystem is presented. The subsystem is a monolithically integrated hardware module, including a DC8000 display controller, a MIPI DSI host controller, and a MIPI D-PHY physical layer interface. The DC8000 display controller, MIPI DSI host controller, and MIPI D-PHY physical layer interface are interconnected within the hardware module via a bus. The hardware module provides four external bus interfaces: One AXI3 Master interface is configured to enable hardware modules to access and interact with DDR storage data; the AXI3 Master interface is directly brought out from the AXI3 Master interface of the DC8000 display controller to the top level of the subsystem. One APB3 Slave interface is configured to independently configure the registers of the DC8000 display controller; the APB3 Slave interface is directly brought out from the APB3 Slave interface of the DC8000 display controller to the top level of the subsystem. The first APB2 Slave interface is configured to be independently configured with respect to the registers of the MIPI DSI host controller; wherein, this first APB2 Slave interface is directly brought out from the APB2 Slave interface of the MIPI DSI host controller to the top level of the subsystem; The second APB2 Slave interface is configured to uniformly configure the top-level control signals of the MIPI DSI host controller and the MIPI D-PHY physical layer interface.

[0021] This invention selects the DC8000 display controller IP, the DWC_mipi_dsi_host controller IP as the MIPI D-PHY host controller, and the DWC_mipi_dphy PHY IP as the MIPI D-PHY physical layer interface to achieve integrated subsystem. The three IPs are interconnected within the hardware module via a bus, enabling the subsystem to connect to the outside as a whole hardware unit.

[0022] The DC8000 display controller, serving as the core of video processing, features an AXI3 Master interface (128-bit) and an APB3 Slave interface. It supports DDR-stored video data reading, RGB / YUV422 / YUV420 multi-format video processing, and DPI output. Integrating dual-buffer management and a DEC400 decompression module reduces video transmission bandwidth requirements and supports asynchronous clock processing with external modules, supporting a maximum resolution of 2048×1080 (2K). To achieve asynchronous clock processing, this invention uses clock domains independent of the core clock for the DC8000 display controller's AXI3 Master interface, APB3 Slave interface, and DPI output interface, and integrates asynchronous FIFOs or buffers within the chip to ensure reliable data transfer across clock domains. Specifically, the AXI3 Master interface is asynchronous with the DC core logic, ensuring that high-speed bus access does not interfere with core image processing; the APB3 Slave interface has an independent clock, supporting low-power configuration access; and the DPI output interface uses an independent pixel clock, which can be dynamically adjusted according to the display resolution. This design allows each clock domain to independently optimize its frequency and layout, avoiding timing conflicts across clock domains and significantly reducing the clock constraint complexity of SOC integration.

[0023] The MIPI DSI host controller supports the MIPI DSI-v1.2 / DCS-v1.3 protocol, supports a maximum of 4 lanes of transmission, 2.5Gbps / lane (total bandwidth 10Gbps), has 2 APB2 Slave interfaces, supports seamless DPI pixel interface docking, integrates video mode / command mode dual transmission modes, supports 16 / 24 / 30 bit RGB color mode and 12 / 16 / 20 bit YUV color mode, and can realize video data packetization and high-speed serial signal transmission; The MIPI D-PHY physical layer interface serves as the core of physical layer transmission. It has a built-in phase-locked loop (PLL), supports switching between LP low-power mode and HS high-speed mode, has 4 data lanes and 1 clock lane, supports bidirectional communication, integrates scan test and analog test bus interfaces, adapts to the hardware resource characteristics of FPGA platforms, and meets the needs of low-power embedded applications.

[0024] Specifically, the second APB2 Slave interface connects to the top-level register control module, which in turn connects to the MIPI DSI host controller and the MIPI D-PHY physical layer interface. The top-level register control module is located internally within the hardware module and includes an APB2 Slave interface, a programmable register set, and a control logic unit. This APB2 Slave interface connects to the SoC system bus, performing register address decoding, read / write control, data sampling and readback, and externally connects to the second APB2 Slave interface of the DM system. Internally, it provides configuration entry points for the registers. The programmable register set is a group of memory-mapped, readable, writable, and observable 32-bit registers that centrally latch configuration parameters from the SoC. The control logic unit directly parses and maps register bit values ​​to pin-level hardware control signals for the MIPI DSI host controller and the MIPI D-PHY physical layer interface. Working principle: First, configure the input and write the configuration to the top-level register control module through the second APB2 Slave interface. The configuration value is written to the programmable register group. The control logic unit converts the register value into control signals that directly manipulate the hardware pins according to the fixed bit field mapping relationship. The signals are connected to the corresponding pins of the MIPI DSI host controller and the MIPI D-PHY physical layer interface to complete the underlying hardware control.

[0025] Top-level control signals refer to PLL parameters, lane modes, test controls, etc. This invention performs logical conversion and synchronization on the interfaces of three IPs that might otherwise be incompatible, providing a unified, simple, and standardized interface, thereby hiding internal complexity and facilitating top-level integration of the SoC.

[0026] This invention is an integrated design of DC+MIPI, hence the name DM subsystem. The DM subsystem integrates one AXI3 Master interface and three APB Slave interfaces (one APB3 and two APB2), which are directly connected to the AMBA bus. At the same time, the DM subsystem accesses and interacts with DDR storage data through the AXI3 Master interface. An external Master interface (such as a CPU) can access the internal registers of the DM subsystem through the APBSlave interface to configure parameters such as display resolution, video format, number of MIPI transmission lanes, and frame rate.

[0027] Furthermore, in addition to the four bus interfaces mentioned above, the hardware module also provides six system clock interfaces, configured to receive six standard input clocks provided by the SOC. These interfaces allocate independent clock domains to the DC8000 display controller, MIPI DSI host controller, and MIPI D-PHY physical layer interface, enabling asynchronous and synchronous processing. After being input from the top layer, the six system clocks are distributed to the corresponding clock ports of each IP address.

[0028] The hardware module also provides three reset interfaces, configured to receive three independent reset signals from the SOC, enabling independent reset control of the DC8000 display controller, MIPI DSI host controller, and MIPI D-PHY physical layer interface. The three reset signals are input from the top layer and then distributed to the corresponding reset ports of each IP.

[0029] The hardware module also provides the following to external users: The interrupt interface is configured to interface with the SOC's interrupt management module; the DM subsystem of this invention integrates an independent interrupt interface, which interacts with the CPU's working status through the interrupt interface management component, and can provide real-time feedback on the completion status of DC video processing and the abnormal status of MIPI transmission. The DPHY differential link interface is configured to directly connect to the MIPI display terminal; The test interface is configured to support mass production testing, online debugging, and hardware fault location for subsystems.

[0030] In summary, the subsystem of this invention achieves integrated packaging of three major IPs—DC8000, DWC_mipi_dsi_host, and DWC_mipi_dphy—through the DM_WRAPPER top-level packaging module. The overall design adopts a standardized AMBA bus interface, exposing only: one AXI3 Master interface, three APB Slave interfaces (one APB3 and two APB2), six system clock interfaces, three reset interfaces, an interrupt interface, a DPHY differential link interface, and a test interface. It can be directly connected to the AMBA bus of the SOC without additional adapter circuitry, significantly improving system integration, reducing SOC integration difficulty, and minimizing FPGA hardware resource consumption.

[0031] Internally, the DC8000 display controller's DPI output interface is directly connected to the DPI input interface of DWC_mipi_dsi_host. The DPI output and input interfaces are naturally matched in signal definition, timing, and level. Therefore, the DC8000 display controller's DPI output signal line can be directly instantiated at the DM_WRAPPER top level and connected to the DPI input port of DWC_mipi_dsi_host without adding any data format conversion circuits, timing adjustment circuits, or level matching circuits. Similarly, all IP bus interfaces use the standard AMBA protocol, allowing direct connection to the SOC bus without bridges or protocol converters. Traditional solutions use display controllers with custom parallel or RGB interfaces instead of standard DPI, or MIPI controllers with other input formats, necessitating conversion logic and additional adapter circuits. However, this invention eliminates the need for adapter circuits at the hardware connection level by ensuring complete standardization and compatibility of the interconnect interfaces of the three IPs during the integration design phase.

[0032] Inside the subsystem, the MIPI DSI host controller connects to the MIPI D-PHY physical layer interface via the PPI interface, including clock lane signals, independent control and data signals for four data lanes, etc.

[0033] Meanwhile, the subsystem has reserved comprehensive debugging and testing interfaces: the JTAG interface supports online debugging of the MIPI controller and PHY, the DFT scan test interface supports mass production testing and fault location of the subsystem, and the PLL configuration interface supports fine adjustment of the MIPI clock, taking into account integration, debuggability and testability.

[0034] To achieve seamless end-to-end standardization, this invention ensures that the DC8000 display controller's native output standard DPI interface and the MIPI DSI host controller's native input standard DPI interface are directly connected at the DM_WRAPPER top layer. This achieves a "one-time format conversion, no code throughout" transmission effect for the entire data path from DDR read to MIPI serial output, eliminating the need for any glue logic. This invention completely separates the configuration link from the three data links: the CPU configures three IPs through three independent APB Slave interfaces, with configuration commands directly reaching each IP core without passing through the data path. This means that during video transmission, the number of MIPI lanes can be adjusted independently, HS / LP modes can be switched, and PLL parameters can be modified without interfering with the ongoing image processing and AXI read operations on the DC. Traditional solutions treat the three IPs as independent black boxes, making it difficult to quickly pinpoint whether a problem originates on the DC, MIPI controller, or PHY side. This invention clearly separates the entire transmission process into three observable layers: the read link, the switching link, and the output link, each with clearly defined interface boundaries. During FPGA debugging, packet capture at the DPI interface can be used to verify whether the DC output is correct, and packet assembly at the PHY input can be used to verify whether the packet is correct, thereby quickly locating the problem.

[0035] To address the issue of requiring additional adaptation logic for interface compatibility between modules in existing solutions, this invention avoids this problem through IP selection and top-level integrated design. Specifically, the DC8000 natively supports the standard DPI video output interface, and the DWC_mipi_dsi_host natively supports the standard DPI video input interface. These two interfaces directly connect at the DM_WRAPPER top level, enabling video data transmission from the DC to the MIPI controller. Simultaneously, all IP configuration interfaces are standardized to the standard APB Slave, and the bus interface is standardized to the standard AXI3 Master. Therefore, the data path, control path, and bus path all use industry-standard interfaces, eliminating the need for any intermediate logic or format conversion circuits, thereby reducing design complexity and timing convergence difficulty.

[0036] Meanwhile, this invention designs an end-to-end standardized video data link for the subsystem, from DDR storage to the MIPI display terminal, without any additional format conversion circuitry. This hardware-level design ensures the integrity and real-time performance of data transmission, specifically comprising a four-layer link: (1) Configuration link: The CPU independently configures the internal registers of the DC8000 display controller, MIPI DSI host controller and MIPI D-PHY physical layer interface through the three APB Slave interfaces of the subsystem, so as to realize flexible settings of video resolution (up to 2K), pixel format RGB / YUV, number of MIPI transmission lanes, HS / LP mode switching, PLL clock parameters, etc. The configuration instructions directly reach the core logic of each IP. (2) Video data reading link: The DC8000 display controller reads the rendered video data from the DDR storage through the AXI3 Master interface (128bit), and after internal MMU storage management and DEC400 decompression, it completes format conversion and image processing, such as gamma correction, alpha mixing, scaling and filtering, to generate a standard DPI interface video data stream; (3) Video data transfer link: The DC8000 display controller sends video pixel data, line synchronization (HSYNC), field synchronization (VSYNC), and data enable (DE) signals to the MIPI DSI host controller through the standardized DPI interface. The MIPI DSI host controller completes data buffering and packet assembly through the internal FIFO and converts it into data packets of the MIPI DSI protocol. (4) Video data output link: The MIPI DSI host controller sends the packaged video data packets to the MIPI D-PHY physical layer interface. The MIPI D-PHY physical layer interface completes the conversion of parallel data to high-speed serial differential signal. The video signal is output to the MIPI display terminal through 4 data lanes and 1 clock lane, realizing stable transmission of 2K level medium and high-definition video.

[0037] To address the display anomalies caused by clock domain conflicts and the lack of coordination among independent clocks of individual modules in existing solutions, this invention designs a parameterizable multi-clock domain collaborative management mechanism. This mechanism receives a unified clock source from the SOC, allocates independent clock domains to the three IPs, and implements asynchronous and synchronous processing, thus resolving the clock asynchrony problem at its root. The specific design is as follows: (1) Unified clock source supply: The subsystem only receives 6 standard input clocks provided by the SOC, covering the DC core clock, AXI bus clock, APB bus clock, pixel clock, MIPI DPHY configuration clock, and MIPI DPHY PLL reference clock. All IP clocks are supplied by the SOC to avoid synchronization deviation caused by multiple clock sources. (2) Clock domain allocation on demand: Independent clock domains are allocated to the three IPs. In this embodiment, the DC core clock is 1250MHz, the AXI bus clock is 800MHz, the APB bus clock is 100MHz, the MIPI DPHY configuration clock is 25MHz, and the PLL reference clock is 25MHz. Each IP supports asynchronous processing to avoid logic conflicts caused by differences in clock frequency. In the existing solution, the three IPs were designed independently by different teams and then directly spliced ​​together, which leads to the following conflicts: The core logic of the DC8000 display controller may require high frequencies to complete complex image processing, but the DPI interface input clock of the MIPI DSI host controller is limited by the DSI protocol and PHY capabilities, typically only reaching a maximum of around 500MHz. If the DC8000 display controller outputs pixel data at 1250MHz, the MIPI DSI host controller simply cannot keep up; if the MIPI DSI host controller requires the DC8000 display controller to downclock to 500MHz, the DC8000 display controller cannot complete 2K@60Hz image processing. The MIPI D-PHY physical layer interface is very sensitive to clock jitter because it is a high-speed serial transmission, and the clock lane directly determines the data sampling window. However, as the core of digital processing, the DC8000 display controller's clock undergoes a large amount of combinational logic and gating, resulting in significantly increased jitter. If the clock of the DC8000 display controller is directly used for the MIPI D-PHY physical layer interface, the MIPI D-PHY physical layer interface will fail to lock due to excessive clock jitter, causing a surge in the bit error rate during high-speed transmission and resulting in screen distortion. To solve this problem, this invention resolves clock conflicts when three IPs are designed independently through a three-layer mechanism of unified supply, independent allocation, and asynchronous isolation. First, the SOC provides six standard input clocks, allocating optimal frequencies to each of the three IPs, avoiding frequency constraints caused by compromises between IPs. Second, each IP uses an independent clock domain, preventing the high jitter clock of the DC8000 display controller from propagating to the jitter-sensitive MIPI D-PHY physical layer interface. The PLL reference clock for the MIPI D-PHY physical layer interface is directly supplied with low jitter by the SOC, resolving clock quality conflicts. Finally, each IP supports asynchronous clock processing internally, and cross-clock domain data transmission is completed through a built-in FIFO or handshake. Meanwhile, the top-level subsystem uses a five-stage workflow to uniformly manage the startup order of each IP, ensuring that the MIPI DSI host controller enters high-speed mode only after the PHY is locked, and the DC8000 display controller starts sending data only after it is ready, eliminating startup order conflicts.

[0038] (3) Dynamic clock adaptation: The pixel clock pixelClk0 is dynamically matched according to the video output resolution and frame rate. For example, 2048×1080@60Hz corresponds to 148.5MHz, and 1920×1080@60Hz corresponds to 173.1MHz. The high-speed transmission byte clock of the D-PHY physical layer interface is adaptively configured according to the number of lanes and the transmission rate. The SOC achieves flexible switching of the clock frequency through a frequency division coefficient. Without modifying the DM subsystem RTL code or resynthesizing the FPGA bit stream, the DM subsystem can adapt to display terminals with different resolutions and frame rates simply by configuring the clock frequency division on the SOC side. The subsystem integrates clock synchronization logic to ensure the correctness of cross-clock domain data transmission. The clock synchronization logic refers to the fact that in this invention, the DC8000 display controller integrates asynchronous bridging between the AXI interface and the core logic, as well as asynchronous processing between the APB interface and the core logic. The MIPI controller internally achieves FIFO isolation and synchronization between the DPI pixel clock domain and the internal processing clock domain through a dual-port pixel memory. The reset signal completes asynchronous reset and synchronous release in its respective local clock domain. All these synchronization logics are built into each IP or integrated in the top layer of DM_WRAPPER, and are transparent to the SOC. The SOC only needs to provide 6 independent clocks, without the need to add additional cross-clock domain processing circuitry.

[0039] In existing solutions, the lack of a unified interface timing standard and cross-clock domain synchronization mechanism among the IPs leads to inconsistent understandings of clock relationships, data validity windows, and handshake protocols between the data sender and receiver. Therefore, existing solutions result in incorrect cross-clock domain transmission. This invention systematically solves the problem of incorrect cross-clock domain transmission through three aspects: "interface standardization, built-in synchronization mechanism, and unified timing constraints." First, the DC8000 display controller and the MIPI DSI host controller strictly adhere to the MIPI DPI-v2.0 standard interface, eliminating uncertainties at the interface protocol level. Second, the DC8000 display controller integrates an asynchronous bridge circuit between the AXI interface and the core logic, the MIPI DSI host controller integrates a dual-port pixel memory as an asynchronous FIFO, and each IP also integrates a reset synchronization release circuit, solidifying all cross-clock domain boundaries within the fully verified IPs. Finally, a unified SDC timing constraint file is written at the top level of the DM_WRAPPER, centrally declaring all asynchronous clock domain relationships to ensure that EDA tools correctly ignore processed asynchronous paths without overlooking potential risks. Therefore, the SOC only needs to provide 6 independent clocks, and the subsystem automatically completes the reliable transmission of all cross-clock domain data without the need for additional external synchronization circuits.

[0040] (4) Clock and synchronization signal binding: At the hardware level, the pixel clock of the DC is synchronized with the DPI interface clock of the MIPI controller to ensure that the video pixel data and the horizontal / vertical synchronization signal are in phase, thus avoiding problems such as screen tearing and ghosting. Synchronization binding means that at the hardware connection level, the pixel data and the horizontal / vertical synchronization signal are driven and sampled using the same clock edge to avoid time misalignment.

[0041] This invention employs a layered clock design, specifically dividing the clock system into four independent layers based on function: bus interface clock, DC core processing clock, pixel output clock, and MIPI physical transmission clock, rather than sharing a single clock source across all modules in traditional solutions. First, the clock domains are physically isolated, significantly reducing the timing convergence difficulties caused by mixed routing of high-frequency core clocks and bus clocks. Second, the independent layering of pixel clocks allows for dynamic configuration by the SOC based on display resolution, adapting to different display terminals without modifying the subsystem's internal logic. Third, cross-clock domain data transmission is achieved through built-in asynchronous FIFOs or handshake logic, avoiding display distortion caused by metastability at the architectural level. Finally, the layering supports independent gating of each clock domain; when MIPI enters low-power mode, the DC core clock and bus clock can be shut down, meeting the low-power requirements of embedded scenarios.

[0042] To address the data transmission errors caused by asynchronous resets and unstable system startup in existing solutions, this invention designs a modular and priority-based reset control mechanism to achieve independent reset control of each IP and coordinated global reset. The specific design is as follows: (1) Reset signal module: The reset signal is bound to the core logic / interface of each IP. resetPin_ corresponds to the DC core logic and pixel clock domain, ARESETn corresponds to the AXI3 Master interface, and PRESETn corresponds to the APB Slave interface (including MIPI controller / DPHY configuration interface) to realize the independent reset of the core logic and bus interface of each IP, so as to avoid the paralysis of the entire subsystem caused by a single reset signal failure; Existing solutions use a single global reset signal to reset all modules simultaneously. If an abnormal transaction on the AXI bus causes the bus interface to hang, different modules have different requirements for reset recovery time. When a system problem occurs, if there is only one global reset signal, it is impossible to determine whether the error is caused by a DC core logic error, an AXI interface error, or an APB configuration error. After the reset, all states are lost, and the problem cannot be reproduced or located. To solve this problem, this invention sets up independent resets by binding the reset signal to each module. Each reset signal is input independently, and the top-level DM_WRAPPER of the subsystem receives three independent reset signals from the SOC, instead of internally splitting one reset signal into three. Furthermore, each reset signal is synchronized to its corresponding local clock domain, so that each reset is released stably within its own clock domain without interference. When this invention uses three independent reset signals, for example, if the AXI bus interface is stuck, the SOC can be reset individually, the DC core logic continues to run, the image data being processed is not lost, and after the bus recovers, the DC core can immediately resume data transmission without reinitializing the entire display link. For example, if the CPU writes an invalid register value, the SOC can be reset independently. It only takes a few APB clock cycles to restore the configuration interface. The DC core and AXI bus are unaffected, and the display will not experience a long black screen.

[0043] (2) Reset priority rules: Establish a reset rule that prioritizes AXI interface reset and cancels it last. If the reset signals cannot be triggered / cancelled at the same time, the AXI3 Master interface must be reset first and canceled last, and the reset of DC8000 display controller and MIPI DSI host controller must be in the middle to avoid DDR data reading errors caused by bus interface reset abnormality. (3) Strict timing constraints on reset: The effective duration of the reset signal and the waiting time after cancellation are subject to uniform timing constraints. For example, the effective duration of the DC reset signal resetPin_ must exceed 32 minimum frequency clock cycles, and after cancellation, it must wait for 128 minimum frequency clock cycles before the function can be enabled. In addition, the corresponding clock must remain valid during the reset process. The reset timing of all IPs is uniformly controlled by the subsystem top-level DM_WRAPPER to ensure stable system startup and state recovery. (4) Reset signal synchronization processing: The top layer of the subsystem synchronizes the external reset signal provided by the SOC to the local clock domain of the three IPs respectively, and then sends it into each IP to avoid metastability caused by cross-clock domain reset and improve reset reliability.

[0044] In this invention, the reset signal is input from the SOC to the DM subsystem and takes effect immediately in an asynchronous manner, enabling each module to respond quickly to the reset request. However, when releasing, it is not released directly, but the reset signal is first synchronized to the local clocks of the DC core clock domain, AXI clock domain, and APB clock domain respectively, and then released on the stable edge of the clock.

[0045] Furthermore, this invention adopts a fully standardized interface design, compatible with the AMBA bus protocol and the MIPI industry standard, enabling seamless integration with SOCs and display terminals without the need for additional adapter circuits. It also provides comprehensive test and interrupt interfaces, balancing adaptability and scalability. The specific interface design is as follows: (1) Bus interface: One AXI3 Master interface enables high-speed data transmission between the subsystem and the SOC DDR (128-bit width), and three APB Slave interfaces (one APB3 and two APB2) enable the CPU to configure the registers of each IP. It is fully compatible with the AMBA bus protocol and can be directly connected to the SOC bus. (2) Peripheral transmission interface: The MIPI DPHY standard differential link interface is adopted, which includes 4 data differential pairs (datap0 / datan0~datap3 / datan3) and 1 clock differential pair (clkp / clkn), directly connected to the MIPI display terminal, and supports high-speed serial transmission and low-power mode switching; (3) Test interface: integrates standard DFT scan test interface, JTAG debugging interface and analog test bus (Atb) interface, supports mass production testing, online debugging and hardware fault location of subsystems, and is compatible with the overall test solution of SOC; (4) Interrupt interface: Exposes two standard interrupt signals, DC_INTR and MIPI_INTR, to the outside world, respectively to report the completion status of DC video processing and the abnormal status of MIPI transmission. It can be seamlessly connected with the interrupt management module of SOC to realize real-time feedback of the working status of each IP. (5) Clock / Reset Interface: Standardized clock input interface and reset input interface are adopted to support unified clock source supply and priority-based reset control of SOC. The interface signal definition is fully matched with the SOC end, reducing integration difficulty.

[0046] In another embodiment, the present invention also provides a MIPI-based FPGA display method, which first performs initialization: Reset the three IPs using the global reset signal; Configure the number of channels to use; Configure the enable bit corresponding to the error interrupt; Configure the DPI interface; Initialize the PHY: Power on and reset the PHY via the PHY_RSTZ register; configure the PLL phase-locked loop of the DPHY via the test interface; configure TxClkesc to 2-20MHz; reset the PHY again; confirm that the PHY's LANE is in the STOP state; Wake up the core and enter working state.

[0047] Includes the following steps: The configuration signals from the CPU are received through one APB3 Slave interface and two APB2 Slave interfaces, and the internal registers of the DC8000 display controller, MIPI DSI host controller, and MIPI D-PHY physical layer interface are configured independently respectively. The rendered video data is read from DDR storage via the AXI3 Master interface, and after being stored and managed by the internal MMU of the DC8000 display controller and decompressed by the DEC400, the format conversion and image processing are completed to generate a standard DPI interface video data stream. The standard DPI interface video data stream is sent to the MIPI DSI host controller through the standardized DPI interface. Inside the MIPI DSI host controller, the data is buffered and packetized through FIFO and converted into MIPI DSI protocol data packets. The MIPI DSI protocol data packets are sent to the MIPI D-PHY physical layer interface, converted into high-speed serial differential signals, and the video signals are output to the MIPI display terminal.

[0048] It also includes the following steps: It receives 6 standard input clocks provided by the SOC and allocates independent clock domains for the DC8000 display controller, MIPI DSI host controller, and MIPI D-PHY physical layer interface, and implements asynchronous and synchronous processing. At the hardware level, the pixel clock of the DC8000 display controller is synchronized and bound with the DPI interface clock of the MIPI DSI host controller.

[0049] It also includes the following steps: The reset signal is bound to the core logic / interface of the DC8000 display controller, MIPI DSI host controller, and MIPI D-PHY physical layer interface, enabling independent reset of the core logic and bus interface of the DC8000 display controller, MIPI DSI host controller, and MIPI D-PHY physical layer interface.

[0050] Reset control within the subsystem follows these sequence rules: The AXI3 Master interface of the DC8000 display controller enters the reset state first and exits the reset state last.

[0051] It also includes the following steps: unifying the effective duration of the reset signal and the waiting time after cancellation.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the scope of the technical solution of the present invention.

Claims

1. A MIPI-based FPGA display subsystem, characterized in that... The subsystem is a single-chip integrated hardware module, including a DC8000 display controller, a MIPI DSI host controller, and a MIPI D-PHY physical layer interface; The DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface are interconnected within the hardware module via a bus. The hardware module provides four bus interfaces, namely: One AXI3 Master interface is configured to enable the hardware module to access and interact with DDR storage data; wherein, the AXI3 Master interface is directly brought out from the AXI3 Master interface of the DC8000 display controller to the top level of the subsystem; One APB3 Slave interface is configured to independently configure the registers of the DC8000 display controller; wherein, the APB3 Slave interface is directly brought out from the APB3 Slave interface of the DC8000 display controller to the top level of the subsystem; The first APB2 Slave interface is configured to independently configure the registers of the MIPI DSI host controller; wherein, the first APB2 Slave interface is directly brought out from the APB2 Slave interface of the MIPI DSI host controller to the top level of the subsystem; The second APB2 Slave interface is configured to uniformly configure the top-level control signals of the MIPI DSI host controller and the MIPI D-PHY physical layer interface.

2. The MIPI-based FPGA display subsystem according to claim 1, characterized in that... The hardware module also provides 6 system clock interfaces, which are configured to receive 6 standard input clocks provided by the SOC, and allocate independent clock domains for the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface and realize asynchronous and synchronous processing.

3. The FPGA display subsystem based on MIPI according to claim 1, characterized in that... The hardware module also provides three reset interfaces, which are configured to receive three independent reset signals from the SOC, thereby enabling independent reset control of the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface.

4. The MIPI-based FPGA display subsystem according to claim 1, characterized in that... The aforementioned hardware module is also provided externally. The interrupt interface is configured to interface with the SOC's interrupt management module; The DPHY differential link interface is configured to directly connect to the MIPI display terminal; The test interface is configured to support mass production testing, online debugging, and hardware fault location for subsystems.

5. A MIPI-based FPGA display method, characterized in that: Applied to a MIPI-based FPGA display subsystem as described in any one of claims 1-4, the subsystem includes the following steps: The configuration signals from the CPU are received through one APB3 Slave interface and two APB2 Slave interfaces, and the internal registers of the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface are configured independently respectively. The rendered video data is read from DDR storage via the AXI3 Master interface, and after being stored and managed by the internal MMU of the DC8000 display controller and decompressed by the DEC400, the format conversion and image processing are completed to generate a standard DPI interface video data stream. The standard DPI interface video data stream is sent to the MIPI DSI host controller through the standardized DPI interface. Inside the MIPI DSI host controller, the data is buffered and packetized through FIFO and converted into MIPI DSI protocol data packets. The MIPI DSI protocol data packet is sent to the MIPI D-PHY physical layer interface, converted into a high-speed serial differential signal, and the video signal is output to the MIPI display terminal.

6. The MIPI-based FPGA display method according to claim 5, characterized in that: It also includes the following steps, It receives 6 standard input clocks provided by the SOC and allocates independent clock domains for the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface, and implements asynchronous and synchronous processing. At the hardware level, the pixel clock of the DC8000 display controller is synchronized and bound with the DPI interface clock of the MIPI DSI host controller.

7. The MIPI-based FPGA display method according to claim 5, characterized in that: It also includes the following steps, The reset signal is bound one by one to the core logic / interface of the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface, so as to realize the independent reset of the core logic and bus interface of the DC8000 display controller, the MIPI DSI host controller, and the MIPI D-PHY physical layer interface.

8. The MIPI-based FPGA display method according to claim 5, characterized in that: The reset control within the subsystem follows the following sequence rules: The AXI3 Master interface of the DC8000 display controller enters the reset state first and exits the reset state last.

9. The MIPI-based FPGA display method according to claim 5, characterized in that: It also includes the following steps: unifying the effective duration of the reset signal and the waiting time after cancellation.

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