Suspended die-to-die interconnect bridge for interposer package

Abstract

Bridge die interposer packaging and related apparatus, systems, and techniques are discussed. The interposer packaging includes a bridge die having a wiring structure to interconnect a plurality of integrated circuit (IC) dies of a package. Power is provided to the IC dies through a mesh power metallization and a mesh ground metallization that extend from outside a perimeter of the bridge die inward of the perimeter and over the wiring structure. The bridge die can be absent through-silicon vias (TSVs) and can be suspended such that the bridge die is exposed at a bottom of the package.

Description

Background Technology

[0001] Higher performance, lower cost, increased miniaturization, greater packaging density, and increased product flexibility are ongoing goals for the electronics industry in integrated circuit (IC) devices. IC packaging is a stage in semiconductor or IC device manufacturing in which one or more monolithically manufactured IC dies are assembled into a package that protects the IC die from physical damage and communicatively connects the IC die to other packaged IC dies and / or scaled host components, such as a package substrate or printed circuit board.

[0002] Multiple IC dies can, for example, be co-assembled into a multi-die package. Some package architectures include IC dies coupled to a passive bridge die, the passive bridge die having a wiring layer and through-silicon vias (TSVs) extending through the bridge die. For example, the high-density wiring capabilities of silicon wafer technology can be utilized to provide die-to-die interconnects through passive bridge dies in a bridge die interposer package. In such an architecture, power to the top IC die is provided by TSVs extending through the bridge die and vertically connecting the bottom-side package-level interconnects of the interposer to the top-side interconnects of the top IC die.

[0003] However, such an architecture presents various challenges, including cost, reliability, and the process complexity associated with manufacturing and embedding bridge dies with TSVs. It is based on these and other considerations that this improvement was proposed. This improvement is likely to become crucial as the expectation of deploying high-performance IC packages across a wider range of devices and systems becomes more widespread. Attached Figure Description

[0004] The materials described herein are illustrated in the accompanying drawings by way of example, not limitation. For simplicity and clarity, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, reference numerals are repeated in the drawings where deemed appropriate to indicate corresponding or similar elements. In the drawings: Figure 1 This is a cross-sectional side view of a portion of the intermediate layer structure of an example suspension bridge core; Figure 2 yes Figure 1 A cross-sectional side view of the portion of the suspension bridge die interlayer structure is shown, illustrating the power, ground, and signal wiring within the suspension bridge die interlayer structure. Figure 3 yes Figure 1 An illustration of a cross-sectional side view of the portion of the suspension bridge core interlayer structure, used to show an exemplary cross-sectional top view of the suspension bridge core interlayer structure; Figure 4 yes Figure 1A top-view diagram of a portion of the grid metallization layer for power wiring in the intermediate layer structure of a suspension core. Figure 5 yes Figure 1 A top-view diagram of a portion of the mesh metallization layer of the grounding wiring in the intermediate layer structure of the suspension core; Figure 6 yes Figure 1 A cross-sectional side view of the entire suspension bridge core interlayer structure is shown, which serves to illustrate an exemplary top view of the suspension bridge core interlayer structure. Figure 7 This is a top view illustration of an example layout of a suspended bridge die interposer structure that includes multiple IC dies covering multiple bridge dies; Figure 8 This is a flowchart illustrating an example method for manufacturing and assembling the interlayer structure of a suspension bridge core; Figure 9 , 10 11, 12, 13, 14, 15, and 16 are when practice Figure 8 The method to form Figure 1 A cross-sectional side view of the intermediate layer structure of the suspension bridge core. Figure 17 It is when practice Figure 8 The method is illustrated by a cross-sectional side view of the encapsulation structure when assembling an encapsulation assembly with a suspension bridge die interlayer. Figure 18 An exemplary system employing an IC assembly including a suspended bridge die interposer structure is shown; and Figure 19 This is a block diagram of a computing device arranged according to at least some embodiments of the present disclosure. Detailed Implementation

[0005] One or more embodiments or implementations will now be described with reference to the accompanying drawings. While specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of this specification. It will be apparent to those skilled in the art that the techniques and / or arrangements described herein can also be used in various other systems and applications different from those described herein.

[0006] The following detailed description refers to the accompanying drawings, which form a part of this specification, wherein parts designated by the same reference numerals denote corresponding or similar elements throughout the specification. It should be understood that, for simplicity and / or clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, it should be understood that other embodiments may be utilized, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references such as up, down, top, bottom, above, below, etc., may be used to aid in the discussion of the drawings and embodiments and are not intended to limit the application of the claimed subject matter. Therefore, the following detailed description should not be construed as limiting in meaning or as defining the scope of the claimed subject matter as defined by the appended claims and their equivalents.

[0007] Numerous details are set forth in the following description. However, it will be apparent to those skilled in the art that the invention can be practiced without these specific details. In some instances, well-known methods and apparatuses are shown in block diagram form rather than in detail to avoid obscuring the invention. Throughout this specification, references to “embodiment” or “one embodiment” mean that a particular feature, structure, function, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment” or “in one embodiment” appearing throughout this specification do not necessarily refer to the same embodiment of the invention. Furthermore, in one or more embodiments, the particular feature, structure, function, or characteristic can be combined in any suitable manner. For example, a first embodiment can be combined with a second embodiment when the particular features, structures, functions, or characteristics associated with two embodiments are not mutually exclusive.

[0008] As used in the specification and appended claims of this invention, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. In this document, the term “substantial” indicates not less than 50% of a particular material or component, the term “substantially pure” indicates not less than 99% of a particular material or component, and the term “pure” indicates not less than 99.9% of a particular material or component. Unless otherwise stated, such material percentages are based on atomic percentages. In this document, unless otherwise stated, the terms concentration and material percentage are used interchangeably and also indicate atomic percentages.

[0009] The terms “coupling” and “connection” and their derivatives may be used herein to describe structural relationships between components. It should be understood that these terms are not intended to be synonyms. Rather, in certain embodiments, “connection” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupling” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., in a causal relationship).

[0010] As used herein, the terms “above,” “below,” “between,” “on,” etc., refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with said other layer or may have one or more intermediate layers. Furthermore, a layer disposed between two layers may be in direct contact with said two layers or may have one or more intermediate layers. Conversely, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, a feature disposed between two features may be in direct contact with an adjacent feature or may have one or more intermediate features. The term “immediately adjacent” indicates that such features are in contact in a direction. Furthermore, the terms “substantially,” “close to,” “approximately,” “near,” and “about” generally refer to within + / - 10% of the target value. The term “layer” as used herein may include a single material or multiple materials. As used throughout this specification and claims, a list of items connected by the terms “at least one of…” or “one or more of…” may represent any combination of the listed items. For example, the phrase "at least one of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0011] This document describes devices, systems, and methods relating to interconnect bridge packages, the bridge packages including bridge dies with wiring structures for interconnecting multiple integrated circuit (IC) dies within the package. Power is supplied to the IC dies via grid power metallization and grid ground metallization, which extend from the outside of the perimeter of the bridge die into the perimeter and above the wiring structure. The bridge die may be without through-silicon vias (TSVs) and may be suspended, thus exposing it at the bottom of the package.

[0012] As described above, current packaging architectures may include multiple IC dies coupled to a passive bridge die, the passive bridge die having a wiring layer adjacent to the IC die and a through-thru TSV extending through the bridge die to provide power to the IC die. For example, power and ground can be provided vertically from package-level interconnects below the bridge die to the IC die above through the bridge die's TSV. However, such architectures require fabricating the TSV within the bridge die and assembly processes to embed the bridge die into the package. These processes are complex, expensive, and prone to losses and other problems.

[0013] In some embodiments, the package architecture includes a bridge die with a wiring structure for interconnecting two or more IC dies packaged on a monolithic substrate of the bridge die. As used herein, the term "monolithic" means a component made of a single material or compound. Notably, passive bridge dies do not have a TSV. The wiring structure on the monolithic substrate is used to conduct signals between IC dies in a multi-IC die package. The bridge die has and defines a perimeter to which the bridge die interconnect extends at least a portion of the IC die. A die-level interconnect is used to transfer power to the IC dies within the perimeter of the bridge die using a power metallization grid and a ground metallization grid. Notably, the die-level interconnect extends vertically from the bottom of the IC die within the perimeter to contact the metallization grid. Each of the power metallization grid and the ground metallization grid extends from the outside of the perimeter into the perimeter to provide power and ground. Each of the power metallization grid and the ground metallization grid is connected to a package-level interconnect outside the perimeter of the bridge die and fed to the die-level interconnect within the perimeter via via structures that contact the associated metallization. Other via structures extend through the metallization and are surrounded by a dielectric material that isolates them from the metallization. As used herein, the terms metallization or continuous metallization are used substantially interchangeably and refer to a continuous metal layer interrupted by vias that are not coupled to the metallization and extend through the metallization surrounded by an insulating dielectric. The metallization may include vias (e.g., vias of any shape) to support dielectric degassing and / or manage the fabrication metal layer density to control metal plating uniformity or warpage due to varying thermal expansion of materials used, for example, in the interlayer or redistribution structure. As used herein, the term power generally means either a power source or a ground source for a power network. The term power source indicates the supply voltage of the power network, and the term ground source indicates the ground source of the power network. Therefore, the term power is used as a general term encompassing either power source or ground source. The terms signal or I / O, and similar terms, indicate input / output, data signaling, etc.

[0014] For example, the interposer package structure discussed in this paper provides power to the die-to-die physical interface without a TSV in the interposer packaged bridge die. It is worth noting that current bridge die interposer packages may require two redistribution layers for I / O routing for the top IC die-to-package level interconnect (e.g., C4 bump), where the routing density requirement in the redistribution layers is relatively low (e.g., 5µm lines / 5µm space), allowing for a relatively thick redistribution layer metallization, for example, approximately 4µm. Currently, within the perimeter of the bridge die region, the redistribution layer is used for stacked vias from the bridge die to the top die, where the stacked vias are used for signals or power. The embodiments in this paper dedicate the stacked vias to signal transmission and use the area between these stacked vias to construct a power grid (e.g., one layer for power (VDD) and one layer for ground (VSS)). These relatively thick power grid layers are powered by package level interconnects (e.g., C4 bumps) laterally adjacent to the bridge die edge and outside the bridge die perimeter. The embodiments discussed have various advantages, including, for example, process simplification, increased yield and reduced cost due to the elimination of the need to fabricate TSVs in the bridge die and the elimination of the need to embed the bridge die.

[0015] Figure 1 This is an illustration of a portion of a cross-sectional side view of an example suspended bridge die interposer structure 100 arranged according to at least some embodiments of the present disclosure. As shown, a redistribution structure 104 (or redistribution layer) is located between active IC dies 124, 126 and bridge die 101, and includes a plurality of metallization layers 105, 106, 107, 108, 109 embedded within a dielectric layer 111. Figure 1 In this diagram, for clarity, dielectric layer 111 is shown as a single dielectric. However, it should be understood that dielectric layer 111 may be multiple discrete layers constructed together with metallization layers 105, 106, 107, 108, and 109 in the z-axis.

[0016] Each of the metallization layers 105, 106, 107, 108, and 109 is fabricated to a specific thickness and has a specific pattern or architecture. In the context of the suspension bridge die interposer structure 100, metallization layers 105, 107, and 109 are via layers, typically including vias (e.g., circular vias, rectangular vias, or vias of other shapes) extending through the corresponding dielectric layer 111, and metallization layers 106 and 108 respectively including grid metallization layers 112 and 115 embedded in the dielectric layer 111. For example, metallization layers 106 and 108 may include grid metallization layers 112 and 115 and other patterns, while metallization layers 105, 107, and 109 typically include via structures for interconnecting metallization layers 106 and 108. In some embodiments, the redistribution structure 104 of the suspension bridge die interposer structure 100 may advantageously be fabricated on a glass carrier for improved flatness and / or thickness control, as discussed below.

[0017] As shown in the figure, the suspended bridge die interposer structure 100 includes any number of active IC dies, such as IC dies 124 and 126 above the redistribution structure 104. In this document, the term "active IC die" refers to an integrated device having an active integrated device structure such as a transistor. The term "passive die" refers to a structure that can provide wiring but does not have active devices, such as the passive bridge die 101. As shown in the figure, active IC dies 124 and 126 respectively include wiring structures 125 and 127, which can be die-level metallization layers that interconnect the devices of IC dies 124 and 126, provide power to the devices of active IC dies 124 and 126, and allow the devices of IC dies 124 and 126 to communicate with each other and with external devices (i.e., devices that the suspended bridge die interposer structure 100 will couple to) using die-level interconnects 128, 129, and 130 and package-level interconnects 123. As discussed further below, die-level interconnect 128 can be a power interconnect, die-level interconnect 129 can be a ground interconnect, and die-level interconnect 130 can be a signal interconnect. In some embodiments, IC dies 124 and 126 each include a device layer (e.g., a transistor layer formed within the substrate of IC dies 124 and 126) immediately adjacent to wiring structures 125 and 127. Although shown with respect to single-level IC dies 124 and 126, each of IC dies 124 and 126 can be a die stack consisting of multiple IC dies or can be replaced by a die stack consisting of multiple IC dies. For example, such an architecture can be deployed in high-bandwidth memory (HBM) applications. As is known in the art, wiring structures 125 and 127 can include any suitable structure, such as any number of metallized line layers interconnected via via layers. As shown in the figure, the bottom filler material 131 can be embedded under the IC dies 124 and 126 to form die-level interconnects 128, 129 and 130, and can provide molding material 144 between the IC dies 124 and 126.

[0018] Bridge die 101 is located below a portion of redistribution structure 104, wherein redistribution structure 104 is vertically positioned between at least a portion of bridge die 101 and portions of IC dies 124, 126. Bridge die 101 is coupled to redistribution structure 104 using bridge interconnect 145. As shown, bridge interconnect 145 and die-level interconnects 128, 129, 130 may include one or more metallization features for interconnection, such as die-side pad 141, redistribution layer-side pad 142, and intermediate solder feature 143 (e.g., flip-chip connection). However, any bonding structure, such as hybrid bonding features, may be used. Under the bridge die, underfill material 103 may be embedded in bridge interconnect 145.

[0019] Bridge die 101 includes a wiring structure 102 on a monolithic substrate 133. The wiring structure 102 includes a die-level metallization layer (e.g., fabricated on a wafer and diced to form bridge die 101) that provides interconnects between IC dies 124, 126 and optional communication with external devices. As discussed further below, bridge interconnect 145 is a signal interconnect and no power interconnect is present because power and ground are provided using mesh metallization layers 112, 115. Monolithic substrate 133 does not contain any through-thru TSVs or any dedicated device layers. Monolithic substrate 133 may include any suitable material. In some embodiments, monolithic substrate 133 includes a Group IV material (e.g., silicon). In some embodiments, monolithic substrate 133 includes a substantially single-crystal material. In some embodiments, monolithic substrate 133 is a non-single-crystal material such as glass. In some embodiments, bridge die 101 is primarily silicon and oxygen, for example, at least 23% silicon and at least 26% oxygen by weight (i.e., wt%). The bridge core 101 may also include one or more additives, such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments, the bridge core 101 is rectangular in shape in a plan view. However, other shapes may be used. The bridge core 101 has and defines a perimeter 132 such that the perimeter 132 is located at the outer edge of the bridge core 101. The term perimeter is used in its common sense to indicate the outer boundary of the bridge core 101, which is typically a geometric shape such as a rectangle, and the perimeter extends vertically such that an object or component may cross the perimeter above or below the bridge core 101.

[0020] As shown in the figure, via structures 118 and 119 extend perpendicularly (i.e., along the z-axis) from bridge die 101 to one of IC dies 124 and 126. It is noteworthy that via structures 118 and 119 are not coupled to other portions of metallization layers 106 and 108, and therefore are not coupled to mesh metallization layers 112 and 115. As discussed below, via structures 118 and 119 can be used for signal transmission. For example, signal transmission can be established between IC dies 124 and 126 using die-level interconnect 130, via structures 118 and 119, bridge interconnect 145, and wiring structure 102.

[0021] Mesh metallization layers 112 and 115 provide power to IC dies 124 and 126, such that mesh metallization layer 112 provides either power or ground, and mesh metallization layer 115 provides the other. In the following, mesh metallization layers 112 and 115 are shown as mesh metallization layer 112 providing power and mesh metallization layer 115 providing ground, but they are interchangeable. It is noteworthy that mesh metallization layer 112 (via metallization layers 106, 107, 108, and 109) is coupled to a metallization structure including metal pillars 113 and metal interconnect features 114. Metal pillars 113 can be characterized as vertical metal interconnects or pillars, and can be or include copper. Metal interconnect features 114 can be characterized as bumps or balls, and can be solder material. Although shown as having metal pillars 113 and metal interconnect features 114, the metallization structure of the package-level interconnect 123 can include any suitable interconnect.

[0022] Similarly, the mesh metallization layer 115 (via metallization layer 109) is coupled to a metallization structure including metal pillars 116 and metal interconnect features 117, and other die-level interconnects 130 (via metallization layers 105, 106, 107, 108, 109) are coupled to a metallization structure including metal pillars 121 and metal interconnect features 122. Therefore, some of the package-level interconnects 123 provide signal transmission, while others provide power and ground transmission.

[0023] In the context of the suspended bridge die interposer structure 100, the power and ground of the package-level interconnect 123 are outside the perimeter 132 of the bridge die 101, and the metallization structure of the package-level interconnect 123 is laterally adjacent to the wiring structure 102 and the monolithic substrate 133. In the example shown, metal pillars 113, 116, and 121 are laterally adjacent to the wiring structure 102 (i.e., all have portions in the same xy plane), metal pillars 113, 116, and 121 are laterally adjacent to a portion of the monolithic substrate 133, and metal interconnect features 114, 117, and 122 are laterally adjacent to another portion of the monolithic substrate 133. However, any suitable structure can be implemented such that the package-level interconnect 123 is laterally adjacent to both the wiring structure 102 and the monolithic substrate 133.

[0024] Furthermore, since power (power supply and ground) is transported upwards from the package-level interconnect 123 to the redistribution structure 104, laterally across the mesh metallization layers 112, 115, and then upwards to the IC dies 124, 126, the package-level interconnect 123 is not deployed below the bridge die 101. This allows the TSV to be omitted from the bridge die 101 and eliminates the need to embed the bridge die 101 in molding material or other dielectric material. Therefore, the bridge die 101 can be defined as a suspended bridge die because it is not fully embedded in or surrounded by other materials or components of the suspended bridge die interposer structure 100. Additionally, no wiring or interconnect structures are provided on the surface of the monolithic substrate 133 opposite to the wiring structure 102.

[0025] As shown in the figure, each of the mesh metallization layers 112, 115 and the redistribution structure 104 are above the bridge die 101 and extend through the perimeter 132 of the bridge die 101. See below for details. Figure 4 and Figure 5 As further shown, each of the mesh metallization layers 112, 115 is a continuous mesh metallization portion or includes a continuous mesh metallization portion, which is a substantially planar metal structure interrupted by vias extending vertically through the metal structure. For example, via structures 118, 119 (which are signal vias) extend vertically through each of the mesh metallization layers 112, 115 within the perimeter 132, wherein each of the via structures 118, 119 is surrounded by a dielectric layer 111, which contacts the via structures 118, 119 and the mesh metallization layers 112, 115. Also as shown, metallization layers 106, 108 can be further used for wiring 120 located outside the mesh metallization layers 112, 115, such that metallization layers 106, 108 can include the mesh metallization layers 112, 115 and other metallization portions of the suspension bridge die interposer structure 100.

[0026] Figure 2 This is an illustration of a cross-sectional side view of a portion of a suspension bridge die interlayer structure 100 arranged according to at least some embodiments of the present disclosure, showing the power, ground, and signal wiring 200 within the suspension bridge die interlayer structure 100. Figure 2 In the illustration, exemplary power wiring 201 is shown with crossshading, exemplary ground wiring 202 is shown with dark fill, and exemplary signal wiring 203 is shown with white fill. For example, Figure 2 and Figure 1 The difference is that it shows an exemplary power, ground, and signal wiring 200.

[0027] As shown with respect to power wiring 201, in some embodiments, power is supplied to IC dies 124, 126 via wiring that leads out power through metal interconnect features 114 and metal pillars 113 (e.g., from an external main structure), where metal interconnect features 114 and metal pillars 113 are one of any number of package-level interconnects 123 metallized structures. Power from power wiring 201 is then transmitted through metallization layer 109 (e.g., vias of metallization layer 109), metallization layer 108 (e.g., traces or planes of metallization layer 108), and metallization layer 107 (e.g., vias of metallization layer 107) to mesh metallization layer 112. As discussed, mesh metallization layer 112 extends laterally along metallization layer 106 from the outside of perimeter 132 into perimeter 132. That is, mesh metallization layer 112 carries power from the outside of perimeter 132 into perimeter 132 to deliver it to IC dies 124, 126. As shown in the figure, the power routing 201 and the via structure 204 of the metallization layer 105 contact the mesh metallization layer 112 within the perimeter 132 and deliver power to the die-level interconnect 128, which can be characterized as a power interconnect for delivery to the IC die 126. Similar routing within the metallization layer 105 and the die-level interconnect 128 can deliver power to the IC die 124 within the perimeter 132.

[0028] Ground connections are provided to IC dies 124 and 126 via ground wiring 202. Ground wiring 202 includes metal interconnect features 117 and metal pillars 116, which are metallization structures of package-level interconnects 123. Ground wiring 202 then extends through metallization layer 109 (e.g., vias of metallization layer 109) to mesh metallization layer 115. Mesh metallization layer 115 extends laterally along metallization layer 108 from the outside of perimeter 132 to within perimeter 132, such that mesh metallization layer 115 provides ground connections for IC dies 124 and 126 from the outside to within perimeter 132. As shown, the via structure 205 of ground wiring 202 and includes metallization portions from metallization layers 105, 106, and 107 contact the mesh metallization layer 115 within perimeter 132 and provide ground for die-level interconnects 129, which can be characterized as ground interconnects. Similar to power routing 201, similar routing within metallization layers 105, 106, 107 and die-level interconnects 129 can provide grounding for IC die 124 within perimeter 132.

[0029] Finally, various signal traces 203 are provided by metallization layers 105, 106, 107, 108, and 109. For example, via structures 118 and 119 extending vertically from bridge die 101 to one of IC dies 124 and 126 provide signal traces 203 originating from trace structure 102 between bridge interconnect 145 and die-level interconnect 130, which can be characterized as signal interconnects. Furthermore, signal traces 203 can be disposed between die-level interconnect 130 and metal pillars 121 and metal interconnect features 122, which are metallization structures among any number of package-level interconnects 123. Such signal traces 203 extend through metallization layers 105, 106, 107, 108, and 109. In some embodiments, one or more of such signal traces 203 are entirely outside the perimeter 132.

[0030] In the illustrated embodiment, the grid metallization layer 112 is a power grid metallization portion above the grid metallization layer 115, which is a ground grid metallization portion. In other embodiments, the ground grid metallization portion is located above the power grid metallization portion. Furthermore, in the illustrated embodiment, only two basic planar metallization layers 108 and 109 are provided in the redistribution structure 104. In other embodiments, additional planar metallization layers are deployed. In some embodiments, one or more planar metallization layers are located between the grid metallization layers 112 and 115 in the redistribution structure 104. In some embodiments, one or more planar metallization layers are above or below the grid metallization layers 112 and 115 in the redistribution structure 104.

[0031] Figure 3 This is an illustration of a portion of a suspension bridge core interlayer structure 100 arranged according to at least some embodiments of the present disclosure, showing an exemplary cross-sectional top view of the suspension bridge core interlayer structure 100 taken at the mesh metallization layers 112, 115. Figure 4-4 'and 5-5'. exist Figures 3 to 5 In order to be clear, exemplary power wiring 201, exemplary ground wiring 202 and exemplary signal wiring 203 are also shown with cross-shading, dark fill and white fill, respectively. Sections 4-4' and 5-5' taken at the mesh metallization layers 112 and 115 provide lateral sections to show the continuous mesh of the mesh metallization layers 112 and 115 and the interconnection of the mesh metallization layers 112 and 115 into the suspension bridge die interposer structure 100.

[0032] Figure 4 This is an illustration of a cross-sectional top view of a portion 400 of the mesh metallization layer 112 of the power wiring 201 in the suspension bridge core interlayer structure 100, arranged according to at least some embodiments of the present disclosure. Figure 4 As shown, in some portions, the mesh metallization layer 112 may be substantially continuous, except for through-via regions 401 that occur where metallization features will pass through the mesh metallization layer 112 (i.e., metallization layer 106) without contacting the mesh metallization layer 112. In some embodiments, the mesh metallization layer 112 may also include a number of holes (e.g., holes of any shape) to support dielectric degassing and / or manage the fabrication metal layer density due to variations in metal plating uniformity or warpage caused by different thermal expansion of materials used, for example, in the interlayer or redistribution structure. Furthermore, the redistribution structure 104 may include more than one power and / or ground mesh metallization portion within the metallization layers 106, 108. For example, the suspension bridge core interlayer structure 100 may require more than one power mesh network. In such a context, metallization layers 106 and / or metallization layers 108 may include more than one power or ground mesh metallization network. As shown in the figure, at each through-hole region 401, the associated via structure extends through the mesh metallization layer 112 and is isolated from the mesh metallization layer 112 by a portion of the dielectric layer 111 (e.g., dielectric material).

[0033] For example, via structure 119 carrying signal wiring 203 (reference) Figure 3 The via structure 205 extends through the mesh metallization layer 112 and is isolated from the mesh metallization layer 112 by the dielectric layer 111. Similarly, a via structure 205 (see reference) is provided for the ground wiring 203. Figure 3 The via structure 204 extends through the mesh metallization layer 112 and is isolated from the mesh metallization layer 112 by the dielectric layer 111. Furthermore, the via structure 204 has the same wiring type as the mesh metallization layer 112 (see reference). Figure 3 In this example, power routing 201 is provided, falling on the mesh metallization layer 112, as shown. Figure 4 The outline is shown in the diagram. For example, the metallization structure of the metallization layer 105 of the via structure 204 falls on the mesh metallization layer 112.

[0034] For example Figure 4As shown, the mesh metallization layer 112 is a continuous mesh metallization section, which is a substantially planar metal structure interrupted by vias or via regions 401 that extend vertically through the mesh metallization layer 112 to interrupt the planar metal structure. The via structures 119, 205 can have any suitable cross-sectional width (e.g., diameter) in the xy plane, for example, a cross-sectional width in the range of approximately 5µm to 25µm. The via structures 119, 205 can have any suitable spacing, for example, a hexagonal spacing not greater than 50µm. The mesh metallization layer 112 can have any suitable thickness (in the z-axis), for example, a thickness of approximately 4µm, which provides effective power to the IC dies 124, 126.

[0035] Figure 5 This is an illustration of a cross-sectional top view of a portion 500 of the mesh metallization layer 115 of the grounding wiring 202 in the suspension bridge core interlayer structure 100, arranged according to at least some embodiments of the present disclosure. Figure 5 As shown, the mesh metallization layer 115 is also continuous outside the through-via region 501, which again occurs where the metallization feature will pass through the mesh metallization layer 115 (i.e., metallization layer 108) without contacting the mesh metallization layer 115. For example, at each through-via region 501, the associated via structure extends through the mesh metallization layer 115 and is isolated from the mesh metallization layer 115 by a portion of the dielectric material of the dielectric layer 111.

[0036] For example, via structure 119 carrying signal wiring 203 (reference) Figure 3 The via also extends through the mesh metallization layer 115 and is isolated from the mesh metallization layer 115 by the dielectric layer 111. In the context of this embodiment, no power via extends through the mesh metallization layer 115; however, as discussed, the power / ground orientation of the mesh metallization layers 112 and 115 can be reversed. In this case, the power via extends through the mesh metallization layer 115 and is isolated from the mesh metallization layer 115 by the dielectric material of the dielectric layer 111. A via structure 205 having the same wiring type as the mesh metallization layer 115 (see reference 205) is also present. Figure 3 In this example, grounding wiring 202 is provided and falls on the mesh metallization layer 115, as shown. Figure 5 The outline is shown in the diagram. For example, the metallization structure of the metallization layer 107 of the via structure 205 falls on the mesh metallization layer 115.

[0037] Similar to mesh metallization layer 112, mesh metallization layer 115 is a continuous mesh metallization section, which is a substantially planar metal structure interrupted by vias or via regions 401 extending vertically through mesh metallization layer 115 to interrupt the planar metal structure. Via structures 119 can have any suitable cross-sectional width and spacing as described above. Mesh metallization layer 115 can have any suitable thickness (in the z-axis), for example, approximately 4 µm. Figure 4 and Figure 5 In the context of this, via structures 119, 204, and 205 have a circular cross-sectional shape, and the dielectric material of the surrounding dielectric layer 111 has the same circular cross-sectional shape. However, via structures 119, 204, and 205 and the dielectric material of the surrounding dielectric layer 111 can have any cross-sectional shape, such as a square, hexagon, or octagon. As shown, the surrounding dielectric material can have a shape conforming to the shape of via structures 119, 204, and 205. The difference between the cross-sectional widths (e.g., depending on the diameter or other width of the shape) of via structures 119, 204, and 205 and the surrounding dielectric layer 111 can be any suitable distance, such as a distance of approximately 5 µm, a distance in the range of 2 µm to 7 µm, a distance in the range of 1 µm to 2 µm, etc. In some embodiments, via structures 119, 204, and 205 and / or the surrounding dielectric material have different cross-sectional shapes, such as oval, square, or rectangular.

[0038] Figure 6 This is an illustration of a cross-sectional side view of an overall 600 of a suspension bridge die interposer structure 100 arranged according to at least some embodiments of the present disclosure, to show an exemplary top view of the suspension bridge die interposer structure 100 taken above IC dies 124, 126. Figure 7-7 '.exist Figure 6 In the context of this, each feature is not labeled, and exemplary wiring coloring is not shown for clarity. Top view Figure 7-7 A view is provided illustrating the multi-core context and lateral power transfer of the suspension bridge core interlayer structure 100.

[0039] Figure 7This is an illustration of a top view of an example layout 700 of a suspended bridge die interposer structure 100 comprising a plurality of IC dies covering a plurality of bridge dies 101, arranged according to at least some embodiments of the present disclosure. The suspended bridge die interposer structure 100 may include any number of IC dies 124, 126, 701, 702, 703, 704 in any suitable layer. In the context of layout 700, each of the IC dies 124, 126, 701, 702, 703, 704 has a portion within a perimeter 132 and a portion outside the perimeter 132 of each of two or three bridge dies 101. However, other layouts are also possible. As shown, the redistribution structure 104 (and each grid metallization layer 112, 115) extends from the outside 705 to the inside 706 of the perimeter 132 of each bridge die 101 to provide power to those portions of IC dies 124, 126, 701, 702, 703, 704 within the perimeter 132 of one or more bridge dies 101 and to provide ground from the outside 705 to the inside 706 of the perimeter 132, as described above.

[0040] Therefore, the suspension bridge die interposer structure 100 includes any number of bridge dies 101, each bridge die 101 having a monolithic substrate 133 and wiring structures 102 on the surface of the monolithic substrate 133. The suspension bridge die interposer structure 100 also includes a redistribution structure 104 above each bridge die 101 (i.e., inside 706 of the perimeter 132) and extending beyond the perimeter 132 of the bridge die 101 (i.e., outside 705 of the perimeter 132). The redistribution structure 104 has metallization layers 106, 108, which include continuous grid metallization layers 112, 115 to provide power and ground, as described above. Any number of via structures 118, 119 provide signal routing and extend through the metallization layers 106, 108 within the perimeter 132, such that via structures 118, 119 are all surrounded by a dielectric layer 111, which contacts the via structures 118, 119 and the mesh metallization layers 112, 115. One, some, or all of the bridge die 101 lacks any TSVs, and the routing structure 102 interconnects the via structures 118, 119 within the perimeter 132 to provide signal transmission.

[0041] Figure 8This is a flowchart illustrating an example method 800 for manufacturing and assembling a suspension bridge die interposer structure arranged according to at least some embodiments of the present disclosure. For example, method 800 can be implemented to manufacture any suspension bridge die interposer structure, encapsulation structure, or component discussed herein. In the illustrated embodiment, method 800 includes one or more operations as shown in operations 801-807. However, embodiments herein may include additional operations, omit certain operations, or perform the operations in a different order than provided. Figure 9-17 The structure and components of practical method 800 are shown.

[0042] Figure 9 , 10 11, 12, 13, 14, 15 and 16 are illustrations of cross-sectional side views of a suspension bridge core interlayer structure when practicing method 800 to form a suspension bridge core interlayer structure 100 arranged according to at least some embodiments of the present disclosure. Figure 17 This is an illustration of a cross-sectional side view of a package structure when practice method 800 is used to assemble a package assembly having a suspension bridge die interlayer arranged according to at least some embodiments of the present disclosure.

[0043] Method 800 begins with operation 801, in which a workpiece, such as a fabricated and diced IC die, a fabricated and diced bridge die, or a glass carrier, is received. For example, the workpiece may be fabricated upstream of method 800. Notably, the IC die will be assembled into a package structure and includes wiring structures for coupling to the redistributed structure. Similarly, the bridge die is fabricated with wiring structures coupled to the redistributed structure, but the bridge die does not have a TSV, and the surface opposite the surface with the wiring structure may be free of any wiring structures, interconnects, etc. The glass carrier may be a large panel format, a wafer format, etc.

[0044] Processing continues at operation 802, where an electrical redistribution structure is built or formed on one side of the glass carrier received at operation 801 in preparation for assembly with bridge dies and multiple IC dies. The fabricated redistribution structure (which can also be characterized as an electrical wiring structure) can have any of the characteristics discussed with respect to redistribution structure 104. The redistribution structure includes multilayer metallization features embedded within any suitable dielectric material. The redistribution structure formed at operation 802 interconnects the IC dies, bridge dies, and transfers power from the periphery of the bridge dies to the IC dies. Therefore, the spacing of the metallization features and the thickness of the metallization layers in the wiring structure are advantageously selected for interconnect density and power transfer.

[0045] Figure 9This is an illustration of a cross-sectional side view of a suspension bridge die interposer structure 900 including a carrier 901, such as a glass carrier, and a redistribution structure 104 constructed on the carrier 901. The carrier 901 can be any suitable material, such as any format of glass, such as large panel format or wafer format, and has any thickness to support subsequent manufacturing operations. The redistribution structure 104 can have any of the features, properties, etc., discussed above. The redistribution structure 104 can be constructed on the carrier 901 using any suitable technique. In some embodiments, a first layer of dielectric layer 111 is applied to the carrier 901 using any suitable coating technique (e.g., lamination, slot coating, spin coating, etc.). The first layer can then be patterned to form openings corresponding to features of metallization layer 109. A second layer of dielectric layer 111 can then be applied and patterned. Metallization layers 109, 108 are then formed by creating metal in the openings using, for example, electroplating. This technique is then repeated for each of the dielectric layer 111 and metallization layers 107, 106, etc. The materials of each layer of dielectric layer 111 may be the same or they may be different. Similarly, the materials of each of metallization layers 105, 106, 107, 108, 109 (or a combination of commonly coated metallization layers) may be the same or they may be different.

[0046] The material of each of the metallization layers 105, 106, 107, 108, and 109 can be any suitable conductive material, such as copper formed within a substrate material like titanium nitride. The dielectric layer 111 can be any suitable one or more insulating materials, such as molding compounds, spin-coating materials, or dry film laminators. In some embodiments, the dielectric layer 111 is applied to the casting in a wet or uncured state and then dried or cured. Alternatively, the dielectric layer 111 can be applied as a semi-cured dry film, which is then fully cured after application. The composition of the dielectric layer 111 can include one or more organic dielectric materials, such as polyimide materials, epoxy resins, phenolic glass, or resin films (e.g., GX series films commercially available from Ajinomoto Co., Ltd. (ABF)). Exemplary epoxy resins used for deployment in the dielectric layer 111 include phenolic varnish acrylates, such as epoxy phenolic varnish (EPN) or epoxy cresol varnish (ECN). Other material systems can be used.

[0047] As discussed, the redistribution structure 104 can have any of the characteristics described above, and metallization layers 105, 106, 107, 108, and 109 include mesh metallization layers 112 and 115 for deployment in the packaging architecture. In some embodiments, metallization layers 106 and 108 each have a thickness of not less than 4 µm (i.e., in the z-axis) to support power transfer as discussed herein. In some embodiments, metallization layers 106 and 108 each have a thickness of not less than 4 µm and not more than 20 µm. In some embodiments, metallization layers 106 and 108 each have a thickness of not less than 6 µm and not more than 12 µm. In some embodiments, metallization layers 106 and 108 each have a thickness of not less than 10 µm. Other thicknesses may be used depending on the use case.

[0048] return Figure 8 Method 800 continues at operation 803, where a plurality of active IC dies are mounted to the redistribution structure manufactured at operation 802. Each of the IC dies assembled at operation 803 includes an active circuit system. In some embodiments, one or more of the IC dies include a logic circuit system having logic gates. The one or more IC dies assembled at operation 803 may also include any photonic circuit system suitable for the detection, emission, or processing of optical signals (e.g., filtering, multiplexing, and demultiplexing). Any number of IC dies (e.g., four, five, six, or more) can be mounted to the redistribution structure. The IC dies can have any suitable active circuit system for any suitable application, such as a logic circuit system, a memory circuit system, an integrated electrical and photonic device, etc. Furthermore, at operation 803, optional underfill and / or molding compound may be applied to embed interconnects formed between the IC dies and the redistribution structure, thereby providing mechanical support and protection from the environment affecting the assembled components.

[0049] Figure 10 This is an illustration of a cross-sectional side view of a suspension bridge die interposer structure 1000, similar to a suspension bridge die interposer structure 900, after any number of IC dies (e.g., IC dies 124, 126) have been mounted onto the redistribution structure 104. IC dies 124 and 126 can be mounted onto the redistribution structure 104 using any suitable technique or one or more (e.g., flip-chip bonding mount), as shown, which can form die-side pads 141, redistribution layer-side pads 142, and intermediate solder features 143. However, any bonding structure can be used, such as hybrid bonding features. Figure 10 As shown, die-level interconnect 128 is coupled to via structure 119, die-level interconnect 128 is coupled to mesh metallization layer 112 through via structure 204, and die-level interconnect 129 is coupled to mesh metallization layer 115 through via structure 205.

[0050] Figure 11 This is an illustration of a cross-sectional side view of a suspension bridge die interposer structure 1100, similar to a suspension bridge die interposer structure 1000, after the application of underfill material 131 and molding material 144. Underfill material 131 and molding material 144 are embedded in die-level interconnects 128, 129, 130 and provide mechanical support and protection from the environment. Underfill material 131 may include any suitable material (e.g., an epoxy-based resin or an acrylate-based resin) and may be applied using any suitable technique or method, such as capillary liquid application followed by curing. Molding material 144 may also be an epoxy-based resin or an acrylate-based resin and may be applied using any suitable technique or method, such as liquid dispensing followed by curing and optional capping removal. In some embodiments, material is removed from the back side of IC dies 124, 126 using, for example, a grinding operation, to bring subsequently applied heat sinks, radiators, or other heat dissipation solutions closer to the device layer of adjacent wiring structures 125, 127.

[0051] return Figure 8 Method 800 continues at operation 804, where the carrier is removed from the workpiece to expose the surface of the redistributed structure opposite the assembled IC die. The IC die side can be characterized as the active side, the top IC die side, etc. Any suitable one or more techniques (e.g., heat and peel, UV release, etc.) can be used to remove the carrier. The workpiece is then flipped to expose the surface of the redistributed structure opposite the assembled IC die for fabrication of package-level interconnects and mounting of pre-fabricated bridge dies. For example, the IC die side can be mounted to a chuck or other working surface for subsequent operations. As discussed, the released carrier provides a high-quality, flat surface for the fabrication of the redistributed structure.

[0052] Figure 12 This is an illustration of a cross-sectional side view of a suspended bridge die interposer structure 1200, similar to a suspended bridge die interposer structure 1100, after removing the carrier 901 to expose the surface 1201 of the redistribution structure 104 and flipping the workpiece to prepare for manufacturing package-level interconnects and mounting prefabricated bridge dies. As discussed, the carrier 901 can be removed by heating and peeling, UV release, or similar processes. The workpiece is also flipped (see reference). Figure 11 It can be mounted to carrier 1202, which can have any of the characteristics discussed with respect to carrier 901.

[0053] Return to Figure 8Method 800 continues at operation 805, wherein metal pads for bridge die attachment are fabricated in the bridge die region, and package-level interconnects are fabricated adjacent to the region dedicated to the bridge die, such that the package-level interconnects are outside the perimeter of the dedicated bridge die. The metal pads for bridge die attachment can be fabricated using any suitable one or more techniques (e.g., photolithography and metal deposition techniques). The package-level interconnects can then be fabricated using any suitable one or more techniques. In some embodiments, a photoresist layer, such as a dry resist layer, is patterned above the exposed surface of the redistributed structure, such that openings in the photoresist layer define metallization features such as metal pillars of the package-level interconnects. The metallization features can then be formed using any suitable one or more techniques, such as plating techniques, followed by planarization techniques to remove any overlays. For example, the metal pillars of the package-level interconnects can be copper. The metal interconnect features of the package-level interconnects can then be formed on the metal pillars using any suitable one or more techniques (e.g., applying solder features to the metal pillars). For example, the metal interconnect features of the package-level interconnects can be solder balls, bumps, etc.

[0054] Figure 13 This is an illustration of a cross-sectional side view of a cantilever die interposer structure 1300, similar to a cantilever die interposer structure 1200, after the formation of the redistribution layer side pads 142 and after the formation of the patterned layer 1301. For example, the redistribution layer side pads 142 can be formed using photolithography and metal deposition techniques, followed by removal of the photolithographic pattern. The patterned layer 1301 can be formed using any suitable technique or one or more, such as bulk deposition of a resist material, exposure to light, and selective removal of portions of the bulk material to define an opening 1302 in the patterned layer 1301. As discussed, the opening 1302 defines the features of metal pillars for package-level interconnects, and the opening 1302 is outside the perimeter 132. In some embodiments, the patterned layer 1301 is then removed.

[0055] Figure 14 This is an illustration of a cross-sectional side view of a cantilever die interposer structure 1400, similar to a cantilever die interposer structure 1300, after the fabrication of the package-level interconnect 123. Any suitable one or more techniques can be used to form the package-level interconnect 123. In some embodiments, metal pillars 113, 116, and 121 are first formed using electroplating techniques, followed by planarization techniques to remove any overlays. Metal interconnect features 114, 117, and 122 can then be formed by depositing solder material on the metal pillars 113, 116, and 121. For example, the metal pillars 113, 116, and 121 can be copper, and the metal interconnect features 114, 117, and 122 can be solder material. In some embodiments, the patterning layer 1301 is then removed, and the solder on the interconnect features 114, 117, and 122 is reflowed, as is known in the art.

[0056] return Figure 8 Method 800 continues at operation 806, wherein a passive bridge die with a prefabricated wiring structure is mounted to a redistribution structure on the surface opposite to the mounting of the IC die discussed in operation 803. As discussed, the bridge die is passive, meaning it contains no active components. Furthermore, the bridge die has no TSV, and the surface opposite the prefabricated wiring structure has no wiring features, metallization, etc. Any suitable technique or one or more (e.g., flip-chip interconnect mounting) can be used to mount the bridge die. Additionally, an underfill can be applied to embed the interconnect formed between the passive bridge die and the redistribution structure, and the workpiece can be removed from the carrier.

[0057] Figure 15 This is an illustration of a cross-sectional side view of a suspended bridge die interposer structure 1500, similar to a suspended bridge die interposer structure 1400, after the bridge die 101 has been mounted into the redistribution structure 104 within the perimeter 132 and the perimeter 132 has been defined. The bridge die 101 can be mounted to the redistribution structure 104 using any suitable one or more techniques (e.g., flip-chip interconnect mounting), as shown, which can form die-side pads 141, redistribution layer-side pads 142, and intermediate solder features 143. However, any bonding structure can be used, such as hybrid bonding features.

[0058] Figure 16 This is an illustration of a cross-sectional side view of a suspension bridge core interlayer structure 100, similar to a suspension bridge core interlayer structure 1500, after the application of underfill material 103. Underfill material 103 is embedded in the bridge interconnects 145 and provides mechanical support and protection for the suspension bridge core interlayer structure 100. Underfill material 103 can include any suitable material and can be applied using any suitable one or more techniques discussed with respect to underfill material 131. The carrier 1202 can then be removed by heating and peeling, UV release, or similar treatments. The suspension bridge core interlayer structure 100 can have any of the features or properties discussed herein, and the suspension bridge core interlayer structure 100 can be deployed in any suitable computing device or system.

[0059] return Figure 8Method 800 continues at operation 807, wherein the final device is packaged, assembled, and output, for example, by attaching the suspension bridge die interposer structure to the main component and other assembly processes. The component or package can be installed in any suitable electronic device, such as laptops, netbooks, notebooks, ultrabooks, smartphones, tablets, PDAs, ultra-mobile PCs, mobile phones, desktop computers, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players, digital video recorders, etc.

[0060] Figure 17 This is an illustration of a cross-sectional side view of a package structure 1700, similar to a suspended bridge die interposer structure 100, attached to the main component 1703 and with one or more heat sinks and / or heat sinks 1702 deployed. As shown, the package structure 1700, which can be characterized as a system, includes a suspended bridge die interposer structure 100 attached to the main component 1703 using package-level interconnects 123. In some embodiments, the package-level interconnects 123 include solder (e.g., SAC) microbumps (i.e., metal interconnect features 114, 117, 122 are solder materials), but other interconnect features may be used as discussed. In some embodiments, the main component 1703 is or includes one or more materials known to be suitable as a package substrate (e.g., epoxy preforms, cored or coreless laminates, etc.). In some embodiments, the main component 1703 is a printed circuit board (PCB). In some embodiments, the main component 1703 includes one or more metallized redistribution layers (not shown) embedded within a dielectric material. The main component 1703 may also include one or more IC dies, one or more passive or active components embedded therein.

[0061] The main component 1703 may include interconnects 1704, which may include solder (e.g., balls, bumps, etc.) suitable for a given motherboard architecture (e.g., surface mount FR4, etc.). Also as shown, one or more heat sinks and / or heat transfer devices 1702 may be coupled to the suspended bridge die interposer structure 100, which may be advantageous, for example, where IC dies 124, 126 include one or more CPU cores or other circuitry with similar power density. Any thermal interface material 1701 may couple IC dies 124, 126 to the heat sink / heat transfer device 1702. Although not shown, IC dies 124, 126 may be ground before the application of the thermal interface material 1701, allowing the heat sink / heat transfer device 1702 to be closer to the device layers of IC dies 124, 126.

[0062] Figure 18Exemplary systems employing IC components including a suspended bridge die interposer structure, arranged according to at least some embodiments of the present disclosure, are illustrated. For example, the system may be a mobile computing platform 1805 and / or a data server machine 1806. Either may employ a component assembly including an IC component comprising a suspended bridge die interposer structure as described elsewhere herein. The server machine 1806 may be any commercial server, for example, including any number of high-performance computing platforms arranged in a rack and networked together for electronic data processing, which in exemplary embodiments includes an IC die component 1850 having a suspended bridge die interposer structure as described elsewhere herein. The mobile computing platform 1805 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform 1805 may be any of a tablet computer, smartphone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1810, and a battery 1815 and / or power circuitry system. Although shown with respect to mobile computing platform 1805, in other examples, chip-level or package-level integrated system 1810 and battery 1815 may be implemented in desktop computing platforms, automotive computing platforms, Internet of Things platforms, etc. As described below, in some examples, the disclosed system may include a subsystem 1860 such as a system-on-a-chip (SOC) or an integrated system of multiple ICs relative to mobile computing platform 1805.

[0063] Whether located within the integrated system 1810 shown in extended view 1820 or as a separate packaged device within a data server machine 1806, subsystem 1860 may include memory circuitry and / or processor circuitry 1840 (e.g., RAM, microprocessor, multi-core microprocessor, graphics processor, etc.), power management integrated circuit (PMIC) 1830, controller 1835, and radio frequency integrated circuit (RFIC) 1825 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies (e.g., memory circuitry and / or processor circuitry 1840) may be assembled and implemented such that one or more IC dies have IC components including the suspended bridge die interposer structure as described herein. In some embodiments, RFIC 1825 includes a digital baseband and an analog front-end module, the analog front-end module further including a power amplifier on the transmit path and a low-noise amplifier on the receive path. Functionally, the PMIC 1830 can perform battery power regulation, DC-DC conversion, etc., and therefore has an input coupled to the battery 1815 and an output that provides current to other functional modules. For example... Figure 18As further illustrated, in an exemplary embodiment, RFIC 1825 has an output coupled to an antenna (not shown) to implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and derivatives thereof, as well as any other wireless protocol designated as 3G, 4G, 5G, and higher. Memory circuitry and / or processor circuitry 1840 can provide memory functionality for subsystem 1860, and provide advanced control, data processing, etc., for subsystem 1860. In alternative embodiments, each of the SOC modules can be integrated onto a separate IC coupled to a package substrate, interposer, or board.

[0064] Figure 19 This is a block diagram of a computing device 1900 according to some embodiments. For example, one or more components of the computing device 1900 may include any package structure or assembly having a suspension bridge die interposer structure as discussed elsewhere herein. Figure 19 Several components are shown, but any one or more of these components may be omitted or copied depending on the application requirements. In some embodiments, some components included in the computing device 1900 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various components among these components may be fabricated on a single system-on-a-chip (SoC) die, or implemented using multiple separate dies or blocks packaged together. Any such packaged component may include, for example, a suspended bridge die interposer structure as discussed herein. Additionally, in various embodiments, the computing device 1900 may not include... Figure 19 The computing device 1900 may include one or more components as shown, but may include an interface circuitry system for coupling to one or more components. For example, the computing device 1900 may not include a display device 1903, but may include a display device interface circuitry system (e.g., connectors and drive circuitry system) to which the display device 1903 may be coupled.

[0065] The computing device 1900 may include a processing device 1901 (e.g., one or more processing devices). As used herein, the term processing device or processor indicates means for processing electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1901 may include a memory 1921, a communication device 1922, a cooling / active cooling device 1923, a battery / power regulation device 1924, logic 1925, interconnection 1926, a thermal regulation device 1927, and a hardware security device 1928.

[0066] The processing device 1901 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable computing units.

[0067] Processing device 1901 may include memory 1902, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drive. In some embodiments, processing device 1901 and memory 1902 share a package. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0068] The computing device 1900 may include a thermal regulation / cooling device 1906. The thermal regulation / cooling device 1906 can maintain the processing device 1901 (and / or other components of the computing device 1900) at a predetermined low temperature during operation. This predetermined low temperature can be any temperature discussed elsewhere herein.

[0069] In some embodiments, computing device 1900 may include communication chip 1907 (e.g., one or more communication chips). For example, communication chip 1907 may be configured to manage wireless communication for transmitting data to and from computing device 1900. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation via a non-solid-state medium.

[0070] For example, computing device 1900 may include any photonic structure discussed herein that may facilitate communication between one or more instances of processing device 1901 and / or one or more instances of memory 1902.

[0071] The computing device 1900 may include a battery / power circuit system 1908. The battery / power circuit system 1908 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the computing device 1900 to an energy source (e.g., AC mains power) that is separate from the computing device 1900.

[0072] The computing device 1900 may include a display device 1903 (or a corresponding interface circuitry system, as described above). The display device 1903 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0073] The computing device 1900 may include an audio output device 1904 (or a corresponding interface circuitry system, as described above). The audio output device 1904 may include any means of generating audible indicators, such as a speaker, headphones, or earphones.

[0074] The computing device 1900 may include an audio input device 1910 (or a corresponding interface circuitry system, as described above). The audio input device 1910 may include any means of generating a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0075] The computing device 1900 may include a Global Positioning System (GPS) device 1909 (or a corresponding interface circuitry system, as described above). The GPS device 1909 may communicate with a satellite-based system and may receive the location of the computing device 1900, as is known in the art.

[0076] The computing device 1900 may include another output device 1905 (or a corresponding interface circuitry system, as described above). Examples include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0077] The computing device 1900 may include another input device 1911 (or a corresponding interface circuitry system, as described above). Examples may include an accelerometer, gyroscope, compass, image capture device, keyboard, cursor control device such as a mouse, stylus, touchpad, barcode reader, quick-response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0078] The computing device 1900 may include a security interface device 1912. The security interface device 1912 may include any means of providing security measures for the computing device 1900, such as intrusion detection, biometric authentication, secure encoding or decoding, management of access lists, malware detection, or spyware detection.

[0079] The computing device 1900 may include an antenna 1913. The antenna 1913 may include any means of converting electric current into radio waves and / or converting radio waves into electric current.

[0080] The computing device 1900 or a subset thereof may have any suitable form factor, such as a server or other networked computing component, a mobile device, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0081] While certain features set forth herein have been described with reference to various embodiments, this description is not intended to be construed as limiting. Therefore, various modifications to the embodiments described herein, as well as other embodiments readily apparent to those skilled in the art to which this disclosure pertains, are considered to fall within the spirit and scope of this disclosure.

[0082] It will be appreciated that the invention is not limited to the described embodiments, but can be practiced with modifications and changes without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features further provided below.

[0083] The following describes exemplary embodiments.

[0084] In one or more first embodiments, a device includes: a bridge die including a monolithic substrate and wiring structures on a first surface of the monolithic substrate; and a redistribution structure above the bridge die and extending beyond a perimeter of the bridge die, the redistribution structure including: a first metallization layer including a power grid metallization portion above the bridge die and extending beyond the perimeter; a plurality of signal vias extending through the first metallization layer within the perimeter, each signal via being surrounded by a dielectric material in contact with the signal vias and the power grid metallization portion; and a power via extending through the first layer within the perimeter, the power via contacting the power grid metallization portion.

[0085] In one or more second embodiments, further for the first embodiment, the power grid metallization includes a power grid metallization, and the power via includes a power via, and the redistribution structure further includes a second metallization layer above or below the first metallization layer, the second metallization layer including a ground grid metallization layer above the bridge die and extending beyond the perimeter, wherein the signal via extends through the second metallization layer within the perimeter, and wherein the dielectric material or the second dielectric material contacts each of the signal via and the ground grid metallization.

[0086] In one or more third embodiments, further for the first or second embodiment, the redistribution structure includes a ground via extending through the first metallization layer within the perimeter, the ground via contacting the ground grid metallization such that the dielectric material contacts the ground via and the power grid metallization.

[0087] In one or more fourth embodiments, further for the first to third embodiments, the bridge die does not have any through-substrate vias, and wherein the wiring structure interconnects the signal vias within the perimeter.

[0088] In one or more fifth embodiments, further for the first to fourth embodiments, the device further includes a metallization structure coupled to the power grid metallization and in contact with the redistribution structure outside the perimeter, the metallization structure extending vertically from the redistribution structure outside the perimeter to a position below a second surface of the bridge die opposite to the first surface.

[0089] In one or more sixth embodiments, and further for the first to fifth embodiments, the metallization structure includes a pillar portion and an interconnect portion, wherein the wiring structure is laterally adjacent to the pillar portion.

[0090] In one or more seventh embodiments, and further for the first to sixth embodiments, the second surface of the bridge die does not contain any signal or power transmission structure.

[0091] In one or more of the eighth embodiments, and further for the first to seventh embodiments, each of the signal vias has a cross-sectional shape, and wherein the power grid metallization includes a substantially conformal cross-sectional shape opening at each of the signal vias.

[0092] In one or more ninth embodiments, and further for the first to eighth embodiments, the device further includes: a first integrated circuit (IC) die having at least a portion within the perimeter and coupled to a first signal via in the signal via; and a second IC die having at least a portion within the perimeter and coupled to a second signal via in the signal via, the first signal via in the signal via and the second signal via in the signal via being interconnected by the wiring structure.

[0093] In one or more tenth embodiments, and further for the first to ninth embodiments, the device further includes a package or main substrate that is coupled to the wiring structure and to the first metallization layer relative to the bridge die.

[0094] In one or more eleventh embodiments, a device includes: a bridge die including a monolithic substrate between a first surface and an opposing second surface and wiring structures on the first surface; a redistribution structure above the bridge die, the redistribution structure including: a first metallization layer including a power grid metallization portion above the bridge die and extending beyond a perimeter of the bridge die; a second metallization layer including a ground grid metallization portion above the bridge die and extending beyond the perimeter; a plurality of signal vias extending through the first metallization layer and the second metallization layer within the perimeter and insulated from the first metallization layer and the second metallization layer; and a power metallization structure and a ground metallization structure, the power metallization structure and the ground metallization structure each extending vertically from the redistribution structure outside the perimeter to a position below the second surface of the bridge die.

[0095] In one or more twelfth embodiments, and further for an eleventh embodiment, the bridge die does not have any through-substrate vias, and wherein the wiring structure interconnects the signal vias within the perimeter.

[0096] In one or more thirteenth embodiments, and further for an eleventh or twelfth embodiment, the power metallization structure includes a pillar portion and an interconnect portion, wherein the wiring structure is laterally adjacent to the pillar portion.

[0097] In one or more of the fourteenth embodiments, and further for the eleventh to thirteenth embodiments, the second surface of the bridge die does not have any signal or power transmission structure.

[0098] In one or more fifteenth embodiments, and further for eleventh to fourteenth embodiments, each of the signal vias has a cross-sectional shape, wherein the power grid metallization and the ground grid metallization both include substantially conformal cross-sectional shape openings at each of the signal vias.

[0099] In one or more sixteenth embodiments, and further for eleventh to fifteenth embodiments, the device further includes: a first integrated circuit (IC) die having at least a portion within the perimeter and coupled to a first signal via in the signal via; and a second IC die having at least a portion within the perimeter and coupled to a second signal via in the signal via, the first signal via in the signal via and the second signal via in the signal via being interconnected by the wiring structure.

[0100] In one or more of the seventeenth embodiments, and further with respect to the eleventh to sixteenth embodiments, the device further includes a package or main substrate that is coupled to the wiring structure and to the first metallization layer relative to the bridge die.

[0101] In one or more eighteenth embodiments, a method includes: forming a redistribution structure on a carrier, the redistribution structure including a metallized grid surrounding a plurality of metal vias; mounting an integrated circuit (IC) die to the redistribution structure, wherein a first die-level interconnect is coupled to a first metal via in the metal vias, and a second die-level interconnect is coupled to the metallized grid; removing the redistribution structure from the carrier; and mounting a bridge die including a monolithic substrate to the redistribution structure, wherein the first die-level interconnect and the second die-level interconnect are within the perimeter of the bridge die.

[0102] In one or more nineteenth embodiments, and further for an eighteenth embodiment, the method further includes forming a metallized structure on the redistributed structure and laterally adjacent to the bridge core outside the perimeter, the metallized structure being coupled to the metallized mesh.

[0103] In one or more twentieth embodiments, and further for the eighteenth or nineteenth embodiment, the method further includes coupling the metallized structure to an electronic substrate.

[0104] It will be appreciated that the invention is not limited to the described embodiments, but can be practiced with modifications and variations without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limited in this respect, and in various implementations, the above embodiments may include only a subset of these features, different orders of implementing these features, different combinations of implementing these features, and / or additional features in addition to those expressly listed. Therefore, the scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: A bridge die, the bridge die comprising a monolithic substrate and a wiring structure on a first surface of the monolithic substrate; as well as A redistribution structure, the redistribution structure being above the bridge core and extending beyond the perimeter of the bridge core, the redistribution structure comprising: A first metallization layer, the first metallization layer including a power grid metallization portion above the bridge die and extending beyond the perimeter; Multiple signal vias extending through the first metallization layer within the perimeter, each signal via being surrounded by a dielectric material in contact with the signal vias and the power grid metallization; and A power via extends through the first metallization layer within the perimeter and contacts the power mesh metallization.

2. The device according to claim 1, wherein, The power grid metallization includes a power grid metallization, and the power vias include power vias. The redistribution structure further includes: A second metallization layer above or below the first metallization layer, the second metallization layer including a ground grid metallization portion above the bridge die and extending beyond the perimeter, wherein the signal via extends through the second metallization layer within the perimeter, and wherein the dielectric material or the second dielectric material contacts each of the signal via and the ground grid metallization portion.

3. The device according to claim 2, wherein, The redistribution structure also includes: A grounding via extends through the first metallization layer within the perimeter and contacts the grounding grid metallization, wherein the dielectric material contacts both the grounding via and the power grid metallization.

4. The device according to claim 1, wherein, The bridge die has no through-substrate vias, and the wiring structure interconnects the signal vias within the perimeter.

5. The device according to any one of claims 1-4, further comprising: A metallized structure coupled to the power grid metallization and in contact with the redistribution structure outside the perimeter, the metallized structure extending vertically from the redistribution structure outside the perimeter to a position below the second surface of the bridge die opposite to the first surface.

6. The device according to claim 5, wherein, The metallized structure includes a pillar portion and an interconnect portion, wherein the wiring structure is laterally adjacent to the pillar portion.

7. The device according to claim 5, wherein, The second surface of the bridge die does not contain any signal or power transmission structure.

8. The device according to any one of claims 1-4, wherein, Each of the signal vias has a cross-sectional shape, and wherein the power grid metallization includes a substantially conformal cross-sectional shape opening at each of the signal vias.

9. The device according to any one of claims 1-4, further comprising: A first integrated circuit (IC) die, the first integrated circuit die having at least a portion within the perimeter and coupled to a first signal via in the signal via; as well as The second IC die has at least a portion within the perimeter and is coupled to a second signal via in the signal via, wherein the first signal via and the second signal via are interconnected through the wiring structure.

10. The device according to claim 9, further comprising: A package or main substrate, which is coupled to the wiring structure and to the first metallization layer relative to the bridge die.

11. An apparatus comprising: A bridge die, the bridge die comprising a monolithic substrate located between a first surface and an opposing second surface, and a wiring structure on the first surface; A redistribution structure, the redistribution structure being above the bridge core, the redistribution structure comprising: A first metallization layer, the first metallization layer including a power grid metallization portion above the bridge die and extending beyond the perimeter of the bridge die; A second metallization layer, the second metallization layer including a ground grid metallization portion above the bridge die and extending beyond the perimeter; and A plurality of signal vias, the plurality of signal vias extending through the first metallization layer and the second metallization layer within the perimeter and being insulated from the first metallization layer and the second metallization layer; and The power supply metallization structure and the ground metallization structure both extend vertically from the redistribution structure outside the perimeter to a position below the second surface of the bridge die.

12. The device according to claim 11, wherein, The bridge die does not have any through-substrate vias.

13. The device according to claim 12, wherein, The wiring structure interconnects the signal vias within the perimeter.

14. The device according to claim 11, wherein, The power metallization structure includes a pillar portion and an interconnect portion, wherein the wiring structure is laterally adjacent to the pillar portion.

15. The device according to claim 11, wherein, The second surface of the bridge die does not contain any signal or power transmission structure.

16. The device according to any one of claims 11-15, wherein, Each of the signal vias has a cross-sectional shape, and wherein the power grid metallization and the ground grid metallization both include substantially conformal cross-sectional shape openings at each of the signal vias.

17. The device according to any one of claims 11-15, wherein, The redistribution structure also includes: A power via extending through the second metallization layer and contacting the power grid metallization.

18. The device according to any one of claims 11-15, wherein, The redistribution structure also includes: A grounding via extends through the first metallization layer and contacts the metallization portion of the grounding grid.

19. The device according to any one of claims 11-15, further comprising: A first integrated circuit (IC) die, the first integrated circuit die having at least a portion within the perimeter and coupled to a first signal via in the signal via; as well as The second IC die has at least a portion within the perimeter and is coupled to a second signal via in the signal via, wherein the first signal via and the second signal via are interconnected through the wiring structure.

20. The apparatus of claim 19, further comprising: A package or main substrate, which is coupled to the wiring structure and to the first metallization layer relative to the bridge die.

21. A method comprising: A redistribution structure is formed on the carrier, the redistribution structure comprising a metallized mesh surrounding a plurality of metal vias; An integrated circuit (IC) die is mounted to the redistributed structure, wherein a first die-level interconnect is coupled to a first metal via in the metal via, and a second die-level interconnect is coupled to the metallized mesh; Remove the redistributed structure from the carrier; and A bridge die, comprising a monolithic substrate, is mounted to the redistributed structure, wherein the first die-level interconnect and the second die-level interconnect are within the perimeter of the bridge die.

22. The method of claim 21, further comprising: A metallized structure is formed on the redistributed structure and laterally adjacent to the bridge core outside the perimeter, the metallized structure being coupled to the metallized mesh.

23. The method of claim 22, further comprising: The metallized structure is coupled to an electronic substrate.

24. The method according to any one of claims 21-23, wherein, The redistribution structure includes a plurality of signal vias extending through the metallized mesh, each of which is surrounded by a dielectric material in contact with the signal vias and the metallized mesh.

25. The method according to any one of claims 21-23, wherein, The bridge die does not have any through-substrate vias.

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