Hybrid bonded package-on-package structure and method of forming the same

Abstract

A hybrid bonding package structure and a forming method thereof, wherein the structure comprises: a first package body having a first conductive structure, a side edge of the first package body serving as a first bonding surface, and the first bonding surface exposing the first conductive structure; a second package body having a second conductive structure, a side edge of the second package body serving as a second bonding surface, and the second bonding surface exposing the second conductive structure; and the first bonding surface and the second bonding surface being hybrid bonded so that the first conductive structure and the second conductive structure are electrically connected. By taking the side edges of the first package body and the second package body as the bonding surfaces, only the flatness of the side edges in one dimension needs to be ensured to meet the process window requirements of hybrid bonding, thereby realizing hybrid bonding of panel-level large-size package bodies. Meanwhile, the linear feature of the side bonding surface significantly improves the tolerance of local minor defects, and the risk of overall bonding failure caused by local unevenness in surface contact can be avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a hybrid bonding board-level packaging structure and its formation method. Background Technology

[0002] With the development of very large-scale integrated circuits (VLSI) approaching its physical limits, three-dimensional integrated circuits (3D integrated circuits), which offer advantages in both physical size and cost, are an effective way to extend Moore's Law and solve advanced packaging problems. Wafer bonding technology is one of the key technologies for 3D circuit integration, especially hybrid bonding technology, which can achieve internal interconnection of thousands of chips while bonding two wafers, greatly improving chip performance and saving costs.

[0003] Copper hybrid bonding technology is becoming a core driving force behind the evolution of next-generation 2.5D and 3D packaging technologies. Compared to traditional microbump stacking and thermoforming bonding, hybrid bonding, through direct copper-to-copper metal bonding and fusion with the dielectric layer, eliminates the height limitations and electrical parasitic effects of solder bumps, thereby achieving higher interconnect bandwidth density and lower signal transmission power consumption. This technical characteristic makes it particularly suitable for applications with stringent requirements for data throughput and energy efficiency, such as artificial intelligence chips and high-bandwidth memories.

[0004] However, existing hybrid bonding techniques still have many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a hybrid bonding board-level packaging structure and a method for forming the same, so as to realize hybrid bonding of the board-level packaging structure.

[0006] To address the aforementioned problems, this invention provides a hybrid bonding board-level packaging structure, comprising: a first package having a first conductive structure, a side of the first package serving as a first bonding surface, the first bonding surface exposing the first conductive structure; and a second package having a second conductive structure, a side of the second package serving as a second bonding surface, the second bonding surface exposing the second conductive structure; wherein the first bonding surface and the second bonding surface are hybrid bonded, thereby electrically connecting the first conductive structure and the second conductive structure.

[0007] Optionally, the first package includes: a first board-level substrate; a plurality of first copper pillars located on the first board-level substrate, the plurality of first copper pillars constituting the first conductive structure; a plurality of first chips, the first chips being bonded to the first board-level substrate; and a first filler layer located on the first board-level substrate, the first filler layer covering the first chips and the first copper pillars, and the first filler layer exposing the surfaces of the first chips and the first copper pillars.

[0008] Optionally, the first package further includes a first rewiring layer located on the first fill layer, the first rewiring layer being electrically connected to the first chip and the first copper pillar respectively.

[0009] Optionally, the second package includes: a second board-level substrate; a plurality of second copper pillars located on the second board-level substrate, the plurality of second copper pillars constituting the second conductive structure; a plurality of second chips, the second chips being bonded to the second board-level substrate; and a second filler layer located on the second board-level substrate, the second filler layer covering the second chips and the second copper pillars, and the second filler layer exposing the surfaces of the second chips and the second copper pillars.

[0010] Optionally, the second package further includes a second rewiring layer located on the second fill layer, the second rewiring layer being electrically connected to the second chip and the second copper pillar, respectively.

[0011] Optionally, the second package includes: an integrated passive device package, the sides of which expose the second conductive structure; and a dielectric layer located on the sides of the integrated passive device package, the dielectric layer filling the grooves in the second conductive structure.

[0012] Optionally, it further includes: a molding layer located on the first package and the second package; a plurality of conductive plugs located within the molding layer, the plurality of conductive plugs being electrically connected to the first package and the second package respectively; and a top redistribution layer located on the molding layer, the top redistribution layer being electrically connected to the conductive plugs.

[0013] Accordingly, the present invention also provides a method for forming a hybrid-bonded board-level package structure, comprising: forming a first package body having a first conductive structure; forming a second package body having a second conductive structure; performing edge processing on the first package body to form a first bonding surface on the side of the first package body, the first bonding surface exposing the first conductive structure; performing edge processing on the second package body to form a second bonding surface on the side of the second package body, the second bonding surface exposing the second conductive structure; and hybrid bonding the first bonding surface and the second bonding surface to electrically connect the first conductive structure and the second conductive structure.

[0014] Optionally, the method of forming the first package includes: providing a first board-level substrate; forming a plurality of first copper pillars on the first board-level substrate, the plurality of first copper pillars constituting the first conductive structure; providing a plurality of first chips; bonding the first chips to the first board-level substrate; forming a first filler layer on the first board-level substrate, the first filler layer covering the first chips and the first copper pillars, and the first filler layer exposing the surfaces of the first chips and the first copper pillars.

[0015] Optionally, the method of forming the first package further includes: after forming the first fill layer, forming a first redistribution layer on the first fill layer, wherein the first redistribution layer is electrically connected to the first chip and the first copper pillar respectively.

[0016] Optionally, the method for edge processing of the first package includes: grinding the side of the first package until the first copper pillar is exposed to form the first bonding surface.

[0017] Optionally, the method of forming the second package includes: providing a second board-level substrate; forming a plurality of second copper pillars on the second board-level substrate, the plurality of second copper pillars constituting the second conductive structure; providing a plurality of second chips; bonding the second chips to the second board-level substrate; and forming a second filler layer on the second board-level substrate, the second filler layer covering the second chips and the second copper pillars.

[0018] Optionally, the method of forming the second package further includes: after forming the second fill layer, forming a second redistribution layer on the second fill layer, the second redistribution layer being electrically connected to the second chip and the second copper pillar respectively.

[0019] Optionally, the method for edge processing of the second package includes: grinding the side of the second package until the second copper pillar is exposed to form the second bonding surface.

[0020] Optionally, the method of forming the second package includes: providing an integrated passive device package, the sides of which expose the second conductive structure; forming a dielectric layer on the sides of the integrated passive device package, the dielectric layer filling the grooves in the second conductive structure and covering the second conductive structure; and polishing the dielectric layer until the second conductive structure is exposed.

[0021] Optionally, after edge processing of the first package and the second package, the method further includes cleaning the first bonding surface and the second bonding surface.

[0022] Optionally, the cleaning process includes: performing RCA cleaning on the first bonding surface and the second bonding surface; performing acid cleaning after the RCA cleaning; and performing plasma cleaning with hydrogen or argon after the acid cleaning.

[0023] Optionally, after bonding the first package and the second package, the method further includes: forming a plurality of conductive plugs on the first package and the second package, the plurality of conductive plugs being electrically connected to the first package and the second package respectively; forming a molding compound on the first package and the second package, the molding compound covering the conductive plugs and exposing the surfaces of the conductive plugs; and forming a top redistribution layer on the molding compound, the top redistribution layer being electrically connected to the conductive plugs.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages: In the hybrid bonding board-level packaging structure of this invention, the sides of the first and second packages are used as bonding surfaces, reducing the two-dimensional surface contact to a unidirectional line contact (the width of the package side is significantly reduced compared to the width of its traditional bonding surface, and can be regarded as a one-dimensional line). Only the flatness of this side dimension needs to be ensured to meet the process window requirements of hybrid bonding. This dimensional reduction fundamentally reduces the difficulty of controlling surface morphology, significantly relaxes the precision dependence on planarization processes such as grinding or polishing, and breaks through the strict limitations of traditional wafer-level bonding on substrate size and shape. Hybrid bonding is no longer limited to circular silicon wafers but can be adapted to the hybrid bonding of large-size rectangular or square panel-level packages. Simultaneously, the linear characteristics of the side bonding surface significantly improve its tolerance to local minor defects, avoiding the risk of overall bonding failure due to local unevenness in the surface contact, effectively improving the production yield and process stability of panel-level packaging. In addition, this structure breaks through the constraint that the substrate size must be matched in traditional packaging, and can flexibly realize the interconnection between substrates of different sizes, or the direct bonding of substrates to independent components, making the design and manufacturing process more flexible.

[0025] Furthermore, the second package includes: an integrated passive device package, the sides of which expose the second conductive structure; and a dielectric layer located on the sides of the integrated passive device package, the dielectric layer filling the grooves in the second conductive structure. By side-bonding the integrated passive device package, the signal transmission distance between the passive device and the active chip is effectively shortened, thereby reducing parasitic inductance and capacitance, improving the circuit's response speed and frequency characteristics, and enhancing the overall package's electrical performance.

[0026] In the method for forming a hybrid-bonded board-level package structure according to the technical solution of the present invention, the sides of the first package and the second package are used as bonding surfaces, reducing the two-dimensional surface contact to a one-dimensional line contact (the width of the side of the package is greatly reduced compared to the width of its traditional bonding surface, and can be regarded as a one-dimensional line). Only the flatness of this side dimension needs to be ensured to meet the process window requirements of hybrid bonding. This dimensional reduction fundamentally reduces the difficulty of controlling surface morphology, significantly relaxes the precision dependence on planarization processes such as grinding or polishing, and breaks through the strict limitations of traditional wafer-level bonding on substrate size and shape. Hybrid bonding is no longer limited to circular silicon wafers, but can be adapted to the hybrid bonding of large-size rectangular or square panel-level packages. At the same time, the linear characteristics of the side bonding surface significantly improve its tolerance to local minor defects, avoiding the risk of overall bonding failure due to local unevenness in the surface contact, and effectively improving the production yield and process stability of panel-level packaging. In addition, this structure breaks through the constraint that the substrate size must be matched in traditional packaging, and can flexibly realize the interconnection between substrates of different sizes, or the direct bonding of substrates to independent components, making the design and manufacturing process more flexible.

[0027] Furthermore, the method for forming the second package includes: providing an integrated passive device package, wherein the sides of the integrated passive device package expose the second conductive structure; forming a dielectric layer on the sides of the integrated passive device package, the dielectric layer filling the grooves in the second conductive structure and covering the second conductive structure; and polishing the dielectric layer until the second conductive structure is exposed. By side-bonding the integrated passive device package, the signal transmission distance between the passive device and the active chip is effectively shortened, thereby reducing parasitic inductance and capacitance, improving the circuit response speed and frequency characteristics, and improving the overall package electrical performance.

[0028] Furthermore, after edge processing of the first and second packages, the method further includes cleaning the first and second bonding surfaces. The cleaning process effectively removes residual particles, organic contaminants, and surface oxide layers generated during the grinding process, thereby improving the cleanliness and surface activity of the bonding surfaces. This provides ideal physical contact conditions for subsequent hybrid bonding, which is beneficial for enhancing the atomic diffusion efficiency and bonding strength of copper-copper bonding, thereby improving the long-term reliability and electrical performance stability of the packaging structure. Attached Figure Description

[0029] Figures 1 to 8 This is a schematic diagram of the steps in the method for forming a hybrid bonding board-level packaging structure according to an embodiment of the present invention; Figure 9 This is a schematic diagram of a hybrid bonding board-level packaging structure according to another embodiment of the present invention; Figure 10 This is a schematic diagram of a hybrid bonding board-level packaging structure according to another embodiment of the present invention. Detailed Implementation

[0030] As described in the background section, existing hybrid bonding techniques still have many problems. These will be explained in detail below.

[0031] Hybrid bonding is currently one of the most important process technologies in advanced packaging. By eliminating intermediate media such as solder, direct copper-to-copper connections exhibit lower resistance, reducing energy loss during signal transmission and minimizing signal propagation time delay. Hybrid bonding is an advanced interconnect technology that combines direct metal-to-metal bonding and direct dielectric-to-dielectric bonding in the same process step. It achieves high-strength, high-density interconnects between chips or between chips and substrates by simultaneously forming atomic-level metal connections and covalent dielectric connections on both surfaces to be bonded.

[0032] Hybrid bonding places extremely high demands on surface roughness and global flatness. Specifically, the surface roughness of the dielectric layer needs to be less than 0.5 nm (with an even stricter requirement of 0.1-0.2 nm), the surface roughness of the copper pads needs to be less than 1 nm, the global flatness needs to be less than 2 μm, and wafer warpage also needs to be strictly controlled.

[0033] However, the challenge of using hybrid bonding for panel level packaging (PLP) is enormous, because the area of ​​panel level packaging is larger than that of wafer packaging, and the warpage and overall flatness of the panel are also much greater than those of the wafer. To achieve direct bonding between the chip and the panel or between the panels, the current process is extremely difficult.

[0034] Based on this, the present invention provides a hybrid bonding board-level packaging structure and its formation method. The sides of the first and second packages are used as bonding surfaces, reducing the two-dimensional surface contact to a unidirectional line contact. Only the flatness of the side surface dimension needs to be ensured to meet the process window requirements of hybrid bonding. This dimensional reduction fundamentally reduces the difficulty of controlling surface morphology, significantly relaxes the precision dependence on planarization processes such as grinding or polishing, and breaks through the strict limitations of traditional wafer-level bonding on substrate size and shape. Hybrid bonding is no longer limited to circular silicon wafers but can be adapted to the hybrid bonding of large-size rectangular or square panel-level packages. Simultaneously, the linear characteristics of the side bonding surface significantly improve its tolerance to local minor defects, avoiding the risk of overall bonding failure due to local unevenness in the surface contact, effectively improving the production yield and process stability of panel-level packaging. Furthermore, this structure breaks through the constraint of matching substrate sizes in traditional packaging, enabling flexible interconnection between substrates of different sizes or direct bonding between substrates and independent components, providing greater flexibility in design and manufacturing processes.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 1 to 8 This is a schematic diagram of the steps in the method for forming a hybrid bonding board-level packaging structure according to an embodiment of the present invention.

[0037] A first package is formed, and the first package has a first conductive structure. Please refer to [reference needed] for the specific formation process. Figures 1 to 4 .

[0038] Please refer to Figure 1 Provides the first board-level substrate 100.

[0039] In this embodiment, the first board-level substrate 100 will serve as the basic support platform for subsequent panel-level packaging processes, and its surface flatness and thermal stability directly affect the forming accuracy of subsequent layer metal structures.

[0040] In this embodiment, since the first package body needs to undergo side hybrid bonding, the shape of the first board-level substrate 100 is rectangular or square.

[0041] Please refer to Figure 2 A plurality of first copper pillars 101 are formed on the first plate-level substrate 100, and the plurality of first copper pillars 101 constitute the first conductive structure.

[0042] In this embodiment, the first copper pillar 101 serves as a key electrical connection conductor for achieving side hybrid bonding, and it is typically formed on the first plate-level substrate 100 using electroplating or filling processes.

[0043] It should be noted that, considering subsequent process requirements, the first copper pillar 101 is initially covered by a filler layer. A grinding process is required to expose the first copper pillar 101 from the filler layer, thus forming a side contact surface suitable for hybrid bonding. However, as a machining process, grinding inevitably causes some material loss to the first copper pillar 101 while removing the filler layer material. If the initial size of the first copper pillar 101 is insufficient, partial loss may occur after grinding, resulting in a reduced electrical connection cross-sectional area and increased contact resistance. Therefore, in the initial manufacturing stage, the amount of material loss from the grinding process needs to be fully estimated, and the volume of the first copper pillar 101 needs to be designed to be relatively ample to ensure that after complete edge grinding, the first copper pillar 101 still maintains sufficient effective contact area and structural integrity, thereby guaranteeing the reliability of the electrical connection and the mechanical bonding strength of subsequent side hybrid bonding.

[0044] Please refer to Figure 3 A plurality of first chips 102 are provided; the first chips 102 are bonded to the first board-level substrate 100.

[0045] In this embodiment, the plurality of first chips 102 are configured by combining chips of different functional types, such as integrating multiple functional devices such as logic chips, memory chips, radio frequency chips, or sensor chips into the same package. This heterogeneous integration method enables the final package structure to achieve system-level integration of diverse functions on a single substrate, breaking through the limitations of traditional single-chip packaging and meeting the application requirements of complex electronic systems for the compact integration of multifunctional modules.

[0046] Please refer to Figure 4 A first filling layer 103 is formed on the first board-level substrate 100. The first filling layer 103 covers the first chip 102 and the first copper pillar 101, and the first filling layer 103 exposes the surfaces of the first chip 102 and the first copper pillar 101.

[0047] In this embodiment, the first filling layer 103 is formed using epoxy resin as the filling material layer, which is formed on the first board-level substrate 100 through coating or injection molding processes. This filling material layer completely covers the first copper pillar 101 and the first chip 102 to provide mechanical support and environmental protection. Subsequently, the filling material layer is ground to gradually remove the surface material until the top surfaces of the first copper pillar 101 and the first chip 102 are exposed, forming a smooth first filling layer 103. Epoxy resin has good insulation, adhesion, and process compatibility, and after grinding, it can achieve high coplanarity with the surfaces of the first copper pillar 101 and the first chip 102.

[0048] Please refer to Figure 5 This forms a second package, which has a second conductive structure.

[0049] In this embodiment, the method for forming the second package includes: providing a second board-level substrate 200; forming a plurality of second copper pillars 201 on the second board-level substrate 200, the plurality of second copper pillars 201 constituting the second conductive structure; providing a plurality of second chips 202; bonding the second chips 202 to the second board-level substrate 200; and forming a second filler layer 203 on the second board-level substrate 200, the second filler layer 203 covering the second chips 202 and the second copper pillars 201.

[0050] It should be noted that the formation process of the second package is the same as that of the first package, and will not be described in detail here. For details, please refer to [link / reference needed]. Figures 1 to 4 As stated in the corresponding explanation.

[0051] In this embodiment, the plurality of second chips 202 are also configured using chips of different functional types, which can complement or coordinate with the first chip 102 in the first package. The first package and the second package are formed simultaneously, which helps to shorten the overall manufacturing cycle, improve process consistency and alignment accuracy, and facilitate the matching and optimization of the package structures on both sides, thereby improving the yield and reliability of subsequent side hybrid bonding.

[0052] Please refer to Figure 6 The first package is edge-processed to form a first bonding surface on the side of the first package, the first bonding surface exposing the first conductive structure; the second package is edge-processed to form a second bonding surface on the side of the second package, the second bonding surface exposing the second conductive structure.

[0053] In this embodiment, the method for edge processing of the first package includes: grinding the side of the first package until the first copper pillar 101 is exposed to form the first bonding surface; the method for edge processing of the second package includes: grinding the side of the second package until the second copper pillar 201 is exposed to form the second bonding surface.

[0054] It should be noted that before performing side-to-side hybrid bonding of the first package and the second package, it is necessary to accurately calculate the position distribution and contact area of ​​the exposed copper pillars on the bonding surfaces of the two packages, establish a spatial coordinate mapping relationship to ensure alignment accuracy, verify the position matching degree and area symmetry of the conductive structures on both sides, and thus formulate a precise bonding alignment strategy to avoid problems such as poor contact, uneven resistance or bonding failure caused by position deviation.

[0055] Please continue to refer to this. Figure 6 In this embodiment, after edge processing of the first package and the second package, the first bonding surface and the second bonding surface are cleaned.

[0056] In this embodiment, the cleaning process includes: performing RCA cleaning on the first bonding surface and the second bonding surface; performing acid cleaning after the RCA cleaning; and performing plasma cleaning with hydrogen or argon after the acid cleaning.

[0057] The cleaning process employs a three-stage progressive procedure to thoroughly purify the bonding surfaces. First, RCA cleaning is performed, using a mixed solution of ammonia, hydrogen peroxide, and deionized water to remove organic contaminants and particulate impurities, restoring surface cleanliness. This is followed by acid cleaning, using a dilute acid solution to dissolve and remove metal oxides and inorganic residues, activating the copper pillar surface. Finally, hydrogen or argon plasma cleaning is performed, using inert or reducing plasma bombardment to further remove nanoscale residual contaminants and reduce copper oxide, while simultaneously improving surface micro-roughness, providing an atomically clean and highly active ideal interface for hybrid bonding.

[0058] Please refer to Figure 7 The first bonding surface and the second bonding surface are mixed and bonded to make the first conductive structure and the second conductive structure electrically connected.

[0059] By using the sides of the first and second packages as bonding surfaces, the two-dimensional surface contact is reduced to a unidirectional line contact (the width of the package side is significantly reduced compared to the width of its traditional bonding surface, and can be regarded as a one-dimensional line). Only the flatness of this side dimension needs to be ensured to meet the process window requirements for hybrid bonding. This dimensional reduction fundamentally reduces the difficulty of controlling surface morphology, significantly relaxes the precision dependence on planarization processes such as grinding or polishing, and breaks through the strict limitations of traditional wafer-level bonding on substrate size and shape. Hybrid bonding is no longer limited to circular silicon wafers but can be adapted to the hybrid bonding of large-size rectangular or square panel-level packages. Simultaneously, the linear characteristics of the side bonding surface significantly improve its tolerance to localized minor defects, avoiding the risk of overall bonding failure due to localized unevenness in surface contact, effectively improving the production yield and process stability of panel-level packaging. Furthermore, this structure breaks through the constraint of matching substrate sizes in traditional packaging, enabling flexible interconnection between substrates of different sizes or direct bonding between substrates and independent components, providing greater flexibility in design and manufacturing processes.

[0060] In this embodiment, the hybrid bonding process involves aligning and bonding the first bonding surface with the second bonding surface, and under specific temperature and pressure conditions, causing atomic diffusion and metal bonding to occur on the exposed copper pillar surfaces on both sides. At the same time, covalent bonding is formed between the dielectric layers, thereby achieving electrical interconnection between the first conductive structure and the second conductive structure and mechanical fixation of the package.

[0061] Please refer to Figure 8 After the first package and the second package are bonded together, a plurality of conductive plugs 300 are formed on the first package and the second package, and the plurality of conductive plugs 300 are electrically connected to the first package and the second package respectively; a molding compound 301 is formed on the first package and the second package, the molding compound 301 covers the conductive plugs 300 and exposes the surface of the conductive plugs 300; a top redistribution layer 302 is formed on the molding compound 301, and the top redistribution layer 302 is electrically connected to the conductive plugs 300.

[0062] It should be noted that in this embodiment, after the first package and the second package are hybrid bonded, the two packages only achieve local electrical contact through copper pillars at the side bonding surfaces, and a complete circuit interconnection path has not yet been formed between the first chip 102 and the second chip 202 inside each package. To achieve system-level functional integration and signal transmission between the packages, conductive plugs 300 need to be formed on the first package and the second package to establish vertical electrical connections with the conductive structures inside the two packages respectively. Then, the molding compound 301 is formed to cover the conductive plugs and provide structural protection, while exposing the top surface of the conductive plugs 300. Finally, the top redistribution layer 302 is formed on the surface of the molding compound 301 to lead out and redistribute the conductive plugs 300, thereby constructing a complete electrical interconnection network spanning the two packages and realizing collaborative work and system functions between the chips.

[0063] In this embodiment, the conductive plug 300 is formed by electroplating. Then, epoxy resin is coated on the package to form the molding layer 301, which covers the conductive plug 300 and fills the gaps. Finally, the molding layer 301 is ground until the surface of the conductive plug 300 is exposed, forming a flat top layer structure, which provides a flat surface for the preparation of the top redistribution layer 302.

[0064] Accordingly, this invention also provides a hybrid bonding board-level packaging structure, please refer to [link / reference]. Figure 8 The package includes: a first package having a first conductive structure, a side of the first package serving as a first bonding surface, the first bonding surface exposing the first conductive structure; a second package having a second conductive structure, a side of the second package serving as a second bonding surface, the second bonding surface exposing the second conductive structure; the first bonding surface and the second bonding surface are mixed-bonded, such that the first conductive structure and the second conductive structure are electrically connected.

[0065] Using the sides of the first and second packages as bonding surfaces reduces the two-dimensional surface contact to a unidirectional line contact (the width of the package side is significantly reduced compared to the width of its traditional bonding surface, and can be considered as a one-dimensional line). Ensuring the flatness of this side dimension is sufficient to meet the process window requirements for hybrid bonding. This dimensional reduction fundamentally reduces the difficulty of controlling surface morphology, significantly relaxes the precision dependence on planarization processes such as grinding or polishing, and breaks through the strict limitations of traditional wafer-level bonding on substrate size and shape. Hybrid bonding is no longer limited to circular silicon wafers but can be adapted to the hybrid bonding of large-size rectangular or square panel-level packages. Simultaneously, the linear characteristics of the side bonding surface significantly improve its tolerance to localized minor defects, avoiding the risk of overall bonding failure due to localized unevenness in surface contact, effectively improving the production yield and process stability of panel-level packaging. Furthermore, this structure breaks through the constraint of matching substrate sizes in traditional packaging, enabling flexible interconnection between substrates of different sizes or direct bonding between substrates and independent components, providing greater flexibility in design and manufacturing processes.

[0066] In this embodiment, the first package includes: a first board-level substrate 100; a plurality of first copper pillars 101 located on the first board-level substrate 100, the plurality of first copper pillars constituting the first conductive structure; a plurality of first chips 102, the first chips 102 being bonded to the first board-level substrate 100; and a first filler layer 103 located on the first board-level substrate 100, the first filler layer 103 covering the first chips 102 and the first copper pillars 101, and the first filler layer 103 exposing the surfaces of the first chips 102 and the first copper pillars 101.

[0067] In this embodiment, the second package includes: a second board-level substrate 200; a plurality of second copper pillars 201 located on the second board-level substrate 200, the plurality of second copper pillars constituting the second conductive structure; a plurality of second chips 202, the second chips 202 being bonded to the second board-level substrate 200; and a second filler layer 203 located on the second board-level substrate 200, the second filler layer 203 covering the second chips 202 and the second copper pillars 201, and the second filler layer 203 exposing the surfaces of the second chips 202 and the second copper pillars 201.

[0068] In this embodiment, it further includes: a molding layer 301 located on the first package and the second package; a plurality of conductive plugs 300 located within the molding layer 301, the plurality of conductive plugs 300 being electrically connected to the first package and the second package respectively; and a top redistribution layer 302 located on the molding layer 301, the top redistribution layer 302 being electrically connected to the conductive plugs 300.

[0069] Figure 9 This is a schematic diagram of a hybrid bonding board-level packaging structure according to another embodiment of the present invention.

[0070] This embodiment is based on the previous embodiment ( Figure 8 Based on the above embodiments, the hybrid bonding board-level packaging structure will be further described. Everything else is the same as in the previous embodiments, except that the first package and the second package have different structural forms. The following will provide a detailed description in conjunction with the accompanying drawings.

[0071] Please refer to Figure 9 The first package further includes a first redistribution layer 104 located on the first fill layer 103, the first redistribution layer 104 being electrically connected to the first chip 102 and the first copper pillar 101 respectively; the second package further includes a second redistribution layer 204 located on the second fill layer 203, the second redistribution layer 204 being electrically connected to the second chip 202 and the second copper pillar 201 respectively.

[0072] In this embodiment, the first redistribution layer 104 is formed after the first fill layer 103 is formed, and the second redistribution layer 204 is formed after the second fill layer 203 is formed.

[0073] In this packaging structure, the first package and the second package each independently have a first rewiring layer 104 and a second rewiring layer 204, respectively completing the electrical redistribution and interconnection between the internal chip and the copper pillars. This layered wiring design allows each package to pre-allocate and optimize its internal circuitry, decomposing the complex system-level wiring task into two relatively independent sub-module wirings, effectively reducing the wiring density and layer requirements of the final top rewiring layer 302. The top rewiring layer 302 formed on the molding compound 301 only needs to achieve the bridging interconnection between the two packages, significantly simplifying the complexity and process difficulty of the top-level wiring, thereby improving the overall packaging manufacturing yield and design flexibility.

[0074] Figure 10 This is a schematic diagram of a hybrid bonding board-level packaging structure according to another embodiment of the present invention.

[0075] This embodiment is based on the previous embodiment ( Figure 8 Based on the above embodiments, the hybrid bonding board-level packaging structure will be further described. Everything else is the same as in the previous embodiments, except that the structure of the second package is different. The following will provide a detailed description in conjunction with the accompanying drawings.

[0076] Please refer to Figure 10The second package includes: an integrated passive device package 400, the side of which exposes the second conductive structure 401; and a dielectric layer 402 located on the side of the integrated passive device package 400, the dielectric layer 402 filling the groove in the second conductive structure 401.

[0077] By side-bonding the integrated passive device package 400, the signal transmission distance between the passive device and the active chip is effectively shortened, thereby reducing parasitic inductance and capacitance, improving the circuit response speed and frequency characteristics, and improving the overall package electrical performance.

[0078] In this embodiment, the method of forming the second package includes: providing an integrated passive device package 400, wherein the side of the integrated passive device package 400 exposes the second conductive structure 401; forming a dielectric layer 402 on the side of the integrated passive device package 400, wherein the dielectric layer 402 fills the groove in the second conductive structure 401 and covers the second conductive structure 401; and polishing the dielectric layer 402 until the second conductive structure 401 is exposed.

[0079] It should be noted that in this embodiment, when the second package uses the integrated passive device package 400, since it is an existing finished product, the position and area of ​​the second conductive structure 401 exposed on the side are fixed and cannot be flexibly adjusted according to bonding requirements. Therefore, before designing and forming the first package, it is necessary to accurately measure the spatial distribution and geometric parameters of the second conductive structure 401 on the integrated passive device package 400 in advance, and based on this, reverse plan the position layout and area size of the first copper pillar 101 on the first board-level substrate 100 to ensure that the conductive structures on both sides can achieve a one-to-one precise match. This strategy of measurement before design makes the fabrication of the first package completely adaptable to the inherent structure of the existing integrated passive device package 400, thereby ensuring high alignment accuracy and reliable electrical connection in subsequent side hybrid bonding.

[0080] In this embodiment, the dielectric layer 402 formed in the second package is used to form a covalent bond with the side of the first filler layer 103 of the first package during the hybrid bonding process, providing mechanical support and sealing protection, while isolating adjacent conductive structures to prevent short circuits, ensuring the insulation reliability of the bonding surface, and creating a stable interface environment for copper-copper metal bonding.

[0081] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A hybrid bonding board-level packaging structure, characterized in that, include: A first package having a first conductive structure, the side of the first package serving as a first bonding surface, the first bonding surface exposing the first conductive structure; A second package having a second conductive structure, the side of the second package serving as a second bonding surface, the second bonding surface exposing the second conductive structure; The first bonding surface and the second bonding surface are mixed and bonded, so that the first conductive structure and the second conductive structure are electrically connected; The first package includes: a first board-level substrate; a plurality of first copper pillars located on the first board-level substrate, the plurality of first copper pillars constituting the first conductive structure; a plurality of first chips, the first chips being bonded to the first board-level substrate; and a first filler layer located on the first board-level substrate, the first filler layer covering the first chips and the first copper pillars, and the first filler layer exposing the surfaces of the first chips and the first copper pillars.

2. The hybrid bonding board-level packaging structure as described in claim 1, characterized in that, The first package further includes a first rewiring layer located on the first fill layer, the first rewiring layer being electrically connected to the first chip and the first copper pillar respectively.

3. The hybrid bonding board-level packaging structure as described in claim 1, characterized in that, The second package includes: a second board-level substrate; a plurality of second copper pillars located on the second board-level substrate, the plurality of second copper pillars constituting the second conductive structure; a plurality of second chips, the second chips being bonded to the second board-level substrate; and a second filler layer located on the second board-level substrate, the second filler layer covering the second chips and the second copper pillars, and the second filler layer exposing the surfaces of the second chips and the second copper pillars.

4. The hybrid bonding board-level packaging structure as described in claim 3, characterized in that, The second package further includes a second rewiring layer located on the second fill layer, the second rewiring layer being electrically connected to the second chip and the second copper pillar respectively.

5. The hybrid bonding board-level packaging structure as described in claim 1, characterized in that, The second package includes: an integrated passive device package, the sidewall of which exposes the second conductive structure, and a groove in the second conductive structure exposes a dielectric layer located on the sidewall of the integrated passive device package, the dielectric layer filling the groove in the second conductive structure.

6. The hybrid bonding board-level packaging structure as described in claim 1, characterized in that, Also includes: Molding layers located on the first package and the second package; A plurality of conductive plugs are located within the molding compound, and the plurality of conductive plugs are electrically connected to the first package and the second package, respectively; a top redistribution layer is located on the molding compound, and the top redistribution layer is electrically connected to the conductive plugs.

7. A method for forming a hybrid bonding board-level packaging structure, characterized in that, include: A first package is formed, the first package having a first conductive structure; A second package is formed, the second package having a second conductive structure; The first package is edge-processed to form a first bonding surface on the sidewall of the first package, and the first bonding surface exposes the first conductive structure. The second package is edge-processed to form a second bonding surface on the sidewall of the second package, and the second bonding surface exposes the second conductive structure; The first bonding surface and the second bonding surface are mixed and bonded to make the first conductive structure and the second conductive structure electrically connected; The method of forming the first package includes: providing a first board-level substrate; forming a plurality of first copper pillars on the first board-level substrate, the plurality of first copper pillars constituting the first conductive structure; providing a plurality of first chips; bonding the first chips to the first board-level substrate; forming a first filler layer on the first board-level substrate, the first filler layer covering the first chips and the first copper pillars, and the first filler layer exposing the surfaces of the first chips and the first copper pillars.

8. The method for forming the hybrid bonding board-level packaging structure as described in claim 7, characterized in that, The method of forming the first package further includes: after forming the first fill layer, forming a first redistribution layer on the first fill layer, wherein the first redistribution layer is electrically connected to the first chip and the first copper pillar respectively.

9. The method for forming a hybrid bonding board-level package structure as described in claim 7 or 8, characterized in that, The method for edge processing of the first package includes: grinding the sidewall of the first package until the first copper pillar is exposed to form the first bonding surface.

10. The method for forming the hybrid bonding board-level packaging structure as described in claim 7, characterized in that, The method of forming the second package includes: providing a second board-level substrate; forming a plurality of second copper pillars on the second board-level substrate, the plurality of second copper pillars constituting the second conductive structure; providing a plurality of second chips; bonding the second chips to the second board-level substrate; and forming a second filler layer on the second board-level substrate, the second filler layer covering the second chips and the second copper pillars.

11. The method for forming the hybrid bonding board-level packaging structure as described in claim 10, characterized in that, The method of forming the second package further includes: after forming the second fill layer, forming a second redistribution layer on the second fill layer, the second redistribution layer being electrically connected to the second chip and the second copper pillar respectively.

12. The method for forming a hybrid bonding board-level package structure as described in claim 10 or 11, characterized in that, The method for edge processing of the second package includes: grinding the sidewall of the second package until the second copper pillar is exposed to form the second bonding surface.

13. The method for forming the hybrid bonding board-level packaging structure as described in claim 7, characterized in that, The method of forming the second package includes: providing an integrated passive device package, the sidewalls of the integrated passive device package exposing the second conductive structure and a groove in the second conductive structure; forming a dielectric layer on the sidewalls of the integrated passive device package, the dielectric layer filling the groove in the second conductive structure and covering the second conductive structure; and polishing the dielectric layer until the second conductive structure is exposed.

14. The method for forming the hybrid bonding board-level packaging structure as described in claim 7, characterized in that, After edge processing of the first package and the second package, the method further includes cleaning the first bonding surface and the second bonding surface.

15. The method for forming the hybrid bonding board-level packaging structure as described in claim 14, characterized in that, The cleaning process includes: performing RCA cleaning on the first bonding surface and the second bonding surface; performing acid cleaning after the RCA cleaning; and performing plasma cleaning with hydrogen or argon after the acid cleaning.

16. The method for forming a hybrid bonding board-level package structure as described in claim 7, characterized in that, After the first package and the second package are hybrid bonded, the method further includes: forming a plurality of conductive plugs on the first package and the second package, the plurality of conductive plugs being electrically connected to the first package and the second package respectively; forming a molding compound on the first package and the second package, the molding compound covering the conductive plugs and exposing the surfaces of the conductive plugs; and forming a top redistribution layer on the molding compound, the top redistribution layer being electrically connected to the conductive plugs.

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