A power device dynamic parameter testing circuit, method and product

Abstract

The application discloses a power device dynamic parameter test circuit, method and product for the field of semiconductor device testing, which comprises an upper test capacitor module and a lower test capacitor module; the upper test capacitor module is composed of a support capacitor, an absorption capacitor and an upper protection switch; the support capacitor is connected with a positive electrode of an input power supply and the upper protection switch; the upper protection switch is connected with the absorption capacitor and a positive electrode of an output test voltage; the support capacitor and the absorption capacitor are connected with each other to form an upper connection end; the lower test capacitor module is symmetrical with the upper test capacitor module in structure; the support capacitor and the absorption capacitor are connected with each other to form a lower connection end; the upper connection end and the lower connection end are connected with each other to form an equipotential midpoint; the positive electrode of the output test voltage and a negative electrode of the output test voltage are connected with a device under test (DUT) to provide a test voltage for the DUT. The application can make the power device test system have a higher withstand voltage level on the basis of considering the system cost.

Description

Technical Field

[0001] This application relates to a power device dynamic parameter testing circuit, method, and product for use in the field of semiconductor device testing. Background Technology

[0002] For various high-power consumption and power transmission scenarios, increasing voltage is a key means to improve power utilization efficiency. Increasing voltage can significantly reduce current while maintaining the same transmission power, thereby reducing losses. Consequently, wide-bandgap semiconductor technologies, represented by SiC, are rapidly developing towards higher voltage levels. SiC semiconductor materials possess high breakdown electric field strength and wide bandgap characteristics, allowing SiC devices to achieve high breakdown voltage in thinner, more heavily doped drift regions, thus reducing on-resistance and losses.

[0003] To accommodate the high-voltage performance of SiC semiconductors, the voltage of the SiC device testing system also needs to be increased to the corresponding level to simulate the voltage of the actual operating environment. Existing device testing systems are mainly designed for medium and high voltage testing, including 650V, 800V, and 1200V. These systems are equipped with protection circuits to promptly disconnect the device under test from the test circuit when a shoot-through fault occurs, preventing irreversible damage to the testing system from sudden surge currents.

[0004] When higher test voltages are required, such as 2000V, 3300V, or even higher voltages in the test system, the withstand voltage ratings of all major components and related protection circuits within the test system must be increased to the corresponding level. This leads to difficulties in selecting test system components and a surge in costs. Summary of the Invention

[0005] The purpose of this application is to overcome the shortcomings of the prior art and provide a power device dynamic parameter testing circuit, method and product that can enable the power device testing system to have a higher withstand voltage level while taking into account system cost.

[0006] Firstly, this application provides a power device dynamic parameter testing circuit for performing characteristic testing on the device under test (DUT), employing the following technical solution: The test circuit includes an upper test capacitor module and a lower test capacitor module; The upper test capacitor module consists of a supporting capacitor, an absorption capacitor, and an upper protection switch. One end of the supporting capacitor is connected to the positive terminal of the input power supply and one end of the upper protection switch in sequence. The other end of the upper protection switch is connected to one end of the absorption capacitor and the positive terminal of the output test voltage. The other end of the supporting capacitor and the other end of the absorption capacitor are connected to each other to form an upper connection terminal. The lower test capacitor module consists of a support capacitor, an absorption capacitor, and a lower protection switch. One end of the support capacitor is connected to the negative terminal of the input power supply and one end of the lower protection switch in sequence. The other end of the lower protection switch is connected to one end of the absorption capacitor and the negative terminal of the output test voltage. The other end of the support capacitor and the other end of the absorption capacitor are connected to each other to form a lower connection terminal. The upper connection end and the lower connection end are connected to each other to form an equipotential midpoint; The positive and negative terminals of the output test voltage are connected to the device under test (DUT) to provide a test voltage to the DUT.

[0007] By adopting the above technical solution, an upper test capacitor module and a lower test capacitor module are constructed, allowing each module to withstand only half of the bus voltage. This significantly reduces the difficulty and cost of selecting support capacitors, absorption capacitors, and protection switches. The equipotential midpoint connecting the upper and lower test capacitor modules is forcibly anchored to the potential reference point, greatly suppressing voltage imbalance between them. This ensures that when the device under test (DUT) experiences a shoot-through fault, the voltage across the upper and lower protection switches is defined and controllable, rather than an unpredictable floating dynamic high voltage. This prevents any single test capacitor module from bearing all or most of the voltage and immediately overvoltage breakdown, reduces the performance requirements of the protection switch, and ensures reliable shutdown by separately cutting off the discharge circuits of the upper and lower test capacitor modules.

[0008] Preferably, the supporting capacitor is a supporting capacitor group composed of several supporting capacitor units Cm connected in series, and each supporting capacitor unit Cm is connected in parallel with a switching switch, which controls the connection or disconnection of the supporting capacitor unit Cm. The supporting capacitor group of the upper test capacitor module and the supporting capacitor group of the lower test capacitor module are structurally symmetrical, and the number of supporting capacitor units Cm is the same.

[0009] By adopting the above technical solution, the number of supporting capacitor units Cm that are put into and cut out can be controlled according to the test voltage level of the power device, so that the number of online supporting capacitor units Cm is adapted to the test voltage, thereby reducing the device performance requirements of a single supporting capacitor unit Cm, ensuring that the supporting capacitor unit Cm operates within a safe range, reducing the aging rate of the capacitor dielectric under high voltage, and improving the lifespan of the test system and the stability of the test data.

[0010] Preferably, the absorption capacitor is an absorption capacitor group composed of several absorption capacitor units Cs connected in series, and each absorption capacitor unit Cs is connected in parallel with a switching switch, which controls the connection or disconnection of the absorption capacitor unit Cs. The absorption capacitor group of the upper test capacitor module and the absorption capacitor group of the lower test capacitor module are structurally symmetrical, and the number of absorption capacitor units Cs is the same.

[0011] By adopting the above technical solution, the number of absorption capacitor units Cs that are put on and cut off can be controlled according to the test voltage level of the power device, so that the number of online absorption capacitor units Cs can meet the requirements of absorbing the drain-source voltage spike of the device under test (DUT) at the current test voltage level.

[0012] Preferably, the upper protection switch is a MOSFET Q1 and the lower protection switch is a MOSFET Q2; The positive terminal of the input power supply is connected to the drain of the MOSFET Q1, the positive terminal of the output test voltage is connected to the source of the MOSFET Q1, and the gate of the MOSFET Q1 is controlled by the upper switch drive signal. The negative terminal of the input power supply is connected to the source of MOSFET Q2, the negative terminal of the output test voltage is connected to the drain of MOSFET Q2, and the gate of MOSFET Q2 is controlled by the lower switch drive signal. The upper switch drive signal and the lower switch drive signal are respectively connected to the shoot-through fault signal source of the device under test (DUT), and control the MOSFET Q1 and MOSFET Q2 to turn off in response to the shoot-through fault signal generated by the DUT.

[0013] Preferably, the upper switch drive signal and the lower switch drive signal are interlocked for shutdown. When either the upper switch drive signal or the lower switch signal responds to the shoot-through fault signal to control the MOS transistor Q1 or MOS segment Q2 to turn off, the other MOS transistor is interlocked for shutdown.

[0014] By adopting the above technical solution, the upper and lower protection switches can automatically shut down in response to the shoot-through fault signal of the device under test (DUT), thus achieving effective protection of the test circuit. The upper switch drive signal and the lower switch drive signal are interlocked for shutdown, so that the upper and lower protection switches can also be shut down in conjunction, which can prevent any one of the switch drive signals from failing due to a single point fault.

[0015] Preferably, the equipotential midpoint is connected to the N-pole of the output test voltage to achieve connection with the three-phase device under test.

[0016] By adopting the above technical solution, the test circuit can be adapted to three-phase devices under test.

[0017] Secondly, this application provides a method for testing the dynamic parameters of power devices, based on the aforementioned test circuit, comprising the following steps: S100, Configure the test circuit based on the test task of the device under test (DUT); S200, connect the device under test (DUT) to the test circuit; S300, turns on the upper and lower protection switches to precharge the support capacitor; The S400 performs characteristic tests on the device under test (DUT) and monitors the shoot-through fault signal of the DUT in real time. S500, the upper and lower protection switches disconnect synchronously in response to the detected shoot-through fault signal of the device under test (DUT).

[0018] Preferably, in S100, the configuration of the test circuit includes configuring the support capacitor and absorption capacitor based on the voltage level of the test task, and configuring the output test voltage port of the test circuit based on the type of the device under test (DUT) and the test requirements.

[0019] Preferably, after the upper and lower protection switches are simultaneously disconnected due to the shoot-through fault signal of the device under test (DUT), and before resetting the upper and lower protection switches, withstand voltage characteristic tests are performed on the upper and lower protection switches respectively.

[0020] Thirdly, this application provides a computer program product, including a computer program or instructions, which enables the computer program or instructions to implement the steps in the above-mentioned power device dynamic parameter testing method.

[0021] In summary, this application includes at least one of the following beneficial technical effects: 1. The system architecture for dynamic parameter testing of power devices in this application has the protection capability to withstand high voltage levels, and can realize the testing of power semiconductor devices with higher operating voltage levels.

[0022] 2. This application, while ensuring voltage withstand level, reduces the voltage withstand level requirements for each circuit component, expands the scope of circuit components, and reduces the difficulty of selection and system design cost.

[0023] 3. This application can conveniently and efficiently adapt and switch the circuit according to the test voltage level requirements of the device under test, without having to configure different test systems for different test voltages, thus expanding the application scope of a single system, reducing test costs, and improving test efficiency. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the power device dynamic parameter testing circuit according to an embodiment of this application; Figure 2 This is a logic architecture diagram of the third and fourth drive signals being turned off and interlocked according to an embodiment of this application. Figure 3 This is a schematic diagram of the power device dynamic parameter testing circuit using a supporting capacitor bank and an absorption capacitor bank, according to an embodiment of this application. Figure 4 This is a schematic diagram of the connection between the power device dynamic parameter testing circuit and the three-phase device under test according to an embodiment of this application; Figure 5 This is a flowchart illustrating the power device dynamic parameter testing method according to an embodiment of this application; Figure 6 This is a schematic diagram of the architecture of an exemplary computer device according to an embodiment of this application. Detailed Implementation

[0025] This specific embodiment is merely an explanation of this application and is not intended to limit it. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of this application.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that in the optional embodiments of this application, the object information and other related data involved require the permission or consent of the object when the embodiments of this application are applied to specific products or technologies, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. That is to say, if the embodiments of this application involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations, and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information requires the consent of the individual. If sensitive information is involved, the separate consent of the information subject is required, and the embodiments also need to be implemented with the authorization and consent of the object.

[0027] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0028] This application discloses a power device dynamic parameter testing circuit for testing the dynamic parameters of semiconductor power devices operating at medium to high voltage and high voltage. To realistically simulate the operating state of power devices in practical applications and accurately evaluate their key dynamic performance, a half-bridge circuit is typically used as the connection method between the power device and the test circuit. The half-bridge circuit is a core topology of power converters such as inverters and frequency converters, capable of reproducing the real electrical stresses experienced by the device under test during switching, including voltage and current change rates. The half-bridge circuit module housing the power device under test is called a half-bridge DUT. The half-bridge DUT typically requires a first drive signal and a second drive signal as test signals to test various dynamic parameters of the device under test.

[0029] Please see Figure 1 An embodiment of this application provides a power device dynamic parameter testing circuit, which includes an upper test capacitor module 1 and a lower test capacitor module 2.

[0030] The upper test capacitor module 1 consists of an upper support capacitor 11, an upper absorption capacitor 12, and an upper protection switch Q1. One end of the upper support capacitor 11 is connected in sequence to the positive terminal of the input power supply BUS+ and the drain of the upper protection switch Q1. The source of the upper protection switch Q1 is connected to one end of the upper absorption capacitor 12 and the positive terminal of the output test voltage MOD_BUS+. The other end of the upper support capacitor 11 and the other end of the upper absorption capacitor 12 are connected to each other to form the upper connection terminal O1.

[0031] The lower test capacitor module 2 consists of a lower support capacitor 21, a lower absorption capacitor 22, and a lower protection switch Q2. One end of the lower support capacitor 21 is connected in sequence to the negative terminal of the input power supply BUS- and the source of the lower protection switch Q2. The drain of the lower protection switch Q2 is connected to one end of the lower absorption capacitor 22 and the negative terminal of the output test voltage MOD_BUS-. The other end of the lower support capacitor 21 and the other end of the lower absorption capacitor 22 are connected to each other to form the lower connection terminal O2.

[0032] The upper connection terminal O1 and the lower connection terminal O2 are connected to each other to form an equipotential midpoint.

[0033] The positive terminal of the output test voltage, MOD_BUS+, and the negative terminal of the output test voltage, MOD_BUS-, are connected to the half-bridge DUT to provide test voltage for the power device under test.

[0034] The upper support capacitor 11 and lower support capacitor 21 provide energy for the turn-on, turn-off, reverse recovery, and short-circuit testing of the device under test (DUT). The upper absorption capacitor 12 and lower absorption capacitor 22 absorb drain-source voltage spikes from the DUT. The upper protection switch Q1 is a high-speed protection device between the upper support capacitor 11 and the upper absorption capacitor 12. It is used to quickly disconnect the connection between the upper support capacitor 11 and the upper absorption capacitor 12 when a shoot-through occurs in the half-bridge DUT, thus protecting the test system. The gate of the upper protection switch Q1 is connected to the third drive signal.

[0035] The functions of the lower support capacitor 21, lower absorption capacitor 22, and lower protection switch Q2 in the lower test capacitor module 2 are similar to those in the upper test capacitor module 1. The gate of the lower protection switch Q2 is connected to the fourth drive signal.

[0036] The third and fourth drive signals are respectively connected to the shoot-through fault signal source of the half-bridge DUT, and control the upper protection switch Q1 and the lower protection switch Q2 to turn off in response to the shoot-through fault signal generated by the half-bridge DUT. The shoot-through fault signal of the half-bridge DUT is the current signal of the main circuit sensor. Once a sharp rise in the current in the circuit is detected, it indicates that the half-bridge DUT is at risk of shoot-through. The upper protection switch Q1 and the lower protection switch Q2 respond to turn off, cutting off the power supply circuit and preventing the surge current from damaging the test circuit. The upper absorption capacitor 12 and the lower absorption capacitor 22 are usually used to suppress voltage spikes during the test. When the upper protection switch Q1 and the lower protection switch Q2 are turned off, the upper absorption capacitor 12 and the lower absorption capacitor 22 form an independent LC oscillation circuit with the stray inductance in the system. Since the main circuit is cut off, this oscillation is local and has limited energy. The energy will form a damped oscillation in the local LC oscillation circuit until it is completely consumed by the parasitic resistance in the circuit.

[0037] It should be noted that since the upper connection terminal O1 and the lower connection terminal O2 are interconnected, forming an equipotential midpoint, the bus voltage from BUS+ to BUS- is divided into two half-voltage domains. This reduces the maximum steady-state voltage that the upper protection switch Q1 and the lower protection switch Q2 need to withstand to half of the bus voltage. This significantly reduces the withstand voltage requirements for the upper protection switch Q1 and the lower protection switch Q2. For a test voltage of 2000V, a protection switch with a withstand voltage of 1200V is sufficient to meet the design requirements. At the same time, the lower withstand voltage requirement allows for a wider range of choices in terms of device type, switching speed, and equipment cost, making it easier to select devices with higher cost-effectiveness and that meet performance requirements.

[0038] In another embodiment, the third drive signal and the fourth drive signal are interlocked for shutdown. When either the third drive signal or the fourth switch signal responds to a through-fault signal to control the upper protection switch Q1 or the lower protection switch Q2 to shut down, the other protection switch is interlocked for shutdown. The upper protection switch Q1 and the lower protection switch Q2 achieve linked shutdown based on either drive signal, which can prevent the protection switch on any one of the switch drive signals from failing due to a single point fault, thus avoiding a single protection switch bearing all the voltage stress.

[0039] Please see Figure 2 One specific implementation is as follows: When the enable pins of the third and fourth drive signals are set to low level, the corresponding protection switches are turned off. The third drive signal is connected to one end of a first-level AND gate U1 and one end of a second-level AND gate U2, respectively. The fourth drive signal is connected to the other end of the first-level AND gate U1 and one end of another second-level AND gate U2, respectively. The output of the first-level AND gate U1 is connected to the other ends of the two second-level AND gates U2, and the outputs of the two second-level AND gates U2 are connected to the gates of the upper protection switch Q1 and the lower protection switch Q2, respectively.

[0040] Under normal test conditions, there is no through-fault signal, the enable pins of the third and fourth drive signals are both high, the first-level AND gate U1 and the second-level AND gate U2 both output high level, the protection switch is normally turned on, and the power supply circuit of the test voltage is turned on.

[0041] When the half-bridge DUT is shot-through, a shot-through fault signal is issued. If the signal feedback and control path of the third and fourth drive signals are normal, the enable pins of the third and fourth drive signals will switch to low level in response to the shot-through fault signal, and both the first-level AND gate U1 and the second-level AND gate U2 will output low level, controlling the upper protection switch Q1 and the lower protection switch Q2 to turn off.

[0042] In another scenario, when the half-bridge DUT is shoot-through, assuming there is a fault in the shoot-through fault signal feedback link or control link of the fourth drive signal, the enable pin fails to switch to a low level in response to the shoot-through fault signal. In this case, the input of the first-stage AND gate U1 is the low level of the third drive signal and the high level of the fourth drive signal, and it still outputs a low level. The input of the second-stage AND gate U2, connected to the fourth drive signal, is the low level of the first-stage AND gate U1 and the high level of the fourth drive signal, and it also outputs a low level, thus still ensuring that the lower protection switch Q2 and the upper protection switch Q1 are synchronously turned off.

[0043] Please see Figure 3In another embodiment, the upper supporting capacitor 11 and the lower supporting capacitor 21 are a group of supporting capacitors consisting of several supporting capacitor units Cm connected in series. Each supporting capacitor unit Cm is connected in parallel with a switching switch K1, which controls the connection or disconnection of the supporting capacitor unit Cm. Selecting a number of supporting capacitor units Cm that are appropriately matched to the test voltage level of the half-bridge DUT reduces the voltage drop across a single supporting capacitor unit Cm, significantly reducing the voltage stress on a single capacitor. This solution reduces the withstand voltage requirement of a single supporting capacitor unit Cm, eliminating the need to adjust or use supporting capacitor units Cm with higher withstand voltage levels as the test voltage level increases. It also allows the supporting capacitor units Cm to operate within a stable voltage range, extending the system's lifespan. In the embodiments of this application, the series connection of two supporting capacitor units Cm is used as an example. Those skilled in the art will understand that the specific number of supporting capacitor units Cm can be selected according to the capacitor type and the test voltage level.

[0044] The supporting capacitor group of the upper test capacitor module 1 and the supporting capacitor group of the lower test capacitor module 2 are symmetrical in structure, and the number of supporting capacitor units Cm is the same to ensure voltage division symmetry.

[0045] Correspondingly, the upper absorption capacitor 12 and the lower absorption capacitor 22 can also be an absorption capacitor group composed of several absorption capacitor units Cs connected in series. Each absorption capacitor unit Cs is connected in parallel with a switching switch K2, which controls the activation or deactivation of the absorption capacitor unit Cs. The absorption capacitor group of the upper test capacitor module and the absorption capacitor group of the lower test capacitor module are structurally symmetrical, and the number of activated absorption capacitor units Cs is the same. The number of absorption capacitor units Cs is selected based on the drain-source voltage spikes of the half-bridge DUT to be absorbed and the potential shoot-through fault risk, and its number does not need to be the same as the number of supporting capacitor units Cm.

[0046] Please see Figure 4 In another embodiment, the equipotential midpoint is connected to the N pole of the output test voltage to achieve connection with the three-phase device under test.

[0047] Those skilled in the art will understand that the structures shown in the above embodiments are merely circuit diagrams of the parts related to the present application solution, and do not constitute a limitation on the circuit structure to which the present application solution is applied. The specific circuit structure may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0048] Please see Figure 5 The present application discloses a method for testing dynamic parameters of power devices, which is based on the above-mentioned test circuit and includes the following steps.

[0049] S100 configures the test circuit based on the test task of the device under test (DUT).

[0050] More specifically, the configuration of the test circuit includes configuring the number of supporting capacitors and absorption capacitors based on the voltage level of the test task, and setting the current warning threshold for the shoot-through fault signal.

[0051] S200 connects the device under test (DUT) to the half-bridge DUT and then connects the half-bridge DUT to the test system.

[0052] S300 precharges the support capacitor and the absorption capacitor.

[0053] One specific implementation involves activating the upper and lower protection switches, pre-charging the supporting and absorbing capacitors using the test voltage. At this time, the main control switch of the test system prevents the initiation of characteristic testing of the device under test (DUT).

[0054] Another feasible implementation is to disconnect the upper and lower protection switches and precharge the support and absorption capacitors using an external power supply. Since the upper and lower protection switches are disconnected, the DUT characteristic test is naturally interrupted.

[0055] S400 initiates characteristic testing of the device under test (DUT) and monitors the DUT's shoot-through fault signal in real time.

[0056] S500, the upper and lower protection switches disconnect synchronously in response to the detected shoot-through fault signal of the device under test (DUT).

[0057] After the upper and lower protection switches are simultaneously disconnected due to the shoot-through fault signal of the device under test (DUT), the withstand voltage characteristics of the upper and lower protection switches are tested respectively before resetting them.

[0058] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0059] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the power device dynamic parameter testing method described above can be referred to the corresponding content in the aforementioned circuit embodiments, and will not be repeated here.

[0060] In one embodiment, a computer device is provided, the internal structure of which can be shown in the figure below. Figure 6As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores test logs for dynamic parameter testing of power devices. The network interface communicates with the half-bridge DUT via a network connection, transmitting test commands and acquiring test parameters. When executed by the processor, the computer program implements a method for dynamic parameter testing of power devices.

[0061] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A dynamic parameter testing circuit for power devices, used to perform characteristic testing on the device under test (DUT), characterized in that, Includes an upper test capacitor module and a lower test capacitor module; The upper test capacitor module consists of a supporting capacitor, an absorption capacitor, and an upper protection switch. One end of the supporting capacitor is connected to the positive terminal of the input power supply and one end of the upper protection switch in sequence. The other end of the upper protection switch is connected to one end of the absorption capacitor and the positive terminal of the output test voltage. The other end of the supporting capacitor and the other end of the absorption capacitor are connected to each other to form an upper connection terminal. The lower test capacitor module consists of a support capacitor, an absorption capacitor, and a lower protection switch. One end of the support capacitor is connected to the negative terminal of the input power supply and one end of the lower protection switch in sequence. The other end of the lower protection switch is connected to one end of the absorption capacitor and the negative terminal of the output test voltage. The other end of the support capacitor and the other end of the absorption capacitor are connected to each other to form a lower connection terminal. The upper connection end and the lower connection end are connected to each other to form an equipotential midpoint; The positive and negative terminals of the output test voltage are connected to the device under test (DUT) to provide a test voltage to the DUT.

2. The power device dynamic parameter testing circuit according to claim 1, characterized in that, The supporting capacitor is a supporting capacitor group composed of several supporting capacitor units Cm connected in series. Each supporting capacitor unit Cm is connected in parallel with a switching switch, which controls the connection or disconnection of the supporting capacitor unit Cm. The supporting capacitor group of the upper test capacitor module and the supporting capacitor group of the lower test capacitor module are structurally symmetrical, and the number of supporting capacitor units Cm is the same.

3. The power device dynamic parameter testing circuit according to claim 2, characterized in that, The absorption capacitor is an absorption capacitor group composed of several absorption capacitor units Cs connected in series. Each absorption capacitor unit Cs is connected in parallel with a switching switch, which controls the connection or disconnection of the absorption capacitor unit Cs. The absorption capacitor group of the upper test capacitor module and the absorption capacitor group of the lower test capacitor module are structurally symmetrical, and the number of absorption capacitor units Cs is the same.

4. The power device dynamic parameter testing circuit according to claim 1, characterized in that, The upper protection switch is a MOSFET Q1, and the lower protection switch is a MOSFET Q2; The positive terminal of the input power supply is connected to the drain of the MOSFET Q1, the positive terminal of the output test voltage is connected to the source of the MOSFET Q1, and the gate of the MOSFET Q1 is controlled by the upper switch drive signal. The negative terminal of the input power supply is connected to the source of MOSFET Q2, the negative terminal of the output test voltage is connected to the drain of MOSFET Q2, and the gate of MOSFET Q2 is controlled by the lower switch drive signal. The upper switch drive signal and the lower switch drive signal are respectively connected to the shoot-through fault signal source of the device under test (DUT), and control the MOSFET Q1 and MOSFET Q2 to turn off in response to the shoot-through fault signal generated by the DUT.

5. The power device dynamic parameter testing circuit according to claim 4, characterized in that, The upper switch drive signal and the lower switch drive signal are interlocked for shutdown. When either the upper switch drive signal or the lower switch signal responds to the shoot-through fault signal to control the MOS transistor Q1 or MOS segment Q2 to turn off, the other MOS transistor Q2 or MOS transistor Q1 is interlocked for shutdown.

6. The power device dynamic parameter testing circuit according to claim 1, characterized in that, The equipotential midpoint is connected to the N pole of the output test voltage to achieve connection with the three-phase device under test.

7. A method for testing dynamic parameters of a power device, implemented based on the test circuit described in any one of claims 1 to 6, characterized in that, Includes the following steps: S100, Configure the test circuit based on the test task of the device under test (DUT); S200, connect the device under test (DUT) to the test circuit; S300, turns on the upper and lower protection switches to precharge the support capacitor and absorption capacitor; The S400 performs characteristic tests on the device under test (DUT) and monitors the shoot-through fault signal of the DUT in real time. S500, the upper and lower protection switches disconnect synchronously in response to the detected shoot-through fault signal of the device under test (DUT).

8. The method for testing dynamic parameters of a power device according to claim 7, characterized in that, In S100, the configuration of the test circuit includes configuring the support capacitor and absorption capacitor based on the voltage level of the test task, and configuring the output test voltage port of the test circuit based on the type of the device under test (DUT) and the test requirements.

9. The method for testing dynamic parameters of a power device according to claim 8, characterized in that, After the upper and lower protection switches are simultaneously disconnected due to the shoot-through fault signal of the device under test (DUT), the withstand voltage characteristics of the upper and lower protection switches are tested respectively before resetting them.

10. A computer program product, characterized in that, The computer program product includes a computer program or instructions that enable the computer program or instructions to perform the steps in the power device dynamic parameter testing method according to any one of claims 7 to 9.

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