LDO circuit with improved loop stability

Abstract

The application discloses an LDO circuit for improving loop stability, and relates to electronic circuits, and aims at the problem of unstable loop in the prior art. An internal ESR compensation module is arranged to generate a zero point for offsetting a secondary pole at the gate end of a power tube, and an output end signal is input to an inverting input end of an error amplifier through negative feedback; a buffer stage is configured with an adaptive load, and the adaptive load is used for dynamically changing the impedance of the gate of the power tube according to the size of a load current. The application has the advantages that a specific ESR value does not need to be provided by an external capacitor, a low ESR ceramic capacitor with low cost and small size can be selected as an output capacitor, and element specification limitation is reduced. When the compensation zero point has not appeared, the voltage at the two ends of the compensation resistor is equalized by using negative feedback, no current passes through, and thus direct current offset is avoided, so that the output voltage is more accurate. The impedance of the gate of the power tube can be dynamically adjusted according to the change of the load current, and this is beneficial to realizing loop stability in the full load range.

Description

Technical Field

[0001] This invention relates to electronic circuit technology, and more particularly to an LDO circuit for improving loop stability. Background Technology

[0002] Modern LDOs increasingly support higher load currents to meet the demands of high-performance RF and analog / mixed-signal subsystems. Providing a load current of 300 mA or greater often requires a larger power transistor, but this introduces larger parasitic capacitances. This causes the high output impedance of the error amplifier and the large parasitic capacitance of the power transistor to form a low-frequency pole, which is close to the dominant pole at the output, significantly reducing loop stability.

[0003] Traditional compensation methods utilize ESR compensation. The basic principle is to use the parasitic ESR resistance of the external capacitor to create a zero point, which cancels out the secondary pole of the system, thereby improving the stability of the LDO system. However, the ESR resistance is merely a parasitic parameter of the external capacitor, and its value is difficult to control accurately. The ESR resistance is also affected by other factors such as temperature, voltage, frequency, and materials. If the ESR resistance varies too much, the generated ESR zero may not accurately cancel out the effect of the non-dominant pole, failing to guarantee system stability. Furthermore, a larger ESR resistance can increase voltage fluctuations at the LDO's output during sudden current changes.

[0004] Currently, a common method to improve the stability of LDO circuits is to insert a buffer stage between the error amplifier and the power transistor. The buffer stage reduces the equivalent impedance at the gate connection of the power transistor, pushing the gate poles of the power transistor far away from the unity-gain bandwidth. In addition, due to the addition of the buffer stage, the parasitic capacitance at the output node of the error amplifier is much smaller than the parasitic capacitance at the gate of the power transistor, thereby pushing the poles at the output node of the error amplifier to higher frequencies.

[0005] However, as the load current increases, the dominant pole at the output will also shift to a higher frequency. Although inserting a buffer stage can shift the secondary pole from a low frequency to a high frequency, under high load current conditions, the secondary pole may still be located within the unity-gain bandwidth, causing loop instability. Therefore, additional compensation circuitry is required. Summary of the Invention

[0006] The purpose of this invention is to provide an LDO circuit that improves loop stability, thereby solving the problems existing in the prior art.

[0007] The LDO circuit for improving loop stability described in this invention includes a buffer stage between the error amplifier and the gate of the power transistor; the drain of the power transistor is the circuit output terminal; and the non-inverting input terminal of the error amplifier is the circuit input terminal. An internal ESR compensation module is provided, which generates a zero to cancel the secondary pole of the power transistor gate and inputs the output signal to the inverting input of the error amplifier through negative feedback. The buffer stage is equipped with an adaptive load, which is used to dynamically change the impedance of the power transistor gate according to the magnitude of the load current.

[0008] The specific structure of the LDO circuit for improving loop stability described in this invention is as follows: The non-inverting input of the error amplifier is connected to the input signal, the inverting input of the error amplifier is connected to node B, and the output of the error amplifier is connected to the gate of the first MOS transistor. The source of the first MOSFET is grounded, and the drain of the first MOSFET is connected to the drain of the second MOSFET. The source of the second MOSFET is connected to VDD, and the gate of the second MOSFET is connected to the drain of the second MOSFET. The source of the third MOSFET is grounded, the drain of the third MOSFET is connected to the source of the thirteenth MOSFET, and the gate of the third MOSFET is connected to the output of the auxiliary amplifier. The source of the fourth MOSFET is connected to VDD, the drain of the fourth MOSFET is connected to the source of the fourteenth MOSFET, and the gate of the fourth MOSFET is connected to the gate of the second MOSFET. The source of the fifth MOSFET is grounded, the drain of the fifth MOSFET is connected to the source of the fifteenth MOSFET, and the gate of the fifth MOSFET is connected to the output of the auxiliary amplifier after being connected in series with the first resistor. The source of the sixth MOSFET is connected to VDD, the drain of the sixth MOSFET is connected to the source of the sixteenth MOSFET, and the gate of the sixth MOSFET is connected to the gate of the second MOSFET. The source of the seventh MOSFET is grounded, and the drain and gate of the seventh MOSFET are shorted together and then an external bias current is applied. The source of the eighth MOSFET is connected to VDD, and the drain of the eighth MOSFET is shorted to the gate of the eighth MOSFET and then connected to the drain of the ninth MOSFET. The source of the ninth MOSFET is grounded, and the gate of the ninth MOSFET is connected to the gate of the seventh MOSFET. The source of the tenth MOSFET is connected to VDD, the drain of the tenth MOSFET is connected to node A, and the gate of the tenth MOSFET is connected to the gate of the eighth MOSFET. The source of the eleventh MOSFET is grounded, the drain of the eleventh MOSFET is connected to the gate of the seventeenth MOSFET, and the gate of the eleventh MOSFET is connected to the gate of the seventeenth MOSFET. The source of the twelfth MOS transistor is connected to VDD, the drain of the twelfth MOS transistor is connected to node B, and the gate of the twelfth MOS transistor is connected to the gate of the eighth MOS transistor. The drain of the thirteenth MOSFET is connected to node A, and the gate of the thirteenth MOSFET is connected to the second bias voltage. The drain of the fourteenth MOS transistor is connected to node A, and the gate of the fourteenth MOS transistor is connected to the first bias voltage; The drain of the fifteenth MOS transistor is connected to node B, and the gate of the fifteenth MOS transistor is connected to the second bias voltage. The drain of the sixteenth MOS transistor is connected to node B, and the gate of the sixteenth MOS transistor is connected to the first bias voltage. The source of the seventeenth MOSFET is connected to VDD, the drain of the seventeenth MOSFET is connected to the drain of the eleventh MOSFET after being connected in series with the second resistor, and the gate of the seventeenth MOSFET is connected to the drain of the second MOSFET. The power transistor's source is connected to VDD, its drain is connected to the output signal, and its gate is connected to the gate of the second MOSFET. The non-inverting input of the auxiliary amplifier is connected to node A, and the inverting input of the auxiliary amplifier is connected to the output signal. One end of the third resistor is connected to VDD, and the other end of the third resistor is connected to the drain of the second MOSFET. One end of the compensation resistor is connected to node B, and the other end of the compensation resistor is connected to the output signal. The output resistor and output capacitor are connected in series between the output signal and ground, respectively. The first capacitor is connected in series between the gate of the fifth MOSFET and ground.

[0009] The width-to-length ratio of the sixth MOSFET and the power transistor is 1:k; the value of k satisfies... .

[0010] The width-to-length ratio of the fourth MOS transistor and the sixth MOS transistor is 1:1.

[0011] The width-to-length ratio of the third MOS transistor and the fifth MOS transistor is 1:1.

[0012] The LDO circuit for improving loop stability described in this invention has the following advantages: (1) It adopts internal ESR compensation, which simulates the ESR of the output capacitor through the built-in circuit. It does not require an external capacitor to provide a specific ESR value. The output capacitor can be a low-cost, small-size low-ESR ceramic capacitor, reducing the limitations of component specifications. (2) It adopts an auxiliary amplifier. Before the compensation zero point appears, it uses negative feedback to make the voltage across the added compensation resistor equal, and no current flows through it, thereby avoiding DC offset and making the output voltage more accurate. (3) The buffer stage adopts an adaptive load, which can dynamically adjust the gate impedance of the power transistor according to the change of load current, which is conducive to achieving loop stability across the entire load range. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the LDO circuit described in this invention.

[0014] Figure 2 The LDO circuit described in this invention operates at a frequency of The equivalent circuit diagram at that time.

[0015] Figure 3 This is a simulated amplitude-frequency curve of the loop stability of the LDO circuit described in this invention.

[0016] Figure 4 This is a simulated phase-frequency curve of the loop stability of the LDO circuit described in this invention.

[0017] Figure reference numerals: M01 to M17 - first MOSFET to seventeenth MOSFET; Mpow - Power transistor; R1 - First resistor, R2 - Second resistor, R3 - Third resistor, R ESR_IN - Compensation resistor, RL- Output resistor; C1 - First capacitor, CL - Output capacitor; AMP - Auxiliary amplifier; EA - Error amplifier; VIN - Input signal, VOUT - Output signal, VFB - Feedback signal; VB1 - First bias voltage, VB2 - Second bias voltage; IBIAS - Bias Current. Detailed Implementation

[0018] The LDO circuit for improving loop stability described in this invention includes a buffer stage between the error amplifier EA and the gate of the power transistor Mpow; the drain of the power transistor Mpow is the circuit output terminal; and the non-inverting input terminal of the error amplifier EA is the circuit input terminal. An internal ESR compensation module is provided, which generates a zero to cancel the secondary pole of the power transistor gate and inputs the output signal to the inverting input of the error amplifier EA through negative feedback. The buffer stage is equipped with an adaptive load, which dynamically changes the gate impedance of the power transistor Mpow according to the magnitude of the load current. The load current is the current flowing through the output resistor RL.

[0019] like Figure 1 As shown, the specific structure of an LDO circuit for improving loop stability described in this invention is as follows: The non-inverting input of error amplifier EA is connected to the input signal VIN, the inverting input of error amplifier EA is connected to node B, and the output of error amplifier EA is connected to the gate of the first MOS transistor M01.

[0020] The source of the first MOSFET M01 is grounded, and the drain of the first MOSFET M01 is connected to the drain of the second MOSFET M02.

[0021] The source of the second MOSFET M02 is connected to VDD, and the gate of the second MOSFET M02 is connected to the drain of the second MOSFET M02.

[0022] The source of the third MOSFET M03 is grounded, the drain of the third MOSFET M03 is connected to the source of the thirteenth MOSFET M13, and the gate of the third MOSFET M03 is connected to the output of the auxiliary amplifier AMP.

[0023] The source of the fourth MOSFET M04 is connected to VDD, the drain of the fourth MOSFET M04 is connected to the source of the fourteenth MOSFET M14, and the gate of the fourth MOSFET M04 is connected to the gate of the second MOSFET M02.

[0024] The source of the fifth MOSFET M05 is grounded, the drain of the fifth MOSFET M05 is connected to the source of the fifteenth MOSFET M15, and the gate of the fifth MOSFET M05 is connected to the output of the auxiliary amplifier AMP after being connected in series with the first resistor R1.

[0025] The source of the sixth MOSFET M06 is connected to VDD, the drain of the sixth MOSFET M06 is connected to the source of the sixteenth MOSFET M16, and the gate of the sixth MOSFET M06 is connected to the gate of the second MOSFET M02.

[0026] The source of the seventh MOSFET M07 is grounded, and the drain and gate of the seventh MOSFET M07 are shorted together and then an external bias current IBIAS is applied.

[0027] The source of the eighth MOSFET M08 is connected to VDD, and the drain of the eighth MOSFET M08 is shorted to the gate of the eighth MOSFET M08 and then connected to the drain of the ninth MOSFET M09.

[0028] The source of the ninth MOSFET M09 is grounded, and the gate of the ninth MOSFET M09 is connected to the gate of the seventh MOSFET M07.

[0029] The source of the tenth MOSFET M10 is connected to VDD, the drain of the tenth MOSFET M10 is connected to node A, and the gate of the tenth MOSFET M10 is connected to the gate of the eighth MOSFET M08.

[0030] The source of the eleventh MOSFET M11 is grounded, the drain of the eleventh MOSFET M11 is connected to the gate of the seventeenth MOSFET M17, and the gate of the eleventh MOSFET M11 is connected to the gate of the seventh MOSFET M07.

[0031] The source of the twelfth MOSFET M12 is connected to VDD, the drain of the twelfth MOSFET M12 is connected to node B, and the gate of the twelfth MOSFET M12 is connected to the gate of the eighth MOSFET M08.

[0032] The drain of the thirteenth MOSFET M13 is connected to node A, and the gate of the thirteenth MOSFET M13 is connected to the second bias voltage VB2.

[0033] The drain of the fourteenth MOS transistor M14 is connected to node A, and the gate of the fourteenth MOS transistor M14 is connected to the first bias voltage VB1.

[0034] The drain of the fifteenth MOS transistor M15 is connected to node B, and the gate of the fifteenth MOS transistor M15 is connected to the second bias voltage VB2.

[0035] The drain of the sixteenth MOS transistor M16 is connected to node B, and the gate of the sixteenth MOS transistor M16 is connected to the first bias voltage VB1.

[0036] The source of the seventeenth MOSFET M17 is connected to VDD. The drain of the seventeenth MOSFET M17 is connected to the drain of the eleventh MOSFET M11 after being connected in series with the second resistor R2. The gate of the seventeenth MOSFET M17 is connected to the drain of the second MOSFET M02.

[0037] The source of the power transistor Mpow is connected to VDD, the drain of the power transistor Mpow is connected to the output signal VOUT, and the gate of the power transistor Mpow is connected to the gate of the second MOSFET M02.

[0038] The non-inverting input of the auxiliary amplifier AMP is connected to node A, and the inverting input of the auxiliary amplifier AMP is connected to the output signal VOUT.

[0039] One end of the third resistor R3 is connected to VDD, and the other end of the third resistor R3 is connected to the drain of the second MOSFET M02.

[0040] Compensation resistor R ESR_IN One end is connected to node B, and the compensation resistor R ESR_IN The other end is connected to the output signal VOUT.

[0041] The output resistor RL and the output capacitor CL are connected in series between the output signal VOUT and ground.

[0042] The first capacitor C1 is connected in series between the gate of the fifth MOSFET M05 and ground.

[0043] The first MOSFET M01 and the second MOSFET M02 constitute the buffer stage. A diode-connected device is used as the load, which reduces the gate impedance of the power transistor and pushes the pole at the gate of the power transistor to a higher frequency, which is beneficial to the stability of the loop.

[0044] The second MOSFET M02, the seventeenth MOSFET M17, the second resistor R2, and the third resistor R3 constitute an adaptive load, sharing the second MOSFET M02 with the buffer stage. The impedance of the power transistor gate can be dynamically changed according to the load current, which is beneficial for achieving loop stability across the entire load range. Under no-load conditions, the third resistor R3 acts as a load to maintain normal loop operation. When the load current is relatively small, the second MOSFET M02 is in the subthreshold region, and the impedance of the seventeenth MOSFET M17 is reduced due to the second resistor R2 being in the saturation region and the diode connection. When the load current is larger, the second MOSFET M02 enters the saturation region, and the gate impedance of the power transistor further decreases. The seventh MOSFET M07, the eighth MOSFET M08, the ninth MOSFET M09, the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 act as a bias circuit, providing appropriate bias current to ensure normal circuit operation.

[0045] The internal ESR compensation module consists of the third MOSFET M03, the fourth MOSFET M04, the fifth MOSFET M05, the sixth MOSFET M06, the thirteenth MOSFET M13, the fourteenth MOSFET M14, the fifteenth MOSFET M15, the sixteenth MOSFET M16, an auxiliary amplifier AMP, a first resistor R1, and a compensation resistor R. ESR_IN Together with the first capacitor C1, it forms a unit. The function of the intermediate auxiliary amplifier AMP is to adjust nodes A and B and the output signal VOUT, so that the compensation resistor R... ESR_IN The voltages at both ends are equal, ensuring that no current flows through the compensation resistor R under DC conditions. ESR_IN This makes the output voltage more accurate. The fourth MOSFET M04, the sixth MOSFET M06, the fourteenth MOSFET M14, and the sixteenth MOSFET M16 bias the third MOSFET M03, the fifth MOSFET M05, the thirteenth MOSFET M13, and the fifteenth MOSFET M15, respectively. The tenth MOSFET M10 and the twelfth MOSFET M12 also bias the third MOSFET M03, the fifth MOSFET M05, the thirteenth MOSFET M13, and the fifteenth MOSFET M15, respectively, to ensure sufficient bias current even under no-load conditions.

[0046] Disconnect the auxiliary amplifier AMP to calculate its input-to-output transfer function: ; Where gm is the equivalent transconductance of the auxiliary amplifier AMP, ro is the output resistance of the auxiliary amplifier AMP, gm3 is the transconductance of the third MOSFET M03, ro3 is the small-signal resistance of the third MOSFET M03, and C3 is the parasitic capacitance at the output. It can be seen that this loop has two poles and one zero. The dominant pole, determined by the first resistor R1 and the first capacitor C1, ensures stability, while the non-dominant pole remains outside the unity-gain bandwidth due to its relatively small parasitic capacitance.

[0047] The zero point of the internal ESR compensation is affected by the operating frequency of the AC signal. At that time, the zero-point compensation was not yet in operation. To avoid issues with the compensation resistor R... ESR_IN A voltage drop is generated across the two terminals. Using the auxiliary amplifier AMP, negative feedback ensures that the voltages at its positive and negative input terminals A and its output signal VOUT are equal. Since the ratio of the fourth MOSFET M04 to the sixth MOSFET M06 is 1:1, the currents in these two branches are equal. Furthermore, because the third MOSFET M03 and the fifth MOSFET M05 are of the same size, their gate voltages and drain voltages are equal, i.e., VA = VOUT and VA = VB, which in turn ensures that VB = VOUT, guaranteeing the compensation resistor R... ESR_IN The voltage across the terminals is zero.

[0048] when At that time, because the gates of the third MOSFET M03 and the fifth MOSFET M05 are at AC ground, the regulation of the auxiliary amplifier is deactivated. The actual circuit is as follows: Figure 2 As shown, the compensation resistor R ESR_IN Connecting it between the circuit output and the feedback, we can obtain: Since the W / L ratio of the sixth MOSFET M06 and the power transistor is 1:k, the current of the sixth MOSFET M06 is... , This refers to the power transistor current. The current flowing through the power transistor is equal to the output voltage divided by the output impedance. The output impedance can be expressed by the formula. Let represent this, and by substituting, we can obtain: ; Choose an appropriate k value so that We can obtain: ; Without loss of generality, the value of k satisfies That's all.

[0049] It can be seen that adding a compensation resistor R ESR_IN It can produce a The zero point of the magnitude is determined by setting the compensation resistor R. ESR_INThe resistance and k-value are used to compensate for the secondary poles, thereby improving loop stability.

[0050] Simulations were performed under various conditions, including light and heavy loads, variable gate impedance of the power transistor, and the presence or absence of compensation. The simulation data are summarized in the table below, yielding the simulated amplitude-frequency and phase-frequency curves for loop stability. Figure 3 , Figure 4 As shown.

[0051]

[0052] Simulation results show that adding adaptive load to the buffer stage effectively improves the phase margin under light load conditions, while the addition of the internal ESR compensation module effectively improves the phase margin under heavy load conditions. Therefore, the circuit structure proposed in this invention can effectively improve the stability of the LDO under both light and heavy load conditions.

[0053] For those skilled in the art, various other corresponding changes and modifications can be made based on the technical solutions and concepts described above, and all such changes and modifications should fall within the protection scope of the claims of this invention.

Claims

1. An LDO circuit for improving loop stability, comprising a buffer stage between the gate of an error amplifier (EA) and a power transistor (Mpow); the drain of the power transistor (Mpow) is the circuit output terminal; and the non-inverting input terminal of the error amplifier (EA) is the circuit input terminal. Its features are, An internal ESR compensation module is provided, which generates a zero to cancel the secondary pole of the power transistor gate and inputs the output signal to the inverting input of the error amplifier (EA) through negative feedback. The buffer stage is configured with an adaptive load, which is used to dynamically change the impedance of the power transistor (Mpow) gate according to the magnitude of the load current. The non-inverting input of the error amplifier (EA) is connected to the input signal (VIN), the inverting input of the error amplifier (EA) is connected to node B, and the output of the error amplifier (EA) is connected to the gate of the first MOS transistor (M01). The source of the first MOSFET (M01) is grounded, and the drain of the first MOSFET (M01) is connected to the drain of the second MOSFET (M02). The source of the second MOSFET (M02) is connected to VDD, and the gate of the second MOSFET (M02) is connected to the drain of the second MOSFET (M02). The source of the third MOSFET (M03) is grounded, the drain of the third MOSFET (M03) is connected to the source of the thirteenth MOSFET (M13), and the gate of the third MOSFET (M03) is connected to the output of the auxiliary amplifier (AMP). The source of the fourth MOSFET (M04) is connected to VDD, the drain of the fourth MOSFET (M04) is connected to the source of the fourteenth MOSFET (M14), and the gate of the fourth MOSFET (M04) is connected to the gate of the second MOSFET (M02). The source of the fifth MOSFET (M05) is grounded, the drain of the fifth MOSFET (M05) is connected to the source of the fifteenth MOSFET (M15), and the gate of the fifth MOSFET (M05) is connected to the output of the auxiliary amplifier (AMP) after being connected in series with the first resistor (R1). The source of the sixth MOSFET (M06) is connected to VDD, the drain of the sixth MOSFET (M06) is connected to the source of the sixteenth MOSFET (M16), and the gate of the sixth MOSFET (M06) is connected to the gate of the second MOSFET (M02). The source of the seventh MOSFET (M07) is grounded, and the drain and gate of the seventh MOSFET (M07) are shorted together and then an external bias current (IBIAS) is applied. The source of the eighth MOSFET (M08) is connected to VDD, and the drain of the eighth MOSFET (M08) is shorted to the gate of the eighth MOSFET (M08) and then connected to the drain of the ninth MOSFET (M09). The source of the ninth MOSFET (M09) is grounded, and the gate of the ninth MOSFET (M09) is connected to the gate of the seventh MOSFET (M07). The source of the tenth MOSFET (M10) is connected to VDD, the drain of the tenth MOSFET (M10) is connected to node A, and the gate of the tenth MOSFET (M10) is connected to the gate of the eighth MOSFET (M08). The source of the eleventh MOSFET (M11) is grounded, the drain of the eleventh MOSFET (M11) is connected to the gate of the seventeenth MOSFET (M17), and the gate of the eleventh MOSFET (M11) is connected to the gate of the seventh MOSFET (M07). The source of the twelfth MOS transistor (M12) is connected to VDD, the drain of the twelfth MOS transistor (M12) is connected to node B, and the gate of the twelfth MOS transistor (M12) is connected to the gate of the eighth MOS transistor (M08). The drain of the thirteenth MOSFET (M13) is connected to node A, and the gate of the thirteenth MOSFET (M13) is connected to the second bias voltage (VB2). The drain of the fourteenth MOS transistor (M14) is connected to node A, and the gate of the fourteenth MOS transistor (M14) is connected to the first bias voltage (VB1). The drain of the fifteenth MOS transistor (M15) is connected to node B, and the gate of the fifteenth MOS transistor (M15) is connected to the second bias voltage (VB2). The drain of the sixteenth MOS transistor (M16) is connected to node B, and the gate of the sixteenth MOS transistor (M16) is connected to the first bias voltage (VB1). The source of the seventeenth MOSFET (M17) is connected to VDD. The drain of the seventeenth MOSFET (M17) is connected to the drain of the eleventh MOSFET (M11) after being connected in series with the second resistor (R2). The gate of the seventeenth MOSFET (M17) is connected to the drain of the second MOSFET (M02). The source of the power transistor (Mpow) is connected to VDD, the drain of the power transistor (Mpow) is connected to the output signal (VOUT), and the gate of the power transistor (Mpow) is connected to the gate of the second MOSFET (M02). The non-inverting input of the auxiliary amplifier (AMP) is connected to node A, and the inverting input of the auxiliary amplifier (AMP) is connected to the output signal (VOUT). One end of the third resistor (R3) is connected to VDD, and the other end of the third resistor (R3) is connected to the drain of the second MOSFET (M02); Compensation resistor (R) ESR_IN One end is connected to node B, and the compensation resistor (R) ESR_IN The other end is connected to the output signal (VOUT); The output resistor (RL) and the output capacitor (CL) are connected in series between the output signal (VOUT) and ground, respectively. The first capacitor (C1) is connected in series between the gate of the fifth MOSFET (M05) and ground.

2. The LDO circuit for improving loop stability according to claim 1, characterized in that, The width-to-length ratio of the sixth MOSFET (M06) and the power transistor (Mpow) is 1:k; the value of k satisfies .

3. The LDO circuit for improving loop stability according to claim 1, characterized in that, The width-to-length ratio of the fourth MOS transistor (M04) and the sixth MOS transistor (M06) is 1:

1.

4. The LDO circuit for improving loop stability according to claim 1, characterized in that, The width-to-length ratio of the third MOS transistor (M03) and the fifth MOS transistor (M05) is 1:1.

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