Dynamic data loading method, graphics processor, readable storage medium

Abstract

A dynamic data loading method, a graphics processor, and a readable storage medium are disclosed. The dynamic data loading method includes: responding to a received data request, detecting the current operating mode of the caching module; the current operating mode is either a first mode or a second mode, where in the first mode the data request reads data in units of cache lines, and in the second mode the data request reads data in units of sub-blocks within a cache line; performing cache line miss detection based on the data request; in the current operating mode, determining whether to perform a cache line swapping operation based on the miss detection result; responding to the determination that a cache line swapping is triggered, performing the cache line swapping operation, and determining whether there is a need to switch operating modes; and determining whether to switch the current operating mode based on the number of times the cache line swapping operation is performed in the current operating mode and the number of times there is a need to switch operating modes. This solution can improve the performance and hit rate of the caching module.

Description

Technical Field

[0001] This invention relates to the field of graphics processor technology, and in particular to a dynamic data loading method and apparatus, a graphics processor, and a readable storage medium. Background Technology

[0002] Cache design aims for low latency and low miss ratio for data requests. Under the same usage conditions, a larger cache capacity and higher bandwidth result in shorter latency and a lower miss ratio. However, increasing bandwidth also increases the size of cache lines, which can lead to the problem of invalid data transfer.

[0003] Sector caching is a cache organization method that divides each cache line into two or more sub-blocks and performs data movement operations on a sub-block basis, reducing bandwidth waste and invalid movement. However, the entire cache line may be evicted before each sub-block is accessed, leading to a higher miss rate and a lower hit rate. Summary of the Invention

[0004] The purpose of this invention is at least to provide a dynamic data loading method, apparatus, graphics processor, and readable storage medium that can improve the hit rate while taking into account the performance of the cache module.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a dynamic data loading method applied to a graphics processor, comprising: in response to receiving a data request, detecting the current operating mode of a cache module; the current operating mode being a first mode or a second mode, wherein in the first mode the data request reads data in units of cache lines, and in the second mode the data request reads data in units of sub-blocks within a cache line; performing a cache line miss check based on the data request; in the current operating mode, determining whether to perform a cache line swapping operation based on the miss check result; in response to determining that a cache line swapping is triggered, performing a cache line swapping operation and determining whether there is a working mode switching requirement; and determining whether to switch the current operating mode based on the number of times the cache line swapping operation is performed in the current operating mode and the number of times there is a working mode switching requirement.

[0006] Upon receiving a data request, the current operating mode of the caching module is checked. The current operating mode can be either mode one or mode two. Based on the number of cache line swapping operations performed in the current operating mode and the number of times a mode switching requirement exists, it is determined whether to switch the current operating mode. Therefore, the operating mode of the caching module can be updated according to the real-time received data requests, allowing the caching module's operating mode to adapt to the current application scenario, thereby improving both the performance of the caching module and the probability of a cache hit.

[0007] Optionally, the i-th cache line has a corresponding i-th line label, which includes a valid bit and a sub-block mask. The valid bit is used to indicate whether the i-th cache line is valid, and the sub-block mask is used to indicate the access status of each sub-block in the i-th cache line. i and N are both positive integers and 1≤i≤N, where N is the total number of cache lines in the cache module.

[0008] Optionally, in the current working mode, determining whether to perform a cache line swapping operation based on the missing hit verification result includes: when the missing hit verification result is a hit on the target data, determining not to perform the cache line swapping operation; the target data corresponds to the data request; when the missing hit verification result is a missing target data, determining to perform the cache line swapping operation, and incrementing the number of times the cache line swapping operation is performed by 1.

[0009] Optionally, the current working mode is the first mode; after determining that the cache line swapping operation is not performed, the method further includes: reading all data in the target cache line where the target data is located, and updating the sub-block mask of the target cache line corresponding to the sub-block where the target data is located to the accessed state.

[0010] Optionally, determining whether there is a working mode switching requirement includes: in response to detecting that the sub-block mask corresponding to the first cache line being swapped out indicates that at least some sub-blocks are in an unaccessed state, determining that there is a working mode switching requirement, and incrementing the number of times the working mode switching requirement exists by 1; in response to detecting that the sub-block mask corresponding to the first cache line indicates that all sub-blocks are in an accessed state, determining that there is no working mode switching requirement.

[0011] In the first mode, if the sub-block mask corresponding to the first cache line being swapped out indicates that at least some sub-blocks have not been accessed, it means that the current scenario primarily involves accessing single sub-blocks. Therefore, it can be determined that there is a need to switch to the second mode. After determining to switch to the second mode, each data read and swap is performed on a sub-block basis, which avoids wasting cache bandwidth and invalid data transfer, thereby improving the performance of the cache module.

[0012] Optionally, the current working mode is the second mode; after determining that the cache line swapping operation is not performed, the method further includes: reading the target data from the target cache line and keeping the sub-block mask in the target cache line unchanged.

[0013] Optionally, determining whether there is a working mode switching requirement includes: in response to detecting that the sub-block mask corresponding to the first cache line being swapped out indicates that all sub-blocks are in an accessed state, determining that there is a working mode switching requirement, and incrementing the number of times the working mode switching requirement exists by 1; in response to detecting that the sub-block mask corresponding to the first cache line indicates that at least some sub-blocks are in an unaccessed state, determining that there is no working mode switching requirement.

[0014] In the second mode, if the sub-block mask indicating the first cache line swapped out is found to have accessed all sub-blocks, it means that the current scenario primarily involves accessing the entire cache line. Therefore, it can be determined that there is a need to switch to the first mode. After switching to the first mode, each data read and swap is performed on a cache line basis, which can improve the cache module's hit rate and thus improve its performance.

[0015] Optionally, determining whether to switch the working mode of the cache module based on the number of times the cache line swapping operation is performed in the current working mode and the number of times there is a working mode switching requirement includes: in the current working mode, if the number of times the cache line swapping operation is performed reaches a first threshold and the number of times there is a working mode switching requirement reaches a second threshold, then it is determined to switch the current working mode; in the current working mode, if the number of times the cache line swapping operation is performed reaches the first threshold and the number of times there is a working mode switching requirement does not reach the second threshold, then the cache module continues to be in the current working mode, and both the number of times the cache line swapping operation is performed and the number of times there is a working mode switching requirement are set to 0; the first threshold is greater than the second threshold.

[0016] In the current working mode, if the number of cache line swapping operations reaches the first threshold, and the number of times there is a need to switch working modes reaches the second threshold, then the current working mode is switched to improve the performance of the caching module and increase the hit rate. If the number of cache line swapping operations reaches the first threshold, but the number of times there is a need to switch working modes does not reach the second threshold, then the current working mode of the caching module can be considered suitable for the current application scenario, and therefore the current working mode can be maintained to ensure that the caching module is always in a better performance state.

[0017] Secondly, the present invention provides a graphics processor, comprising: a cache module, a working mode detection unit, a missing hit verification unit, an execution unit, a mode status register, a first counter, and a second counter, wherein: the cache module includes multiple cache lines, each cache line including at least two sub-blocks; the working mode detection unit, in response to receiving a data request, acquires the value in the mode status register to detect the current working mode of the cache module; the current working mode is a first mode or a second mode, wherein in the first mode the data request reads data in units of cache lines, and in the second mode the data request reads data in units of sub-blocks in the cache line; the missing hit verification unit performs missing hit verification of the cache lines based on the data request; the execution unit, in the current working mode, determines whether to perform a cache line swapping operation based on the missing hit verification result; in response to determining that a cache line swapping is triggered, performs a cache line swapping operation and determines whether there is a working mode switching requirement; and determines whether to switch the current working mode based on the count value of the first counter and the count value of the second counter; the first counter is used to count the number of times the cache line swapping operation is performed in the current working mode; and the second counter is used to count the number of times there is a working mode switching requirement.

[0018] Optionally, the i-th cache line has a corresponding i-th line label, which includes a valid bit and a sub-block mask. The valid bit is used to indicate whether the i-th cache line is valid, and the sub-block mask is used to indicate the access status of each sub-block in the i-th cache line. i and N are both positive integers and 1≤i≤N, where N is the total number of cache lines in the cache module.

[0019] Optionally, the execution unit determines not to perform the cache line swapping operation when the missing hit verification result is a hit with the target data; the target data corresponds to the data request; when the missing hit verification result is a missing target data, it determines to perform the cache line swapping operation and increments the number of times the cache line swapping operation is performed by 1.

[0020] Optionally, the current working mode is the second mode, where after determining that the cache line swapping operation is not performed, the execution unit reads the target data from the target cache line and keeps the sub-block mask in the target cache line unchanged.

[0021] Optionally, the current working mode is the second mode; the execution unit, in response to detecting that the sub-block mask corresponding to the first cache line being swapped out indicates that all sub-blocks are in an accessed state, determines that there is a working mode switching requirement, and increments the number of times the working mode switching requirement exists by 1; in response to detecting that the sub-block mask corresponding to the first cache line indicates that at least some sub-blocks are in an unaccessed state, determines that there is no working mode switching requirement.

[0022] Optionally, in the current working mode, if the number of times the cache line swapping operation is performed reaches a first threshold and the number of times there is a working mode switching requirement reaches a second threshold, then the execution unit determines to switch the current working mode; if in the current working mode, the number of times the cache line swapping operation is performed reaches the first threshold and the number of times there is a working mode switching requirement does not reach the second threshold, then the cache module continues to be in the current working mode, and both the number of times the cache line swapping operation is performed and the number of times there is a working mode switching requirement are set to 0; the first threshold is greater than the second threshold.

[0023] Thirdly, the present invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, wherein the computer program is executed by a processor to perform the steps of any of the above-described dynamic data loading methods. Attached Figure Description

[0024] Figure 1 This is a flowchart of a dynamic data loading method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a graphics processor according to an embodiment of the present invention. Detailed Implementation

[0025] In existing technologies, increasing the cache size typically corresponds to increasing the cache line size to improve the performance of the caching module. However, in some application scenarios, only a portion of the data in a cache line may be needed, rather than the entire data in that line. Therefore, reading data from the cache line by line can lead to wasted bandwidth and invalid data transfer.

[0026] In sub-block caching, a cache line is divided into several sub-blocks, and data is moved in units of sub-blocks, reducing bandwidth waste and invalid data movement. However, the entire cache line may be evicted before each sub-block is accessed, leading to a higher miss rate and a lower hit rate.

[0027] In this embodiment of the invention, upon receiving a data request, the current operating mode of the caching module is detected. The current operating mode of the caching module can be either a first mode or a second mode. Based on the number of times a cache line swapping operation is performed in the current operating mode and the number of times there is a need to switch operating modes, it is determined whether to switch the current operating mode. Therefore, the operating mode of the caching module can be updated according to the real-time received data requests, so that the operating mode of the caching module adapts to the current application scenario, thereby improving the performance of the caching module while increasing the hit probability. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] This invention provides a dynamic data loading method, referring to... Figure 1 The following will provide a detailed explanation through specific steps.

[0029] In this embodiment of the invention, the dynamic data loading method provided in steps 101 to 105 below can be applied to a graphics processing unit (GPU). The GPU may include a processor capable of executing the dynamic data loading method described below.

[0030] Step 101: In response to receiving a data request, detect the current working mode of the cache module.

[0031] In this embodiment of the invention, upon receiving a new data request, the current working mode of the caching module can be detected first.

[0032] In practice, the caching module can operate in either mode one or mode two. When the caching module operates in mode one, data requests read data from the caching module in units of cache lines; when the caching module operates in mode two, data requests read data in units of sub-blocks within a cache line.

[0033] In practice, a cache line can be divided into two or more sub-blocks. The length of each sub-block can be equal or unequal.

[0034] In the second mode, a data request can access only a portion of the sub-blocks in the cache line, or it can access all the sub-blocks in the cache line.

[0035] In this embodiment of the invention, the caching module may include N cache lines. Each of the N cache lines may have a corresponding line label.

[0036] Specifically, for the i-th row label in N cache lines, it can include a validity bit and a sector mask. The validity bit corresponding to the i-th row label is used to indicate whether the i-th cache line is valid, and the sector mask corresponding to the i-th row label is used to indicate the access status of each sector in the i-th cache line. i and N are both positive integers and 1≤i≤N. The length (or number of bits) of the sector mask can be equal to the number of sector blocks included in the cache line.

[0037] In practice, the access status of any sub-block in the i-th cache line can be either: unaccessed or accessed. When the access status of any sub-block is unaccessed, it means that the data stored in that sub-block has not been accessed; when the access status of any sub-block is accessed, it means that the data stored in that sub-block has been accessed.

[0038] In practical implementation, regarding the aforementioned sub-block mask, in the second mode, the data request carries the corresponding sub-block mask to indicate which sub-blocks in the corresponding cache line to read data from. Specifically, in the second mode, the specific function and purpose of the sub-block mask can refer to existing technologies.

[0039] It should be noted that in the existing technology, there is no concept of sub-block mask as mentioned above for the first mode.

[0040] In this embodiment of the invention, in the first mode, the sub-block mask from the second mode can be reused. The sub-block mask corresponding to the i-th cache line is used to characterize the access state of each sub-block in the i-th cache line. In the second mode, the sub-block mask corresponding to the i-th cache line can, based on the existing sub-block mask correspondence function, add the function of characterizing the access state of each sub-block in the i-th cache line.

[0041] In some embodiments, in the second mode, a cache line is divided into two equal sub-blocks. Accordingly, the cache line has a 2-bit sub-block mask. In the sub-block mask, the first bit corresponds to the first sub-block in the cache line, and the second bit corresponds to the second sub-block in the cache line. When the first bit is 0, it indicates that the first sub-block has not been accessed; when the first bit is 1, it indicates that the first sub-block has been requested for access. Similarly, when the second bit is 0, it indicates that the second sub-block has not been requested for access; when the second bit is 1, it indicates that the second sub-block has been requested for access. When the sub-block mask corresponding to the cache line is 11, it indicates that both sub-blocks have been requested for access.

[0042] In practice, the size of a cache line can be predefined. A cache line size can be 2kbit, 4kbit, 8kbit, or other values. The number of cache lines and the size of each cache line can differ for different cache module sizes.

[0043] For example, a cache line is predefined to be 2kbit in size. Accordingly, a cache line is divided into two sub-blocks, each of which is 1kbit in length.

[0044] In practice, a one-to-one sub-block mask register can be configured for each cache line to store the sub-block mask corresponding to each cache line.

[0045] Step 102: Perform a cache line missing hit verification based on the data request.

[0046] In this embodiment of the invention, after determining the current working mode of the caching module, a hit miss verification can be performed on the data request to determine whether the target data corresponding to the data request is stored in the caching module.

[0047] In practice, a missing data hit check is performed based on the data request to obtain the missing data hit check result. When the target data corresponding to the data request exists in the cache module, the missing data hit check result can be "hit", meaning the target data is hit; when the target data corresponding to the data request does not exist in the cache module, the missing data hit check result can be "miss", meaning the target data is missing.

[0048] Step 103: In the current working mode, based on the missing hit verification result, determine whether to perform the swap out cache line operation.

[0049] Step 104: In response to determining that a cache line has been triggered, perform a cache line swapping operation and determine whether there is a working mode switching requirement.

[0050] In this embodiment of the invention, when the missing hit verification result is a hit, it can be determined that the operation of swapping out cache lines will not be performed.

[0051] In specific implementation, when the current working mode is the first mode and the missing hit verification result is a hit, the target cache line where the target data is located can be read, and the access status of the sub-block mask corresponding to the target cache line and the sub-block mask corresponding to the target data can be updated to the accessed status.

[0052] For example, the target data is stored in the second sub-block of cache line 1. In the first mode, if the missing hit verification result is a hit, the data stored in cache line 1 can be read, and the mask value corresponding to the second sub-block in the sub-block mask of cache line 1 can be updated to 1, indicating that the second sub-block in cache line 1 has been accessed.

[0053] In this embodiment of the invention, when the missing hit verification result is missing, it can be further determined whether to perform a cache line swapping operation.

[0054] In practice, if the missing hit verification result is "miss" and there are unused cache lines in the caching module, it is determined that no cache line needs to be swapped out. After determining that the missing hit verification result is "miss," the target data corresponding to the data request is retrieved from the preset memory (or other cache), and the retrieved target data is stored in any of the aforementioned unused cache lines. The sub-block mask in the sub-block mask register corresponding to that cache line is also updated. After that, the next data request is retrieved and processed.

[0055] In practice, if there are other unused cache lines in the cache module, it can be determined that there is no need to swap out the cache lines; if there are no other unused cache lines in the cache module, it can be determined that there is a need to swap out the cache lines.

[0056] The above-mentioned change line can be to clear all the data stored in the cache line and re-cache the new data.

[0057] In practice, different methods can be used to determine the cache lines to be swapped out.

[0058] In some embodiments, a cache line can be randomly selected from N cache lines as the cache line to be swapped out. In other embodiments, the cache line containing the sub-block whose access time is longest from the current time can be selected from the N cache lines as the cache line to be swapped out. The specific implementation process and rules for determining the cache line to be swapped out can be found in relevant existing technologies, and will not be elaborated here.

[0059] Once it is determined that a cache line swapping is triggered, the cache line swapping operation is executed. After the cache line swapping operation is completed, it can be determined whether there is a need to switch working modes.

[0060] In this embodiment of the invention, a first counter and a second counter can be set, wherein: the first counter can be used to count the number of times a cache line swapping operation is performed in the current working mode, and the second counter can be used to count the number of times there is a working mode switching requirement.

[0061] The count value of the first counter is simply referred to as the first count value, which represents the number of times a cache line swapping operation has been performed in the current working mode; the count value of the second counter is simply referred to as the second count value, which represents the number of times a working mode switching requirement exists in the current working mode.

[0062] In the first mode, if it is determined that a cache line needs to be swapped out (let's say cache line n), the cache line swapping operation is performed, and the first count value is incremented by 1. After the cache line swapping operation is completed, the sub-block mask corresponding to cache line n is used to further determine whether there is a working mode switching requirement.

[0063] Specifically, if the value of the sub-block mask corresponding to cache line n indicates that all sub-blocks have been accessed, then the cache module is currently in the first mode, and therefore there is no need to switch working modes, so there is no need to increase the value of the second counter. If the value of the sub-block mask corresponding to cache line n indicates that at least one sub-block has not been accessed, then the cache module is not currently in the first mode, and therefore there is a need to switch working modes, so the value of the second counter needs to be increased.

[0064] When the sub-block mask corresponding to cache line n indicates that at least one sub-block has not been accessed, it means that the target data is read in units of sub-blocks in the current scenario. Therefore, the first mode may not be applicable to the current scenario, so it can be determined that there is a working mode switching request.

[0065] Correspondingly, when the sub-block mask corresponding to cache line n indicates that all sub-blocks have been accessed, it means that the target data is read in line units in the current scenario. Therefore, the first mode is applicable to the current scenario, so it can be determined that there is no need to switch working modes, that is, there is no working mode switching request.

[0066] For example, when it is determined that cache line n needs to be swapped out, if the sub-block mask value in the sub-block mask register corresponding to cache line n is 11, then it is determined that both sub-blocks have been accessed, and there is no need to increment the value of the second counter. Conversely, if the sub-block mask value corresponding to cache line n is 10, 01, or 00, then the value of the second counter is incremented.

[0067] In this embodiment of the invention, in the second mode, if the missing hit verification result is a hit, then there is no need to update the sub-block mask corresponding to the target cache line, and the next data request can continue to be received and processed.

[0068] For example, the target data is stored in the second sub-block of cache line 1. The sub-block mask corresponding to cache line 1 is 11, indicating that both sub-blocks corresponding to cache line 1 have been accessed. In the second mode, if the missing hit verification result is a hit, the data stored in the second sub-block of cache line 1 is read, and the next data request is received and processed. During this process, there is no need to update the sub-block mask corresponding to cache line 1.

[0069] In the second mode, if the missing hit verification result is missing, and it is determined that a certain cache line needs to be swapped out (let's say cache line m), then the cache line swapping operation is performed, cache line m is swapped out, and the first count value is updated. Updating the first count value as described above simply increments the first count value by 1.

[0070] In the second mode, based on the sub-block mask corresponding to cache line m, it is further determined whether there is a need to switch working modes. If the sub-block mask corresponding to cache line m indicates that all sub-blocks are accessed, it indicates that the current scenario is suitable for data reading on a per-cache-line basis, therefore it is determined that the second mode is not applicable in the current scenario, and thus a need to switch working modes exists. If the sub-block mask corresponding to cache line m indicates that at least some sub-blocks are not accessed, it indicates that the current scenario is suitable for data reading on a per-sub-block basis, and the second mode applies, therefore no need to switch working modes exists.

[0071] When a working mode switching requirement is determined, the second counter value can be incremented by 1. When no working mode switching requirement is determined, there is no need to update the second counter value.

[0072] For example, if the sub-block mask corresponding to cache line m is 11, it indicates that the cache module is not currently applicable to the second mode, so it is determined that there is a working mode switching requirement, and the second count value is increased; conversely, if the sub-block mask corresponding to cache line m is 10, 01 or 11, it indicates that the cache module is currently applicable to the second mode, it is determined that there is no working mode switching request, so it is determined that there is no need to increase the second count value.

[0073] Step 105: Based on the number of times the cache line swapping operation is performed in the current working mode and the number of times there is a need to switch working modes, determine whether to switch the current working mode.

[0074] In this embodiment of the invention, it can be determined whether the current working mode needs to be switched based on the first count value and the second count value.

[0075] In practice, if the current working mode is mode one and it is determined that a switch to the current working mode is needed, then switch to mode two. Conversely, if the current working mode is mode two and it is determined that a switch to the current working mode is needed, then switch to mode one.

[0076] In this embodiment of the invention, when the value of the second counter reaches the second threshold and the value of the first counter reaches the first threshold, the working mode of the cache module is switched.

[0077] For example, the current operating mode of the cache module is mode one. If the value of the first counter reaches the first threshold and the value of the second counter reaches the second threshold, the operating mode of the cache module is switched to mode two.

[0078] In this embodiment of the invention, if the value of the first counter reaches the first threshold, but the value of the second counter does not reach the second threshold, the current working mode of the cache module can be maintained, and the values ​​of the first and second counters can be cleared. The next data request can then be received.

[0079] Accordingly, if the value of the first counter does not reach the first threshold, the current working mode of the cache module can be maintained and the next data request can continue to be received.

[0080] In practice, the specific values ​​of the first and second thresholds can be set according to the specific application scenario. Since the process first determines whether a cache line switching is triggered, and only after determining that a cache line switching is triggered is the determination of whether a working mode switching requirement exists, the number of times a cache line switching is triggered is usually greater than the number of times a working mode switching requirement exists. Therefore, the first count value can be set to be greater than the second count value.

[0081] In some embodiments, the second threshold can be the product of the first threshold and a scaling factor. This scaling factor can be 0.6, 0.7, or other values. The specific value of the scaling factor can be set according to actual needs.

[0082] For example, the first threshold value is 100, and the second threshold value is 60. Or, the first threshold value is 200, and the second threshold value is 140.

[0083] In summary, the dynamic data loading method provided in the above embodiments, upon receiving a data request, detects the current working mode of the cache module, which can be either a first mode or a second mode. Based on the number of times a cache line swapping operation is performed in the current working mode and the number of times a working mode switching requirement exists, it determines whether to switch the current working mode. Therefore, the working mode of the cache module can be updated according to the real-time received data requests, allowing the working mode of the cache module to adapt to the current application scenario, thereby improving the performance of the cache module while increasing the hit probability.

[0084] Reference Figure 2 The present invention provides a graphics processor according to an embodiment of the invention. The graphics processor may include: a cache module 200, a mode status register 201, a working mode detection unit 202, a missing hit verification unit 203, an execution unit 204, a first counter 205, and a second counter 206, wherein: The cache module 200 includes multiple cache lines, and each cache line includes at least two sub-blocks; The mode status register 201 stores a value that indicates whether the current operating mode of the cache module is the first mode or the second mode. The working mode detection unit 202, in response to receiving a data request, obtains the value in the mode status register 201 to detect the current working mode of the cache module; the current working mode is a first mode or a second mode, in the first mode the data request reads data in units of cache lines, in the second mode the data request reads data in units of sub-blocks in the cache line; Missing hit verification unit 203 performs missing hit verification based on the data request; In the current working mode, the execution unit 204 determines whether to perform a cache line swapping operation based on the missing hit verification result; in response to determining that a cache line swapping is triggered, it performs a cache line swapping operation and determines whether there is a working mode switching requirement; based on the count value of the first counter 205 and the count value of the second counter 206, it determines whether to switch the current working mode. The first counter 205 is used to count the number of times the cache line swapping operation is performed in the current working mode; The second counter 206 is used to count the number of times there is a need to switch working modes.

[0085] In specific implementation, the specific execution process of the above-mentioned mode status register 201, working mode detection unit 202, and missing hit verification unit 203 can be referred to the relevant records of steps 101 to 105 in the above embodiment, which will not be repeated here.

[0086] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0087] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0088] This invention also provides a computer-readable storage medium, which is a non-volatile or non-transient storage medium, storing a computer program thereon. When the computer program is run by a processor, it executes the steps of the dynamic data loading method provided in any of the above embodiments.

[0089] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include ROM, RAM, disk, or optical disk, etc.

[0090] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A dynamic data loading method, applied to a graphics processor, characterized in that, include: In response to receiving a data request, the current working mode of the caching module is detected; the current working mode is either a first mode or a second mode, in which the data request reads data in units of cache lines, and in which the data request reads data in units of sub-blocks in a cache line; Based on the data request, perform cache line missing hit verification; In the current working mode, based on the missing hit verification result, it is determined whether to perform a cache line swapping operation; In response to the determination that a cache line has been triggered to be swapped out, the cache line swapping operation is performed, and it is determined whether there is a need to switch working modes; The determination of whether there is a need to switch working modes includes: determining whether there is a need to switch working modes based on the access status of each sub-block in the cache line that has been swapped out; Determining whether to switch the current working mode based on the number of times the cache line swapping operation is performed in the current working mode and the number of times there is a working mode switching requirement includes: if the number of times the cache line swapping operation is performed reaches a first threshold and the number of times there is a working mode switching requirement reaches a second threshold in the current working mode, then it is determined to switch the current working mode; if the number of times the cache line swapping operation is performed reaches the first threshold and the number of times there is a working mode switching requirement does not reach the second threshold, then the cache module continues to be in the current working mode, and both the number of times the cache line swapping operation is performed and the number of times there is a working mode switching requirement are set to 0; the first threshold is greater than the second threshold.

2. The dynamic data loading method as described in claim 1, characterized in that, The i-th cache line has a corresponding i-th line label, which includes a validity bit and a sub-block mask. The validity bit is used to indicate whether the i-th cache line is valid, and the sub-block mask is used to indicate the access status of each sub-block in the i-th cache line. i and N are both positive integers and 1≤i≤N, where N is the total number of cache lines in the cache module.

3. The dynamic data loading method as described in claim 2, characterized in that, In the current working mode, determining whether to perform a cache line swapping operation based on the missing hit verification result includes: When the missing hit verification result is a hit with the target data, it is determined that the cache line swapping operation will not be performed; the target data corresponds to the data request. When the missing hit verification result indicates that the target data is missing, it is determined that a cache line swapping operation will be performed, and the number of times the cache line swapping operation will be performed is incremented by 1.

4. The dynamic data loading method as described in claim 3, characterized in that, The current working mode is the first mode; after determining that the cache line swapping operation will not be performed, the following is also included: Read all data in the target cache line where the target data is located, and update the sub-block mask in the target cache line corresponding to the sub-block where the target data is located to the accessed state.

5. The dynamic data loading method as described in claim 4, characterized in that, The determination of whether there is a need to switch working modes includes: In response to detecting that the sub-block mask corresponding to the first cache line that has been swapped out indicates that at least some sub-blocks are in an unaccessed state, it is determined that there is a working mode switching requirement, and the number of times the working mode switching requirement exists is incremented by 1; In response to the detection that the sub-block mask corresponding to the first cache line indicates that all sub-blocks are in an accessed state, it is determined that there is no need for the working mode switching.

6. The dynamic data loading method as described in claim 3, characterized in that, The current working mode is the second mode; after determining that the cache line swapping operation will not be performed, the following is also included: The target data is read from the target cache line, while the sub-block mask in the target cache line remains unchanged.

7. The dynamic data loading method as described in claim 6, characterized in that, The determination of whether there is a need to switch working modes includes: In response to the detection that the sub-block mask corresponding to the first cache line that has been swapped out indicates that all sub-blocks are in an accessed state, it is determined that there is a working mode switching requirement, and the number of times the working mode switching requirement exists is incremented by 1; In response to detecting that at least some sub-blocks corresponding to the first cache line are in an unaccessed state, it is determined that there is no need for the working mode switching.

8. A graphics processor, characterized in that, include: The system comprises a cache module, a working mode detection unit, a missing hit verification unit, an execution unit, a mode status register, a first counter, and a second counter, wherein: The caching module includes multiple cache lines, and each cache line includes at least two sub-blocks; The working mode detection unit, in response to receiving a data request, obtains the value in the mode status register to detect the current working mode of the cache module; the current working mode is a first mode or a second mode, in which the data request reads data in units of cache lines, and in which the data request reads data in units of sub-blocks in cache lines; The missing hit verification unit performs missing hit verification of cache lines based on the data request; The execution unit, in the current working mode, determines whether to perform a cache line swapping operation based on the missing hit verification result; in response to determining that a cache line swapping is triggered, it performs the cache line swapping operation and determines whether there is a working mode switching requirement; based on the count values ​​of the first counter and the second counter, it determines whether to switch the current working mode, including: in the current working mode, if the number of times the cache line swapping operation is performed reaches a first threshold and the number of times there is a working mode switching requirement reaches a second threshold, then it determines to switch the current working mode; in the current working mode, if the number of times the cache line swapping operation is performed reaches the first threshold and the number of times there is a working mode switching requirement does not reach the second threshold, then the cache module continues to be in the current working mode, and the number of times the cache line swapping operation is performed and the number of times there is a working mode switching requirement are both set to 0; the first threshold is greater than the second threshold; determining whether there is a working mode switching requirement includes: determining whether there is a working mode switching requirement based on the access status corresponding to each sub-block in the swapped cache line; The first counter is used to count the number of times the cache line swapping operation is performed in the current working mode; The second counter is used to count the number of times the working mode switching requirement exists.

9. The graphics processor as described in claim 8, characterized in that, The i-th cache line has a corresponding i-th line label, which includes a validity bit and a sub-block mask. The validity bit is used to indicate whether the i-th cache line is valid, and the sub-block mask is used to indicate the access status of each sub-block in the i-th cache line. i and N are both positive integers and 1≤i≤N, where N is the total number of cache lines in the cache module.

10. The graphics processor as claimed in claim 9, characterized in that, When the missing hit verification result is a hit with the target data, the execution unit determines not to perform the cache line swapping operation; the target data corresponds to the data request. When the missing hit verification result indicates that the target data is missing, it is determined that a cache line swapping operation will be performed, and the number of times the cache line swapping operation will be performed is incremented by 1.

11. The graphics processor as claimed in claim 10, characterized in that, The current working mode is the second mode. After determining that the cache line swapping operation will not be performed, the execution unit reads the target data from the target cache line and keeps the sub-block mask in the target cache line unchanged.

12. The graphics processor as claimed in claim 11, characterized in that, The current working mode is the second mode; the execution unit, in response to detecting that the sub-block mask corresponding to the first cache line that has been swapped out indicates that all sub-blocks are in an accessed state, determines that there is a working mode switching requirement and increments the number of times the working mode switching requirement exists by 1; in response to detecting that the sub-block mask corresponding to the first cache line indicates that at least some sub-blocks are in an unaccessed state, determines that there is no working mode switching requirement.

13. A computer-readable storage medium, said computer-readable storage medium being a non-volatile storage medium or a non-transient storage medium, having stored thereon a computer program, characterized in that, The computer program is executed by the processor to perform the steps of the dynamic data loading method according to any one of claims 1 to 7.

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