Microcontroller and method of operating a microcontroller

Abstract

This invention discloses a microcontroller and a method for operating the microcontroller. The microcontroller is coupled to a host device. The method includes: providing a read-only memory to permanently store a boot code; providing a static random access memory (SRAM); when a system of the host device restarts, booting up according to the boot code, obtaining operating conditions of the microcontroller from the host device, and temporarily storing the operating conditions in the SRAM; and loading, setting, and updating a firmware program or restoring the state of the microcontroller according to the operating conditions temporarily stored in the SRAM.

Description

Technical Field

[0001] This invention relates to a microcontroller mechanism, and more particularly to a microcontroller and a method for operating the microcontroller. Background Technology

[0002] Generally, existing microcontrollers have a flash memory to permanently store corresponding firmware program information and boot information. However, this undoubtedly makes the circuit size of the microcontroller itself too large. In addition, when a sudden power outage occurs, existing microcontrollers cannot immediately return to the execution state they were previously executing after power is restored. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a novel microcontroller circuit and corresponding operating method to solve the problems of the prior art.

[0004] According to an embodiment of the present invention, a microcontroller is disclosed. The microcontroller is coupled to a host device and includes a read-only memory (ROM), a static random access memory (SRAM), and a control circuit. The ROM permanently stores a boot code. The control circuit is coupled to the ROM and the SRAM. When a system of the host device restarts, the control circuit powers on the microcontroller according to the boot code, obtains operating conditions of the microcontroller from the host device, temporarily stores the operating conditions in the SRAM, and loads, sets, and updates a firmware program or restores the state of the microcontroller based on the temporarily stored operating conditions in the SRAM.

[0005] According to an embodiment of the present invention, a method for operating a microcontroller is further disclosed. The microcontroller is coupled to a host device, and the method includes: providing a read-only memory to permanently store a boot code; providing a static random access memory (SRAM); upon system restart of the host device, booting up according to the boot code, obtaining operating conditions of the microcontroller from the host device, temporarily storing the operating conditions in the SRAM; and loading, setting, and updating a firmware program or restoring the state of the microcontroller according to the temporarily stored operating conditions in the SRAM. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a microcontroller according to an embodiment of the present invention.

[0007] Figure 2 This is a schematic diagram of a microcontroller according to another embodiment of the present invention.

[0008] Figure 3According to an embodiment of the present invention Figure 1 The microcontroller shown (or Figure 2 The diagram shows the power-on process of the microcontroller shown.

[0009] Figure 4 According to an embodiment of the present invention Figure 1 The diagram shows the timing sequence of operations for updating and verifying data in static random access memory between the microcontroller and the host device's driver.

[0010] Figure 5 According to another embodiment of the present invention Figure 2 The diagram shows the timing sequence of operations for updating and verifying data in external flash memory between the microcontroller and the host device's driver.

[0011] Figure 6 According to an embodiment of the present invention Figure 1 (or Figure 2 The diagram shows the timing of a verification operation performed by a microcontroller.

[0012] Figure 7 This is a timing diagram illustrating the operating conditions of a microcontroller stored in a host device according to an embodiment of the present invention.

[0013] Figure 8 This is a schematic diagram of the process steps of a host device performing an initial state check when reading information temporarily stored in a microcontroller through the reading program according to an embodiment of the present invention.

[0014] Figure 9 This is a schematic diagram of the process steps of a main device performing a pause check on a microcontroller according to an embodiment of the present invention.

[0015] Figure 10 This is a schematic diagram of the process steps of a host device starting a reading program on a microcontroller to back up and store data, according to an embodiment of the present invention.

[0016] Figure 11 This is a schematic diagram of the process steps of a host device starting a reading program on a microcontroller for backup and storage according to another embodiment of the present invention.

[0017] Explanation of icon numbers

[0018] 100, 200: Microcontrollers

[0019] 101: Main unit

[0020] 102: Operating System

[0021] 103: Driver

[0022] 104: Storage device

[0023] 105: Read-Only Memory

[0024] 110: Static Random Access Memory

[0025] 115: Control Circuit

[0026] 205: External flash memory Detailed Implementation

[0027] The present invention aims to provide an electronic device, such as a microcontroller (MCU), and a corresponding operating method. The microcontroller can store the information of its operating conditions on an external device and temporarily store the information of the operating conditions through a volatile memory, such as a static random access memory (SRAM), without the need to set up an electronically erasable rewritable read-only memory (e.g., a flash memory) inside the microcontroller to record and store the operating conditions.

[0028] The operating conditions include, for example, firmware information and / or execution state information of the microcontroller. The firmware information is used to load, set, or update the main firmware and operating environment of the microcontroller, while the execution state information relates to and includes the state of the microcontroller, such as the current state or stage of the software program being executed or before a sudden power outage, information stored by the user, etc. The microcontroller can restore its state based on the execution state information.

[0029] Therefore, the provided microcontroller can handle the loading, updating, and setting of different firmware programs, as well as all possible execution state scenarios, without internal flash memory. In practice, the microcontroller does not include internal flash memory to reduce its circuit size and cost. Furthermore, specifically (but not limited to), the microcontroller can be an image processing chip for a sensor and applied in a monitoring system device. This image processing chip can perform image processing operations such as detecting the presence of a person and recognizing a face.

[0030] Compared to prior art, the embodiments of this invention reduce reliance on persistent storage devices such as flash memory and simplify the overall system architecture by writing firmware information into the microcontroller's internal static random access memory (SRAM) and directly loading and executing the firmware update and settings corresponding to the firmware information from the SRAM. Furthermore, in one embodiment, a host device driver, such as a system-level window driver, can be used to perform simpler and more direct firmware updates and settings with the microcontroller.

[0031] Furthermore, regarding the restoration of the microcontroller's state, the embodiments of this application propose a power interrupt handler mechanism without permanent storage. This mechanism periodically or irregularly stores the microcontroller's execution state information (e.g., the program state being executed by the system) to an external storage device, such as the host device's hard drive. This more efficiently preserves the program state and ensures that the microcontroller can quickly restore to the previously executed program state when power is restored after a sudden power interruption. Moreover, after a sudden power interruption and subsequent power restoration, the microcontroller can skip certain re-handshake mechanisms during state restoration, enabling a faster and seamless restoration to the previously used and / or executed program state, thereby enhancing system reliability.

[0032] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a microcontroller 100 according to an embodiment of the present invention. Figure 1 As shown, the microcontroller 100 can be applied to a human interface device (HID-I2C) and coupled to a host device 101 (e.g., a human computer) via a specific connection interface. This specific connection interface can be, for example, a communication protocol supporting communication between the human interface device and an integrated circuit bus (HID-I2C), or it can be a Serial Peripheral Interface (SPI) Bus, allowing the human interface device (e.g., a keyboard, touchpad, touchscreen, and sensor) to communicate on the integrated circuit bus or via the SPI Bus.

[0033] The microcontroller 100 includes a read-only memory 105, a static random access memory 110, and a control circuit 115. The host device 101 includes an operating system 102, a driver 103 corresponding to the microcontroller 100, and a storage device 104. The storage device 104 is, for example, a hard disk implemented with flash memory, that is, an external flash memory for the microcontroller 100. The read-only memory 105 is used to permanently store (or internally record) a read-only boot code (ROM boot code) for powering on, also known as a boot loader. The static random access memory 110 is used to temporarily store an operating condition (e.g., firmware information and / or execution status information). The firmware information and / or the execution status information can be backed up, updated, and written by the host device 101. In other words, the firmware information and / or the execution status information are not permanently stored inside the microcontroller 100.

[0034] The control circuit 115 is coupled to the read-only memory 105 and the static random access memory 110, and is used to boot the host device 101's operating system 102 after an initial boot or a reboot following a sudden power outage, according to the boot code, obtain the operating conditions of the microcontroller 100 from the host device 101, temporarily store the operating conditions in the static random access memory 110, and load, set, and update a firmware program or restore a state of the microcontroller 100 according to the operating conditions temporarily stored in the static random access memory 110. For example, it can set, execute, and update a firmware program according to the firmware information, and immediately restore the state of the microcontroller 100 according to the execution status information.

[0035] For example, in one embodiment, the firmware information and the execution status information may be stored periodically or intermittently in the driver 103 of the host device 101 (or in its Basic Input / Output System (BIOS) program). When the operating system 102 performs a program update, the driver 103 or the software program of the operating system 102 may send the firmware information to the microcontroller 100, so that the control circuit 115 of the microcontroller 100 may set, execute, and update the firmware according to the firmware information. In addition, the driver 103 or the software program of the operating system 102 may also send the execution status information to the microcontroller 100, so that the control circuit 115 may restore the status of the microcontroller 100 according to the execution status information.

[0036] For example, when the microcontroller 100 is powered on and the read-only boot code is executed, the driver 103 (or the Basic Input / Output System (BIOS) program) can update and move the firmware information and execution status information to the static random access memory 110 inside the microcontroller 100 through the specific connection interface described above. Therefore, after the data information has been moved and written, the control circuit 115 can perform the setting and updating of the firmware program corresponding to the firmware information and perform status recovery according to the execution status information.

[0037] In another embodiment, the firmware information and execution status information of the microcontroller 100 are periodically backed up and stored in the storage device 104 of the host device 101, wherein the storage device 104 is inaccessible to the microcontroller 100. When the microcontroller 100 is powered on and the read-only boot code is executed, the operating system 102 can read the firmware information and execution status information from the storage device 104, and then update and move the firmware information and execution status information to the static random access memory 110 inside the microcontroller 100 through the aforementioned specific connection interface. After the data information is moved and written, the control circuit 115 can execute the setting and updating of the firmware program corresponding to the firmware information and perform status recovery according to the execution status information.

[0038] Alternatively, in one embodiment, the microcontroller 100 may also be externally connected to a flash memory device to back up the operating conditions (firmware information and execution status information). Please refer to... Figure 2 , Figure 2 This is a schematic diagram of a microcontroller 200 according to another embodiment of the present invention. Figure 2 As shown, the microcontroller 200 has the same function and operation as the microcontroller 100 and can be externally connected to a flash memory device 205 through another specific communication interface. This other specific communication interface is, for example, another serial peripheral interface bus (SPI bus) (but not limited to). The microcontroller 200 can periodically or periodically back up and store the firmware program information and execution status information in its external flash memory device 205 through this other SPI bus.

[0039] If the flash memory device 205 is fault-free, after the microcontroller 200 is powered on and the read-only boot code is executed, the microcontroller 200 can obtain the firmware information and execution status information from the flash memory device 205 via the other SPI bus. Therefore, the control circuit 115 can perform the setting and updating of the firmware program corresponding to the firmware information and perform status recovery based on the execution status information. However, if the flash memory device 205 malfunctions or the stored data is incorrect, after the microcontroller 200 is powered on and the read-only boot code is executed, the driver 103 (or the Basic Input / Output System (BIOS) program) can still update and move the firmware information and execution status information from the host device 101 to the static random access memory 110 inside the microcontroller 200 via the specific connection interface mentioned above. After the data is moved and written, the control circuit 115 can perform the setting and updating of the firmware program corresponding to the firmware information and perform status recovery based on the execution status information.

[0040] Please refer to Figure 3 , Figure 3 According to an embodiment of the present invention Figure 1 The microcontroller 100 shown (or Figure 2 The diagram shows the boot flow (or power-on process) of the microcontroller 200. The following is a brief description of the process steps:

[0041] Step S305: When the microcontroller 100 is powered on or reset, the microcontroller 100 (or control circuit 115) starts to execute the read-only boot code from the read-only memory 105. The read-only boot code, for example, starts executing from address 0x00000000 to set the system environment of the microcontroller 100. The read-only boot code is an initial boot loader.

[0042] Step S310: The initial bootloader initializes multiple hardware components of the chip (i.e., microcontroller 100), such as performing chip initialization to initialize the hardware clock, general-purpose input / output (GPIO), and memory settings. In addition, it performs interface initialization to set up multiple communication interfaces to ensure that the microcontroller 100 can interact with other peripheral devices. Furthermore, it performs USB enumeration. Finally, after initialization and enumeration, the microcontroller 100 can enter an idle state to save power while waiting for a specific event.

[0043] Step S315: The microcontroller 100 (or control circuit 115) waits for the specific event in the idle state, such as a static random access memory update event;

[0044] Step S320: The driver 103 (or BIOS program) on the host device 101 triggers and sends an update event of the static random access memory to the microcontroller 100 through the specific connection interface, for example, loading, moving and writing the firmware program information and execution status information stored in the driver 103 (or BIOS program) into the static random access memory 110 inside the microcontroller 100;

[0045] Step S325: The microcontroller 100 (or control circuit 115) executes the initial boot program to verify the correctness of the received data step by step. If the verification operation is successfully completed, the process proceeds to step S330. Otherwise, if the verification operation fails, the process returns to step S320 to repeat steps S320 and S325, so that the firmware program information and the execution status information can be fully loaded, moved and written to the static random access memory 110 inside the microcontroller 100 for verification. Furthermore, for example, this verification operation can also be used to verify whether peripheral devices are correctly configured, to verify whether the initial bootloader correctly reads and loads the firmware information and execution status information into static random access memory 110, to perform checksum or hash function verification to ensure that the loaded firmware information and execution status information match the expected firmware image, and to verify whether control is correctly transferred from the initial bootloader to one of the main firmware programs corresponding to the firmware information, so that the microcontroller 100 (or control circuit 115) can then start the execution of the main application code after booting; and

[0046] Step S330: The microcontroller 100 (or control circuit 115) restarts one of the main firmware programs corresponding to the firmware program information in the static random access memory 110.

[0047] Please refer to Figure 4 , Figure 4 According to an embodiment of the present invention Figure 1 The diagram shows the timing sequence of operations for updating and verifying data in the static random access memory 110 between the microcontroller 100 and the driver 103 of the host device 101. Figure 4As shown, the driver 103 first triggers and sends an update event to the static random access memory (SRAM) to the microcontroller 100 (or control circuit 115). For example, the control circuit 115 may also include an update register. If the microcontroller 100 still needs to transmit firmware information and execution status information, the control circuit 115 can write the value of the update event into the update register. Next, the driver 103 can check the value stored in the update register of the control circuit 115. If the value indicates that an update is needed, the next step will be performed; otherwise, the control circuit 115 will be in an idle state waiting for other events. When the value indicates that an update is needed, the driver 103 then sends the multiple data entries to be updated (i.e., firmware information and / or execution status information) to the microcontroller 100 (or control circuit 115) one by one. For example, this data can be transmitted in packets over the specific connection interface, with the last packet including, for example, a finish flag or a checksum value. Upon receiving each data entry, the microcontroller 100 (or control circuit 115) sequentially writes each data entry into the static random access memory 110. When the microcontroller 100 (or control circuit 115) finally receives the finish flag or checksum value, it can then perform a verification operation on the data stored in the internal static random access memory to complete the verification process. If the verification operation is successful, the microcontroller 100 (or control circuit 115) will restart.

[0048] Please refer to Figure 5 , Figure 5 According to another embodiment of the present invention Figure 2 This diagram illustrates the timing sequence of operations between the microcontroller 200 and the driver 103 of the host device 101 for updating and verifying data in the external flash memory 205. Figure 5As shown, similarly, the driver 103 triggers and sends an update event from the external flash memory to the microcontroller 100 (or control circuit 115). For example, the control circuit 115 includes an update buffer. If the microcontroller 100 still needs to transmit firmware information and execution status information, the control circuit 115 can write the value of the update event into the update buffer. Then, the driver 103 can check the value stored in the update buffer. If the value indicates that an update is needed, the next step will be performed; otherwise, the control circuit 115 will remain idle, waiting for other events. When the value indicates that an update is needed, the driver 103 sends the data to be updated (i.e., firmware information and / or execution status information) to the microcontroller 100 (or control circuit 115) one by one. Upon receiving each piece of data, the microcontroller 100 (or control circuit 115) sequentially writes each piece of data into the external flash memory 205. When the microcontroller 200 (or control circuit 115) finally receives the end flag or checksum value, it can then perform a verification operation on the data stored in the external flash memory 205 to complete the verification process. If the verification operation is successful, the microcontroller 200 (or control circuit 115) will restart. It should be noted that, in one embodiment, when the microcontroller 100 (or control circuit 115) receives each piece of data, the control circuit 115 will sequentially write each piece of data into the static random access memory 110 and then write it into the external flash memory 205. Therefore, the verification operation performed on the data stored in the external flash memory 205 can also be used to verify the static random access memory 110 at the same time.

[0049] Please refer to Figure 6 , Figure 6 According to an embodiment of the present invention Figure 1 (or Figure 2 The diagram shows the timing sequence of a verification operation performed by the microcontroller 100 (or 200). Figure 6As shown, when the host device 101 or driver 103 wants to verify or check the integrity of data, the driver 103 sends a verification event (e.g., a verification event related to a checksum) to the microcontroller 100 (or control circuitry 115). Upon receiving the verification event, the microcontroller 100 (or control circuitry 115) begins executing a verification operation or program, for example, to verify data stored in the static random access memory 110 or data stored in the external flash memory 205, where the stored data refers to firmware information and / or execution status information. Finally, the control circuitry 115 writes the verification result to its specific cache. The driver 103 can then obtain and check the verification result by examining the value in that specific cache.

[0050] Furthermore, regarding the storage of execution status information, the microcontroller 100 (or control circuit 115) has, for example, multiple system caches, such as 53 cache banks, and each cache bank includes 128 8-bit registers. The microcontroller 100 (or control circuit 115) can periodically or irregularly store the values ​​of these system caches (i.e., the execution status of the microcontroller 100) in the storage device 104 of the host device 101, for example, in the hard disk of the file management system of the window operating system of a personal computer, so that the execution status information can be retrieved from the storage device 104 of the host device 101 to correctly restore the execution status of the microcontroller 100 (or control circuit 115). For example, when an interrupt event occurs or a certain condition is met, the control circuit 115 can trigger and execute a state storage routine to store the execution state of the microcontroller 100 to the storage device 104 of the host device 101. The state storage routine can, for example, read the current values ​​of some system caches and store them to the storage device 104. These values ​​are, for example, the stack pointer value, the global pointer value, the thread pointer value, the program counter value, or the values ​​of all general purpose caches. In one embodiment, the microcontroller 100 (or the internal memory of the control circuit 115) may also include an instruction local memory (ILM) and / or a data local memory (DLM) to store the instructions that the control circuit 115 is about to execute and / or the data required in the instruction operation, respectively. The execution status information may also include the instructions to be executed and / or the data required in the instruction operation. In other words, the status storage routine may, for example, store the instructions to be executed and / or the data required in the storage device 104 of the host device 101, so that the instructions and data can be retrieved from the storage device 104 of the host device 101 to correctly restore the execution status of the microcontroller 100 (or the control circuit 115). In addition, the instruction local memory and / or data local memory can be implemented through a portion of the storage space of the static random access memory 110.

[0051] In addition, regarding the recovery of execution status information, when a power outage occurs between the microcontroller 100 and the host device 101, or when the host device 101's system restarts, the operating system 102 of the host device 101 initializes a recovery procedure. This recovery procedure reads the stored execution status information from the corresponding location of the storage device 104, a corresponding part of the driver 103, or a corresponding part of the BIOS program and transmits it to the microcontroller 100. This allows the microcontroller 100 to recover the execution status before the power outage or the host device 101's system restart based on the execution status information, so as to continue the operation performed in the previous execution status and achieve a seamless operation effect.

[0052] Furthermore, in one embodiment, the backup and storage of the aforementioned operating conditions can be triggered at a time when the host device 101 needs to perform power-saving operations. Please refer to... Figure 7 , Figure 7 This is a timing diagram illustrating the operating conditions of the microcontroller 100 stored in the host device 101 according to an embodiment of the present invention. Figure 7 As shown, firstly, the driver 103 of the host device 101 checks the status (or execution status) of the microcontroller 100. Next, the driver 103 determines whether its status meets the conditions for power saving. If the status meets the conditions for power saving, the driver 103 sends an ILM (Instruction Management Memory) event to the microcontroller 100 (or control circuit 115), causing the microcontroller 100 (or control circuit 115) to correspondingly transfer the instruction data temporarily stored in the instruction area memory to the host device 101, thereby backing it up and storing it in the driver 103 and / or storage device 104. Alternatively, the driver 103 can also send a DLM (Data Management Memory) event to the microcontroller 100 (or control circuit 115), causing the microcontroller 100 (or control circuit 115) to correspondingly transfer the data temporarily stored in the data area memory to the host device 101, thereby backing it up and storing it in the driver 103 and / or storage device 104. In addition, driver 103 can also send a microcontroller data storage event to microcontroller 100 (or control circuit 115), causing microcontroller 100 (or control circuit 115) to correspondingly transfer the data temporarily stored in one or more buffers of microcontroller 100 to host device 101, thereby backing it up and storing it in driver 103 and / or storage device 104. Next, driver 103 can also send a buffer group storage event to microcontroller 100 (or control circuit 115), causing microcontroller 100 (or control circuit 115) to correspondingly transfer the data temporarily stored in one or more buffer groups of microcontroller 100 to host device 101, thereby backing it up and storing it in driver 103 and / or storage device 104. It should be noted that... Figure 7The order in which the events are sent shown is only one embodiment and is not a limitation of this invention. Different orders can be used to send these events in other embodiments. Furthermore, Figure 7 The operation of the illustrated embodiment can also be applied to Figure 2 When the microcontroller 200 receives a corresponding storage event, it can back up and store the data corresponding to the storage event in the external flash memory 205. At the same time, it can also transmit the data temporarily stored in one or more cache groups of the microcontroller 100 to the host device 101 to back up and store it in the driver 103 and / or storage device 104. For the sake of simplicity, it will not be described in detail here.

[0053] In one embodiment, the microcontroller 100 (or 200) may periodically or irregularly store its operating conditions in static random access memory 110 and / or external flash memory 205. The host device 101 reads, stores, and backs up the information temporarily stored by the microcontroller 100 (or 200) through a dump process. Please refer to... Figure 8 , Figure 8 This is a schematic diagram illustrating the process steps of an initial state check performed by the host device 101 when reading information temporarily stored in the microcontroller 100 (or 200) through the reading program according to an embodiment of the present invention. The process steps are briefly described below:

[0054] Step S805: The driver 103 of the host device 101 is about to suspend the microcontroller 100;

[0055] Step S810: Driver 103 checks the state of microcontroller 100 to determine whether the state is ready; when the state is ready, the process proceeds to step S815, otherwise the process proceeds to step S813.

[0056] Step S813: Determine whether the microcontroller 100's retry meets the abandonment condition. If the abandonment condition is met, proceed to step S835. Otherwise, if the abandonment condition is not met, return to step S810.

[0057] Step S815: The driver 103 determines whether the microcontroller 100 has only one read memory in its non-volatile memory. If it only has read memory, the process proceeds to step S825. If it still has an external flash memory, the process proceeds to step S820.

[0058] Step S820: Driver 103 determines whether to back up the data in a flash memory. If it is necessary to back up the data in the flash memory, the process proceeds to step S830. If it is not necessary to back up the data in the flash memory, the process proceeds to step S850.

[0059] Step S825: Driver 103 determines whether to back up data in a static random access memory 110. If backing up data in the static random access memory 110 is required, the process proceeds to step S840. If no backup is required, the process proceeds to step S835.

[0060] Step S830: Set up the procedure and related steps for backing up and updating data in the flash memory;

[0061] Step S835: It is not necessary to store the operating conditions of the microcontroller 100;

[0062] Step S840: Begin reading, backing up, and storing the instructions and data temporarily stored in the instruction area memory and data area memory;

[0063] Step S845: Read, back up, and save the current state; and

[0064] Step S850: Execute the reading program.

[0065] Please refer to Figure 9 , Figure 9 This is a continuation of an embodiment of the present invention. Figure 8 The flowchart below illustrates the process steps of step S850, where the main device 101 performs a suspend check on the microcontroller 100 (or 200). The following is a brief description of the process steps:

[0066] Step S905: Execute the reading program (same as step S850);

[0067] Step S910: Determine whether the microcontroller 100 is paused. If it is paused, proceed to step S915. If it is not paused, proceed to step S925.

[0068] Step S915: Determine whether the wakeup retry of the microcontroller 100 meets an abandoned condition. If the abandoned condition is met, proceed to step S920. If the abandoned condition is not met, return to step S910.

[0069] Step S920: Reading program failed; and

[0070] Step S925: Start the reading process.

[0071] Please refer to Figure 10 , Figure 10 This is a continuation of an embodiment of the present invention. Figure 8 The flowchart below illustrates the steps of S840, where the host device 101 begins a reading procedure on the microcontroller 100 (or 200) to back up and store data. The following is a brief description of the process steps:

[0072] Step S1005: Start reading, backing up and storing the instructions and data temporarily stored in the instruction area memory and data area memory (same as step S840);

[0073] Step S1010: Determine whether the microcontroller 100 is ready to be read data. If it is ready to be read data, proceed to step S1025. Otherwise, if it is not ready to be read data, proceed to step S1015.

[0074] Step S1015: Determine whether the microcontroller 100's retry meets the abandonment condition. If the abandonment condition is met, the process proceeds to step S1020; otherwise, if the abandonment condition is not met, the process returns to step S1010.

[0075] Step S1020: Unable to successfully read the instructions and data temporarily stored in the instruction area memory and data area memory;

[0076] Step S1025: Set the microcontroller 100 to an idle state;

[0077] Step S1030: Determine whether the microcontroller 100 is busy at this time. If the microcontroller 100 is busy at this time, the process proceeds to step S1035. Otherwise, if the microcontroller 100 is not busy at this time, the process proceeds to step S1040.

[0078] Step S1035: Determine whether the microcontroller 100's retry meets the abandonment condition. If the abandonment condition is met, proceed to step S1020; otherwise, if the abandonment condition is not met, return to step S1030.

[0079] Step S1040: Read and store the instructions and data temporarily stored in the instruction area memory and the data area memory.

[0080] Please refer to Figure 11 , Figure 11 This is a continuation of another embodiment of the present invention. Figure 8The diagram illustrates the process steps of step S850, where the host device 101 begins reading the program from the microcontroller 100 (or 200) to back up and store the data. The following is a brief description of the process steps:

[0081] Step S1105: Begin preparing a backup to update the state of the microcontroller 100 (e.g., data in the register);

[0082] Step S1110: Determine whether the microcontroller 100 is ready to back up data. If it is ready to back up data, proceed to step S1125. Otherwise, if it is not ready to back up data, proceed to step S1115.

[0083] Step S1115: Determine whether the microcontroller 100's retry meets the abandonment condition. If the abandonment condition is met, proceed to step S1120. Otherwise, if the abandonment condition is not met, return to step S1110.

[0084] Step S1120: Unable to successfully read (fail to dump) the state of microcontroller 100 (e.g., data in the register);

[0085] Step S1125: Set the microcontroller 100 to an idle state;

[0086] Step S1130: Determine whether the microcontroller 100 is busy at this time. If the microcontroller 100 is busy at this time, the process proceeds to step S1135. Otherwise, if the microcontroller 100 is not busy at this time, the process proceeds to step S1140.

[0087] Step S1135: Determine whether the microcontroller 100's retry meets the abandonment condition. If the abandonment condition is met, proceed to step S1120; otherwise, if the abandonment condition is not met, return to step S1130.

[0088] Step S1140: Read the state of the microcontroller 100 (e.g., data from the register) for backup and storage.

[0089] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A microcontroller for coupling to a host device, wherein, The microcontroller includes: A read-only memory is used to permanently store a boot code; A static random access memory; and A control circuit, coupled to the read-only memory and the static random access memory, is configured to power on the microcontroller according to the boot code after a system restart of the host device, obtain the operating conditions of the microcontroller from the host device, temporarily store the operating conditions in the static random access memory, and load, set, and update a firmware program or restore the state of the microcontroller according to the operating conditions temporarily stored in the static random access memory.

2. The microcontroller as described in claim 1, wherein, The operating conditions include firmware information. The control circuit obtains the firmware information of the microcontroller from the host device, temporarily stores the firmware information in the static random access memory, and loads, sets, and updates the firmware based on the firmware information temporarily stored in the static random access memory.

3. The microcontroller as described in claim 1, wherein, The operating conditions include execution status information of one of the microcontrollers. The control circuit obtains the execution status information of the microcontroller from the host device, temporarily stores the execution status information in the static random access memory, and restores the status of the microcontroller based on the execution status information temporarily stored in the static random access memory.

4. The microcontroller as claimed in claim 1, wherein, The control circuit transmits the operating conditions to the host device, and backs up and stores the information of the operating conditions in a driver program of the host device or a storage device of the host device.

5. The microcontroller as described in claim 4, wherein, In response to a specific storage event sent by the host device, the control circuit backs up and stores the corresponding status information included in the information of the operating conditions in the storage device of the host device.

6. The microcontroller of claim 4, wherein, The microcontroller is also connected to an external flash memory via another serial peripheral interface bus. The control circuit transmits the operating conditions to the external flash memory, so that the information of the operating conditions is backed up and stored in the external flash memory.

7. The microcontroller of claim 1, wherein, These operating conditions are not permanently retained in the microcontroller.

8. A method of operating a microcontroller, the microcontroller being coupled to a host device, wherein, The operation method includes: Provide a read-memory unit to permanently store a boot code; Provide a static random access memory; After one of the host devices restarts, it boots up according to the boot code, obtains the operating conditions of one of the microcontrollers from the host device, and temporarily stores the operating conditions in the static random access memory; and Based on the operating conditions temporarily stored in the static random access memory, a firmware program is loaded, set, and updated, or a state of the microcontroller is restored.

9. The operating method as described in claim 8, wherein, The operating conditions include firmware information, and the operating method further includes: The firmware information of the microcontroller obtained from the host device is temporarily stored in the static random access memory, and the firmware information is loaded, configured and updated according to the firmware information temporarily stored in the static random access memory.

10. The operating method as described in claim 8, wherein, The operating conditions include execution status information of one of the microcontrollers, and the operating method further includes: The system obtains the execution status information of the microcontroller from the host device, temporarily stores the execution status information in the static random access memory, and restores the status of the microcontroller based on the execution status information temporarily stored in the static random access memory.

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