Method and apparatus for optimizing circuit design of digital in-memory computation macro

Abstract

This invention discloses a computer-implemented method for optimizing the circuit design of a Digital In-Memory Computation (DCIM) macro. The method includes: performing design space exploration (DSE) based on a DCIM macro template and the structural parameters of the DCIM macro to obtain a first design configured as a DCIM macro without pipeline stages, and multiple circuit units used to complete one or more pipeline stage couplings to provide a pipeline architecture; performing a rapid PPA evaluation on the first design based on power-performance-area (PPA) constraints and using a DCIM module library to determine the optimal pipeline architecture for the DCIM macro, thereby obtaining a second design; and performing timing margin-power co-tuning on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture based on the second design to obtain a third design for the DCIM macro.

Description

[0001] Cross-reference to related applications

[0002] The application claims priority to provisional application No. 63 / 743,242, filed with the United States Patent and Trademark Office on January 9, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The following content broadly relates to the design and optimization of in-memory computing (CIM) circuits, and more specifically, to computer-based implementation methods and related devices for optimizing the circuit design of digital CIM (DCIM) macros. Background Technology

[0004] For the sake of completeness, it is hereby clarified that any formatting restriction in any paragraph (one or more) of this disclosure, such as “[Reference X]”, shall be understood to refer to the corresponding reference “X” in the “References” section of this disclosure. For example, [Reference 10] refers to the reference

[10] listed in the “References” section of this disclosure, while [References 4-7] refers to references [4]-[7] accordingly.

[0005] It is known in the art that in-memory computing (CIM) research typically focuses on optimizing energy efficiency, which is considered more critical for edge artificial intelligence (AI) scenarios that emphasize low power consumption and high energy efficiency [References 1-4]. However, recent developments and breakthroughs in large language models (LLMs) have created a strong demand for high-performance AI accelerators for training LLMs [References 5, 6]. Figure 1 As described in the various high-performance AI scenarios outlined in 100, traditional CIM macros typically achieve peak energy efficiency primarily by significantly reducing voltage. However, this also reduces the operating frequency (e.g., below 300MHz, or even below 100MHz [References 1-4]), making them potentially unsuitable for high-performance applications. It's worth noting that TSMC has successfully applied 2-stage and 3-stage pipelined architectures to digital CIM (DCIM) macros by segmenting in-memory combinational logic and presenting pipelined DCIM at high frequencies (e.g., frequencies greater than 1GHz at high voltage [References 7-8]).

[0006] However, there is a general lack of systematic research and targeted optimization for pipelined DCIMs designed for high-performance scenarios. This may lead to challenges in terms of register overhead, pipeline stage timing margins, and design trade-offs.105 (i.e., reference) Figure 1 This can be explained as:

[0007] (1) The use of pipeline registers will bring a large area overhead to the chip, and this overhead will increase with the increase of pipeline stages, which is not advisable.

[0008] (2) Since only the critical path stage determines the chip’s highest frequency, the timing margin of the non-critical path can be used to further adjust the power consumption-performance-area (PPA) without reducing the overall chip performance.

[0009] (3) The number of pipeline stages and their location significantly affect the PPA trade-off. Determining the optimal pipeline DCIM architecture for a scenario requires exploring a large amount of design space. In this regard, traditional DCIM design often relies heavily on manual labor, which is unnecessarily time-consuming and inefficient for design space exploration (DSE).

[0010] Therefore, there is a need for solutions that can address at least one problem of the prior art and / or provide useful alternatives in the field. Summary of the Invention

[0011] The techniques described herein may relate to computer-based implementation methods and related devices for optimizing circuit designs for digital in-memory computing (DCIM) macros in terms of power, performance, and area efficiency.

[0012] According to a first aspect, a computer implementation method for optimizing the circuit design of a Digital In-Memory Computation (DCIM) macro is disclosed, comprising: performing Design Space Exploration (DSE) based on a DCIM macro template and structural parameters of the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages; and multiple circuit units used to complete one or more pipeline stage couplings to form a pipeline architecture, wherein the multiple circuit units include combinations of Static Random Access Memory (SRAM), Bitwise Multipliers (MUL), Adder Trees (AddT), and Shift Accumulators (SAc); performing a fast PPA evaluation on the first design based on power consumption-performance-area (PPA) constraints and using a DCIM module library to determine the optimal pipeline architecture of the DCIM macro in order to obtain its second design, wherein the second design is obtained by fast PPA evaluation. The maximum value of the set of points on the Pareto boundary formed by the PA evaluation corresponds to the indication of the optimal pipeline architecture, where its pipeline registers are based on true single-phase clock (TSPC) flip-flops (TSPC-FF); and based on the second design, timing margin-power joint tuning is performed on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture to obtain a third design of the DCIM macro, which includes evaluating a combination of all lower power modules for the non-critical paths based on delay and power consumption criteria to allow identification of a combination that meets the delay and power consumption criteria for selection as the third design, wherein the delay criterion limits the total delay configured for the combination to be as large as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture, and wherein the power consumption criterion limits the energy consumption of the combination to be as low as possible.

[0013] Alternatively, structural parameters can be provided by the designer of the DCIM macro.

[0014] Alternatively, PPA constraints can be defined by the designer of the DCIM macro.

[0015] Alternatively, performing a rapid PPA evaluation on the first design to determine the optimal pipeline architecture may include the number and location of pipeline stages to be allocated among the plurality of circuit units.

[0016] Alternatively, the structural parameters may include input height (H), weighted columns (C), minimum data precision (P), and storage-to-computation ratio (R).

[0017] Alternatively, the TSPC-FF can be configured as an 11T dynamic circuit unit.

[0018] Alternatively or concurrently, the method may also include: configuring a DCIM cell library based on a process design kit (PDK) that includes template designs of SRAM, full adders, and TSPC-FF, wherein the PDK is provided by a semiconductor foundry and includes template designs of standard circuit cells.

[0019] Alternatively, the DCIM module library can be configured based on the PDK and DCIM unit library.

[0020] Alternatively, the SRAM template design may include a standard version and a low-power version of the SRAM, wherein the low-power version is characterized by a higher threshold voltage (V) compared to the standard version. t It also features a unit structure with lower energy consumption and longer critical delay.

[0021] Alternatively, the template design of the full adder may include a normal version and a low-power version of the full adder, wherein the low-power version is characterized by a higher threshold voltage (V) compared to the normal version. t ), and a unit structure configured with lower energy consumption and longer critical delay.

[0022] Alternatively or alternatively, based on a third design, the DCIM macro can be configured to operate within a maximum frequency range between 1.03 GHz and 1.40 GHz.

[0023] Alternatively, based on a third design, DCIM macros can be manufactured via a 28nm CMOS node.

[0024] Alternatively or concurrently, the method may also include: a third design based on DCIM macros to generate a hierarchical schematic design.

[0025] Alternatively or alternatively, the first design of a DCIM macro can be a baseline design.

[0026] According to a second aspect, a computing device for optimizing circuit design of a Digital In-Memory Computation (DCIM) macro is disclosed, comprising: one or more memories having executable code; and one or more processors coupled to the one or more memories and configured to execute the code such that the device: performs Design Space Exploration (DSE) based on a DCIM macro template and structural parameters for the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages; and a plurality of circuit units used to complete one or more pipeline stages coupled to form a pipelined architecture, wherein the plurality of circuit units include combinations of Static Random Access Memory (SRAM), Bitwise Multipliers (MUL), Adder Trees (AddT), and Shift Accumulators (SAc); and performs a fast PPA evaluation on the first design based on power-performance-area (PPA) constraints and using a DCIM module library. To determine the optimal pipeline architecture of a DCIM macro, a second design is obtained, wherein the maximum value of the set of points on the Pareto boundary formed by fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, wherein its pipeline registers are based on true single-phase clock (TSPC) flip-flops (TSPC-FF); and based on the second design, timing margin-power joint tuning is performed on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture to obtain a third design of the DCIM macro, which includes evaluating combinations of all lower power modules in the non-critical paths based on delay and power consumption criteria to allow identification of a combination that meets the delay and power consumption criteria for selection as the third design, wherein the delay criterion dictates that the total delay for the combination should be maximized as much as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture, and wherein the power consumption criterion dictates that the power consumption of the combination should be minimized as much as possible.

[0027] According to a third aspect, a non-transitory computer-readable medium is disclosed, comprising executable code that, when executed by a processor of a computing device, causes the device to perform the method of the first aspect.

[0028] Further benefits and advantages of the aspects disclosed in the specification and drawings may become apparent. These benefits and / or advantages may be obtained individually from the various aspects and features in the specification and drawings, and need not be provided in their entirety for the purpose of obtaining one or more of these benefits and / or advantages. Attached Figure Description

[0029] The same reference numerals in the accompanying drawings denote the same or functionally similar elements in the respective individual views, and these drawings, together with the following detailed description, are incorporated in and form part of the specification to illustrate various aspects and explain the various principles and advantages according to this disclosure.

[0030] Figure 1 It describes an example high-performance AI scenario based on existing technologies, which raises the need for pipelined digital in-memory computing (DCIM) and presents challenges in terms of design trade-offs, register overhead, and stage timing margins.

[0031] Figure 2 This is a flowchart of a computer implementation method for optimizing the circuit design of a DCIM macro according to aspects of this disclosure.

[0032] Figure 3 Depicting aspects of this disclosure and Figure 2 The diagram illustrates the method.

[0033] Figure 4 The aspects based on this disclosure are described. Figure 2 The diagram illustrates the method for configuring automated design tools and further depicts the use of these tools in typical high-performance AI scenarios.

[0034] Figure 5 The aspects described in this disclosure are as follows: Figure 4 The concept of scalable DCIM macro templates and Design Space Exploration (DSE) used in automated design tools.

[0035] Figure 6 The aspects based on this disclosure are described. Figure 2 The method is used for the analysis of true single-phase clock flip-flops (TSPC-FF) in the pipeline register used for DCIM macros.

[0036] Figure 7 The aspects based on this disclosure are described. Figure 2 The method is used to analyze the timing margin-power joint tuning of non-critical paths in DCIM macros.

[0037] Figure 8 A chip micrograph depicting a test chip according to aspects of this disclosure is shown, including the use of... Figure 4 The example DCIM macro is designed using automated design tools.

[0038] Figure 9a The arrangement in accordance with aspects of this disclosure is described. Figure 8 The corresponding pipeline architecture and related circuit characteristics of the DCIM macro in the test chip.

[0039] Figure 9b According to aspects of the present invention, conventional DCIM macros are combined with... Figure 8 The measurement results are compared with the DCIM macros arranged in the test chip.

[0040] Figure 10 The aspects of this disclosure are described for evaluation Figure 8 A schematic diagram and photograph of the test platform for the test chip.

[0041] Figure 11 Depicting aspects of this disclosure for Figure 8 The DCIM macro arranged in the test chip, and the Shmoo plot of the measurement results of the relationship between frequency and voltage.

[0042] Figure 12 This disclosure shows aspects related to... Figure 8 Measurement results of pipeline stage delay and power crash of DCIM macros arranged in the test chip.

[0043] Figure 13 and Figure 14 This is a block diagram of a device for optimizing the circuit design of a DCIM macro according to aspects of this disclosure.

[0044] Figure 15 This is a block diagram of a computation manager for optimizing the circuit design of DCIM macros according to aspects of this disclosure.

[0045] Figure 16 It is for implementation according to aspects of this disclosure. Figure 2 A schematic diagram of an exemplary computing device for the method.

[0046] Figure 17 It is for implementation according to aspects of this disclosure. Figure 2 A schematic diagram of an exemplary computing device for the method. Detailed Implementation

[0047] This disclosure describes methods and corresponding devices for optimizing circuit design of digital in-memory computing (DCIM) macros to improve power-performance-area (PPA) efficiency. Specifically, the proposed method 200 (i.e., see [link to method 200]) Figure 2 This method enables a scalable pipelined DCIM macro architecture, which is named "PipeDCIM" (hereinafter referred to as "PipeDCIM") in this paper. The method 200 can be implemented as an end-to-end automated design tool (hereinafter referred to as the "PipeDCIM design tool"), partially used for agile development and PPA optimization of DCIM macro circuit design. Furthermore, method 200 can also be considered a pipelined optimization method for DCIM macros.

[0048] According to this disclosure, the proposed method 200 can achieve the following (but is not limited to):

[0049] 1) Based on PipeDCIM, scalable DCIM macro templates are provided to enable exploration and design of pipeline stages, which are related to the number and location allocation of pipeline stages in the DCIM macro. Based on the scalable templates, the PipeDCIM design tool allows for rapid design space exploration (DSE) and can further enable the automatic generation of circuits for specific scenarios required by chip designers.

[0050] 2) PipeDCIM uses true single-phase clock flip-flops (TSPC-FF) to implement the pipelined registers, which are considered as an 11T dynamic structure with fewer transistors to reduce on-chip area overhead. Because PipeDCIM may update the pipelined registers frequently, data retention issues caused by dynamic circuit leakage are mitigated in high-performance scenarios.

[0051] 3) By selectively replacing ordinary cells with slower, low-power cells, PipeDCIM achieves joint timing margin and power optimization of non-critical paths of DCIM macros, thereby enabling energy saving without causing performance loss to DCIM macros.

[0052] The following description provides examples of methods and corresponding devices for optimizing the circuit design of DCIM macros, but they do not limit the scope, applicability, or examples described in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various procedures or components may be omitted, substituted, or added as needed in the various examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to certain examples may be combined into other examples. For example, any number of aspects described herein may be used to implement the device, or any number of aspects described herein may be used to practice the method. Furthermore, the scope of this disclosure is intended to cover such devices or methods practiced using structures, functions, or structures and functions other than or different from the aspects disclosed herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements in the claims. The term “exemplary” as used herein means “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects.

[0053] Aspects of this disclosure will be described by way of example only and with reference to the accompanying drawings. Like reference numerals and characters in the drawings denote like elements or equivalents.

[0054] Figure 2 This is a flowchart illustrating a computer-implemented method 200 for optimizing a DCIM macro circuit design according to aspects of this disclosure. The operation of method 200 can be implemented by computing devices 1600, 1700 (or components thereof), such as... Figure 16-17 As described. For example, the operation of method 200 can be derived from a reference. Figure 13-14 The described computation managers 1315 and 1415 execute and can be installed on and execute on computation devices 1600 and 1700 (or components thereof). In some examples, computation devices 1600 and 1700 (or components thereof) can execute a set of instructions to control the functional elements of computation devices 1600 and 1700 to perform the functions described below. Alternatively or additionally, computation devices 1600 and 1700 can use dedicated hardware to perform aspects of the functions described below.

[0055] In step 205, method 200 may include: performing a design space exploration (DSE) based on a DCIM macro template and the structural parameters of the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages, and multiple circuit units that will be used to complete one or more pipeline stage couplings to form a pipelined architecture. These multiple circuit units may include combinations of static random access memory (SRAM), bitwise multipliers (MUL), adder trees (AddT), and shift accumulators (SAc). It will be understood that the structural parameters can be provided by the designer of the DCIM macro. The structural parameters of the DCIM macro are considered as top-level structural parameters of the DCIM macro, and they may include the following: input height (H), weight column (C), minimum data precision (P), and storage-to-computation ratio (R). Furthermore, the first design of the DCIM macro can be considered as a baseline design.

[0056] In step 210, method 200 may include: performing a fast PPA evaluation on a first design based on power-performance-area (PPA) constraints and using a DCIM module library to determine the optimal pipeline architecture for the DCIM macro, in order to obtain its second design, wherein the maximum value of the set of points on the Pareto boundary formed by the fast PPA evaluation corresponds to an indication of the optimal pipeline architecture. According to method 200, the pipeline registers in the optimal pipeline architecture will be implemented based on true single-phase clock (TSPC) flip-flops (TSPC-FF) configured as 11T dynamic circuit cells. It will be understood that the PPA constraints can be limited by the designer of the DCIM macro.

[0057] Alternatively, it should be emphasized that performing a rapid PPA evaluation on the first design to determine the optimal pipeline architecture may include the number and location of pipeline stages to be allocated among the multiple circuit units. In this context, the term "location" refers to where the pipeline stages will be positioned among the multiple circuit units.

[0058] In step 215, method 200 may include: performing timing margin-power joint tuning on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture, based on the second design, to obtain a third design for the DCIM macro. Performing timing margin-power joint tuning includes evaluating combinations of all lower-power modules used in the non-critical paths based on delay and power consumption criteria (i.e., delay criterion and power consumption criterion) to allow identification of a combination that meets the delay and power consumption criteria for selection as the third design. The delay criterion limits the total delay configured for the combination to be as large as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture. The power consumption criterion then limits the energy consumption of the combination to be as low as possible.

[0059] In some examples, method 200 may also optionally include: a third design based on the DCIM macro, generating a hierarchical schematic design of the DCIM macro that facilitates its fabrication.

[0060] In some examples, based on a third design, the DCIM macro can be configured to operate over a maximum frequency range between 1.03 GHz and 1.40 GHz. Additionally, or alternatively, based on a third design, the DCIM macro can be fabricated using a 28nm CMOS node (e.g., from TSMC).

[0061] In some implementations, the operation of method 200 may be programmed and stored as corresponding computer-readable code executable by computing devices 1600, 1700 (or components thereof).

[0062] Alternatively or concurrently, method 200 may also include: a DCIM cell library configured with template designs including SRAM, full adders, and TSPC-FFs based on a process design kit (PDK), wherein the PDK may be provided by a semiconductor foundry and may include template designs of standard circuit cells such as AND gates, NOR gates, AOI gates, NAND gates, D-type flip-flops (DFFs), MUXs, etc.

[0063] In some aspects, the DCIM module library can be configured based on the PDK and DCIM unit library.

[0064] In some aspects, the SRAM template design can include a standard version and a low-power version of the SRAM, wherein the low-power version is characterized by a higher threshold voltage (V) compared to the standard version. t), and a cell structure configured to have lower energy consumption and longer critical delay.

[0065] In another aspect, the template design of the full adder can include a normal version and a low-power version of the full adder, wherein the low-power version is characterized by a higher threshold voltage (V) compared to the normal version. t ), and a cell structure configured to have lower energy consumption and longer critical delay.

[0066] According to aspects of this disclosure, a computing device for optimizing the circuit design of digital in-memory computing (DCIM) macros is disclosed (e.g., such as...). Figure 16-17 The depicted computing device (1600, 1700) includes: one or more memories having executable code; and one or more processors coupled to the one or more memories and configured to execute the code to cause the device to:

[0067] 1) Based on the DCIM macro template and the structural parameters of the DCIM macro, perform design space exploration (DSE) to obtain a first design of the DCIM macro configured without pipeline stages, and multiple circuit units that will be used to complete one or more pipeline stage couplings to form a pipeline architecture, wherein the multiple circuit units include a combination of static random access memory (SRAM), bitwise multiplier (MUL), adder tree (AddT) and shift accumulator (SAc);

[0068] 2) Based on power-performance-area (PPA) constraints and using the DCIM module library, perform a fast PPA evaluation on the first design to determine the optimal pipeline architecture for the DCIM macros, thereby obtaining its second design. The maximum value of the set of points on the Pareto boundary formed by the fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, where its pipeline registers are based on true single-phase clock (TSPC) flip-flops (TSPC-FF).

[0069] 3) Based on the second design, perform timing margin-power joint tuning on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture to obtain a third design for the DCIM macro. This includes evaluating all combinations of lower power modules in the non-critical paths based on delay and power consumption criteria to allow identification of a combination that meets the delay and power consumption criteria to be selected as the third design. The delay criterion specifies that the total delay of the combination should be maximized as much as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture. The power consumption criterion specifies that the energy consumption of the combination should be minimized as much as possible.

[0070] The following description elaborates on further details of the above-mentioned aspects of the disclosed method 200.

[0071] According to this disclosure, Figure 3 Depicting and Figure 2 The method 200 proposed in the diagram 300 is related to this. More specifically, based on PipeDCIM, a scalable DCIM macro template 305 is proposed for scalable DCIM macro structures with pipeline design space, such as... Figure 3 As shown. The macro template 305 is designed to be logically divided into the following segments (or parts): SRAM segment, MUL segment, AddT segment and SAc segment, which together with peripherals for input feeding and output fusion form a whole.

[0072] It is important to understand that, as required by the design, pipeline stages can be assigned and inserted between different segments, or they can be assigned and inserted into the hierarchy within the AddT segment.

[0073] Based on the design specifications defined by the designer (i.e., the user of the PipeDCIM design tool), the proposed method 200 comprises three aspects, which can be implemented as corresponding features in the PipeDCIM design tool: a pipeline register optimizer 310 (referred to as feature 1), a timing margin-power joint tuning operator 315 (referred to as feature 2), and a tool-aided pipeline parameter explorer 320 (referred to as feature 3). The tool-aided pipeline parameter explorer 320 is configured to receive input in the form of a user specification 325 for the expected DCIM macro, and a generic design file 330 from at least one PDK (which may be provided by a foundry). Therefore, the PipeDCIM design tool may be able to implement an optimized pipeline strategy 335 (as output) that determines the circuit design for the DCIM macro.

[0074] Feature 1: The pipeline register optimizer 310 implements circuit optimization steps designed to utilize fewer transistors in register circuit design, thereby reducing the area overhead associated with arranging pipeline stages in the DCIM macro. For example, in pipeline registers, dynamic 11TTSPC-FFs can be advantageously used instead of standard DFFs. Because the DCIM macro frequently updates the pipeline registers, data retention issues caused by dynamic circuit leakage can be avoided compared to using TSPC-FFs in high-performance scenarios.

[0075] Feature 2: The timing margin-power joint tuning operator 315 implements a further circuit optimization step designed to provide a functional unit-level design based on a slower (in terms of delay speed) and lower power implementation. Since the highest frequency achieved in the DCIM macro is determined by the associated delay of the critical path, it is possible to improve the overall energy efficiency of the DCIM macro without suffering a frequency drop (and thus affecting performance) by increasing the total delay of the non-critical paths (of the DCIM macro) to be (sufficiently) close to, or in other words, as close as possible to, the critical delay, while simultaneously reducing power consumption.

[0076] In this context, "close to (critical delay)" means that the total delay is as close as possible to, but does not exceed, the critical delay. It should be understood that, in the context of this disclosure, it may not be possible to provide a precise numerical value to technically define "close," as this value can vary depending on the circumstances, since the definition of "close" to the critical delay depends at least on the specific design of the DCIM macro and the design options available in each case. Instead, the general guideline is to minimize timing margins: during the timing margin-power joint tuning process, among all possible combinations of non-critical paths used to implement the DCIM macro, the combination that provides the maximum delay while still being less than or equal to the critical delay is selected as the final combination.

[0077] Feature 3: The disclosed method 200 can be implemented under the PipeDCIM design tool to easily explore the allocation of the number and arrangement of pipeline stages, providing a flexible and scalable approach to optimize the circuit design of DCIM macros. Based on the scalable DCIM macro template, pipeline stage designs with various configurations can then be generated using the PipeDCIM design tool, allowing for rapid identification of the optimal pipeline design for the DCIM macros relevant to the desired use case.

[0078] According to this disclosure, Figure 4 Depicting based on Figure 2 The proposed method 200 is illustrated in the diagram 400 of the PipeDCIM design tool, and it further describes the use of the tool in a typical high-performance AI scenario (where maximum performance is set as the first objective, minimum power is set as the second objective, and the chip area of ​​the DCIM macro should be ≤A, where “A” is a user-defined parameter).

[0079] Specifically, the PipeDCIM design tool is designed to integrate the following features: a pipeline register optimizer 310 (i.e., feature 1), a timing margin-power joint tuning operator 315 (i.e., feature 2), and a tool-aided pipeline parameter explorer 320 (i.e., feature 3), as referenced above. Figure 3The PipeDCIM design tool can be understood to be executed in a sequence of three main steps: (1) DCIM library setup (i.e., in...). Figure 4 (2) DCIM pipeline exploration (i.e., in the middle marked as "step 0" 405); Figure 4 (marked as "Step 1" 410); and (3), timing margin-power joint tuning (i.e. Figure 4 (marked as "Step 2" 415).

[0080] In step 0 405, a custom DCIM cell library 420 is developed based on the PDK provided by the (semiconductor) foundry, which includes template designs for SRAM cells, full adder (FA) cells, and TSPC-FF cells. The PDK provides a standard cell library 425 for the basic cells. It should be understood that the template designs for SRAM cells and FA cells have both standard and low-power versions, the latter characterized by a threshold voltage (V) t The low-power version is configured to use transistors with higher threshold voltages in the cell circuitry, or to configure other cell structures with the same functionality but lower leakage power (i.e., thus lower power consumption), but with a longer critical latency. Based on the standard cell library 425 and the custom DCIM cell library 420, a PipeDCIM-based DCIM module library 430 was developed, which has design files for all types of cell modules (that can be used to design DCIM macros). Therefore, step 0 405 can be considered as initializing the DCIM module library 430. It should be understood that in some examples, step 0 405 may be optional, as these libraries may also be alternatively provided by third-party software vendors as standalone software modules (therefore, initializing the DCIM module library 430 is unnecessary).

[0081] In step 1 410, after the library initialization is completed in step 0 405, the PipeDCIM design tool is configured to be based on the extensible DCIM macro template 305 (as described below). Figure 3 The required specifications for the DCIM macro (discussed below) and user-provided DCIM macros are used to perform DSE. These specifications include the structural parameters and PPA constraints of the DCIM macro. The structural parameters can set the design of the baseline DCIM macro (i.e., the first design), which uses a conventional cell arrangement and is pipeline-free. As mentioned above, the structural parameters can include the following: input height (H), weight column (C), minimum data precision (P), and storage-to-computation ratio (R). The scalable DCIM macro template 305 can be based on the DCIM module library 430. It should be understood that the process under step 1 410 can correspond to step 205 of the disclosed method 200.

[0082] Then, based on the first design, a pipeline architecture exploration (through rapid PPA evaluation) is performed to form a design space to explore and determine the different numbers of pipeline stages and the possible arrangements of these pipeline stages. It should be understood that this process can correspond to step 210 of the disclosed method 200. Taking into account PPA constraints and using the DCIM cell library, a Pareto boundary is formed by performing a rapid PPA evaluation on the first design to derive a second design with an optimal pipeline architecture. The maximum value of the set of points on the Pareto boundary corresponds to an indication of the optimal pipeline architecture to be achieved under the first objective of highest performance.

[0083] In step 2,415, the PipeDCIM design tool is configured to further perform timing margin-power joint tuning on the non-critical paths of the DCIM macro based on the second design, to derive a third design for the expected DCIM macro. It should be understood that this process can correspond to step 215 of the disclosed method 200. By exploring different lower-power module versions, the (overall) total latency of the non-critical paths (in the design) is increased to near-critical levels, thereby maximizing the power reduction to be achieved under the second objective of minimum power.

[0084] It's important to understand that in this context, "exploring different lower-power module versions" means that all possible combinations of low-power versions will be systematically explored and evaluated by the PipeDCIM design tool at step 2415. That is, for each combination that generates the final design of the DCIM macro, the latency and power consumption of the design are evaluated. The process of selecting a specific combination (from all combinations) as the final design of the DCIM macro is described below:

[0085] (1) Delay Constraints: Among all combinations, first determine the combination of key delay constraints for the design that is closest to, but does not exceed, the overall (total) delay of the DCIM macro. In some cases, it is possible that only one combination will be determined.

[0086] (2) Power Optimization: If multiple combinations are determined to meet the criteria under delay constraints, the combination with the lowest total power consumption is selected as the third design for the target DCIM macro. Therefore, the selected combination is the one that meets the delay requirements and uses the least power for the target DCIM macro. Thus, timing margin-power joint tuning is a thorough search and evaluation process performed by the PipeDCIM design tool, guided by delay and power consumption criteria.

[0087] Therefore, the PipeDCIM design tool outputs a third design (as the final design) of the DCIM macro with the lowest power consumption and no (or minimal) performance loss, and can also generate hierarchical schematic designs for the DCIM macro to facilitate its subsequent manufacturing. The PipeDCIM design tool is also designed to allow for the installation of future plug-in extensions for advanced technologies, macro architectures, and circuit design techniques.

[0088] Figure 5 The aspects described in this disclosure are as follows: Figure 4 The PipeDCIM design tool uses the Scalable DCIM Macro Template 500 and the concept of Design Space Exploration (DSE). It's important to understand that the DCIM Macro Template 500 here is related to... Figure 3 The same as the extensible DCIM macro template 305. Furthermore, it should be understood that each segment in the DCIM macro template 500 (i.e., SRAM segment, MUL segment, AddT segment, and SAc segment) is constructed from pre-implemented DCIM modules (i.e., P×R-bSRAM, P×1-bMUL, Pb ADD) in the DCIM module library 430, where the SRAM and ADD modules can be adjusted by modifying the SRAM and FA unit versions.

[0089] Based on DSE, Figure 5 It also shows that at 0.9V, TSMC 28 nm CMOS node, with parameters H=256, C=64, P=4 / 8, and R=1, the pipelined DSE only trades off with the DSE of a regular cell. To reiterate, H represents height, C represents weighted columns, P represents minimum data precision, and R represents the memory-to-computation ratio. The chip size of the baseline DCIM macro without pipelined design is 0.6347 mm. 2 It runs at 427.48MHz. Figure 5 In the frequency diagram 505 depicted, Design A was evaluated as the highest performance point, and the DCIM macro (under Design A) is arranged with 3 pipeline stages, with pipeline registers inserted after the 7-b ADD stage and at the end of AddT. The DCIM macro under Design A is configured to operate at a frequency of 1.12 GHz, which is 2.62 times higher than the baseline design, while incurring only 2.85% of the area overhead cost.

[0090] Again in Figure 5 In the same frequency diagram 505 depicted, Design B represents the highest performance point. The DCIM macro (under Design B) is configured with four pipeline stages, with adjustments made to the pipeline stage positions in AddT and the addition of new pipeline stages. The DCIM macro under Design B operates at a frequency of 1.33 GHz, which is 3.11 times higher than the baseline design, while incurring only 9.53% of the area overhead cost.

[0091] Figure 6 The aspects described in this disclosure are based on Figure 2 The proposed method 200 analyzes the TSPC-FF in the pipelined register of the DCIM macro 600. Compared to the standard DFF, the TSPC-FF is an 11T dynamic circuit that requires no reset logic. The TSPC-FF is configured with 11 transistors, while the standard DFF is configured with 17 transistors. This reduction in transistor usage advantageously saves 2.63 times the chip area and further reduces power consumption by 1.44 times. Figure 6 As shown, during initialization, holding the input may automatically reset all registers along the pipeline stage, thus eliminating the need for specific reset logic for pipeline registers. Furthermore, while the dynamic architecture of TSPC-FF may cause data retention issues, these are essentially resolved and mitigated by the high-frequency pipelined implementation under PipeDCIM.

[0092] In measurements, at 0.9V and the TSMC 28 nm CMOS node, the retention time of the TSPC-FF was measured to be 227.8 ns. This time is considered within the safe margin for maintaining data integrity because it is significantly longer than the typical clock cycle (e.g., less than 1 ns) of a high-frequency pipeline under PipeDCIM. Therefore, by using the TSPC-FF in the pipeline registers, 2.25x and 2.24x pipeline register area can be saved in Design A and Design B, respectively, which reduces the corresponding ratios to 2.78% and 8.69% of the total DCIM macro area, respectively. It is important to understand that the term "ratio" in the context of the preceding statements refers to the ratio of the area occupied by the TSPC-FF to the total area of ​​the entire DCIM macro. In addition to the savings in chip area for implementing the pipeline registers, the operating power of the corresponding DCIM macros under Design A and Design B can be reduced by 7.29% and 16.32%, respectively, and the latency per pipeline stage can be reduced by 0.96% to 11.34%.

[0093] Figure 7 The invention is based on aspects described. Figure 2 Method 200 analyzes the timing margin-power joint tuning of non-critical paths in a DCIM macro. In a DCIM macro, SRAM and AddT cells typically account for over 70% of the power consumption [Reference 8], and therefore, according to Method 200, it is recommended to perform timing margin-power joint tuning on SRAM and FA cells (i.e., also refer to...). Figure 4 Step 2 (415) in which: 1-b SRAM cells are in a standard version (e.g., at a standard V of 382.6mV). t (at) and two low-power versions (e.g., high V, 457.1mV) t At; and an ultra-high V of 529.1mV. tThe 1-b FA unit is then implemented in 28T, 14T, and 12T versions to construct the ADD module. For the 4-b SRAM module, high and ultra-high V... t They achieved energy savings of 28.63% and 47.83% respectively, and extended the delay by 1.14 times and 1.23 times respectively.

[0094] For the 4-b ADD module, the 14T and 12T versions achieved energy savings of 3.88% and 51.11% respectively, with latency increases of 1.10 times and 2.87 times. (Reference) Figure 5 In Design B discussed earlier, "Stage 3" (of the pipeline stage) is considered the critical path. "Stage 4" (of the pipeline stage) has a relatively short timing margin, so adjusting Stage 4 may only result in a reduction of approximately 0.90% in operating power. "Stage 1" and "Stage 2" (of the pipeline stage) achieve delay increases of 1.18x and 1.17x, respectively, but not exceeding the delay of Stage 3, and achieve operating power reductions of 17.22% and 36.29%. At the same frequency, the entire DCIM macro achieves an operating power reduction of 9.06%.

[0095] In one example, design B is used to verify the techniques disclosed in method 200, wherein five example DCIM macros are designed using the PipeDCIM design tool and arranged in a wafer micrograph of test chip 800 for testing and verification purposes—see [link to documentation]. Figure 8 The dimensions of the test chip 800 were measured to be approximately 2.558 mm (L) x 2.558 mm (W). Figure 8 For ease of discussion in this paper, the five DCIM macros on the test chip 800 are labeled as "Macro 0" 805-a, "Macro 1" 805-b, "Macro 2" 805-c, "Macro 3" 805-d and "Macro 4" 805-e.

[0096] Figure 9a The arrangement according to aspects of this disclosure is described in Figure 8 The corresponding pipeline architectures 900 of the five DCIM macros 805-a, 805-b, 805-c, 805-d, and 805-e in the test chip 800, and a summary table 905 detailing the relevant circuit characteristics.

[0097] Refer again Figure 8In one example, the five DCIM macros 805-a, 805-b, 805-c, 805-d, and 805-e are manufactured using a TSMC 28nm CMOS node. It should be understood that, in this example, the DCIM macros 805-a, 805-b, 805-c, 805-d, and 805-e are configured with capacities ranging from 8 to 256 Kb and wafer sizes ranging from 0.0863 to 1.0350 mm. 2 With a maximum frequency of 1.03 to 1.40 GHz and operating at 45.27 to 125.73 mW at 0.9 V, it can be used as a CIM core for various high-performance AI applications. Comparing a functionally equivalent baseline without pipeline with a baseline designed using the proposed method 200, the proposed DCIM macros 805-a, 805-b, 805-c, 805-d, and 805-e achieve 1.93 to 3.12 times higher frequencies and 1.79 to 2.70 times better energy efficiency, while power and area increase by only 1.02 to 1.15 times and 1.04 to 1.10 times, respectively.

[0098] According to this disclosure, Figure 8 The DCIM macro marked "Macro 0" in the 805-a test chip 800 was also compared with the traditional CIM macro, such as... Figure 9b The description. Figure 9b Table 905 shows the measurement results comparing “Macro 0” 805-a with conventional DCIM macros. In one example, “Macro 0” 805-a is configured to operate from 0.6 to 0.9 V and from 0.30 to 1.24 GHz. Advantageously, due to the use of DSE provided by the PipeDCIM design tool, the optimal pipeline architecture can be determined under given constraints. The pipeline architecture proposed under PipeDCIM achieves frequencies 5.39 times and 5.08 times higher than two non-pipelined CIM macros in 28nm [References 1-2] at 0.9 V. The operating frequencies evaluated for “Macro 0” 805-a are even comparable to two pipelined TSMC DCIM macros configured in more advanced 4nm and 3nm nodes (operating at 1.49 GHz and 1.60 GHz, respectively) [References 7-8].

[0099] Due to the acceleration provided by feature 1 (i.e., reference) Figure 3 (Discussion at the location) and the energy-saving features provided by characteristics 2-3 (i.e., also refer to the discussion at the location) and features 2-3. Figure 3(As discussed in the previous section), PipeDCIM achieves a peak INT8 energy efficiency of 29.82 TOPS / W at 0.9V, which is 1.09 times and 1.44 times higher than the prior art in [Reference 1] and [Reference 2], respectively, which focus on energy efficiency optimization. Silicon verification results demonstrate that, with the aid of the PipeDCIM design tool, the proposed scalable PipeDCIM architecture provides a promising solution for flexible DCIM development. It is important to understand that the PipeDCIM design tool allows users to easily develop custom DCIM macros by simply providing structural parameters and PPA constraints. The proposed IC design approach may advantageously contribute to a sustainable ecosystem for DCIM macros and processors, particularly in the rapidly evolving field of AI applications.

[0100] Figure 10 The aspects of this disclosure are described for evaluation Figure 8 A schematic diagram and photograph of the test platform 1000 for the test chip 800 are shown. In this platform, the FPGA transmits control signals and data to the test chip 800, and the DC power supply provides the test chip 800 with a core voltage of 0.7 to 1.0V. The calculation results collected by the FPGA from the test chip 800 are forwarded to the computer for analysis.

[0101] Figure 11 Depicting aspects of this disclosure regarding Figure 8 Shmoo Figure 1100 shows the measurement results of the frequency-voltage relationship of the DCIM macros 805-a, 805-b, 805-c, 805-d, and 805-e configured in the test chip 800. It is worth noting that the frequency measured at 0.9V reached 1.24GHz (approximately 93.23% close to the simulation), which verifies the accuracy of the design implemented using the PipeDCIM design tool.

[0102] Figure 12 This disclosure shows aspects relating to [the present disclosure]. Figure 8 The pipeline stage delay and power crash measurements were obtained for four of the five DCIM macros configured in the test chip 800: 805-b, 805-c, 805-d, and 805-e.

[0103] Figure 13 This is a block diagram of device 1305 for optimizing the circuit design of a DCIM macro according to aspects of this disclosure. Device 1305 may be... Figure 16-17 Examples of aspects of the 1600 and 1700 computing devices, and which can be configured to perform... Figure 2Method 200. Device 1305 may include receiver 1310, computing manager 1315, and transmitter 1320. Computing manager 1315 may be implemented at least in part by one or both of a modem and a processor. Each of these components may communicate with each other (e.g., via one or more buses).

[0104] Receiver 1310 can receive information related to various information channels (e.g., control channels, data channels, etc.), such as data packets, user data, or control information. This information can be passed to other components of device 1305. Receiver 1310 can be an example of a radio receiver or an Ethernet adapter. In some examples, receiver 1310 may use a single antenna or a set of antennas (e.g., for MIMO communication).

[0105] The Compute Manager 1315 can be configured to perform the following operations:

[0106] (1) Based on the DCIM macro template and the structural parameters of the DCIM macro, perform design space exploration (DSE) to obtain a first design of the DCIM macro configured without pipeline stages, and multiple circuit units that will be used to complete one or more pipeline stages coupled to form a pipeline architecture, wherein the multiple circuit units include a combination of static random access memory (SRAM), bitwise multiplier (MUL), adder tree (AddT) and shift accumulator (Sac);

[0107] (2) Based on power-performance-area (PPA) constraints and using the DCIM module library, a fast PPA evaluation is performed on the first design to determine the optimal pipeline architecture of the DCIM macros in order to obtain its second design, wherein the maximum value of the set of points on the Pareto boundary formed by the fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, wherein its pipeline registers are based on true single-phase clock (TSPC) flip-flops (TSPC-FF); and

[0108] (3) Based on the second design, perform timing margin-power joint tuning on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture to obtain a third design for the DCIM macro, which includes: evaluating all combinations of lower power modules in the non-critical paths based on delay and power consumption criteria to allow the identification of combinations that meet the delay and power consumption criteria for selection as the third design, wherein the delay criterion qualifies that the total delay for the combination will be maximized as much as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture, and wherein the power consumption criterion qualifies that the energy consumption of the combination will be minimized as much as possible.

[0109] Transmitter 1320 can transmit signals generated by other components of device 1305. For example, transmitter 1320 may be an example of a radio transmitter or an aspect of an Ethernet adapter. In some examples, transmitter 1320 may use a single antenna or a set of antennas (e.g., for MIMO communication). In some examples, transmitter 1320 may be co-located with receiver 1210 in a transceiver assembly.

[0110] Figure 14 This is a block diagram of device 1405 for optimizing the circuit design of a DCIM macro according to aspects of this disclosure. Device 1405 may be... Figure 16-17 Examples of aspects of device 1305 or computing devices 1600, 1700, and which can be configured to perform Figure 2 Method 200. Device 1405 may include receiver 1410, computing manager 1415, and transmitter 1420. Computing manager 1415 may be implemented at least in part by one or both of a modem and a processor. Each of these components may communicate with each other (e.g., via one or more buses).

[0111] Receiver 1410 can receive information related to various information channels (e.g., control channels, data channels, etc.), such as data packets, user data, or control information. The information can be passed to other components of device 1405. Receiver 1410 can be an example of a radio receiver or an Ethernet adapter. Receiver 1410 can use a single antenna or a set of antennas (e.g., for MIMO communication).

[0112] The compute manager 1415 may include a first (first) execution component 1425, a second (second) execution component 1430, and a third (third) execution component 1435.

[0113] The first execution component 1425 can perform design space exploration (DSE) based on the DCIM macro template and the structural parameters of the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages, and multiple circuit units that will be used to complete one or more pipeline stage couplings to form a pipeline architecture, wherein the multiple circuit units include combinations of static random access memory (SRAM), bitwise multipliers (MUL), adder trees (AddT), and shift accumulators (Sac).

[0114] The second execution component 1430 can perform a fast PPA evaluation on the first design based on power-performance-area (PPA) constraints and using the DCIM module library to determine the optimal pipeline architecture of the DCIM macro in order to obtain its second design, wherein the maximum value of the set of points on the Patolei boundary formed by the fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, wherein its pipeline register is based on a true single-phase clock (TSPC) flip-flop (TSPC-FF).

[0115] The third execution component 1435 can perform timing margin-power joint tuning on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture, based on the second design, to obtain a third design for the DCIM macro. This includes evaluating all combinations of lower-power modules for the non-critical paths based on delay and power consumption criteria to allow identification of a combination that meets the delay and power consumption criteria for selection as the third design. The delay criterion specifies that the total delay for the combination should be maximized as much as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture, and the power consumption criterion specifies that the energy consumption of the combination should be minimized as much as possible.

[0116] In some examples, the first execution component 1425, the second execution component 1430, and the third execution component 1435 can be implemented as a single execution component configured to jointly perform all the functions of the three components 1425, 1430, and 1435.

[0117] Transmitter 1420 can transmit signals generated by other components of device 1405. For example, transmitter 1420 may be an example of a radio transmitter or an Ethernet adapter. Transmitter 1420 may use a single antenna or a set of antennas (e.g., for MIMO communication). In some examples, transmitter 1420 may be co-located with receiver 1410 in a transceiver assembly.

[0118] Figure 15 This is a block diagram of a communication manager 1505 for optimizing the circuit design of a DCIM macro according to aspects of this disclosure. The communication manager 1505 may be the calculation manager 1315 described herein. Figure 13 (in Chinese) or Calculator Manager 1415 ( Figure 14 Examples of aspects of (the following). The communication manager 1505 may include a first execution component 1510, a second execution component 1515, and a third execution component 1520. Each of these components may communicate directly or indirectly with each other 1525 (e.g., via one or more buses).

[0119] The first execution component 1510 can perform design space exploration (DSE) based on the DCIM macro template and the structural parameters of the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages, and multiple circuit units that will be used to complete one or more pipeline stages coupled to form a pipeline architecture, wherein the multiple circuit units include combinations of static random access memory (SRAM), bitwise multipliers (MUL), adder trees (AddT), and shift accumulators (Sac).

[0120] The second execution component 1515 can perform a fast PPA evaluation on the first design based on power-performance-area (PPA) constraints and using the DCIM module library to determine the optimal pipeline architecture of the DCIM macro in order to obtain its second design, wherein the maximum value of the set of points on the Patolei boundary formed by the fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, wherein its pipeline register is based on a true single-phase clock (TSPC) flip-flop (TSPC-FF).

[0121] The third execution component 1520 can perform timing margin-power joint tuning on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture based on the second design to obtain a third design for the DCIM macro. This includes evaluating all combinations of lower power modules in the non-critical paths based on delay and power consumption criteria to allow identification of a combination that meets the delay and power consumption criteria to be selected as the third design. The delay criterion specifies that the total delay for the combination will be maximized as much as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture, and the power consumption criterion specifies that the energy consumption of the combination will be minimized as much as possible.

[0122] In some examples, it is feasible that the first execution component 1510, the second execution component 1515, and the third execution component 1520 can be implemented as a single execution component configured to jointly perform all the functions of the three components 1510, 1515, and 1520.

[0123] Figure 16 It is based on aspects of this disclosure for implementation and execution. Figure 2 A schematic diagram of an exemplary (first) computing device 1600 of method 200.

[0124] The computing device 1600 may include a keyboard 1602, a touchscreen 1604, a microphone 1606, a speaker 1608, and an antenna 1610. Users can operate the computing device 1600 to perform various functions / tasks, such as making phone calls, sending SMS messages, browsing the Internet, sending emails, and providing satellite navigation.

[0125] The computing device 1600 may include hardware to perform communication functions (such as telephone or data communication), as well as an application processor and corresponding supporting hardware to enable the computing device 1600 to perform other functions, such as messaging, internet browsing, email, etc. The communication hardware may include a radio frequency (RF) processor 1612 that provides RF signals to an antenna 1610 for transmitting and receiving data signals from the antenna 1610. A baseband processor 1614 may be provided that provides signals to and receives signals from the RF processor 1612. The baseband processor 1614 may also interact with a Subscriber Identity Module (SIM) 1616, as is known in the art. The communication subsystem enables the computing device 1600 to communicate via a variety of different communication protocols, including 3G, 4G, 5G, New Radio (NR), GSM, WiFi, and Bluetooth. TM And / or CDMA. The communication subsystem of computing device 1600 is beyond the scope of this disclosure.

[0126] The keyboard 1602 and touchscreen 1604 are controlled by the application processor 1618. A power and audio controller 1620 is provided to supply power from the battery 1622 to the communication subsystem, application processor 1618, and other hardware. The power and audio controller 1620 can also control input from the microphone 1606 and audio output through the speaker 1608. A Global Positioning System (GPS) antenna and associated receiver element 1624 are also provided, controlled by the application processor 1618 and capable of receiving GPS signals for use with the satellite navigation function of the computing device 1600.

[0127] Various types of memory can be provided in computing device 1600 to complement the operation of application processor 1618. Computing device 1600 may include random access memory (RAM) 1626 coupled to application processor 1618, where data and program code can be written to and read from. Executable code stored in RAM 1626 can be executed by application processor 1618 from RAM 1626. RAM 1626 represents a form of volatile memory in computing device 1600.

[0128] The computing device 1600 may also include a non-volatile (long-term) storage device 1628 coupled to an application processor 1618. The storage device 1628 may be logically divided into three partitions: an operating system (OS) partition 1630, a system partition 1632, and a user partition 1634. The storage device 1628 may represent the non-volatile memory of the computing device 1600.

[0129] In one example, OS partition 1630 may contain the firmware of computing device 1600, which includes the operating system. Other computer programs, such as applications (also known as apps), may also be stored in storage device 1628. Specifically, in the case of smartphones, communication applications, etc., applications considered essential to the operation of computing device 1600 are typically stored in system partition 1632. Applications stored on system partition 1632 are typically programmed with their default factory settings on computing device 1600.

[0130] Applications subsequently added and installed by the user on computing device 1600 can typically be stored in user partition 1634.

[0131] Figure 16 The various functional components shown can alternatively be combined into a single component. For example, storage device 1628 may include NAND flash memory, NOR flash memory, hard disk drive, or a combination thereof.

[0132] Figure 17 The aspects of this disclosure are available for implementation and execution. Figure 2 A schematic diagram of an exemplary (second) computing device 1700 for method 200. The following description of computing device 1700 is provided by way of example only and is not intended to be limiting.

[0133] like Figure 17 As depicted, the example computing device 1700 may include a processor 1704 for executing software routines / programs. Although only a single processor is shown for simplicity, the computing device 1700 may also be configured as a multiprocessor system (i.e., containing multiple processors). The processor 1704 is coupled to a communication infrastructure 1706 for communicating with other components of the computing device 1700. The communication infrastructure 1706 may include, for example, a communication bus, a crossbar network, or a network.

[0134] The computing device 1700 also includes a main memory 1708, such as random access memory (RAM), and a secondary memory 1710. The secondary memory 1710 may include, for example, a hard disk drive 1712 and / or a removable storage drive 1714, which may include a floppy disk drive, a magnetic tape drive, an optical disk drive, etc. The removable storage drive 1714 reads from and / or writes to the removable storage unit 1718, as known in the art. The removable storage unit 1718 may include a floppy disk, magnetic tape, optical disk, Universal Serial Bus (USB) flash drive, etc., which may be read from and / or written to by the removable storage drive 1714. As will be appreciated by those skilled in the art, the removable storage unit 1718 may also include a computer-readable storage medium in which computer-executable program code instructions and / or data are stored.

[0135] In other respects, the auxiliary memory 1710 may additionally or alternatively include other similar devices for allowing computer programs or other instructions to be loaded into the computing device 1700 for execution. Such devices may include, for example, a removable storage unit 1722 and an associated interface 1720. Examples of removable storage units 1722 and interfaces 1720 may include a USB flash drive and USB interface, a program card and card interface (e.g., a program card and card interface as found in video game console devices), a removable memory chip (e.g., EPROM or PROM) and an associated slot, as well as other exemplary removable storage units 1722 and interfaces 1720 that enable the transfer of software programs and / or data between the removable storage unit 1722 and the computing device 1700.

[0136] The computing device 1700 also includes at least one communication interface 1724. The communication interface 1724 allows software programs and data to be transferred between the computing device 1700 and external devices via a communication path 1726. In various aspects, the communication interface 1724 allows data to be transferred between the computing device 1700 and a data communication network (e.g., a public or private data communication network). The communication interface 1724 can be used to exchange data between different computing devices 1700 that may together form part of an interconnected computer network. Examples of the communication interface 1724 may include a modem, a network interface (e.g., an Ethernet card), a communication port, an antenna with associated circuitry, etc. The communication interface 1724 can be configured to be wired or wireless. The software and data transmitted through the communication interface 1724 are in the form of signals, which may be electronic signals, electromagnetic signals, optical signals, or other signals that can be received by the communication interface 1724. These signals are provided to the communication interface via the communication path 1726.

[0137] The computing device 1700 may also include a display interface 1702 configured to perform operations of rendering an image to an associated display 1730, and an audio interface 1732 configured to perform operations of playing audio content via one or more associated speakers 1734.

[0138] As used herein, the term "computer program product" may refer in part to removable storage unit 1718, removable storage unit 1722, hard disk installed in hard disk drive 1712, or a carrier wave carrying software transmitted to communication interface 1724 via communication path 1726 (e.g., via a wireless link or cable). Computer-readable storage medium refers to any non-transitory tangible storage medium that provides recorded instructions and / or data to computing device 1700 for execution and / or processing. Examples of such storage media include floppy disks, USB drives, magnetic tapes, CD-ROMs, DVDs, and Blu-ray discs. TM Disks, hard disk drives, ROMs or integrated circuits, USB storage devices, magneto-optical disks, or computer-readable cards (such as PCMCIA cards), whether such devices are located inside or outside the computing device 1700. Examples of transient or non-tangible computer-readable transmission media that may also be involved in providing software, applications, instructions, and / or data to the computing device 1700 include radio or infrared transmission channels, network connections to another computer or networked device, and the Internet or intranet, including email transmissions and information recorded on websites.

[0139] The computer program (also referred to as computer program code / instructions) is stored in main memory 1708 and / or auxiliary memory 1710. The computer program may also be received via communication interface 1724. When executed, such a computer program enables computing device 1700 to perform one or more aspects of the present disclosure. In various aspects of the present disclosure, the computer program, when executed, enables processor 1704 to perform one or more aspects of the present disclosure. Therefore, such a computer program can represent the (logic) controller of computing device 1700.

[0140] The software can be stored in a computer program product and loaded onto a computing device 1700 using a removable storage drive 1714, a hard disk drive 1712, or an interface 1720. Alternatively, the computer program product can be downloaded directly to the computing device 1700 via communication path 1726. When executed by the processor 1704, the software causes the computing device 1700 to perform aspects of this disclosure.

[0141] What will be understood is... Figure 17The computing device 1700 shown is for illustrative purposes only. Therefore, in some aspects, one or more features of the computing device 1700 may be omitted. Furthermore, in other aspects, one or more features of the computing device 1700 may be combined or juxtaposed. Additionally, in some aspects, one or more features of the computing device 1700 may be separated into one or more component parts.

[0142] What will be understood is... Figure 17 The elements shown can also be used to provide execution Figure 2 The various functional means of the method 200 disclosed herein, as described in aspects of this disclosure, are as follows. Furthermore, the terms "computing device" 1600, 1700 may include or refer to mobile devices, wireless devices, remote devices, handheld devices, smartphones, tablets, laptops, computer servers, computer terminals, blade servers, and other examples. The computing devices 1600, 1700 described herein may be capable of communicating with various types of devices, such as other computing devices 1600, 1700 that may sometimes act as repeaters, or working together in a configuration to function as a computer cluster to perform high-performance computing.

[0143] All methods described herein are presented with possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are also possible. Furthermore, aspects of two or more methods may be combined, if applicable.

[0144] The information and signals described herein can be represented using a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout this specification can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0145] The various example boxes and components described herein can be implemented or performed by a general-purpose processor, DSP, ASIC, CPU, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0146] The functions described herein can be implemented by hardware, software executed by a processor, firmware, or any combination thereof. If implemented by software executed by a processor, these functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in different locations, including portions distributed such that functions are implemented at different physical locations.

[0147] Computer-readable media include non-transitory computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium accessible to a general-purpose or special-purpose computer. For example, and not limitingly, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), flash memory, compact disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the required program code in the form of instructions or data structures and is accessible to a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of computer-readable media. The discs and platters used in this article include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Discs typically copy data magnetically, while platters use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0148] As used herein (including in the claims), the word "or" in a list of items (e.g., a list of items beginning with phrases such as "at least one" or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (e.g., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0149] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, different components of the same type can be distinguished by a dashed line following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second or other subsequent reference numerals.

[0150] The exemplary configurations described herein, in conjunction with the accompanying drawings, are not representative of all implementable or claim-scoped examples. The term "example" as used herein means "serving as an example, instance, or illustration," and not "preferred" or "superior to other examples." The detailed description includes specific details intended to provide an understanding of the techniques described. However, these techniques can be practiced without these specific details. In some cases, known structures and devices are shown in block diagram form to avoid obscuring the concepts of the examples.

[0151] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

[0152] Example

[0153] According to this disclosure, the following examples are disclosed.

[0154] Example 1: A computer-implemented method for optimizing the circuit design of a Digital In-Memory Computation (DCIM) macro, comprising: performing a design space exploration (DSE) based on a DCIM macro template and structural parameters of the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages, and a plurality of circuit units that will be used to complete one or more pipeline stages coupled to form a pipeline architecture, wherein the plurality of circuit units include combinations of static random access memory (SRAM), bitwise multipliers (MUL), adder trees (AddT), and shift accumulators (Sac); performing a fast PPA evaluation on the first design based on power-performance-area (PPA) constraints and using a DCIM module library to determine the optimal pipeline architecture of the DCIM macro to obtain its second design, wherein the second design is further defined by the circuit design of the DCIM macro. The maximum value of the set of points on the Pareto boundary formed by the fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, wherein its pipeline register is based on true single-phase clock (TSPC) flip-flops (TSPC-FF); and based on the second design, timing margin-power joint tuning is performed on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture to obtain a third design of the DCIM macro, which includes evaluating all combinations of lower power modules in the non-critical paths based on delay and power consumption criteria to allow identification of a combination that meets the delay and power consumption criteria to be selected as the third design, wherein the delay criterion qualifies that the total delay for the combination will be maximized as much as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture, and wherein the power consumption criterion qualifies that the power consumption of the combination will be minimized as much as possible.

[0155] Example 2: Following the method of Example 1, where the structural parameters are provided by the designer of the DCIM macro.

[0156] Example 3: The method of any of Examples 1-2, where the PPA constraint is limited by the designer of the DCIM macro.

[0157] Example 4: According to the method of any one of Examples 1-3, a fast PPA evaluation is performed on the first design to determine the optimal pipeline architecture, including the number and location of pipeline stages to be allocated among the plurality of circuit units.

[0158] Example 5: Following the method of Example 4, the structural parameters include input height (H), weight column (C), minimum data precision (P), and storage-to-computation ratio (R).

[0159] Example 6: The method of any one of Examples 1-5, wherein the TSPC-FF is configured as an 11T dynamic circuit unit.

[0160] Example 7: The method according to any one of Examples 1-6 further includes: configuring a DCIM cell library based on a process design kit (PDK) that includes template designs of SRAM, full adders and TSPC-FF, wherein the PDK is provided by a semiconductor foundry and includes template designs of standard circuit cells.

[0161] Example 8: Following the method in Example 7, the DCIM module library is configured based on the PDK and the DCIM cell library.

[0162] Example 9: According to the method of Example 7, the SRAM template design includes a normal version and a low-power version of the SRAM, wherein the low-power version is characterized by a higher threshold voltage (V) compared to the normal version. t ) and configured as a cell structure with lower energy consumption and longer critical delay.

[0163] Example 10: According to the method of Example 7, the template design of the full adder includes a normal version and a low-power version of the full adder, wherein the low-power version is characterized by a higher threshold voltage (V) compared to the normal version. t ) and configured as a cell structure with lower energy consumption and longer critical delay.

[0164] Example 11: According to the method of any one of Examples 1-10, where, based on the third design, the DCIM macro is configured to operate in the maximum frequency range between 1.03 GHz and 1.40 GHz.

[0165] Example 12: According to any of the methods in Examples 1-11, where, based on the third design, the DCIM macro will be manufactured via a 28nm CMOS node.

[0166] Example 13: Based on any of the methods in Examples 1-12, it also includes: a third design based on DCIM macros to generate a hierarchical schematic design.

[0167] Example 14: According to any of the methods in Examples 1-13, where the first design of the DCIM macro is the baseline design.

[0168] Example 15: A computing device for optimizing circuit design of a Digital In-Memory Computation (DCIM) macro, comprising: one or more memories having executable code; and one or more processors coupled to the one or more memories and configured to execute the code to cause the device to: perform design space exploration (DSE) based on a DCIM macro template and structural parameters of the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages; and a plurality of circuit units that will be used to complete one or more pipeline stages coupled to form a pipelined architecture, wherein the plurality of circuit units include combinations of static random access memory (SRAM), bitwise multipliers (MUL), adder trees (AddT), and shift accumulators (Sac); and perform a fast PPA evaluation on the first design based on power-performance-area (PPA) constraints and using a DCIM module library to determine the performance-area (PPA) of the first design. The optimal pipeline architecture of the DCIM macro is determined to obtain its second design, wherein the maximum value of the set of points on the Pareto boundary formed by the fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, wherein its pipeline register is based on a true single-phase clock (TSPC) flip-flop (TSPC-FF); and based on the second design, timing margin-power joint tuning is performed on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture to obtain a third design of the DCIM macro, which includes evaluating all combinations of lower power modules in the non-critical paths based on delay and power consumption criteria to allow identification of a combination that meets the delay and power consumption criteria to be selected as the third design, wherein the delay criterion determines that the total delay for the combination will be maximized as much as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture, wherein the power consumption criterion determines that the power consumption of the combination will be minimized as much as possible.

[0169] Example 16: A computing device for optimizing circuit design of a Digital In-Memory Computation (DCIM) macro, comprising: a device for performing design space exploration (DSE) based on a DCIM macro template and structural parameters of the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages; and a plurality of circuit units that will be used to complete one or more pipeline stage couplings to form a pipeline architecture, wherein the plurality of circuit units include combinations of static random access memory (SRAM), bitwise multipliers (MUL), adder trees (AddT), and shift accumulators (Sac); and a device for performing a fast PPA evaluation on the first design based on power-performance-area (PPA) constraints and using a DCIM module library to determine the optimal pipeline architecture of the DCIM macro to obtain a second design thereof, wherein... The maximum value of the set of points on the Pareto boundary formed by the fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, wherein its pipeline register is based on a true single-phase clock (TSPC) flip-flop (TSPC-FF); and a device that performs timing margin-power joint tuning on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture based on the second design to obtain a third design of the DCIM macro, which includes a device that evaluates all combinations of lower power modules in the non-critical paths based on delay and power consumption criteria to allow identification of a combination that meets the delay and power consumption criteria to be selected as the third design, wherein the delay criterion specifies that the total delay for the combination will be maximized as much as possible and less than or equal to the delay of the critical path in the determined optimal pipeline architecture, and wherein the power consumption criterion specifies that the power consumption of the combination will be minimized as much as possible.

[0170] Example 17: A non-transitory computer-readable medium comprising executable code that, when executed by a processor of a computing device, causes the device to perform the method of any one of Examples 1-14.

[0171] References

[0172] [1] Y. He et al., “A 28nm 38-to-102-TOPS / W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference”, ISSCC, pp. 130-131, 2023. https: / / doi.org / 10.1109 / ISSCC42615.2023.10067305

[0173] [2] A. Guo et al., “A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs”, ISSCC, pp. 570-571, 2024. https: / / doi.org / 10.1109 / ISSCC49657.2024.10454278

[0174] [3] P. Chen et al., “A 22nm Delta-Sigma Computing-In-Memory (ΔΣCIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38 TOPS / W for 8b-MAC Edge AI Processing”, ISSCC, pp. 140-141, 2023. https: / / doi.org / 10.1109 / ISSCC42615.2023.10067289

[0175] [4] S. Hsieh et al., “A 70.85–86.27 TOPS / W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation”, ISSCC, pp. 136–137, 2023. https: / / doi.org / 10.1109 / ISSCC42615.2023.10067335

[0176] [5] F. Tu et al., “MuITCIM: A 28nm 2.24uJ / Token Attention-Token-Bit HybridSparse Digital CIM Based Accelerator for Multimodal Transformers”, ISSCC, pp. 248-249, 2023. https: / / doi.org / 10.1109 / ISSCC42615.2023.10067842

[0177] [6] S. Kim et al., “DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching”, ISSCC, pp. 256-257, 2023. https: / / doi.org / 10.1109 / ISSCC42615.2023.10067352

[0178] [7] H. Mori et al., “A 4nm 6163-TOPS / W / b 4790-TOPS / mm2 / b SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update,” ISSCC, pp. 132-133, 2023. https: / / doi.org / 10.1109 / ISSCC42615.2023.10067555

[0179] [8] H. Fujiwara et al., “A 3nm, 32.5TOPS / W, 55.0TOPS / mm2 and 3.78Mb / mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12×INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell”, ISSCC, pp. 572-573, 2024. https: / / doi.org / 10.1109 / ISSCC49657.2024.10454556

Claims

1. A computer-implemented method for optimizing the circuit design of a Digital In-Memory Computation (DCIM) macro, the method comprising: Design space exploration (DSE) is performed based on the DCIM macro template and the structural parameters of the DCIM macro to obtain a first design of the DCIM macro configured without pipeline stages, and multiple circuit units used to complete one or more pipeline stages coupled to form a pipeline architecture. The plurality of circuit units include a combination of static random access memory (SRAM), bitwise multiplier (MUL), adder tree (AddT), and shift accumulator (Sac); Based on power-performance-area (PPA) constraints and using the DCIM module library, a fast PPA evaluation is performed on the first design to determine the optimal pipeline architecture of the DCIM macros to obtain its second design, wherein the maximum value of the set of points on the Pareto boundary formed by the fast PPA evaluation corresponds to the indication of the optimal pipeline architecture, wherein its pipeline registers are based on true single-phase clock (TSPC) flip-flops (TSPC-FF); and Based on the second design, timing margin-power joint tuning is performed on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture to obtain a third design of the DCIM macro, which includes: evaluating all combinations of lower power modules in the non-critical paths based on latency and power consumption criteria to allow identification of a combination that meets the latency and power consumption criteria to select it as the third design; The latency criterion is configured such that the total latency used for combination is maximized and is less than or equal to the latency of the critical path in the determined optimal pipeline architecture. The power consumption standard limits the energy consumption of the combination to be as low as possible.

2. The method according to claim 1, characterized in that, The structural parameters are provided by the designer of the DCIM macro.

3. The method according to claim 1, characterized in that, The PPA constraints are defined by the designer of the DCIM macro.

4. The method according to claim 1, characterized in that, Performing a rapid PPA evaluation on the first design to determine the optimal pipeline architecture includes determining the number and location of pipeline stages to be allocated among the plurality of circuit units.

5. The method according to claim 4, characterized in that, The structural parameters include input height (H), weight column (C), minimum data precision (P), and storage-to-computation ratio (R).

6. The method according to claim 1, characterized in that, The TSPC-FF is configured as an 11T dynamic circuit unit.

7. The method according to claim 1, characterized in that, Also includes: Based on the Process Design Kit (PDK), configure a DCIM cell library that includes template designs for SRAM, full adders, and TSPC-FF. The PDK is provided by a semiconductor foundry and includes a template design for standard circuit units.

8. The method according to claim 7, characterized in that, Configure the DCIM module library based on the PDK and the DCIM unit library.

9. The method according to claim 7, characterized in that, The SRAM template design includes a standard version and a low-power version of the SRAM, wherein the low-power version is characterized by a higher threshold voltage (V) compared to the standard version. t It also features a unit structure with lower energy consumption and longer critical delay.

10. The method according to claim 7, characterized in that, The template design of the full adder includes a normal version and a low-power version of the full adder, wherein the low-power version is characterized by a higher threshold voltage (V) compared to the normal version. t It also features a unit structure with lower energy consumption and longer critical delay.

11. The method according to claim 1, characterized in that, Based on the third design, the DCIM macro is configured to operate within a maximum frequency range of 1.03 GHz to 1.40 GHz.

12. The method according to claim 1, characterized in that, Based on the third design, the DCIM macro will be manufactured using a 28nm CMOS node.

13. The method according to claim 1, characterized in that, Also includes: Based on the third design of the DCIM macro, a hierarchical schematic design is generated.

14. The method according to claim 1, characterized in that, The first design of the DCIM macro is the baseline design.

15. A computing device for optimizing the circuit design of digital in-memory computing (DCIM) macros, comprising: One or more memories containing executable code; as well as One or more processors, coupled to the one or more memories and configured to execute the code, to cause the device to: Based on the DCIM macro template and the structural parameters of the DCIM macro, a design space exploration (DSE) is performed to obtain a first design of the DCIM macro configured without pipeline stages, and multiple circuit units used to complete one or more pipeline stages coupled to form a pipeline architecture. The plurality of circuit units include a combination of static random access memory (SRAM), bitwise multiplier (MUL), adder tree (AddT), and shift accumulator (Sac); Based on power-performance-area (PPA) constraints and using the DCIM module library, a fast PPA evaluation is performed on the first design to determine the optimal pipeline architecture of the DCIM macro for obtaining its second design. The maximum value of the set of points on the Pareto boundary formed by the fast PPA evaluation corresponds to an indication of the optimal pipeline architecture, where its pipeline registers are based on True Single-Phase Clock (TSPC) flip-flops (TSPC-FF). Based on the second design, timing margin-power joint tuning is performed on the non-critical paths of the DCIM macro defined by the optimal pipeline architecture to obtain a third design for the DCIM macro, which includes: evaluating all combinations of lower power modules in the non-critical paths based on latency and power consumption criteria to allow identification of a combination that meets the latency and power consumption criteria to select it as the third design. The latency criterion is configured such that the total latency used for combination is maximized and is less than or equal to the latency of the critical path in the determined optimal pipeline architecture. The power consumption standard limits the energy consumption of the combination to be as low as possible.

16. A non-transitory computer-readable medium comprising executable code, which, when executed by a processor of a computing device, causes the device to perform the method of claim 1.

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