A method for optimizing the thermal effects of gallium arsenide PP laser chips

Abstract

This invention provides a thermal effect optimization design method for gallium arsenide (GaAs) PP laser chips, relating to the field of optical chip manufacturing technology. It establishes a carrier injection field, heat source density field, quantum well temperature field, thermally induced refractive index field, cavity surface absorption thermal field, and P-surface interface thermal resistance field. The P-surface is divided into thermal impedance coding units. The thermal failure chain gain of each unit is calculated, and the dominant amplification node is identified. This generates a P-surface thermal impedance coding layout, P-type side epitaxial heat source migration parameters, cavity surface cold end breakage structure parameters, solder low-impedance alignment pattern, and segmented electrode connection diagram. This method configures ohmic injection, insulating thermal conduction, current-limiting trenches, thick metal thermal ridges, solder anchoring, and segmented electrode assignment in local regions of the P-surface according to the thermal failure chain. It is applicable to the design, manufacturing, packaging, and testing of high-power continuous-output GaAs-based pumped laser chips.

Description

Technical Field

[0001] This invention relates to the field of optical chip manufacturing technology, specifically to a method for optimizing the thermal effects of gallium arsenide PP laser chips. Background Technology

[0002] Gallium arsenide (GaAs)-based semiconductor laser chips have important applications in fiber laser pump sources, lidar emission sources, industrial processing light source modules, and high-reliability optoelectronic systems. P-plane power-type GaAs-based pumped laser chips typically employ an epitaxial structure with the quantum well active region close to the P-plane, connected to the solder layer, heat sink, and external heat dissipation structure via a P-plane-down flip-chip configuration. This structure shortens the heat conduction path from the quantum well to the heat sink. However, under high-power continuous operation conditions, the coupling of P-side series resistance heat, P-plane contact heat, cavity surface absorption heat, and solder interface thermal resistance leads to localized hot spots, wavelength drift, far-field angle drift, cavity surface thermal instability, and output power attenuation.

[0003] Current chip thermal design typically aims to reduce average junction temperature and average thermal resistance, focusing on techniques such as thickening the P-side metal, using high thermal conductivity heat sinks, improving end-face film tolerance, and reducing solder voids. These measures treat the epitaxial structure, electrode layout, cavity structure, and packaging interface as independent improvement targets, lacking a unified modeling of localized thermal failure propagation paths. In actual failure processes, current injection first creates Joule heating at the high-resistance location on the P-side. This localized heat source is transferred to the quantum well, causing a temperature rise. This temperature rise leads to changes in the effective refractive index and lateral thermal lensing. Optical mode shift alters the cavity surface photon flux distribution. The cavity surface photon flux, along with end-face absorption, forms cavity surface absorption heat. When this heat flux is released through the P-side solder interface, it is amplified by localized interface thermal resistance. This process constitutes a continuous thermal failure chain, and simply reducing the average thermal resistance cannot stop the localized amplification nodes.

[0004] Therefore, a thermal effect optimization design method is needed that can simultaneously process the epitaxial heat source location, P-side current injection distribution, cavity surface heat source superposition, solder interface low impedance alignment, and finished product operating current distribution during the chip design stage. This method can directly convert the design results into epitaxial growth parameters, P-side mask patterns, end face structure parameters, solder patterns, and segmented electrode control parameters, thereby solving the problem of local thermal failure chain amplification in gallium arsenide PP laser chips during high-power continuous operation. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for optimizing the thermal effects of gallium arsenide PP laser chips, thus solving the problems of existing technologies.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for optimizing the thermal effect of a gallium arsenide (GaAs) PP laser chip, wherein the GaAs PP laser chip is a P-plane power-type GaAs-based pumped laser chip, comprising a GaAs substrate, an N-type confinement layer, a waveguide layer, a quantum well active layer, a P-type confinement layer, a P-type contact layer, a P-plane composite metal layer, an N-plane metal layer, a front cavity film layer, a rear cavity film layer, a P-plane welding interface, and a heat sink. The method includes: establishing a three-dimensional model of the chip including a carrier injection field, a heat source density field, a quantum well temperature field, a thermally induced refractive index field, a cavity surface absorption thermal field, and a P-plane interface thermal resistance field; dividing the P-plane projection region into... The thermal impedance encoding unit, and for the first Each thermal impedance encoding unit establishes a three-dimensional control region. ,in ; calculate the first one respectively Electrothermal conversion amplification factor of each thermal impedance encoding unit Quantum well temperature rise amplification factor Thermally induced refractive index magnification factor Cavity surface heat absorption amplification factor and interface thermal resistance amplification factor And obtain the first according to the following formula Thermal failure chain gain of each thermal impedance encoding unit According to the thermal failure chain gain And the dominant amplification node among the five amplification factors, generating the first The encoding vector of each thermal impedance encoding unit Based on the encoding vectors of all thermal impedance encoding units, the P-side thermal impedance encoding layout, P-type side epitaxial heat source migration parameters, cavity cold end chain breakage structure parameters, solder low impedance alignment pattern, and segmented electrode connection diagram are generated. ; ; in, Inject the domain area into the Ohm domain. For the area of ​​the insulating and thermally conductive zone, The equivalent cross-sectional area of ​​the thermal ridge of the thick metal. The equivalent length of the flow-limiting trench. For local interface thermal resistance, Number the segmented electrodes.

[0007] Preferably, the three-dimensional model of the chip has the center of the P-plane composite metal layer as the origin and the length direction of the resonant cavity as the coordinate axis. The axis is defined by the horizontal width direction of the light strip. The axis is the thickness direction of the epitaxial layer. The input data includes the target emission wavelength, cavity length, emission stripe width, number of quantum well layers, quantum well location, N-type confinement layer thickness, waveguide layer thickness, P-type confinement layer thickness, P-type contact layer thickness, P-type side doping concentration distribution, P-plane composite metal layer material and thickness, front cavity surface reflectivity, rear cavity surface reflectivity, solder material, solder thickness, heat sink material, target operating current, and target output power; the data output by the chip 3D model includes location. Current density at Material conductivity Heat source density Temperature rise Thermally induced refractive index change Light field intensity Cavity surface photon flux Heat flux vector and local interface thermal resistance ,in Indicates the internal spatial location of the chip.

[0008] Preferably, the electrothermal conversion amplification factor, quantum well temperature rise amplification factor, thermally induced refractive index amplification factor, cavity surface heat absorption amplification factor, and interface thermal resistance amplification factor are determined according to the following formulas: ; ; ; ; ; in, For the active region of the quantum well, For the cavity surface thermal sensitive area, This is the P-side interface area. To activate only the first The thermal impedance encoding unit has a heat source location. Temperature rise at the location, For the first Total thermal power of each thermal impedance encoding unit For the first The thermally induced refractive index change caused by the temperature rise of each thermal impedance encoding unit The cavity surface absorption coefficient, For the first The cavity surface photon flux caused by the thermal impedance coding unit after thermally induced optical mode shift The cavity surface reference photon flux. For the first Each thermal impedance encoding unit generates a heat flow vector that flows to the P-face interface region. , , , and These are the normalized constants for current, thermal power, optical field, photon flux, and heat flux, respectively.

[0009] Preferably, the dominant amplification node is determined according to the node contribution rate, and the node contribution rate is: ; in, For the first In the thermal impedance encoding unit, the first The contribution rate of each amplification node Indicates the electrothermal conversion node. Indicates the quantum well temperature rise node. Indicates the thermally induced refractive index drift node. Indicates the heat absorption node on the cavity surface. Indicates the interface thermal resistance node. For the first In the thermal impedance encoding unit, the first The magnification factor of each magnification node. The translation constant is the nodal magnification factor. Number the nodes to be summed; assign the first node to the summation node. In each thermal impedance encoding unit The node with the maximum value is determined as the dominant amplification node, and the encoding vector is adjusted according to the dominant amplification node. The corresponding structural parameters in.

[0010] Preferably, when the dominant amplification node is an electrothermal conversion node, the area of ​​the ohmic injection domain is reduced. And increase the equivalent length of the flow-limiting trench. When the dominant amplification node is the quantum well temperature rise node, the area of ​​the insulating thermally conductive domain is increased. and the equivalent cross-sectional area of ​​the thick metal thermal ridge When the dominant amplification node is a thermally induced refractive index drift node, adjust the distribution of the ohmic injection domain in the lateral width direction and adjust the distribution density of the thick metal thermal ridge in the edge region of the light-emitting strip; when the dominant amplification node is a cavity surface absorption heat node, set a cavity surface no-injection retreat band, a band gap lifting low absorption band, and a lateral thermal bridge; when the dominant amplification node is an interface thermal resistance node, adjust the solder low impedance alignment pattern in relation to the first... The position of the solder anchoring domain relative to each thermal impedance coding unit and the thickness of the heat sink transition layer.

[0011] Preferably, the area of ​​the ohmic injection domain, the area of ​​the insulating thermally conductive domain, and the equivalent cross-sectional area of ​​the thick metal thermal ridge are determined according to the following formulas: ; ; ; in, The total area of ​​a single thermal impedance coding unit. The lower limit of the area ratio of the Ohm injection domain. The upper limit of the area ratio of the Ohm injection domain. This is the baseline value for the gain in the thermal failure chain. For the first The area occupied by the current-limiting trenches, dielectric isolation boundaries, and process safety clearances within each thermal impedance coding unit. The minimum equivalent cross-sectional area of ​​the thermal ridge of thick metal. It represents the maximum equivalent cross-sectional area of ​​the thermal ridge of thick metal.

[0012] Preferably, the migration parameters of the P-type side epitaxial heat source include the thickness of the low-absorbing carrier buffer layer, the doping gradient of the resistive thermal migration layer, the thickness of the high-conductivity thermal release layer, the thickness of the P-type contact layer, and the contact resistance modulation distribution. The center of the P-type side heat source is determined according to the following formula: ; in, This refers to the location of the center of the P-type heat source in the thickness direction. The boundary coordinates of the quantum well near the P-type side are: The boundary coordinates of the P-type contact layer near the P-face composite metal layer are given. Coordinates of the P-type epitaxial layer in the thickness direction Heat source density at that location, The thickness direction is a micro-element; the migration parameters of the P-type side epitaxial heat source satisfy... ,in This is the safe separation distance between the center of the P-type heat source and the boundary of the quantum well.

[0013] Preferably, the cavity surface cold end break-chain structure parameters include the length of the non-injection receding band on the front cavity surface, the length of the non-injection receding band on the rear cavity surface, the length of the bandgap lift low absorption band, the width of the transverse thermal bridge, the thickness of the end-face stress buffer film, and the position of the P-face cold end anchoring region. The normalized overlap coefficient of the cavity surface heat source, current injection, and optical field intensity is: ; in, This is the normalized overlap coefficient among the cavity surface heat source, current injection, and optical field intensity. For position Density of heat source absorbed at the cavity surface The heat source normalization constant; the parameters of the cold end chain break structure of the cavity surface satisfy... ,in This represents the upper limit of the overlap coefficient of the three fields of the cavity surface.

[0014] Preferably, the low-impedance alignment pattern of the solder is determined according to an interface alignment coefficient, wherein the interface alignment coefficient is: ; in, This is the interface alignment factor between the P-side thermal impedance coding unit and the low-impedance region of the solder. For the first Thermal failure chain weights of each thermal impedance encoding unit For the first The thermal extraction capability of each thermal impedance encoding unit For the first The low impedance level of the solder interface below each thermal impedance coding unit; the solder low impedance alignment pattern satisfies ,in The lower limit of the interface alignment coefficient is set, and a solder anchoring domain and a heat sink transition layer are set below the thermal impedance encoding unit with high thermal failure chain weight.

[0015] Preferably, the segmented electrode connection diagram includes a first working electrode, a second working electrode, and a third working electrode, wherein the connection of the first working electrode satisfies the following conditions: The main gain injection region, the second working electrode connection satisfies The compensation injection region, the third working electrode connection satisfies Or a controlled injection region adjacent to the thermally sensitive area of ​​the cavity surface, wherein The gain threshold of the first thermal failure chain. The gain threshold for the second thermal failure chain is defined as follows: After packaging, low duty cycle test pulses are applied to the first, second, and third working electrodes, respectively, and the result is obtained according to the following formula. Thermal risk index of each working electrode And determine the first Operating current of each working electrode : ; ; in, This represents the rate of change of voltage over time. The rate of change of wavelength with current. This represents the lateral offset of the near-field center. For transient thermal resistance, , , and These are the weighting coefficients. This represents the total operating current of the chip. Number the segments of the electrode summation.

[0016] This invention provides a method for optimizing the thermal effects of gallium arsenide (GaAs) PP laser chips. It offers the following advantages: 1. This invention establishes a thermal failure chain breakage model and generates a thermal impedance encoding unit array. It integrates the electrothermal conversion, quantum well temperature rise, thermally induced refractive index drift, cavity surface heat absorption, and interface thermal resistance amplification of the chip's local area into a solvable local thermal failure chain gain. Then, based on the dominant amplification node of each local area, it outputs the corresponding P-plane layout, epitaxial parameters, cavity surface structure, package alignment pattern, and segmented electrode connection relationship, so that the thermal effect optimization of the gallium arsenide PP laser chip is transformed from global average cooling to local failure chain breakage.

[0017] 2. This invention clarifies the source of thermal risk in each local region of the P-side through thermal failure chain gain calculation, transforming the design focus from the average thermal resistance of the entire chip to the breakage of local thermal failure chains. Through thermal impedance encoding units, the P-side simultaneously forms current injection paths, thermal extraction paths, current-limiting isolation paths, solder alignment positions, and segmented electrode assignments. By migrating the P-type epitaxial heat source, the main resistive thermal center of the P-type side is moved away from the quantum well and closer to the P-side heat dissipation path. The cavity surface cold-end chain-breaking structure reduces the overlap of end-face heat sources, current injection, and optical field intensity. Low-impedance solder alignment ensures that the strong heat extraction region inside the chip corresponds to the low interface thermal resistance region of the package. Segmented electrode thermal fingerprints and operating current allocation ensure that the finished chip allocates operating current according to actual thermal risk. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the layered structure and the flip-chip heat dissipation path of a gallium arsenide PP laser chip. Figure 2 This is a schematic diagram of a thermal failure chain fracture model; Figure 3 This is a schematic diagram of a P-plane thermal impedance coding unit array; Figure 4 This is a schematic diagram of the P-type side extensional heat source migration structure; Figure 5 This is a schematic diagram of the cold end chain breakage structure of the cavity surface; Figure 6 A schematic diagram of solder low-impedance alignment and segmented electrode thermal fingerprinting process; Figure 7 This is a schematic diagram of the chip structure of the present invention; Figure 8 This is a SEM image of the chip from the present invention; Figure 9 This is a screenshot of the interface of the optimized method of the present invention; Figure 10 This is a screenshot of the optimization method module of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Specific Implementation Example 1: like Figures 1 to 10 As shown, a method for optimizing the thermal effects of a gallium arsenide (GaAs) PP laser chip is proposed. This method establishes a three-dimensional model of the chip, including the carrier injection field, heat source density field, quantum well temperature field, thermally induced refractive index field, cavity surface absorption thermal field, and P-surface interface thermal resistance field. The P-surface projection region is divided into multiple thermal impedance coding units. Five amplification factors are calculated for each thermal impedance coding unit and multiplied together to obtain the thermal failure chain gain. The dominant amplification node is identified by the node contribution rate. Based on the thermal failure chain gain and the dominant amplification node, a coding vector is generated, consisting of the ohmic injection domain area, the insulating thermal conduction domain area, the equivalent cross-sectional area of ​​the thick metal thermal ridge, the equivalent length of the current-limiting trench, the local interface thermal resistance, and the segmented electrode number. Based on all coding vectors, the P-surface thermal impedance coding layout, P-type side epitaxial heat source migration parameters, cavity surface cold end chain breakage structure parameters, solder low-impedance alignment pattern, and segmented electrode connection diagram are generated.

[0021] The gallium arsenide (GaAs) PP laser chip is a p-plane power-type GaAs-based pumped laser chip. Its basic structure includes a GaAs substrate, an N-type AlGaAs confinement layer, a waveguide layer, an InGaAs / GaAs quantum well active layer, a p-type AlGaAs confinement layer, a p-type GaAs contact layer, a p-plane composite metal layer, an N-plane metal layer, a front cavity film layer, a rear cavity film layer, a p-plane solder interface, and a heat sink. The chip is mounted p-plane-down. The heat generated by the quantum well active layer is mainly dissipated through the p-type epitaxial layer, the p-type contact layer, the p-plane composite metal layer, the solder layer, and the heat sink. In this embodiment, the internal thermal effects of the chip are represented as a thermal failure chain from current injection to interface thermal resistance amplification. The p-plane is discretized into multiple thermal impedance encoding units, and local chain breakage design is performed on each unit.

[0022] First, a three-dimensional model of the chip is established. The origin of the coordinate system is the center of the P-plane composite metal layer, and the length direction of the resonant cavity is used as the coordinate axis. The axis is defined by the horizontal width direction of the light strip. The shaft, with its outer thickness direction as An axis is defined as any position within the chip. The input parameters are: target emission wavelength, target output power, target operating current, cavity length, emission stripe width, number of quantum well layers, quantum well location, N-type confinement layer thickness, waveguide layer thickness, P-type confinement layer thickness, P-type contact layer thickness, P-type side doping concentration, P-side metal material, end-face reflectivity, solder material, solder thickness, and heat sink material. The current density is obtained by applying the current continuity equation, heat conduction equation, optical mode solutions, and interface thermal resistance boundary conditions. Material conductivity Heat source density Temperature rise Thermally induced refractive index change Light field intensity Cavity surface photon flux Heat flux vector and local interface thermal resistance .

[0023] The P-plane projection region is divided into The thermal impedance encoding unit. Each thermal impedance encoding unit corresponds to a three-dimensional control region. The shape of the thermal impedance coding unit on the P-plane is determined by the minimum linewidth of the photolithography, the metal spacing, the minimum width of the thermal ridge, the current-limiting trench process capability, and the segmented electrode wiring rules. Each thermal impedance coding unit includes an ohmic injection domain, an insulating thermally conductive domain, a current-limiting trench domain, a thick metal thermal ridge domain, a solder anchoring domain, and a segmented electrode connection domain. The ohmic injection domain contacts the P-type GaAs contact layer, the insulating thermally conductive domain is located above the P-type contact layer and is composed of an AlN thin film or a SiN / AlN composite film, the current-limiting trench domain is etched into the upper part of the P-type contact layer or P-type limiting layer, the thick metal thermal ridge domain is located above the insulating thermally conductive domain and is connected to the P-plane composite metal layer, the solder anchoring domain corresponds to the low-impedance soldering area on the P-plane soldering interface, and the segmented electrode connection domain connects the unit to the first working electrode, the second working electrode, or the third working electrode.

[0024] Calculate the thermal failure chain gain for each thermal impedance encoding unit. The thermal failure chain gain of each thermal impedance coding unit is .in, This indicates the degree to which the injected current is amplified into a local heat source. This indicates the degree of amplification of the local heat source transfer to the quantum well. This indicates the amplification of the thermally induced refractive index shift caused by the temperature rise of the quantum well. This indicates the degree of amplification resulting from the thermally induced optical mode shift, leading to increased heat absorption at the cavity surface. This indicates the degree of amplification caused by localized thermal resistance when heat flows through the P-face interface. Each amplification factor is calculated using the following formula: The electrothermal conversion amplification factor, quantum well temperature rise amplification factor, thermally induced refractive index amplification factor, cavity surface heat absorption amplification factor, and interface thermal resistance amplification factor are determined according to the following formulas: ; ; ; ; ; in, For the active region of the quantum well, For the cavity surface thermal sensitive area, This is the P-side interface area. The temperature rise at position r when only the heat source of the b-th thermal impedance encoding unit is activated. The total thermal power of the b-th thermal impedance encoding unit. The thermally induced refractive index change caused by the temperature rise of the b-th thermal impedance encoding unit. The cavity surface absorption coefficient, Let be the cavity surface photon flux after the thermally induced optical mode shift caused by the b-th thermal impedance coding unit. The cavity surface reference photon flux. The heat flow vector generated for the b-th thermal impedance encoding unit and flowing towards the P-face interface region is... , , , and These are the normalized constants for current, thermal power, optical field, photon flux, and heat flux, respectively.

[0025] In this embodiment, , , , and Take the integral value of the normal working condition in the corresponding denominator. to This ensures that the numerical solution is stable and does not change the physical magnitude under normal operating conditions.

[0026] Identify the dominant amplification node. For the first... Each thermal impedance encoding unit calculates the contribution rate of five nodes according to the node contribution rate formula, and the node with the largest contribution rate is determined as the dominant amplification node. When the dominant amplification node is an electrothermal conversion node, the structural adjustment direction of this unit is to reduce the ohmic injection domain area and increase the equivalent length of the current-limiting trench; when the dominant amplification node is a quantum well temperature rise node, the structural adjustment direction of this unit is to increase the area of ​​the insulating thermally conductive domain and the equivalent cross-sectional area of ​​the thick metal thermal ridge, and coordinate with the migration of the P-type side epitaxial heat source; when the dominant amplification node is a thermally induced refractive index drift node, the structural adjustment direction of this unit is to change the lateral injection window and the distribution of the thick metal thermal ridge; when the dominant amplification node is a cavity surface heat absorption node, the structural adjustment direction of this unit is to set a cavity surface no-injection retreat zone, a band gap lifting low absorption zone, and a lateral thermal bridge; when the dominant amplification node is an interface thermal resistance node, the structural adjustment direction of this unit is to adjust the solder anchoring domain and the heat sink transition layer.

[0027] Generate a thermal impedance encoding vector. The encoding vector of each thermal impedance encoding unit is Among them, the area of ​​the Ohm injection domain. The area of ​​the insulating thermally conductive zone is determined according to the formula. The equivalent cross-sectional area of ​​the thermal ridge of thick metal is determined according to the area conservation formula. The gain function of the thermal failure chain is determined. This encoding process ensures that local cells with high thermal failure chain gain have a smaller ohmic injection area and a larger thermal extraction cross section, while local cells with low thermal failure chain gain have a larger ohmic injection area and undertake the main gain injection.

[0028] A P-side epitaxial heat source migration design was implemented. From the quantum well towards the P-plane, a low-absorption carrier buffer layer, a resistive thermal migration layer, a high-conductivity thermal release layer, and a P-type contact resistance modulation layer were sequentially arranged on the P-side epitaxial layer. The low-absorption carrier buffer layer, located close to the quantum well, employs a combination of low doping concentration and high bandgap to reduce free carrier absorption near the quantum well. The resistive thermal migration layer adjusts the P-side resistive thermal center through a nonlinear doping gradient. The high-conductivity thermal release layer, located close to the P-type contact layer, reduces the series resistance on the P-plane side. The P-type contact resistance modulation layer sets the local contact resistance based on the P-plane thermal impedance coding pattern. The P-side heat source center is... and satisfy .in, The boundary coordinates of the quantum well near the P-type side are: The coordinates of the boundary of the P-type contact layer near the P-face composite metal layer are given. Coordinates of the P-type epitaxial layer in the thickness direction Heat source density at that location, For safe separation distance.

[0029] A cold-end break-chain structure is generated on the cavity surface. The inner sides of the front and rear cavity surfaces are respectively equipped with a no-injection retreat band, a bandgap-lifted low-absorption band, a transverse thermal bridge, an end-face stress buffer film, and a P-side cold-end anchoring region. The ohmic injection domain is eliminated within the no-injection retreat band, retaining only the insulating thermally conductive domain and the thick metal thermal ridge extension. The bandgap-lifted low-absorption band is formed through quantum well hybridization or local component modulation. The transverse thermal bridge connects the insulating thermally conductive domain near the cavity surface with the thick metal thermal ridge on the P-side. The end-face stress buffer film adopts a multi-layer dielectric film thickness-graded structure. The P-side cold-end anchoring region is aligned with the low-impedance region of the solder. The normalized overlap coefficient of the cavity surface heat source, current injection, and optical field intensity is calculated. Calculate using the following formula: Overlap coefficient for: ; in, This is the normalized overlap coefficient among the cavity surface heat source, current injection, and optical field intensity. The density of the heat source absorbed by the cavity surface at position r. The heat source normalization constant; the parameters of the cold end chain break structure of the cavity surface satisfy... ,in This represents the upper limit of the overlap coefficient of the three fields of the cavity surface.

[0030] In one embodiment, the length of the non-injection relief band on the front cavity surface is 8 μm to 18 μm, and the length of the non-injection relief band on the rear cavity surface is 6 μm to 15 μm. The length of the non-injection relief band on the front cavity surface is greater than that on the rear cavity surface to match the heat load distribution corresponding to the higher output power of the front cavity surface.

[0031] Generate a low-impedance solder alignment pattern. The low-impedance solder alignment pattern includes a solder anchoring region, a low-impedance soldering region, a thermal expansion buffer region, and a heat sink transition layer pattern. According to the... Thermal failure chain weights of each thermal impedance encoding unit Thermal extraction capability Low impedance at the solder interface Calculate the interface alignment coefficient and make During manufacturing, the solder anchoring region corresponds to the position of the P-side high-heat extraction coding unit, the thermal expansion buffer region is set at the chip edge and stress-sensitive areas, and the heat sink transition layer is set between the solder layer and the high thermal conductivity heat dissipation layer. Through this alignment design, the main heat flow outlet inside the P-side corresponds to the low interface thermal resistance region of the solder layer.

[0032] A segmented electrode thermal fingerprint was established. The P-side segmented electrode connection diagram includes a first working electrode, a second working electrode, and a third working electrode. The connection of the first working electrode satisfies... The main gain injection region, the second working electrode connection satisfies The compensation injection region, the third working electrode connection satisfies Or a controlled injection region adjacent to the cavity surface thermistor. After chip packaging, low duty cycle test pulses are applied to the three working electrodes, and the voltage transient, wavelength transient, near-field center offset, and transient thermal resistance of the corresponding region of each electrode are collected, according to... Obtain the heat risk index, and then follow Calculate the current allocation value for each working electrode. This current allocation value is written into the chip module drive control parameters to ensure that the actual operating state of the chip is consistent with the thermal impedance coding design.

[0033] formula middle, Indicates the first Thermal failure chain gain of each thermal impedance encoding unit Indicates the thermal impedance encoding unit number. Indicates the first The electrothermal conversion amplification factor of each thermal impedance encoding unit Indicates the first The quantum well temperature rise amplification factor of each thermal impedance encoding unit Indicates the first Thermo-induced refractive index amplification factor of each thermal impedance encoding unit Indicates the first The cavity surface absorption thermal amplification factor of each thermal impedance encoding unit Indicates the first The interface thermal resistance amplification factor of each thermal impedance encoding unit.

[0034] formula middle, Indicates the first The encoding vector of each thermal impedance encoding unit, Indicates the first Area of ​​the ohmic injection domain of each thermal impedance encoding unit Indicates the first The thermally conductive area of ​​each thermal impedance encoding unit Indicates the first The equivalent cross-sectional area of ​​the thick metal thermal ridge of each thermal impedance encoding unit. Indicates the first Equivalent length of the current-limiting trench for each thermal impedance encoding unit Indicates the first The local interface thermal resistance corresponding to each thermal impedance encoding unit Indicates the first The segment electrode number to which each thermal impedance coding unit belongs.

[0035] formula middle, Indicates the first The three-dimensional control area corresponding to each thermal impedance encoding unit Indicates position Current density at that point Indicates the internal spatial location of the chip. Indicates position The electrical conductivity of the material, Represents a three-dimensional volume element. This represents the current normalization constant.

[0036] formula middle, Indicates the active region of the quantum well. Indicates that only the first one is activated. The thermal impedance encoding unit has a heat source location. Temperature rise at the location, Indicates the first Total thermal power of each thermal impedance encoding unit This represents the normalization constant for thermal power. This indicates the operation of finding the maximum value.

[0037] formula middle, Indicates the first The thermally induced refractive index change caused by the temperature rise of each thermal impedance encoding unit Indicates position The light field intensity at that location, Represents the normalization constant of the light field. This indicates the operation of taking the absolute value.

[0038] formula middle, Indicates the thermally sensitive area of ​​the cavity surface. Indicates position The absorption coefficient at the cavity surface, Indicates the first The cavity surface photon flux caused by the thermal impedance coding unit after thermally induced optical mode shift Represents the cavity surface reference photon flux. This represents the photon flux normalization constant.

[0039] formula middle, This indicates the P-side interface area. Indicates the first Each thermal impedance encoding unit generates a heat flow vector that flows to the P-face interface region. Indicates position Local interface thermal resistance at the location, This represents the heat flux normalization constant.

[0040] formula middle, Indicates the first In the thermal impedance encoding unit, the first The contribution rate of each amplification node Indicates the enlarged node number, This indicates the summation number of the magnified nodes. Indicates the first In the thermal impedance encoding unit, the first The magnification factor of each magnification node. Represents the translation constant of the nodal magnification factor. Represents the natural logarithm operation.

[0041] formula middle, This represents the total area of ​​a single thermal impedance coding unit. This indicates the lower limit of the area ratio of the Ohm injection domain. This indicates the upper limit of the area ratio of the Ohm injection domain. This represents the baseline value for the thermal failure chain gain.

[0042] formula middle, Indicates the first The thermally conductive area of ​​each thermal impedance encoding unit Indicates the first The area occupied by the current-limiting trench, dielectric isolation boundary, and process safety clearance within each thermal impedance coding unit.

[0043] formula middle, This represents the minimum equivalent cross-sectional area of ​​the thermal ridge of a thick metal. This represents the maximum equivalent cross-sectional area of ​​the thermal ridge of a thick metal.

[0044] formula middle, This indicates the position of the center of the P-type heat source in the thickness direction. This represents the boundary coordinates of the quantum well near the P-type side. This indicates the boundary coordinates of the P-type contact layer near the P-face composite metal layer. Represents the integral variable in the thickness direction. Represents the coordinates of the P-type epitaxial layer in the thickness direction. Heat source density at that location, Represents a micro-element in the thickness direction. This represents the safe separation distance between the center of the P-type heat source and the boundary of the quantum well.

[0045] formula middle, This represents the normalized overlap coefficient among the cavity surface heat source, current injection, and optical field intensity. Indicates position Density of heat source absorbed at the cavity surface This represents the normalization constant of the heat source. This represents the upper limit of the overlap coefficient of the three fields of the cavity surface.

[0046] formula middle, This represents the interface alignment factor between the P-side thermal impedance coding unit and the low-impedance region of the solder. Indicates the first Thermal failure chain weights of each thermal impedance encoding unit Indicates the first The thermal extraction capability of each thermal impedance encoding unit Indicates the first The low impedance level of the solder interface below each thermal impedance coding unit. This indicates the lower limit of the interface alignment coefficient.

[0047] formula middle, Indicates the first Thermal risk index of each working electrode Indicates the segmented electrode number, Indicates the test pulse of the first The voltage change of each working electrode This indicates the amount of change in the test pulse time. Indicates the first The change in center wavelength under the excitation of each working electrode Indicates the first The change in current at each working electrode Indicates the first The lateral offset of the near-field center after excitation of each working electrode. Indicates the first Transient thermal resistance of the region corresponding to each working electrode. , , and This represents the weighting coefficient of the thermal risk index.

[0048] formula middle, Indicates the first The working current is allocated to each working electrode. This indicates the total operating current of the chip. Indicates the first Thermal risk index of the area corresponding to each working electrode This indicates the number of the segmented electrode summation. Specific Implementation Example 2: This embodiment provides sample parameters for a 940nm gallium arsenide PP-pumped laser chip. The chip cavity length is 2.5mm, the emission stripe width is 120μm, the quantum well adopts an InGaAs / GaAs dual quantum well structure, the P-type confinement layer is made of AlGaAs material, and the chip is mounted using a P-side flip-chip. The side length of the P-side thermal impedance encoding unit is 8μm to 20μm; the ohmic injection domain area in the high thermal failure chain gain region accounts for 25% to 45% of the unit area, the insulating thermally conductive domain area accounts for 35% to 60% of the unit area, and the thickness of the thick metal thermal ridge is 3μm to 8μm; the ohmic injection domain area in the low thermal failure chain gain region accounts for 55% to 78% of the unit area, and this region connects to the first working electrode and serves as the main gain injection region. The depth of the current-limiting trench is controlled within the range from the P-type contact layer to the upper part of the P-type confinement layer, and a safe epitaxial thickness is maintained between the bottom of the trench and the quantum well active layer. The solder layer uses AuSn or sintered silver, and the heat sink uses a combination of CuW transition layer and high thermal conductivity heat dissipation layer. The low impedance area of ​​the solder is aligned with the P-side strong heat extraction coding unit.

[0050] The manufacturing process of this embodiment includes epitaxial design and growth, P-side thermal impedance coding pattern fabrication, current-limiting trench etching, dielectric film deposition, ohmic contact window opening, P-side composite metal deposition, thick metal hot ridge plating, substrate thinning, N-side metallization, chip cleaving, cavity cold end chain breakage structure fabrication, front and rear cavity film deposition, P-side flip-chip mounting, solder alignment inspection, segmented electrode thermal fingerprint testing, and operating current configuration. After epitaxial growth, layer thickness, emission wavelength, and doping level are confirmed by high-resolution X-ray diffraction, photoluminescence, and Hall effect testing. After P-side patterning is completed, linewidth, trench depth, and contact resistance are confirmed by profilometry, microscopic inspection, and electrical testing. After mounting, solder interface is confirmed by X-ray inspection, acoustic scanning, and shear strength testing. In the finished product testing stage, the consistency between the chip and the design model is confirmed by LIV curves, spectral temperature drift, near-field distribution, transient thermal resistance, and segmented electrode thermal fingerprint testing.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a reference structure" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0052] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for optimizing the thermal effect of a gallium arsenide (GaAs) PP laser chip, wherein the GaAs PP laser chip is a P-plane power-type GaAs-based pumped laser chip, comprising a GaAs substrate, an N-type confinement layer, a waveguide layer, a quantum well active layer, a P-type confinement layer, a P-type contact layer, a P-plane composite metal layer, an N-plane metal layer, a front cavity film layer, a rear cavity film layer, a P-plane welding interface, and a heat sink, characterized in that, The method includes: establishing a three-dimensional chip model comprising a carrier injection field, a heat source density field, a quantum well temperature field, a thermally induced refractive index field, a cavity surface absorption thermal field, and a P-plane interface thermal resistance field; and dividing the P-plane projection region into... The thermal impedance encoding unit, and for the first thermal impedance encoding unit, Each thermal impedance encoding unit establishes a three-dimensional control region. ,in ; calculate the first one respectively Electrothermal conversion amplification factor of each thermal impedance encoding unit Quantum well temperature rise amplification factor Thermally induced refractive index magnification factor Cavity surface heat absorption amplification factor and interface thermal resistance amplification factor And obtain the first according to the following formula Thermal failure chain gain of each thermal impedance encoding unit According to the thermal failure chain gain And the dominant amplification node among the five amplification factors, generating the first The encoding vector of each thermal impedance encoding unit Based on the encoding vectors of all thermal impedance encoding units, the P-side thermal impedance encoding layout, P-type side epitaxial heat source migration parameters, cavity cold end chain breakage structure parameters, solder low impedance alignment pattern, and segmented electrode connection diagram are generated. in, Inject the area of ​​the ohmic domain. For the area of ​​the insulating and thermally conductive zone, The equivalent cross-sectional area of ​​the thermal ridge of the thick metal. The equivalent length of the flow-limiting trench. For local interface thermal resistance, Number the segmented electrodes; The chip's three-dimensional model uses the center of the P-plane composite metal layer as the origin and the length direction of the resonant cavity as the coordinate axis. The axis is defined by the horizontal width direction of the light strip. The axis is the thickness direction of the epitaxial layer. The input data includes the target emission wavelength, cavity length, emission stripe width, number of quantum well layers, quantum well location, N-type confinement layer thickness, waveguide layer thickness, P-type confinement layer thickness, P-type contact layer thickness, P-type side doping concentration distribution, P-plane composite metal layer material and thickness, front cavity surface reflectivity, rear cavity surface reflectivity, solder material, solder thickness, heat sink material, target operating current, and target output power; the data output by the chip 3D model includes location. Current density at Material conductivity Heat source density Temperature rise Thermally induced refractive index change Light field intensity Cavity surface photon flux Heat flux vector and local interface thermal resistance ,in Indicates the internal spatial location of the chip; The electrothermal conversion amplification factor, quantum well temperature rise amplification factor, thermally induced refractive index amplification factor, cavity surface heat absorption amplification factor, and interface thermal resistance amplification factor are determined according to the following formulas: in, For the active region of the quantum well, For the cavity surface thermal sensitive area, This is the P-side interface area. To activate only the first The thermal impedance encoding unit has a heat source location. Temperature rise at the location, For the first Total thermal power of each thermal impedance encoding unit For the first The thermally induced refractive index change caused by the temperature rise of each thermal impedance encoding unit The cavity surface absorption coefficient, For the first The cavity surface photon flux caused by the thermal impedance coding unit after thermally induced optical mode shift The cavity surface reference photon flux. For the first Each thermal impedance encoding unit generates a heat flow vector that flows to the P-face interface region. , , , and These are the normalized constants for current, thermal power, optical field, photon flux, and heat flux, respectively.

2. The method for optimizing the thermal effect of gallium arsenide PP laser chips according to claim 1, characterized in that, The dominant amplification node is determined according to its node contribution rate, which is: in, For the first In the thermal impedance encoding unit, the first The contribution rate of each amplification node Indicates the electrothermal conversion node. Indicates the quantum well temperature rise node. Indicates the thermally induced refractive index drift node. Indicates the heat absorption node on the cavity surface. Indicates the interface thermal resistance node. For the first In the thermal impedance encoding unit, the first The magnification factor of each magnification node. The translation constant is the nodal magnification factor. Number the nodes to be summed; assign the first node to the summation node. In each thermal impedance encoding unit The node with the maximum value is determined as the dominant amplification node, and the encoding vector is adjusted according to the dominant amplification node. The corresponding structural parameters in the code.

3. The method for optimizing the thermal effect of gallium arsenide PP laser chips according to claim 2, characterized in that, When the dominant amplification node is an electrothermal conversion node, the area of ​​the ohmic injection domain is reduced. And increase the equivalent length of the flow-limiting trench. ; When the dominant amplification node is the quantum well temperature rise node, the area of ​​the insulating thermally conductive domain is increased. and the equivalent cross-sectional area of ​​the thick metal thermal ridge When the dominant amplification node is a thermally induced refractive index drift node, adjust the distribution of the ohmic injection domain in the lateral width direction and adjust the distribution density of the thick metal thermal ridge in the edge region of the light-emitting strip; when the dominant amplification node is a cavity surface absorption heat node, set a cavity surface no-injection retreat band, a band gap lifting low absorption band, and a lateral thermal bridge; when the dominant amplification node is an interface thermal resistance node, adjust the solder low impedance alignment pattern in relation to the first... The relative solder anchoring location and heat sink transition layer thickness of each thermal impedance coding unit.

4. The method for optimizing the thermal effect of a gallium arsenide PP laser chip according to claim 3, characterized in that, The area of ​​the ohmic injection domain, the area of ​​the insulating thermally conductive domain, and the equivalent cross-sectional area of ​​the thick metal thermal ridge are determined according to the following formulas: in, The total area of ​​a single thermal impedance coding unit. The lower limit of the area ratio of the Ohm injection domain. The upper limit of the area ratio of the Ohm injection domain. This is the baseline value for the gain in the thermal failure chain. For the first The area occupied by the current-limiting trenches, dielectric isolation boundaries, and process safety clearances within each thermal impedance coding unit. The minimum equivalent cross-sectional area of ​​the thermal ridge of thick metal. It represents the maximum equivalent cross-sectional area of ​​the thermal ridge of thick metal.

5. The method for optimizing the thermal effect of a gallium arsenide PP laser chip according to claim 1, characterized in that, The migration parameters of the P-type side epitaxial heat source include the thickness of the low-absorption carrier buffer layer, the doping gradient of the resistive heat migration layer, the thickness of the high-conductivity heat release layer, the thickness of the P-type contact layer, and the contact resistance modulation distribution. The center of the P-type side heat source is determined according to the following formula: in, This refers to the location of the center of the P-type heat source in the thickness direction. The boundary coordinates of the quantum well near the P-type side are: The boundary coordinates of the P-type contact layer near the P-face composite metal layer are given. Coordinates of the P-type epitaxial layer in the thickness direction Heat source density at that location, The thickness direction is a micro-element; the migration parameters of the P-type side epitaxial heat source satisfy... ,in This is the safe separation distance between the center of the P-type heat source and the boundary of the quantum well.

6. The method for optimizing the thermal effect of a gallium arsenide PP laser chip according to claim 1, characterized in that, The structural parameters of the cold-end break-chain structure of the cavity surface include the length of the non-injection retreat band on the front cavity surface, the length of the non-injection retreat band on the rear cavity surface, the length of the bandgap lift low absorption band, the width of the transverse thermal bridge, the thickness of the end-face stress buffer film, and the position of the cold-end anchoring region on the P-face. The normalized overlap coefficient of the cavity surface heat source, current injection, and optical field intensity is: in, This is the normalized overlap coefficient among the cavity surface heat source, current injection, and optical field intensity. For position Density of heat source absorbed at the cavity surface The heat source normalization constant; the parameters of the cold end chain break structure of the cavity surface satisfy... ,in This represents the upper limit of the overlap coefficient of the three fields of the cavity surface.

7. The method for optimizing the thermal effect of a gallium arsenide PP laser chip according to claim 1, characterized in that, The low-impedance alignment pattern of the solder is determined according to the interface alignment coefficient, which is: in, This is the interface alignment factor between the P-side thermal impedance coding unit and the low-impedance region of the solder. For the first Thermal failure chain weights of each thermal impedance encoding unit For the first The thermal extraction capability of each thermal impedance encoding unit For the first The low impedance level of the solder interface below each thermal impedance coding unit; the solder low impedance alignment pattern satisfies ,in The lower limit of the interface alignment coefficient is set, and a solder anchoring domain and a heat sink transition layer are set below the thermal impedance encoding unit with high thermal failure chain weight.

8. The method for optimizing the thermal effect of a gallium arsenide PP laser chip according to claim 1, characterized in that, The segmented electrode connection diagram includes a first working electrode, a second working electrode, and a third working electrode. The connection of the first working electrode satisfies... The main gain injection region, the second working electrode connection satisfies The compensation injection region, the third working electrode connection satisfies Or a controlled injection region adjacent to the thermally sensitive area of ​​the cavity surface, wherein The gain threshold of the first thermal failure chain. The gain threshold for the second thermal failure chain is determined by the following formula: After packaging, low duty cycle test pulses are applied to the first, second, and third working electrodes respectively, and the result is obtained according to the formula below. Thermal risk index of each working electrode And determine the first Operating current of each working electrode : in, This represents the rate of change of voltage over time. The rate of change of wavelength with current. This represents the lateral offset of the near-field center. For transient thermal resistance, , , and These are the weighting coefficients. This represents the total operating current of the chip. Number the segments of the electrode summation.

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