Improved routing method and chip design system

Abstract

This invention discloses an improved pathfinding method and chip design system, comprising the following steps: generating multiple routing rule matrices with the same grid size; adding various routing constraints to the corresponding routing rule matrices; obtaining a total routing rule matrix; forming an outer polygon P1; calculating the movement cost of all possible moving positions within the outer polygon P1; generating corresponding mask matrices and transition matrices according to the constraint type; starting pathfinding from the starting point, and extracting a submatrix centered at the new position and with the same size as the mask matrix from the total routing rule matrix at each new position; obtaining the constraint cost; selecting the adjacent position with the lowest constraint cost as the next moving point, and repeating the above steps until the destination is reached. The pathfinding speed of this invention is 45.4% faster than traditional algorithms, and when the number of lines increases from 1 to 5, the pathfinding speed is 75.6% faster than traditional algorithms, making it particularly suitable for high-density, multi-constraint chip routing environments.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit layout design technology, specifically relating to an improved pathfinding method and chip design system. Background Technology

[0002] In the field of chip layout design, as chip size increases, design rules and circuit constraints become more complex, and manual routing can no longer meet design requirements. Automatic routing, as an effective means to deal with large-scale and complex constraints, can effectively avoid design problems caused by human error.

[0003] As the core of the automatic routing engine, the pathfinding algorithm's performance directly determines the success, quality, and runtime of the routing results. With the continuous evolution of process nodes, design rules become increasingly complex, and the number of routing layers increases. Within the chip, there are a large number of fixed obstacles such as macro modules, IP cores, power networks, clock trees, and existing interconnects, forming a pathfinding space with massive meshes and high-density constraints.

[0004] Current mainstream routers generally employ mesh-based pathfinding algorithms such as A*, BFS, and JPS. During pathfinding, the movement cost of each mesh point to be expanded needs to be evaluated in real time. This cost typically includes the actual cost from the starting point to the point (G value) and the estimated cost to the destination (H value). However, when dealing with ultra-large-scale meshes within complex chips, traditional G value calculations (such as Manhattan distance) are overly simplified and fail to accurately reflect complex design constraints (such as different line widths, line spacing, and distances from obstacles / vias / pads). This leads to the algorithm needing to perform a large number of repetitive rule checks and collision detection calculations, especially in high-density routing areas, resulting in huge computational overhead, a sharp drop in pathfinding speed, and even failure to complete routing due to exhaustion of computational resources. Furthermore, the algorithm is prone to getting trapped in local optima and struggles to find feasible paths in globally congested environments.

[0005] Therefore, there is an urgent need for a pathfinding algorithm that can pre-digest complex design rules, reduce real-time computation during pathfinding, and possess efficient local obstacle avoidance capabilities, in order to meet the challenges of chip wiring under advanced processes. Summary of the Invention

[0006] To address the shortcomings of existing technologies in complex chip wiring scenarios, such as slow pathfinding speed and low efficiency due to the large amount of computation required for real-time rule checking, the present invention aims to provide an improved pathfinding method and chip design system.

[0007] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows: An improved pathfinding method includes the following steps: Step 1: Divide the entire chip wiring area into uniform grids according to the set grid size, and generate multiple wiring rule matrices with the same grid size. The number of matrices is the same as the number of wiring constraint types. Step 2: Add each type of routing constraint to the corresponding routing rule matrix; Step 3: Multiply each routing rule matrix by its corresponding constraint weight and then sum them to obtain the overall routing rule matrix; Step 4: Connect the starting point and the ending point of the wiring to form line segment L1. Obtain the range that intersects with L1 or is less than the threshold S1 in the overall wiring rule matrix. Combine the starting point and the ending point to form the outer polygon P1. Step 5: Calculate the movement cost of all possible positions within the bounding polygon P1 and store it in the movement cost matrix; Step 6: Generate the corresponding mask matrix and transition matrix according to the constraint type; Step 7: Start the pathfinding from the starting point. Each time you move to a new position, extract a submatrix from the overall wiring rule matrix that is centered at the new position and has the same size as the mask matrix. Step 8: Calculate the constraint cost by combining the submatrix with the mask matrix and transition matrix of the same size; Step 9: Select the adjacent position with the lowest constraint cost as the next moving point, and repeat steps 7 to 9 until the destination is reached.

[0008] Furthermore, in step 1, the mesh size is 0.1μm, 1μm, 5μm, 10μm or 20μm.

[0009] Furthermore, in step 2, the methods of adding include: For the distance constraint between the line and the obstacle, within the influence range of the obstacle, the matrix value is set to the first preset value, which is 2 or other values, and the rest are 0; For the spacing constraint between the line and other lines, within the influence range of the line, the matrix value is set to the second preset value, which takes the value of 1 or other values, and 0 for the rest; For the line-via spacing constraint, set the matrix value at the center point of the via to the third preset value, which can be 1 or other values, and 0 for the rest; For the line-pad spacing constraint, set the matrix value at the center point of the pad to the fourth preset value, which is 0.5 or other values, and 0 for the rest.

[0010] Furthermore, in step 3, the weight value ranges from 0 to 1, and the more important the constraint, the higher the weight value.

[0011] Furthermore, in step 4, the formula for calculating the threshold S1 is: ; Where D1 is the distance from the start point to the end point, DX and DY are the length and width of the chip, respectively, and K1 is the grid size.

[0012] Furthermore, in step 5, the formula for calculating the movement cost (Cost) is as follows: Cost = G + T + S; ; ; ; Wherein, the current starting point coordinates are (x1, y1); the target moving position coordinates are (x2, y2); the ending position coordinates are (xF, yF); G is the grid distance cost; T is the turning cost; S is the ending distance cost; and O1 is the turning angle to the target position.

[0013] Furthermore, in step 6, the mask matrix and the transition matrix have the same size; The method of dimension calculation is related to the type of constraint: For the constraint on the distance between the line and the obstacle, the dimension is (line width / 2 + maximum line spacing) × 2 + 1; For the spacing constraint between the line and other lines, the dimension is (line width + maximum line spacing) × 2 + 1; For the constraint on the spacing between lines and vias, the dimension is (line width / 2 + via diameter / 2) × 2 + 1; For the line-pad spacing constraint, the dimension is (line width / 2 + pad diameter / 2)×2+1.

[0014] Furthermore, the constraint types also include at least one of the following: spacing between lines and other layers, spacing between lines and special areas, spacing between vias and obstacles, spacing between vias and other lines, spacing between vias, and spacing between vias and pads. The special area refers to a rectangular, circular, or polygonal area of ​​any size specified in the chip wiring area according to actual design needs, and within it, different constraints are used compared to other locations.

[0015] Furthermore, in step 6, the transition matrix is ​​a matrix with a center value of 1 that gradually decreases outward according to a binary normal distribution.

[0016] The present invention also discloses a chip design system, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement an improved pathfinding method as described above.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) The pre-calculated wiring range can cover most of the line locations, and the results can be directly used during routing, which greatly speeds up the routing process; 2) For sections repeatedly traversed by multiple routes, it can avoid redundant calculations during the route finding process; 3) During the pathfinding process, only the intervals (submatrices) near the current path are processed, and obstacles far away from the current path are not involved to avoid invalid calculations; 4) Implement constraint priority management through weight settings to improve cabling quality; 5) The pathfinding speed of this invention is 45.4% faster than the traditional A* algorithm. When the number of paths increases from 1 to 5, the pathfinding speed is 75.6% faster than the traditional A* algorithm. 6) By pre-generating the routing rule matrix, calculating local cost, and performing dynamic submatrix operations, efficient obstacle avoidance and path planning are achieved, making it particularly suitable for high-density, multi-constraint chip routing environments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating the generation of the outer polygon P1 according to the present invention; Figure 2 This is a schematic diagram illustrating the extraction of sub-matrices during the pathfinding process of this invention; Figure 3 This is a flowchart illustrating the calculation process of the submatrix, mask matrix, and transition matrix of this invention. Figure 4 This is a schematic diagram showing the different determination interval shapes of the mask matrix of the present invention; Figure 5 This is a schematic diagram of the pathfinding results in Embodiment 1 of the present invention. Detailed Implementation

[0019] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0020] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0021] like Figures 1-5 As shown, this invention discloses an improved pathfinding method, comprising the following steps: Step 1: Divide the entire chip wiring area into uniform grids with equal spacing according to the set grid size, and generate multiple wiring rule matrices with the same grid size. The number of matrices is the same as the number of wiring constraint types. Step 2: Add each type of routing constraint to the corresponding routing rule matrix; Step 3: Multiply each routing rule matrix by its corresponding constraint weight and then sum them to obtain the overall routing rule matrix; Step 4: Connect the starting point and ending point of the wiring to form line segment L1. Obtain the range that intersects with L1 or is less than the threshold S1 in the overall wiring rule matrix. Combine the starting point and ending point to form the outer polygon P1. The larger the value of the threshold S1, the larger the area of ​​P1 and the greater the amount of wiring calculation. Step 5: Calculate the movement cost of all possible positions within the bounding polygon P1, and store it in the movement cost matrix for later use in pathfinding. Step 6: Generate all possible mask matrices and transition matrices based on the different constraints; Step 7: Start the pathfinding from the starting point. Each time you move to a new position, extract a submatrix from the overall wiring rule matrix that is centered at the new position and has the same size as the mask matrix. Step 8: Calculate the constraint cost by combining the submatrix with the mask matrix and transition matrix of the same size; Step 9: Select the adjacent position with the lowest constraint cost as the next moving point, and repeat steps 7 to 9 until the destination is reached.

[0022] In some implementations, in step 1, the mesh size is 0.1 μm, 1 μm, 5 μm, 10 μm, or 20 μm, etc.

[0023] In some implementations, the size of the matrix is ​​equal to the chip size divided by the grid size.

[0024] In some implementations, step 2 includes the following methods of addition: For the distance constraint between the line and the obstacle, within the influence range of the obstacle, the matrix value is set to the first preset value, which is 2 or other values, and the rest are 0; For the spacing constraint between the line and other lines, within the influence range of the line, the matrix value is set to the second preset value, which takes the value of 1 or other values, and 0 for the rest; For the line-via spacing constraint, set the matrix value at the center point of the via to the third preset value, which can be 1 or other values, and 0 for the rest; For the line-pad spacing constraint, set the matrix value at the center point of the pad to the fourth preset value, which is 0.5 or other values, and 0 for the rest.

[0025] In some implementations, in step 3, the weight value ranges from 0 to 1, and the more important the constraint, the higher the weight value.

[0026] In some implementations, the formula for calculating the threshold S1 in step 4 is: ; Where D1 is the distance from the start point to the end point, DX and DY are the length and width of the chip, respectively, and K1 is the grid size.

[0027] In some implementations, the formula for calculating the movement cost (Cost) in step 5 is: Cost = G + T + S; ; ; ; Wherein, the current starting point coordinates are (x1, y1); the target moving position coordinates are (x2, y2); the ending position coordinates are (xF, yF); G is the grid distance cost; T is the turning cost; S is the ending distance cost; and O1 is the turning angle to the target position.

[0028] In some implementations, in step 6, the mask matrix and the transition matrix have the same size; The method of dimension calculation is related to the type of constraint: For the constraint on the distance between the line and the obstacle, the dimension is (line width / 2 + maximum line spacing) × 2 + 1; For the spacing constraint between the line and other lines, the dimension is (line width + maximum line spacing) × 2 + 1; For the constraint on the spacing between lines and vias, the dimension is (line width / 2 + via diameter / 2) × 2 + 1; For the line-pad spacing constraint, the dimension is (line width / 2 + pad diameter / 2)×2+1.

[0029] In some implementations, the mask matrix uses different shaped decision intervals depending on the constraints; within the decision interval, the matrix value is 1, and outside the decision interval, the matrix value is 0; the shape of the decision interval includes, but is not limited to, octagon, circle, and rectangle.

[0030] In some implementations, the constraint types in steps 2 and 6 further include at least one of the following: spacing between lines and other layers, spacing between lines and special areas, spacing between vias and obstacles, spacing between vias and other lines, spacing between vias, and spacing between vias and pads. A special area refers to a rectangular, circular, or polygonal region of any size specified according to actual design needs within the chip wiring area, and within which constraints different from those in other locations are applied.

[0031] In some implementations, in step 6, the transition matrix is ​​a matrix with a center value of 1 that gradually decreases outward according to a binary normal distribution.

[0032] The present invention also discloses a chip design system, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement an improved pathfinding method as described above.

[0033] Example 1

[0034] like Figures 1-5 As shown, an improved pathfinding method includes the following steps: Step 1: Divide the entire chip wiring area into uniform grids with equal spacing according to the set grid size, and generate multiple wiring rule matrices with the same grid size. The number of matrices is the same as the number of wiring constraint types. Step 2: Add each type of routing constraint to the corresponding routing rule matrix; Step 3: Multiply each routing rule matrix by its corresponding constraint weight and then sum them to obtain the overall routing rule matrix; Step 4: As Figure 1 As shown, the starting point and ending point of the wiring are connected to form a line segment L1. The range that intersects with L1 or is less than the threshold S1 is obtained in the overall wiring rule matrix. Combined with the starting point and ending point, an outer polygon P1 is formed. The larger the value of the threshold S1, the larger the area of ​​P1 and the greater the amount of wiring calculation. Step 5: Calculate the movement cost of all possible positions within the bounding polygon P1, and store it in the movement cost matrix for later use in pathfinding. Step 6: Generate all possible mask matrices and transition matrices based on the different constraints; Step 7: As Figure 2 As shown, the pathfinding starts from the starting point. Each time a new position is reached, a submatrix with the same size as the mask matrix and centered at the new position is extracted from the overall wiring rule matrix. Step 8: As Figure 3 As shown, the constraint cost is obtained by calculating the submatrix with a mask matrix and a transition matrix of the same size; Step 9: Select the adjacent position with the lowest constraint cost as the next moving point, and repeat steps 7 to 9 until the destination is reached.

[0035] In step 2, the methods for adding include: For the distance constraint between the line and the obstacle, the matrix value is set to the first preset value of 2 within the influence range of the obstacle, and 0 for the rest; For the spacing constraint between the line and other lines, within the influence range of the line, the matrix value is set to the second preset value, which is 1, and 0 for the rest; For the line-via spacing constraint, the matrix value at the center point of the via is set to the third preset value, which is 1, and the rest are 0; For the line-pad spacing constraint, the matrix value at the center point of the pad is set to the fourth preset value, which is 0.5, and the rest are 0.

[0036] In step 3, the weight values ​​range from 0 to 1. The more important the constraint, the higher the weight value.

[0037] In step 4, the formula for calculating the threshold S1 is: ; Where D1 is the distance from the start point to the end point, DX and DY are the length and width of the chip, respectively, and K1 is the grid size.

[0038] In step 5, the formula for calculating the movement cost (Cost) is as follows: Cost = G + T + S; ; ; ; Wherein, the current starting point coordinates are (x1, y1); the target moving position coordinates are (x2, y2); the ending position coordinates are (xF, yF); G is the grid distance cost; T is the turning cost; S is the ending distance cost; and O1 is the turning angle to the target position.

[0039] In step 6, the mask matrix and the transition matrix have the same size; The method of dimension calculation is related to the type of constraint: For the constraint on the distance between the line and the obstacle, the dimension is (line width / 2 + maximum line spacing) × 2 + 1; For the spacing constraint between the line and other lines, the dimension is (line width + maximum line spacing) × 2 + 1; For the constraint on the spacing between lines and vias, the dimension is (line width / 2 + via diameter / 2) × 2 + 1; For the line-pad spacing constraint, the dimension is (line width / 2 + pad diameter / 2)×2+1.

[0040] like Figure 4 As shown, the mask matrix uses different shaped decision intervals depending on the constraints.

[0041] In step 6, the transition matrix is ​​a matrix with a central value of 1 that gradually decreases outward according to a bivariate normal distribution. The bivariate normal distribution is a commonly used method in mathematics, and its formula is as follows: ; Where µx and µy are the average values ​​of variables X and Y, respectively. These are the correlation coefficients for variables X and Y, respectively. By inputting coordinates X and Y, the value at each position in the transition matrix can be calculated using the formula above.

[0042] In this embodiment, the mesh size is 10μm, the wiring area is a square with a side length of 200μm, and the number of meshes is 20×20=400. The starting mesh coordinates are (2,2), the ending mesh coordinates are (19,19), and the threshold S1 is 5 mesh sizes. The area contains five obstacles (gray), three pads (orange), and three vias (blue). The pathfinding result is as follows. Figure 5 As shown by the purple line.

[0043] The constraint items and weights, the selection of submatrices, mask matrices, transition matrices and mask matrix types are shown in Table 1.

[0044] Table 1 Through the above pathfinding steps, the pathfinding speed of this embodiment is 45.4% faster than the traditional A* algorithm. When the number of routes increases from 1 to 5, the pathfinding speed is 75.6% faster than the traditional A* algorithm because redundant calculations are avoided.

[0045] This invention achieves efficient obstacle avoidance and path planning by pre-generating a wiring rule matrix, calculating local area costs, and performing dynamic submatrix operations. It is particularly suitable for high-density, multi-constraint chip wiring environments.

[0046] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0047] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. An improved pathfinding method for chip wiring, characterized in that, Includes the following steps: Step 1: Divide the entire chip wiring area into uniform grids according to the set grid size, and generate multiple wiring rule matrices with the same grid size. The number of matrices is the same as the number of wiring constraint types. Step 2: Add each type of routing constraint to the corresponding routing rule matrix; Step 3: Multiply each routing rule matrix by its corresponding constraint weight and then sum them to obtain the overall routing rule matrix; Step 4: Connect the starting point and the ending point of the wiring to form line segment L1. Obtain the range that intersects with L1 or is less than the threshold S1 in the overall wiring rule matrix. Combine the starting point and the ending point to form the outer polygon P1. Step 5: Calculate the movement cost of all possible positions within the bounding polygon P1 and store it in the movement cost matrix; Step 6: Generate the corresponding mask matrix and transition matrix according to the constraint type; Step 7: Start the pathfinding from the starting point. Each time you move to a new position, extract a submatrix from the overall wiring rule matrix that is centered at the new position and has the same size as the mask matrix. Step 8: Calculate the constraint cost by combining the submatrix with the mask matrix and transition matrix of the same size; Step 9: Select the adjacent position with the lowest constraint cost as the next moving point, and repeat steps 7 to 9 until the destination is reached; In step 2, the methods for adding include: For the distance constraint between the line and the obstacle, the matrix value is set to the first preset value within the influence range of the obstacle, and 0 for the rest; For the spacing constraint between the line and other lines, the matrix value is set to the second preset value within the influence range of the line, and 0 for the rest; For the line-via spacing constraint, set the matrix value to the third preset value at the center point of the via, and 0 for the rest; For line-pad spacing constraints, set the matrix value at the center point of the pad to the fourth preset value, and set the rest to 0; In step 4, the formula for calculating the threshold S1 is: ； Where D1 is the distance from the start point to the end point, DX and DY are the length and width of the chip, respectively, and K1 is the grid size; In step 6, the mask matrix and the transition matrix have the same size; the size calculation method depends on the constraint type. In step 6, the transition matrix is ​​a matrix with a center value of 1 that gradually decreases outward according to a binary normal distribution.

2. The improved pathfinding method for chip wiring according to claim 1, characterized in that, In step 1, the mesh size is 0.1μm, 1μm, 5μm, 10μm or 20μm.

3. The improved pathfinding method for chip wiring according to claim 1, characterized in that, In step 2, the first preset value is 2, the second preset value is 1, the third preset value is 1, and the fourth preset value is 0.

5.

4. The improved pathfinding method for chip wiring according to claim 1, characterized in that, In step 3, the weight values ​​range from 0 to 1. The more important the constraint, the higher the weight value.

5. An improved pathfinding method for chip wiring according to claim 1, characterized in that, In step 5, the formula for calculating the movement cost (Cost) is as follows: Cost = G + T + S; ； ； ； Wherein, the current starting point coordinates are (x1, y1); the target moving position coordinates are (x2, y2); the ending position coordinates are (xF, yF); G is the grid distance cost; T is the turning cost; S is the ending distance cost; and O1 is the turning angle to the target position.

6. An improved pathfinding method for chip wiring according to claim 1, characterized in that, In step 6, the method of dimension calculation is related to the constraint type: For the constraint on the distance between the line and the obstacle, the dimension is (line width / 2 + maximum line spacing) × 2 + 1; For the spacing constraint between the line and other lines, the dimension is (line width + maximum line spacing) × 2 + 1; For the constraint on the spacing between lines and vias, the dimension is (line width / 2 + via diameter / 2) × 2 + 1; For the line-pad spacing constraint, the dimension is (line width / 2 + pad diameter / 2)×2+1.

7. An improved pathfinding method for chip wiring according to claim 6, characterized in that, The constraint types also include at least one of the following: spacing between lines and other layers, spacing between lines and special areas, spacing between vias and obstacles, spacing between vias and other lines, spacing between vias, and spacing between vias and pads; The special area refers to a rectangular, circular, or polygonal area of ​​any size specified in the chip wiring area according to actual design needs, and within it, different constraints are used compared to other locations.

8. A chip design system, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement an improved routing method for chip wiring as described in any one of claims 1-7.

Images