Polar coordinate amplifier with dynamic cascode biasing

Abstract

This disclosure provides a polar coordinate amplifier with dynamic cascode bias. An electronic device may include a wireless circuit of a polar coordinate amplifier having an output radio frequency signal. The amplifier may include a first cascode stage and a second cascode stage coupled between a supply voltage and a reference voltage, as well as a first cascode stage and a second cascode stage. The supply voltage may carry amplitude modulation for the radio frequency signal. The gate terminal of the cascode stage may receive a local oscillator signal carrying phase modulation for the radio frequency signal. A dynamic charge pump may be coupled between the supply input and the gate terminal of the first cascode stage. A dynamic level shifter may be coupled to the charge pump. The level shifter and the charge pump may generate a voltage at the gate terminal of the first cascode stage that tracks the supply voltage without clipping, even when the supply voltage drops to near zero amplitude.

Description

[0001] This application claims priority to U.S. Patent Application No. 19 / 016,634, filed January 10, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates in general to electronic devices, including electronic devices having wireless circuitry. Background Technology

[0003] Electronic devices may possess wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless circuitry, which includes one or more antennas. The wireless transceiver circuitry within the wireless circuitry uses the antennas to transmit and receive radio frequency signals.

[0004] The radio frequency (RF) signal transmitted by the antenna can be fed through one or more power amplifiers configured to amplify the low-power analog signal into a higher-power signal more suitable for long-distance transmission over the air. Providing a power amplifier with sufficient performance levels can be challenging. For example, if not carefully managed, the power amplifier may exhibit insufficient dynamic range and linearity, which could limit the RF performance of the wireless circuitry. Summary of the Invention

[0005] Electronic devices may include wireless circuitry. This wireless circuitry may include a transmission path. The transmission path may include a polar-coordinate power amplifier that outputs a radio frequency (RF) signal. The amplifier may include a first common-source stage, a first common-source cascode stage, a second common-source cascode stage, and a second common-source stage, all series-coupled between a power supply input and a reference voltage. The power supply input may receive a power supply voltage carrying amplitude modulation for the RF signal. The gate terminals of the transistors in the first and second common-source stages may receive a local oscillator signal carrying phase modulation for the RF signal. The gate terminal of the first common-source cascode stage (e.g., a PMOS common-source cascode stage) may be coupled to a common-source cascode node.

[0006] A dynamic charge pump can be coupled between the power supply input and the cascode node. The dynamic charge pump may include a capacitor coupled between the power supply input and the cascode node. The dynamic charge pump may also include a cross-coupled inverter having a power supply terminal coupled between the power supply input and the cascode node. A first dynamic level shifter and a second dynamic level shifter can be coupled to the dynamic charge pump. Each dynamic level shifter may include an inverter powered by a bias voltage and receiving a local oscillator signal. The dynamic level shifters and the dynamic charge pump can generate a voltage at the cascode node that tracks the power supply voltage without clipping, even when the power supply voltage drops to near zero.

[0007] One aspect of this disclosure provides an amplifier circuit configured to output a radio frequency (RF) signal. The amplifier circuit may include a first common-source stage configured to receive a supply voltage for amplitude modulation of the RF signal. The amplifier circuit may include a first common-source cascode stage including a first transistor and a second transistor having gate terminals coupled to a common-source cascode node. The amplifier circuit may include a second common-source cascode stage, wherein the first common-source cascode stage is coupled between the second common-source cascode stage and the first common-source stage. The amplifier circuit may include a second common-source stage coupled to a reference voltage, wherein the second common-source cascode stage is coupled between the second common-source stage and the first common-source cascode stage. The amplifier circuit may include a cross-coupled inverter having a power input coupled between the supply voltage and the common-source cascode node.

[0008] One aspect of this disclosure provides an amplifier circuit configured to output a radio frequency signal. The amplifier circuit may include a first common-source stage comprising a first transistor and a second transistor, wherein the gate terminal of the first transistor receives a positive local oscillator signal, and the gate terminal of the second transistor receives a negative local oscillator signal. The amplifier circuit may include a common-source cascode stage comprising a third transistor and a fourth transistor, wherein the first transistor is series-coupled between the third transistor and a power supply input of the amplifier circuit, the second transistor is series-coupled between the fourth transistor and the power supply input, and the gate terminals of the third and fourth transistors are coupled to a common-source cascode node. The amplifier circuit may include a first circuit configured to generate at least a portion of the voltage at the common-source cascode node based on a positive local oscillator signal. The amplifier circuit may include a second circuit configured to generate at least a portion of the voltage at the common-source cascode node based on a negative local oscillator signal.

[0009] One aspect of this disclosure provides a polar coordinate power amplifier. The polar coordinate power amplifier may include a first transistor having a gate terminal for receiving a positive clock signal. The polar coordinate power amplifier may include a second transistor having a gate terminal for receiving a negative clock signal, and the first and second transistors have source terminals coupled to a power supply input. The polar coordinate power amplifier may include a third transistor having a source terminal coupled to a drain terminal of the first transistor. The polar coordinate power amplifier may include a fourth transistor having a source terminal coupled to a drain terminal of the second transistor, and the third and fourth transistors have gate terminals coupled to a circuit node. The polar coordinate power amplifier may include a first capacitor series-coupled between the power supply input and the circuit node. The polar coordinate power amplifier may include a first inverter having a power supply terminal coupled between the power supply input and the circuit node. The polar coordinate power amplifier may include a second inverter having a power supply terminal coupled between the power supply input and the circuit node. The polar coordinate power amplifier may include a third inverter having an input for receiving a positive clock signal and an output communicatively coupled to the input of the first inverter and the output of the second inverter. The polar power amplifier may include a fourth inverter having an input that receives a negative clock signal and an output that is communicatively coupled to an input of a second inverter and an output of a first inverter. Attached Figure Description

[0010] Figure 1 These are illustrations of exemplary electronic devices including wireless circuits according to some implementation schemes.

[0011] Figure 2 This is a diagram of an exemplary wireless circuit including a radio frequency amplifier, based on some implementation schemes.

[0012] Figure 3 This is a diagram of an exemplary transmitting circuit including a polar coordinate amplifier according to some implementation schemes.

[0013] Figure 4 This is a circuit diagram of an exemplary polar coordinate amplifier with dynamic common-source cascode bias, based on some implementation schemes.

[0014] Figure 5 This is an example based on some implementation schemes. Figure 4 The graphs showing the power supply voltage and cascode voltage versus time in a polar coordinate amplifier of the type shown.

[0015] Figure 6 It is based on some implementation plans. Figure 4 The graph shows the voltage waveforms at different nodes of the polar coordinate amplifier of the type shown.

[0016] Figure 7 This is an example based on some implementation schemes. Figure 4 The graph shows how dynamic cascode bias in a polar amplifier of the type shown can reduce amplitude modulation to amplitude modulation (AMAM) distortion and amplitude modulation to phase modulation (AMPM) distortion in a polar amplifier.

[0017] Figure 8 This is an example based on some implementation schemes. Figure 4 The graph shows how dynamic cascode bias in a polar amplifier of the type shown can reduce the adjacent channel leakage ratio (ACLR) of the polar amplifier. Detailed Implementation

[0018] Figure 1 The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a hanging device, a headset or handset, a device embedded in glasses, goggles, a helmet, or other equipment worn on a user's head (e.g., an augmented, virtual, or mixed reality head-mounted display); or another wearable or micro device, a television set, a computer monitor without an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in a kiosk or a car), a voice-controlled speaker connected to the wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that enables the functionality of two or more of these devices; or other electronic equipment.

[0019] like Figure 1 As shown in the functional block diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some embodiments, housing 12 may be partially or entirely formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12, or at least some of the structures constituting housing 12, may be formed of metallic elements.

[0020] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage device circuitry 16. Storage device circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage device circuitry 16 may include storage devices integrated within device 10, and / or removable storage media.

[0021] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more processors, such as a microprocessor, microcontroller, digital signal processor, host processor, baseband processor integrated circuit, application-specific integrated circuit, central processing unit (CPU), graphics processing unit (GPU), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage device circuitry 16 (e.g., storage device circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage device circuitry 16 may be executed by processing circuitry 18.

[0022] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as Wi-Fi). ® ), such as Bluetooth ®Protocols such as those used for other short-range wireless communication links, including wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 3GPP fifth-generation (5G) new radio (NR) protocols, sixth-generation (6G) protocols, sub-THz protocols, THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), satellite communication (SATCOM) protocols, antenna-based spatial ranging protocols, optical communication protocols, or any other desired communication protocols. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0023] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice and joysticks, and other input-output devices may be coupled to device 10 via wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0024] Input-output circuitry 20 may include wireless circuitry 24 to support or perform radio frequency (RF) signal transmission and / or reception of device 10. Wireless circuitry 24 may be used for wireless communication. Wireless communication performed by wireless circuitry 24 may include or involve wireless data communication (e.g., where wireless data is carried by RF signals transmitted bidirectionally or unidirectionally between wireless circuitry 24 and other communication equipment), RF signal transmission, RF signal reception, and / or radio-based spatial ranging / sensing (e.g., radio detection and ranging (radar) operation, short-range object detection such as object detection based on near-field RF signals, etc.). RF signals transmitted by wireless circuitry 24 may include or carry wireless data (e.g., organized into frames, packets, symbols, datagrams, etc.), radar or other spatial ranging waveforms, continuous wave signals, chirped signals, control signals, management signals, reference signals, beacon signals, tones, pulse / pulse signals, waveforms associated with one or more communication protocols, and / or any other RF waveforms or signals. Wireless circuitry 24 is sometimes referred to herein as wireless communication circuitry 24, communication circuitry 24, or simply circuitry 24. Wireless circuit 24 may include one or more antennas. Wireless circuit 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, RF transmission lines, and / or any other circuitry for transmitting and / or receiving RF signals using the antennas. Some or all of the components of wireless circuit 24 may be disposed on the same substrate (e.g., printed circuit board, semiconductor substrate, chip, integrated circuit (IC), IC package, etc.), mounted to the same substrate, communicatively coupled to the same substrate, and / or integrated within the same substrate, or may be distributed between two or more substrates (e.g., printed circuit board, semiconductor substrate, chip, IC, IC package, etc.).

[0025] Wireless circuit 24 can transmit and / or receive radio frequency signals within the corresponding frequency band of a radio frequency (sometimes referred to herein as a communication band or simply a "band"). The frequency band processed by wireless circuit 24 may include wireless local area network (WLAN) bands (e.g., Wi-Fi). ® (IEEE 802.11) or other WLAN communication bands such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), Wi-Fi ® 6E band (e.g., 5925MHz to 7125MHz), Wi-Fi ® 7-band and / or other Wi-Fi ® Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) frequency bands such as 2.4GHz Bluetooth. ®Frequency bands or other WPAN communication bands; cellular phone bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave bands between 10 GHz and 100 GHz; sub-THz bands between approximately 100 GHz and 10 THz (e.g., 6G bands); near field communication (NFC) bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Navigation Satellite System (BDS) bands, etc.); ultra-wideband (UWB) bands operating under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; satellite communication (satcom) bands (e.g., IEEE...). C-band (4GHz to 8GHz), S-band (2GHz to 4GHz), L-band (1GHz to 2GHz), X-band (8GHz to 12GHz), W-band (75GHz to 110GHz), V-band (40GHz to 75GHz), K-band (18GHz to 27GHz), K a Frequency band (26.5GHz to 40GHz), K u Frequency bands (12GHz to 18GHz, etc.); unlicensed frequency bands; communication frequency bands under the 3GPP wireless communication standard family; communication frequency bands under the IEEE 802.XX standard family; and / or any other desired frequency bands of interest.

[0026] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. (Example...) Figure 2 As shown, wireless circuitry 24 may include a processor such as processor 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Processor 26 may be a baseband processor, application processor, general-purpose processor, microprocessor, microcontroller, digital signal processor, host processor, dedicated signal processing hardware, or other type of processor. Processor 26 may be coupled to transceiver 28 via path 34. Transceiver 28 may be coupled to antenna 42 via RF transmission line path 36. RF front-end module 40 may be disposed on RF transmission line path 36 between transceiver 28 and antenna 42.

[0027] exist Figure 2In the example, for clarity, wireless circuit 24 is illustrated as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally, wireless circuit 24 may include any desired number of processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmit line path 36. Each RF transmit line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmit line path 36. If desired, one or more RF transmit line paths 36 in wireless circuit 24 may be implemented without any front-end modules disposed thereon.

[0028] The RF transmit line path 36 may be coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmit line path 36 may have a positive transmit line signal path coupled to a positive antenna feed terminal on the antenna 42. The RF transmit line path 36 may also have a ground transmit line signal path coupled to a ground antenna feed terminal on the antenna 42. This example is illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections coupled to one or more RF transmit line paths 36.

[0029] RF transmission path 36 may include a means for communication with device 10 ( Figure 1 The transmitting lines in device 10 route the radio frequency antenna signals within the device. The transmitting lines in device 10 may include coaxial cables, microstrip transmitting lines, stripline transmitting lines, edge-coupled microstrip transmitting lines, edge-coupled stripline transmitting lines, and transmitting lines formed by combinations of these types of transmitting lines. The transmitting lines in device 10 (such as the transmitting lines in radio frequency transmitting line path 36) may be integrated into rigid and / or flexible printed circuit boards.

[0030] During wireless transmission, processor 26 can provide a transmit signal (e.g., a digital or baseband signal) to transceiver 28 via path 34. Transceiver 28 may also include circuitry for converting the transmit (baseband) signal received from processor 26. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) the transmit (baseband) signal to radio frequency before transmission via antenna 42. The processor 26 communicates with transceiver 28 in this manner. Figure 2 The examples are illustrative. Generally, transceiver 28 can communicate with a baseband processor, application processor, general-purpose processor, microcontroller, microprocessor, or one or more processors within circuit 18. Transceiver circuit 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 can transmit radio frequency (RF) signals via transmitter (TX) 30 through RF transmission line path 36 and front-end module 40 via antenna 42. Antenna 42 can transmit the RF signal to external wireless equipment by radiating the RF signal into free space.

[0031] During wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver 28 via RF transmission path 36 and front-end module 40. Transceiver 28 may include circuitry, such as receiver (RX) 32, for receiving signals from front-end module 40 and for converting the received RF signals into corresponding baseband signals. For example, transceiver 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to baseband frequencies before transmitting the received signals via path 34 to processor 26.

[0032] Front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on radio frequency signals transmitted (transmitted and / or received) via radio frequency transmit line path 36. For example, FEM 40 may include front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, dual-signal circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifiers 50 and / or one or more low-noise amplifier circuitry 52), signal attenuators, impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 with the impedance of radio frequency transmit line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on the radio frequency signals transmitted and / or received by antenna 42. Each of the front-end module components can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip. If desired, amplifier circuit 48 and / or other components in front-end 40 (such as filter circuit 44) can also be implemented as part of transceiver circuit 28.

[0033] Filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry may be disposed along RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to regulate the frequency response and wireless performance of antenna 42 over time.

[0034] Transceiver 28 may be separate from front-end module 40. For example, transceiver 28 may be formed on another substrate such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of front-end module 40. Although for clarity, in Figure 1In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of processor 26 and / or transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on processor 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) to control the operation of front-end module 40.

[0035] Transceiver 28 may include a frequency band for processing WLAN communication (e.g., Wi-Fi). ® (IEEE 802.11) or other WLAN communication bands such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), Wi-Fi ® 6E band (e.g., 5925MHz to 7125MHz) and / or other Wi-Fi ® Wireless LAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz Bluetooth. ® Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits that process cellular phone frequency bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, 6G bands above 100 GHz, etc.); near field communication (NFC) transceiver circuits that process near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits that process satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); and circuits that use IEEE... Ultra-wideband (UWB) transceiver circuitry for handling communications using the 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuitry for covering any other desired communication frequency band of interest.

[0036] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0037] As described above, the front-end module 40 may include one or more power amplifiers (PAs) 50 in the transmit (uplink) path. Power amplifiers 50 (sometimes referred to as RF power amplifiers, transmit amplifiers, or amplifiers) can be configured to amplify RF signals without altering the signal shape, format, or modulation. For example, amplifiers 50 may be used to provide 10dB gain, 20dB gain, 10dB-20dB gain, less than 20dB gain, more than 20dB gain, or other suitable amounts of gain.

[0038] Figure 3 This is a diagram illustrating an exemplary transmission path 58 of wireless circuit 24. Transmission path 58 is sometimes referred to herein as transmission chain 58 or transmission circuit 58. Figure 3 As shown, wireless circuit 24 may include processing circuitry such as one or more processors 26, converter circuitry such as converter circuitry 54, radio frequency amplifier circuitry such as radio frequency amplifier 50 (e.g., a power amplifier), and an antenna 42 configured to radiate the radio frequency signal output by amplifier 50. Additional components (not shown) may also be provided at different locations along the transmission path 58 if desired.

[0039] Amplifier 50 can be set on FEM 40 or Figure 2 In the transceiver circuit 28. Processor 26 may represent one or more processors, such as a baseband processor, application processor, digital signal processor, microcontroller, microprocessor, central processing unit (CPU), programmable device, combination of these circuits and / or Figure 1 One or more processors are included within circuit 18. Processor 26 may be configured to generate a digital baseband signal Dbb (e.g., a digital data bit stream at baseband). Signal Dbb is sometimes referred to as a digital signal or a transmit signal. As an example, signal Dbb generated by processor 26 may include in-phase (I) and quadrature-phase (Q) signals, radius and phase signals, vector inputs, or other digitally encoded signals.

[0040] In the specific implementation described herein as an example, amplifier 50 is implemented as a polar power amplifier (PA). Therefore, amplifier 50 is sometimes referred to herein as a polar PA 50, a polar RF amplifier 50, or simply a polar amplifier 50. For example, a polar amplifier can be more easily scaled during the fabrication / manufacturing of wireless circuit 24 than a non-polar amplifier architecture. Implementing amplifier 50 as a polar amplifier also allows the transmission circuit 58 to be implemented without an additional / dedicated mixer for up-converting the signal to RF (e.g., because amplifier 50 uses a local oscillator signal to drive the amplifier output an amplified RF signal as the RF signal RFSIG).

[0041] When implemented as a polar coordinate amplifier, amplifier 50 may include a first power supply voltage terminal or input, such as power input 68 (sometimes referred to herein as power terminal 68 or power input terminal 68). Amplifier 50 may also include a second power supply voltage terminal or input, such as a reference voltage input coupled to a reference voltage 66 (e.g., ground, VSS, or another reference potential). The reference voltage input and power input 68 may, for example, form a power supply voltage rail for amplifier 50.

[0042] Amplifier 50 may also include a clock terminal or input different from power supply input 68, such as a local oscillator (LO) input 70 (sometimes referred to herein as LO terminal 70 or LO input terminal 70). Amplifier 50 may receive an LO signal at its LO input 70. In a specific implementation described herein as an example, the LO signal may include a differential LO signal pair comprising a first (positive) LO signal LOP and a second (negative) LO signal LON. Amplifier 50 may receive a power supply voltage, such as power supply voltage VDD, at its power supply input 68. Amplifier 50 may use the local oscillator signals LOP and LON and the power supply voltage VDD to generate an RF signal RFSIG (e.g., without using upconversion or mixer circuitry separate from amplifier 50).

[0043] The input of converter circuit 54 can be communicatively coupled to the output of processor 26. Converter circuit 54 may have a first output communicatively coupled to the LO input 70 of amplifier 50 via signal path 60. Converter circuit 54 may also have a second output communicatively coupled to the power input 68 of amplifier 50 via signal path 62. Signal path 60 is sometimes referred to herein as phase signal path 60. Signal path 62 is sometimes referred to herein as amplitude signal path 62.

[0044] The converter circuit 54 may include signal conversion circuitry, such as a digital-to-analog converter (DAC) circuit and a Cartesian-to-polar coordinate converter circuit. As an example, the Cartesian-to-polar coordinate converter circuit may be implemented using one or more digital signal processors within the converter circuit 54. The Cartesian-to-polar coordinate converter circuit can convert the signal Dbb from a single signal in Cartesian coordinates into two distinct signals in polar coordinates. The two signals in polar coordinates may include an amplitude signal (waveform) A(t) and a corresponding phase signal (waveform) θ(t).

[0045] The amplitude signal A(t) represents the amplitude of the signal Dbb at time t, and the phase signal θ(t) represents the phase of the signal Dbb at the same time t. The DAC circuit in converter circuit 54 may include, for example, a first DAC (e.g., one or more DAC units in a first group) to convert the amplitude signal A(t) from the digital domain to the analog domain, and may include a second DAC (e.g., one or more DAC units in a second group) to convert the phase signal θ(t) from the digital domain to the analog domain. Converter circuit 54 may output the amplitude signal A(t) to signal path 62 (in the analog domain). Converter circuit 54 may simultaneously output the phase signal θ(t) to signal path 60 (in the analog domain).

[0046] If desired, wireless circuit 24 may include amplifier circuitry, such as an envelope amplifier 64 disposed on signal path 62 between converter circuit 54 and amplifier 50. Envelope amplifier 64 may amplify (scale) the amplitude signal A(t) to generate a supply voltage VDD provided to amplifier 50 (e.g., the supply voltage VDD may vary over time according to the amplitude signal A(t), or equivalently, the amplitude signal A(t) may represent the supply voltage VDD before being scaled by envelope amplifier 64). If desired, envelope amplifier 64 may be replaced by any desired supply voltage generation circuitry (e.g., a power integrated circuit, a power management unit, an envelope tracking integrated circuit, etc.) that generates the supply voltage VDD based on the amplitude signal A(t) (e.g., by scaling or otherwise processing the amplitude signal A(t)). Alternatively, envelope amplifier 64 may be omitted, and the supply voltage VDD may be formed from the amplitude signal A(t) without scaling or amplification. Generally speaking, the power supply voltage VDD can be a voltage waveform that encodes or carries the amplitude information (modulation) of the radio frequency signal RFSIG to be output by amplifier 50 (e.g., represented by the amplitude signal A(t)). Power supply input 68 is sometimes also referred to herein as the amplitude modulation (AM) input of amplifier 50.

[0047] Wireless circuit 24 may include clock circuitry, such as an LO generator 56 disposed on the signal path 60 between converter circuit 54 and amplifier 50. LO generator 56 may generate local oscillator signals LOP and LON provided to the LO input 70 of amplifier 50 based on the phase signal θ(t). (E.g., the local oscillator signals LOP and LON may encode phase information (modulation) of the radio frequency signal RFSIG to be output by amplifier 50.) LO generator 56 may include, for example, a synthesizer, a signal generator, oscillator circuitry (e.g., a crystal oscillator, voltage-controlled oscillator (VCO), etc.), loop circuitry (e.g., one or more phase-locked loops, frequency-locked loops, etc.), and / or any other desired circuitry that converts the phase signal θ(t) into local oscillator signals LOP and LON. More generally, the local oscillator signals LOP and LON may be any desired oscillating or periodic clock signal used to drive amplifier 50 using phase modulation output from converter circuit 54 (e.g., phase modulation of the radio frequency signal RFSIG to be transmitted). Phase modulation (coding) performed by amplifier 50 under the control of local oscillator signals LOP and LON (e.g., based on phase signal θ(t)) and / or amplitude modulation (coding) performed by amplifier 50 under the control of power supply voltage VDD (e.g., based on amplitude signal A(t)) can collectively represent the radio data carried by signal Dbb (e.g., converter circuit 54 can convert the radio data in signal Dbb (such as baseband data representing streams of symbols, packets, frames, datagrams, etc.) into time-varying amplitude modulation carried by amplitude signal A(t) and time-varying phase modulation carried by phase signal θ(t).

[0048] During signal transmission, local oscillator signals LOP and LON drive amplifier 50, while simultaneously powering amplifier 50 with the corresponding voltage waveform of the power supply voltage VDD. This allows amplifier 50 to output an amplified radio frequency (RFSIG) signal in the corresponding frequency band at its output. The RFSIG signal may have a phase (as a function of time) given by the local oscillator signals LOP and LON and the phase signal θ(t). The RFSIG signal may also have a corresponding amplitude (as a function of time) given by the power supply voltage VDD and the amplitude signal A(t). Antenna 42 can radiate the RFSIG signal.

[0049] Figure 4 This is a circuit diagram of amplifier 50 (e.g., a polar coordinate amplifier that generates an RF signal RFSIG based on local oscillator signals LON and LOP and the supply voltage VDD). Figure 4As shown, amplifier 50 may include a first common-source transistor stage, a first common-gate transistor stage, a second common-gate transistor stage, and a second common-source transistor stage. The first common-source transistor stage includes common-source transistors 72A and 72B, and the first common-gate transistor stage includes transistors 74A and 74B. The second common-gate transistor stage includes transistors 76A and 76B, and the second common-source transistor stage includes common-source transistors 78A and 78B. All transistor stages are connected in series between power supply input 68 and reference voltage 66. Transistors 72A, 74A, 76A, and 78A may be connected in series between power supply input 68 and reference voltage 66. Transistors 72B, 74B, 76B, and 78B may be connected in series between power supply input 68 and reference voltage 66. Transistors 72A, 74A, 76A, and 78A may be connected in parallel with transistors 72B, 74B, 76B, and 78B between power supply input 68 and reference voltage 66.

[0050] The first common-source stage can be, for example, a common-source p-channel metal-oxide-semiconductor (PMOS) stage, and transistors 72A and 72B can be PMOS transistors. Transistors 72A and 72B are sometimes also referred to herein as p-type transistors 72A and 72B, p-type common-source transistors 72A and 72B, PMOS transistors 72A and 72B, common-source transistors 72A and 72B, or PMOS common-source transistors 72A and 72B. The first common-source cascode stage can be, for example, a PMOS common-source cascode stage, and transistors 74A and 74B can be PMOS transistors. Transistors 74A and 74B are sometimes referred to herein as p-type transistors 74A and 74B, p-type cascode transistors 74A and 74B, PMOS transistors 74A and 74B, PMOS cascode transistors 74A and 74B, or simply as cascode transistors 74A and 74B.

[0051] The second cascode stage can be, for example, an n-channel metal-oxide-semiconductor (NMOS) stage, and transistors 76A and 76B can be NMOS transistors. Transistors 76A and 76B are sometimes referred to herein as n-type transistors 76A and 76B, n-type cascode transistors 76A and 76B, NMOS transistors 76A and 76B, NMOS cascode transistors 76A and 76B, or simply cascode transistors 76A and 76B. The second cascode stage can be, for example, a cascode NMOS stage, and transistors 78A and 78B can be NMOS transistors. Transistors 78A and 78B are sometimes referred to herein as n-type transistors 78A and 78B, n-type common-source transistors 78A and 78B, NMOS transistors 78A and 78B, common-source transistors 78A and 78B, or NMOS common-source transistors 78A and 78B. In this way, amplifier 50 can be implemented as a complementary metal-oxide-semiconductor (CMOS) common-source cascode amplifier, wherein the first common-source stage and the first common-source cascode stage form the PMOS portion or block of the amplifier, and wherein the second common-source stage and the second common-source cascode stage form the NMOS portion or block of the amplifier.

[0052] When referring to the current-conducting terminals of a metal-oxide-semiconductor (MOS) transistor, the terms "source" and "drain" are sometimes used interchangeably. Therefore, the source and drain terminals are sometimes referred to as "source-drain" terminals (e.g., a transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal). Transistors 72A and 72B may each have a corresponding first source-drain terminal (e.g., a source terminal) coupled to a power input 68 for receiving a power supply voltage VDD. Transistors 72A and 72B may each have a corresponding second source-drain terminal (e.g., a drain terminal) coupled to a first cascode transistor. For example, the second source-drain terminal of transistor 72A may be coupled to the first source-drain terminal (e.g., a source terminal) of cascode transistor 74A. The second source-drain terminal of transistor 72B may be coupled to the first source-drain terminal (e.g., a source terminal) of cascode transistor 74B.

[0053] Similarly, transistors 78A and 78B may each have a corresponding first source-drain terminal (e.g., a source terminal) coupled to a reference voltage 66. Transistors 78A and 78B may each have a corresponding second source-drain terminal (e.g., a drain terminal) coupled to a second cascode stage. For example, the second source-drain terminal of transistor 78A may be coupled to the first source-drain terminal (e.g., a source terminal) of cascode transistor 76A. Similarly, the second source-drain terminal of transistor 78B may be coupled to the first source-drain terminal (e.g., a source terminal) of cascode transistor 76B. The second source-drain terminal (e.g., a drain terminal) of cascode transistor 76A may be coupled to the second source-drain terminal (e.g., a drain terminal) of cascode transistor 74A. The second source-drain terminal (e.g., the drain terminal) of the cascode transistor 76B can be coupled to the second source-drain terminal (e.g., the drain terminal) of the cascode transistor 74B.

[0054] Amplifier 50 may have an RF output 86 coupled between a first cascode stage and a second cascode stage (e.g., between the PMOS and NMOS portions of amplifier 50). RF output 86 may include a first (positive) RF output terminal 86P coupled to the second source-drain terminals (e.g., drain terminals) of transistors 74A and 76A. RF output 86 may also include a second (negative) RF output terminal 86N coupled to the second source-drain terminals (e.g., drain terminals) of transistors 74B and 76B. During signal transmission, amplifier 50 may generate an output voltage VOUT between its output terminals 86P and 86N. The output voltage VOUT may, for example, be the RF signal RFSIG output by amplifier 50 to antenna 42. Figure 3 The voltage waveform of ).

[0055] The gate terminals of common-source transistors 72A, 72B, 78A, and 78B can be coupled to signal path 60 ( Figure 3The gate terminals of common-source transistors 72A and 78A may, for example, form part of the LO input 70 of amplifier 50, which is sometimes referred to herein as the phase-modulation (PM) input of amplifier 50. The gate terminals of common-source transistors 72A and 78A may, for example, each receive a local oscillator signal LOP from signal path 60 (e.g., operatively coupled to a first (positive) LO input terminal of signal path 60). Simultaneously, the gate terminals of common-source transistors 72B and 78B may receive a local oscillator signal LON from signal path 60 (e.g., operatively coupled to a second (negative) LO input terminal of signal path 60). The local oscillator signal LOP may drive the gate terminals of transistors 72A and 78A to selectively activate or deactivate transistors 72A and 78A (e.g., to induce or deactivate current flow between the source-drain terminals of transistors 72A and 78A). The local oscillator signal LON can drive the gate terminals of transistors 72B and 78B to selectively activate or deactivate transistors 72A and 78B (e.g., to selectively cause or stop current flow between the source-drain terminals of transistors 72B and 78B).

[0056] The term "activation" in this document refers to or is defined as the action of placing the switch in a "conducting" or low-impedance state, such that the two terminals of the switch are electrically connected to conduct current. Activating a switch may sometimes be referred to as turning on or closing a switch. The term "deactivation" in this document refers to or is defined as the action of placing the switch in a "de-off" or high-impedance state, such that the two terminals of the switch / transistor are electrically disconnected with minimal leakage current. Deactivating a switch may sometimes be referred to as turning off or opening a switch.

[0057] Both the gate terminals of transistors 76A and 76B can be coupled to the reference voltage 66 via capacitor 84 (e.g., one or more capacitors). For example, the gate terminals of transistors 76A and 76B can each be coupled to circuit node 82 (sometimes referred to herein as cascode node 82, NMOS cascode node 82, or cascode gate node 82). Capacitor 84 can be coupled in series between circuit node 82 and circuit node 80 (e.g., capacitor 84 can include one or more capacitors coupled together in series, parallel, or any other desired manner between circuit node 82 and circuit node 80, and may include one or more distributed capacitors, etc.). The first source-drain terminals (e.g., source terminals) of transistors 78A and 78B can both be coupled to circuit node 80. Circuit node 80 can be coupled to the reference voltage 66 or can otherwise receive the reference voltage. Circuit node 80 can, for example, form a power supply voltage input or terminal (e.g., reference, ground, or VSS input or terminal) of amplifier 50.

[0058] Both the gate terminals of transistors 74A and 74B can be coupled to circuit node 88 (sometimes referred to herein as cascode node 88, PMOS cascode node 88, or cascode gate node 88). Cascode node 88 can be coupled to power input 68 via, through, or on capacitor 98 (e.g., one or more capacitors). Capacitor 98 can be coupled in series between cascode node 88 and power input 68 (e.g., capacitor 98 may include one or more capacitors coupled together in series, parallel, or any other desired manner between cascode node 88 and power input 68, and may include one or more distributed capacitors, etc.). In this way, power input 68 and the first source-drain terminals (e.g., source terminals) of transistors 72A and 72B can be coupled to a first side, end, electrode, terminal, or plate of capacitor 98. Cascode node 88 can be coupled to a second side, end, electrode, terminal, or plate of capacitor 98. Capacitor 98 is sometimes referred to as cascode capacitor 98 (e.g., containing one or more cascode capacitors).

[0059] In some specific implementations, during signal transmission, a power supply reference bias generator is used to generate a first bias voltage based on the power supply voltage VDD and provide the first bias voltage to the cascode node 88. Simultaneously, a ground reference bias generator is used to generate a second bias voltage based on the power supply voltage VDD and provide the second bias voltage to the circuit node 82. The power supply voltage VDD drives the power input 68 of amplifier 50 using the amplitude-modulated component of the RF signal RFSIG output by amplifier 50 at output 86. The bias voltage generated by the power supply reference bias generator and the power supply voltage VDD enable the generation of a cascode voltage VCASCP at the cascode node 88. Simultaneously, the bias voltage generated by the ground reference bias generator and the reference voltage 66 enable the generation of a cascode voltage VCASCN at the circuit node 82.

[0060] The local oscillator signals LON and LOP drive the gate terminals of transistors 72A, 72B, 78A, and 78B (e.g., according to the signals generated by the local oscillator). Figure 3 The phase signal output by the converter circuit 54 provides phase modulation), the cascode voltage VCASCP drives the gate terminals of transistors 74A and 74B, and the cascode voltage VCASCN drives the gate terminals of transistors 76A and 76B, thereby causing different amounts of current to flow between the source and drain terminals of each cascode transistor to generate a corresponding voltage VOUT at output 86 (e.g., ...). Figure 3 The radio frequency signal RFSIG). The voltage VOUT can exhibit phase modulation over time as given by the local oscillator signals LOP and LON (e.g., based on). Figure 3 The phase signal θ(t) can exhibit amplitude modulation over time as given by the supply voltage VDD. Phase and / or amplitude modulation can carry or encode wireless data of the signal Dbb. Figure 3 ).

[0061] In this way, the power supply reference bias generator can make the cascode voltage VCASCP track the AM waveform of the power supply voltage VDD received at power supply input 68. However, the power supply reference bias generator cannot provide a bias voltage with an amplitude exceeding the current amplitude of the power supply voltage VDD and the reference voltage 66. Because polar coordinate modulation may require the power supply voltage VDD to drop to a relatively low amplitude during signal transmission (e.g., to 0.5V or less), this can cause the cascode voltage VCASCP to be clipped at a relatively low amplitude close to 0V, which may push the PMOS transistor into the subthreshold region and may produce a sharp drop in phase shift in the signal output by the amplifier. This clipping of the cascode voltage VCASCP in Figure 5 As shown by curve 114.

[0062] Figure 5 Curve 110 plots the supply voltage VDD as a function of time (e.g., the voltage carried by the power supply voltage VDD). Figure 1 The amplitude signal A(t) gives the amplitude modulation. As shown in curve 114, when the supply voltage VDD drops below the threshold voltage V1 (e.g., 0.5V), such as when the amplitude modulation includes a relatively large minimum value 116, the cascode voltage VCASCP is clipped, clamped, or limited to the threshold voltage V1. This causes the cascode voltage VCASCP, and therefore the voltage VOUT, to incorrectly or incompletely track the full amplitude modulation of the supply voltage VDD (e.g., effectively losing information encoded by the amplitude modulation associated with the minimum value 116 in the supply voltage VDD).

[0063] To mitigate these issues, a dynamic bias voltage generated based on the local oscillator signals LOP and LON, along with additional voltages such as a bias voltage VB, can be used to bias the PMOS cascode stage of amplifier 50. Return to Figure 4 For example, amplifier 50 may include a dynamic level shifting circuit and a cross-coupled inverter stage for dynamically biasing the PMOS cascode stage of amplifier 50 based on local oscillator signals LOP and LON. Figure 4 As shown, the dynamic level shifting circuit may include a first (positive) dynamic level shifter 102A and a second (negative) dynamic level shifter 102B. A cross-coupled inverter stage may include a first inverter 100A cross-coupled with the second inverter 100B. Inverters 100A and 100B may be coupled between the outputs of dynamic level shifters 102A and 102B.

[0064] The dynamic level shifter 102A (sometimes referred to herein as a dynamic level shifting circuit, dynamic level shifting circuitry, or dynamic PMOS cascode bias circuit) may include amplifier circuitry such as inverter 90A. The input of inverter 90A may receive a local oscillator signal LOP (e.g., may be coupled to...). Figure 3The positive terminal of signal path 60). The output of inverter 90A can be coupled to the input of inverter 100A via a positive bias line such as bias line 94A. A level shift capacitor, such as capacitor 96A, can be disposed on bias line 94A and can be coupled in series between the output of inverter 90A and the input of inverter 100A. Capacitor 96A may include one or more capacitors, one or more distributed capacitors, etc., coupled in series and / or in parallel between inverter 90A and inverter 100A. Inverter 90A may have a first (e.g., PMOS) power supply input or terminal that receives a bias voltage VB and may have a second (e.g., NMOS) power supply input or terminal that receives a reference voltage 66 (e.g., the bias or power supply input of inverter 90A may be coupled between a power supply voltage rail formed by the bias voltage VB and the reference voltage 66). If desired, a power supply reference bias generator (not shown) can generate a bias voltage VB based on the power supply voltage VDD and the bias voltage VB can be used to power inverter 90A.

[0065] Similarly, the dynamic level shifter 102B may include amplifier circuitry, such as an inverter 90B. The input of the inverter 90B may receive a local oscillator signal LON (e.g., it may be coupled to...). Figure 3 The negative terminal of signal path 60). In this way, the gate terminals of transistors 72A, 72B, 78A and 78B, as well as the inputs of dynamic level shifters 102A and 102B (e.g., the inputs of inverters 90A and 90B) can collectively form the LO input 70 of amplifier 50. Figure 3 The output of inverter 90B can be coupled to the input of inverter 100B via a negative bias line such as bias line 94B. A level shifting capacitor, such as capacitor 96B, can be disposed on bias line 94A and can be coupled in series between the output of inverter 90B and the input of inverter 100B. Capacitor 96B may include one or more capacitors, one or more distributed capacitors, etc., coupled in series and / or in parallel between inverter 90B and inverter 100B. Inverter 90B may have a first (e.g., PMOS) power supply input that receives a bias voltage VB and may have a second (e.g., NMOS) power supply input (e.g., a reference or ground terminal) that receives a reference voltage 66 (e.g., the bias or power supply input of inverter 90B may be coupled between the power supply voltage rails formed by the bias voltage VB and the reference voltage 66).

[0066] The output of inverter 100A can be communicatively coupled to the input of inverter 100B and the output of inverter 90B. For example, as Figure 4As shown, the output of inverter 100A can be coupled to a negative dynamic bias terminal or node, such as circuit node 108 on bias line 94B. Circuit node 108 can be inserted on bias line 94B between inverter 100B and capacitor 96B. Similarly, the output of inverter 100B can be communicatively coupled to the input of inverter 100A and the output of inverter 90A. For example, as Figure 4 As shown, the output of inverter 100B can be coupled to a positive dynamic bias terminal or node, such as circuit node 106 on bias line 94A. Circuit node 106 can be inserted on bias line 94A between inverter 100A and capacitor 96A.

[0067] Within the cross-coupled inverter stage, inverter 100A may have a first (e.g., PMOS) power input (terminal) coupled to power input 68 and the first source-drain terminals of transistors 72A and 72B. Inverter 100B may also have a second (e.g., NMOS) power input (e.g., a reference or ground terminal) coupled to cascode node 88. Similarly, inverter 100B may have a first (e.g., PMOS) power input (terminal) coupled to power input 68 and the first source-drain terminals of transistors 72A and 72B. Inverter 100B may also have a second (e.g., NMOS) power input (e.g., a reference or ground terminal) coupled to cascode node 88. In this way, the bias or power input of inverter 100A may be coupled between the power supply voltage VDD and the cascode voltage VCASCP. Similarly, the bias or power input of inverter 100A can be coupled between the power supply voltage VDD and the power supply voltage rail at the cascode voltage VCASCP. The capacitor 98 within inverters 100A and 100B, as well as the PMOS cascode portion of amplifier 50, is sometimes collectively referred to herein as dynamic charge pump circuit 104 or dynamic charge pump 104. Circuit nodes 106 and 108 are sometimes also referred to herein as intermediate nodes of dynamic charge pump 104 or intermediate circuit nodes.

[0068] During signal transmission, inverter 90A can amplify (e.g., invert) the local oscillator signal LOP based on bias voltage VB and reference voltage 66 to drive / charge capacitor 96A. Capacitor 96A can be used to shift the DC level of the output of inverter 90A (e.g., the local oscillator signal LOP), which drives or generates a level-shifted voltage at circuit node 106. Inverter 100A can drive an inverted version of the voltage at circuit node 106 to circuit node 108. Simultaneously, inverter 90B can amplify (e.g., invert) the local oscillator signal LON based on bias voltage VB and reference voltage 66 to drive / charge capacitor 96B. Capacitor 96B can be used to shift the DC level of the output of inverter 90B (e.g., the local oscillator signal LON), which drives or generates a level-shifted voltage at circuit node 108. Inverter 100A can drive an inverted version of the voltage at circuit node 108 to circuit node 106. In this way, the dynamic level shifter can shift the local oscillator signal to the DC level of the power supply voltage VDD at circuit nodes 106 and 108. The swing of the voltage amplitude between circuit nodes 106 and 108 can be set by the bias voltage VB via dynamic level shifters 102A and 102B (e.g., it can be equal to the bias voltage VB).

[0069] The voltage swing between circuit nodes 106 and 108 drives a dynamic charge pump 104, which charges a capacitor 98 coupled to a cascode node 88. The voltage difference between the cascode voltage VCASCP at the cascode node 88 and the supply voltage VDD is equal to the voltage swing amplitude of the voltage swing between circuit nodes 106 and 108, which is equal to the bias voltage VB. In other words, the dynamic charge pump 104 and the dynamic level shifters 102A / 102B can shift the voltage swing between circuit nodes 106 and 108 (which is equal to the bias voltage VB) to a voltage equal to VDD-VB at the cascode node 88. This voltage at the cascode node 88 forms the cascode voltage VCASC (e.g., VB = VDD-VCASC or equivalently VCASC = VDD-VB). The bias voltage VB itself does not need to track the amplitude modulation of the supply voltage VDD, so its bandwidth requirements can be relatively relaxed. When driven by dynamic charge pump 104 and dynamic level shifters 102A and 102B, the cascode voltage VCASCP can track all amplitude modulations in the supply voltage VDD very quickly without clipping, even if the supply voltage VDD drops below the threshold V1. Figure 5 ).

[0070] Figure 5Curve 144 illustrates the cascode voltage VCASCP at cascode node 88 when driven by dynamic level shifters 102A and 102B and dynamic charge pump 104. As shown in curve 112, when the supply voltage VDD exhibits a minimum value 116, the cascode voltage VCASCP drops below the threshold voltage V1 and is not clipped, clamped, or limited to the threshold voltage V1. The difference between curves 110 and 112 at each time t can correspond to the voltage swing between circuit nodes 102 and 104 at time t, which can be equal to the bias voltage VB used to power inverters 90A and 90B in dynamic level shifters 102A and 102B. In this way, the common-source cascode voltage VCASCP and therefore the voltage VOUT can accurately, completely and quickly track the full amplitude modulation of the supply voltage VDD (e.g., in the RF signal RFSIG output by amplifier 50, all the information encoded by the amplitude modulation associated with the minimum value 116 in the supply voltage VDD is effectively preserved).

[0071] Figure 6 The voltage waveforms at different nodes of amplifier 50 during signal transmission are illustrated (e.g., the change of voltage (V) over time t). Figure 5 (Observed within the magnified region 118). Curve 120 plots the voltage at circuit node 108. Dashed curve 122 plots the voltage at circuit node 106. When the voltage at circuit node 106 drops (e.g., at times T1 and T2), the dynamic charge pump 104 can cause the voltage at circuit node 108 to begin to rise. Conversely, when the voltage at circuit node 108 drops (e.g., at time T2), the dynamic charge pump 104 can cause the voltage at circuit node 106 to begin to rise. As shown by curves 122 and 120, when the local oscillator signals LOP and LON continue to drive the LO input 70 of amplifier 50 ( Figure 3 When the voltage at circuit node 106 and circuit node 108 can be at the supply voltage VDD (e.g., corresponding to the supply voltage VDD), the voltage at circuit node 106 and circuit node 108 can be at the supply voltage VDD (e.g., corresponding to the supply voltage VDD). Figure 5 Curve 110) and cascode voltage VCASCP (e.g., corresponding to Figure 5 The difference between curves 120 and 122 at any given time (e.g., the voltage swing between circuit node 106 and circuit node 108) can be equal to the bias voltage VB used to power dynamic level shifters 102A and 102B.

[0072] Compared to the specific implementation that omits the dynamic level shifters 102A / 102B and the dynamic charge pump 104, the absence of clipping in the cascode voltage VCASCP, even when the supply voltage VDD drops to a relatively low level, can also help improve the amplitude modulation to amplitude modulation (AMAM) distortion and amplitude modulation to phase modulation (AMPM) distortion of amplifier 50. Figure 7 Includes graphs showing how dynamic level shifters 102A / 102B and dynamic charge pump 104 can improve AMAM and AMPM distortion of amplifier 50 at different supply voltage levels VDD.

[0073] Figure 7 Curve 124 plots the AMAM distortion of the amplifier as a function of the supply voltage VDD when dynamically biased at the PMOS cascode stage of amplifier 50 by dynamic level shifters 102A / 102B and dynamic charge pump 104. Curve 126 plots the AMAM distortion of amplifier 50 without dynamic level shifters 102A / 102B and dynamic charge pump 104. Curve 130 plots the AMPM distortion of the amplifier when dynamically biased at the PMOS cascode stage of amplifier 50 by dynamic level shifters 102A / 102B and dynamic charge pump 104. Curve 128 plots the AMPM distortion of amplifier 50 without dynamic level shifters 102A / 102B and dynamic charge pump 104. As shown in curves 124 to 130, clipping in the cascode voltage VCASC at a supply voltage VDD less than the threshold V1 (e.g., 0.5V) can produce significant nonlinear AMAM and nonlinear AMPM distortion at amplifier 50, which may degrade the transmitting circuit 58. Figure 3 The overall wireless performance of the amplifier 50. Conversely, the dynamic level shifters 102A / 102B and the dynamic charge pump 104 can effectively reduce, mitigate, or eliminate nonlinearity in AMAM and AMPM distortion of the amplifier 50 by allowing the cascode voltage VCASC to drop below the threshold voltage V1 when the supply voltage VDD drops below the threshold voltage V1.

[0074] Compared to the specific implementation that omits the dynamic level shifters 102A / 102B and the dynamic charge pump 104, the absence of clipping in the cascode voltage VCASCP, even when the supply voltage VDD drops to a relatively low level, can also help improve the adjacent channel leakage ratio (ACLR) of amplifier 50. Figure 8 This is a graph showing how the dynamic level shifter 102A / 102B and the dynamic charge pump 104 can improve the ACLR of the amplifier 50.

[0075] Curve 134 plots the signal level (e.g., power) of the RF signal RFSIG (output voltage VOUT) as a function of frequency F in the absence of dynamic level shifters 102A / 102B and dynamic charge pump 104 in amplifier 50. Transmitting circuitry 58 can transmit the RF signal RFSIG within a corresponding frequency allocation 132 extending from frequency FA to frequency FB. Frequency allocation 132 can span one or more consecutive resource blocks, resource elements, sub-channels, and / or another spectrum / resource set, and is sometimes referred to herein as frequency range 132 (e.g., consecutive resource blocks / element sets, frequency channels, some or all of a frequency / communication band, etc.). Frequency allocation 132 can be determined by communication scheduling of device 10 (e.g., as maintained by a wireless network), by one or more applications running on device 10, by one or more communication requests imposed on device 10, etc.

[0076] As shown in curve 134, the RF signal RFSIG can exhibit a signal peak within frequency allocation 132. However, clipping exists in the cascode voltage VCASCP at cascode node 88 (see, for example...). Figure 5 Curve 114) can cause the RF signal RFSIG to exhibit a relatively high signal level at frequencies outside of frequency allocation 132 (e.g., where the signal level gradually decreases with increasing offset from frequency allocation 132). This can cause amplifier 50 to exhibit a relatively high or excessively high ACLR. The signal level of the RF signal RFSIG may, for example, exceed a threshold or limit, such as transmit mask 138. Transmit mask 138 may represent an upper limit (e.g., imposed on device 10 by the manufacturer, regulatory body, or group of device 10 or wireless circuit 24, a communication protocol or standard governing the transmission of transmit circuit 58, one or more applications running on device 10, etc.). Transmit mask 138 exceeding frequency allocation 132 may, for example, cause wireless circuit 24 to disable the transmit mask and / or may otherwise degrade the wireless performance of amplifiers, other circuitry in device 10, and / or external devices receiving RF signals.

[0077] Curve 136 plots the signal level of the RF signal RFSIG as a function of frequency when amplifier 50 includes dynamic level shifters 102A / 102B and dynamic charge pump 104. As shown in curve 136, the RF signal RFSIG can still exhibit a signal peak within frequency allocation 132. However, eliminating clipping in the cascode voltage VCASCP at the cascode node 88 via dynamic charge pump 104 and dynamic level shifters 102A / 102B allows the RF signal RFSIG to exhibit a relatively low signal level at frequencies outside frequency allocation 132 (e.g., where the signal level decreases rapidly with increasing offset from frequency allocation 132). This allows amplifier 50 to exhibit a relatively low ACLR. The signal level of the RF signal RFSIG can, for example, be less than that of the transmit mask 138 at all frequencies outside frequency allocation 132. Figures 6 to 8 The curves 120 to 136 can actually have other shapes. As another example, relative to a specific implementation of amplifier 50 without dynamic level shifters 102A / 102B and dynamic charge pump 104, dynamic level shifters 102A / 102B and dynamic charge pump 104 can also be used to increase the error vector magnitude (EVM) of the RF signal RFSIG by up to 11 dB to 12 dB.

[0078] The above combination Figures 1 to 8 The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage device circuitry 16 and / or wireless communication circuitry 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory (such as non-volatile random access memory (NVRAM)), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of the device 10 (e.g., processing circuitry in wireless communication circuitry 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0079] As used herein, the term "concurrent" means at least partially overlapping in time. In other words, the first and second events are referred to herein as "concurrent" if at least some of the first events occur simultaneously with at least some of the second events (e.g., if at least some of the first events occur during, concurrently with, or when at least some of the second events occur). The first and second events can be concurrent if they are synchronized (e.g., if the entire duration of the first event overlaps with the entire duration of the second event in time), but they can also be concurrent if they are asynchronous (e.g., if the first event begins before or after the second event, ends before or after the second event, or does not partially overlap in time). As used herein, the term "at the time of" is synonymous with "concurrent".

[0080] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

[0081] According to one embodiment, an amplifier circuit is configured to output a radio frequency (RF) signal, the amplifier circuit comprising: a first common-source stage configured to receive a power supply voltage for amplitude modulation of the RF signal; a first common-source cascode stage including a first transistor and a second transistor having gate terminals coupled to a common-source cascode node; a second common-source cascode stage, wherein the first common-source cascode stage is coupled between the second common-source cascode stage and the first common-source stage; a second common-source stage coupled to a reference voltage, wherein the second common-source cascode stage is coupled between the second common-source stage and the first common-source cascode stage; and a cross-coupled inverter having a power input coupled between the power supply voltage and the common-source cascode node.

[0082] According to another embodiment, the amplifier circuit may optionally include a capacitor coupled in series between the power supply voltage and the common source / common gate node.

[0083] According to another embodiment, the amplifier circuit may optionally include a radio frequency (RF) output configured to transmit the RF signal, wherein the RF output is coupled between the first cascode stage and the second cascode stage.

[0084] According to another embodiment, the first common-source stage may optionally include a third transistor and a fourth transistor, the third transistor being series coupled between the power supply voltage and the first transistor, the fourth transistor being series coupled between the power supply voltage and the second transistor, the gate terminal of the third transistor being configured to receive a positive local oscillator signal, the gate terminal of the fourth transistor being configured to receive a negative local oscillator signal, and the positive local oscillator signal and the negative local oscillator signal being transmitted for phase modulation of the radio frequency signal.

[0085] According to another embodiment, the second cascode stage may optionally include a fifth transistor and a sixth transistor, the first transistor being series coupled between the fifth transistor and the third transistor, the second transistor being series coupled between the sixth transistor and the fourth transistor, the gate terminals of the fifth transistor and the sixth transistor being coupled to a circuit node, and capacitively coupled between the circuit node and the reference voltage.

[0086] According to another embodiment, the second cascode stage may optionally include a seventh transistor and an eighth transistor, the seventh transistor being coupled in series between the fifth transistor and the reference voltage, the eighth transistor being coupled in series between the sixth transistor and the reference voltage, the gate terminal of the seventh transistor being configured to receive a positive local oscillator signal, and the gate terminal of the eighth transistor being configured to receive a negative local oscillator signal.

[0087] According to another embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are optionally p-type transistors, and the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are optionally n-type transistors.

[0088] According to another embodiment, the cross-coupled converter may optionally include: a first inverter having a first power input coupled between the power supply voltage and the cascode node; and a second inverter having a second power input coupled between the power supply voltage and the cascode node, wherein the output of the first inverter is communicatively coupled to the input of the second inverter, and wherein the output of the second inverter is communicatively coupled to the input of the first inverter.

[0089] According to another embodiment, the amplifier circuit may optionally include: a first level shifting circuit, the first level shifting circuit being communicatively coupled to the input of the first inverter via a first bias path, the output of the second inverter being coupled to a first circuit node on the first bias path; and a second level shifting circuit, the second level shifting circuit being communicatively coupled to the input of the second inverter via a second bias path, the output of the first inverter being coupled to a second circuit node on the second bias path.

[0090] According to another embodiment, the first level shifting circuit may optionally include: a third inverter having an output coupled to the first bias path; and a first capacitor disposed on the first bias path between the third inverter and the first circuit node, wherein the third inverter is configured to drive a first voltage on the first circuit node through the first capacitor based on the positive local oscillator signal and a bias voltage different from the power supply voltage.

[0091] According to another embodiment, the second level shifting circuit may optionally include: a fourth inverter having an output coupled to the second bias path; a second capacitor disposed on the second bias path between the fourth inverter and the second circuit node, wherein the fourth inverter is configured to drive a second voltage on the second circuit node through the second capacitor based on the negative local oscillator signal and the bias voltage; and a third capacitor coupled between the power supply voltage and the cascode node.

[0092] According to one embodiment, an amplifier circuit is configured to output a radio frequency signal, the amplifier circuit comprising: a first common-source stage, the first common-source stage including a first transistor and a second transistor, wherein the gate terminal of the first transistor receives a positive local oscillator signal, and the gate terminal of the second transistor receives a negative local oscillator signal; a common-source cascode stage, wherein the common-source cascode stage includes a third transistor and a fourth transistor, the first transistor being series coupled between the third transistor and a power supply input of the amplifier circuit, the second transistor being series coupled between the fourth transistor and the power supply input, and the gate terminals of the third transistor and the fourth transistor being coupled to a common-source cascode node; a first circuit configured to generate at least a portion of a voltage at the common-source cascode node based on the positive local oscillator signal; and a second circuit configured to generate at least a portion of the voltage at the common-source cascode node based on the negative local oscillator signal.

[0093] According to another embodiment, the amplifier circuit may optionally include a charge pump coupled between the power supply input and the cascode node, wherein the charge pump is configured to generate at least a portion of the voltage at the cascode node.

[0094] According to another embodiment, the charge pump may optionally include: a first inverter having a first power terminal coupled to the power input, a second power terminal coupled to the cascode node, an input communicatively coupled to the first circuit, and an output communicatively coupled to the second circuit; and a capacitor coupled between the power input and the cascode node.

[0095] According to another embodiment, the charge pump may also optionally include a second inverter having a third power terminal coupled to the power input, a fourth power terminal coupled to the cascode node, an input communicatively coupled to the output of the second circuit and the first inverter, and an output communicatively coupled to the input of the first circuit and the first inverter.

[0096] According to another embodiment, the first circuit may optionally include: a first inverter having a first power supply terminal for receiving a bias voltage, a second power supply terminal for receiving a reference voltage, and an input for receiving the positive local oscillator signal; and a first capacitor connected in series between the output of the first inverter and the charge pump.

[0097] According to another embodiment, the second circuit may optionally include: a second inverter having a third power supply terminal for receiving the bias voltage, a fourth power supply terminal for receiving the reference voltage, and an input for receiving the negative local oscillator signal; and a second capacitor connected in series between the output of the second inverter and the charge pump, wherein the bias voltage is equal to the power supply voltage received at the power supply input minus the voltage at the cascode node.

[0098] According to another embodiment, the amplifier circuit may optionally include: an additional cascode stage, wherein the cascode stage is coupled between the additional cascode stage and the cascode stage; an additional cascode stage, wherein the additional cascode stage is coupled between the additional cascode stage and a reference voltage; and an output terminal configured to output the radio frequency signal, wherein the output terminal is coupled between the cascode stage and the additional cascode stage.

[0099] According to one embodiment, a polar coordinate power amplifier includes: a first transistor having a gate terminal for receiving a positive clock signal; a second transistor having a gate terminal for receiving a negative clock signal, the first transistor and the second transistor having source terminals coupled to a power supply input; a third transistor having a source terminal coupled to a drain terminal of the first transistor; a fourth transistor having a source terminal coupled to a drain terminal of the second transistor, the third transistor and the fourth transistor having gate terminals coupled to a circuit node; a first capacitor connected in series between the power supply input and the circuit node; a first inverter having a power terminal coupled between the power supply input and the circuit node; a second inverter having a power terminal coupled between the power supply input and the circuit node; a third inverter having an input for receiving the positive clock signal and an output communicatively coupled to the input of the first inverter and the output of the second inverter; and a fourth inverter having an input for receiving the negative clock signal and an output communicatively coupled to the input of the second inverter and the output of the first inverter.

[0100] According to another embodiment, the polar coordinate power amplifier optionally includes: a second capacitor coupled in series between the output of the third inverter and the input of the first inverter; a third capacitor coupled in series between the output of the fourth inverter and the input of the second inverter, wherein the third inverter and the fourth inverter are powered by a bias voltage different from the power supply voltage received at the power supply input; a fifth transistor having a drain terminal coupled to the drain terminal of the third transistor; a sixth transistor having a drain terminal coupled to the drain terminal of the fourth transistor; a seventh transistor having a drain terminal coupled to the source terminal of the fifth transistor and a source terminal for receiving a reference voltage; an eighth transistor having a drain terminal coupled to the source terminal of the sixth transistor and a source terminal for receiving the reference voltage; a fourth capacitor coupling the gate terminals of the seventh transistor and the eighth transistor to the reference voltage; and an RF output between the drain terminals of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

[0101] The foregoing is merely illustrative and various modifications can be made to the described implementation scheme. The foregoing implementation scheme can be implemented individually or in any combination.

Claims

1. An amplifier circuit configured to output a radio frequency signal, the amplifier circuit comprising: A first common-source stage is configured to receive a power supply voltage for transmitting amplitude modulation of the radio frequency signal; A first cascode stage, the first cascode stage including a first transistor and a second transistor having gate terminals coupled to a cascode node; The second cascode stage, wherein the first cascode stage is coupled between the second cascode stage and the first cascode stage; A second common-source stage, the second common-source stage being coupled to a reference voltage, wherein the second common-source cascode stage is coupled between the second common-source stage and the first common-source cascode stage; as well as A cross-coupled inverter having a power input coupled between the power supply voltage and the common source cascode node.

2. The amplifier circuit according to claim 1, further comprising: A capacitor, which is coupled in series between the power supply voltage and the common source cascode node.

3. The amplifier circuit according to claim 2, further comprising: Radio frequency output, the radio frequency output being configured to transmit the radio frequency signal, wherein the radio frequency output is coupled between the first cascode stage and the second cascode stage.

4. The amplifier circuit of claim 1, wherein the first common-source stage comprises a third transistor and a fourth transistor, the third transistor being series coupled between the power supply voltage and the first transistor, the fourth transistor being series coupled between the power supply voltage and the second transistor, the gate terminal of the third transistor being configured to receive a positive local oscillator signal, the gate terminal of the fourth transistor being configured to receive a negative local oscillator signal, and the positive local oscillator signal and the negative local oscillator signal being used for phase modulation of the radio frequency signal.

5. The amplifier circuit of claim 4, wherein the second cascode stage comprises a fifth transistor and a sixth transistor, the first transistor is coupled in series between the fifth transistor and the third transistor, the second transistor is coupled in series between the sixth transistor and the fourth transistor, the gate terminals of the fifth transistor and the sixth transistor are coupled to a circuit node, and are capacitively coupled between the circuit node and the reference voltage.

6. The amplifier circuit of claim 5, wherein the second cascode stage comprises a seventh transistor and an eighth transistor, the seventh transistor being coupled in series between the fifth transistor and the reference voltage, the eighth transistor being coupled in series between the sixth transistor and the reference voltage, the gate terminal of the seventh transistor being configured to receive the positive local oscillator signal, and the gate terminal of the eighth transistor being configured to receive the negative local oscillator signal.

7. The amplifier circuit of claim 6, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are p-type transistors, and the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are n-type transistors.

8. The amplifier circuit of claim 4, wherein the cross-coupled converter comprises: A first inverter, the first inverter having a first power input coupled between the power supply voltage and the common source cascode node; as well as A second inverter has a second power input coupled between the power supply voltage and the cascode node, wherein the output of the first inverter is communicatively coupled to the input of the second inverter, and wherein the output of the second inverter is communicatively coupled to the input of the first inverter.

9. The amplifier circuit according to claim 8, further comprising: A first level shifting circuit is communicatively coupled to the input of the first inverter via a first bias path, and the output of the second inverter is coupled to a first circuit node on the first bias path. as well as A second level shift circuit is communicatively coupled to the input of the second inverter via a second bias path, and the output of the first inverter is coupled to a second circuit node on the second bias path.

10. The amplifier circuit according to claim 9, wherein the first level shifting circuit comprises: A third inverter, the third inverter having an output coupled to the first bias path; as well as A first capacitor is disposed on the first bias path between the third inverter and the first circuit node, wherein the third inverter is configured to drive a first voltage on the first circuit node through the first capacitor based on the positive local oscillator signal and a bias voltage different from the power supply voltage.

11. The amplifier circuit according to claim 10, wherein the second level shifting circuit comprises: A fourth inverter, the fourth inverter having an output coupled to the second bias path; A second capacitor is disposed on the second bias path between the fourth inverter and the second circuit node, wherein the fourth inverter is configured to drive a second voltage on the second circuit node through the second capacitor based on the negative local oscillator signal and the bias voltage. as well as A third capacitor is coupled between the power supply voltage and the common source / common gate node.

12. An amplifier circuit configured to output a radio frequency signal, the amplifier circuit comprising: The first common-source stage includes a first transistor and a second transistor, wherein the gate terminal of the first transistor receives a positive local oscillator signal, and the gate terminal of the second transistor receives a negative local oscillator signal. A common-source, common-gate stage, wherein the common-source, common-gate stage includes a third transistor and a fourth transistor, the first transistor being coupled in series between the third transistor and the power input of the amplifier circuit, the second transistor being coupled in series between the fourth transistor and the power input, and the gate terminals of the third transistor and the fourth transistor being coupled to a common-source, common-gate node; A first circuit is configured to generate at least a portion of the voltage at the common source cascode node based on the positive local oscillator signal. as well as A second circuit is configured to generate at least a portion of the voltage at the common source cascode node based on the negative local oscillator signal.

13. The amplifier circuit according to claim 12, further comprising: A charge pump coupled between the power input and the cascode node, wherein the charge pump is configured to generate at least a portion of the voltage at the cascode node.

14. The amplifier circuit of claim 13, wherein the charge pump comprises: A first inverter has a first power terminal coupled to the power input, a second power terminal coupled to the common source cascode node, an input communicatively coupled to the first circuit, and an output communicatively coupled to the second circuit. as well as A capacitor is coupled between the power input and the common source / common gate node.

15. The amplifier circuit of claim 14, wherein the charge pump further comprises: The second inverter has a third power terminal coupled to the power input, a fourth power terminal coupled to the common source cascode node, an input communicatively coupled to the output of the second circuit and the first inverter, and an output communicatively coupled to the input of the first circuit and the first inverter.

16. The amplifier circuit of claim 13, wherein the first circuit comprises: A first inverter, the first inverter having a first power supply terminal for receiving a bias voltage, a second power supply terminal for receiving a reference voltage, and an input for receiving the positive local oscillator signal; as well as A first capacitor is coupled in series between the output of the first inverter and the charge pump.

17. The amplifier circuit of claim 16, wherein the second circuit comprises: The second inverter has a third power supply terminal for receiving the bias voltage, a fourth power supply terminal for receiving the reference voltage, and an input for receiving the negative local oscillator signal. as well as A second capacitor, connected in series between the output of the second inverter and the charge pump, wherein the bias voltage is equal to the power supply voltage received at the power supply input minus the voltage at the cascode node.

18. The amplifier circuit according to claim 12, further comprising: An additional cascode stage, wherein the cascode stage is coupled between the additional cascode stage and the cascode stage; An additional common-source stage is coupled between the additional common-source cascode stage and the reference voltage. as well as An output terminal configured to output the radio frequency signal, wherein the output terminal is coupled between the cascode stage and the additional cascode stage.

19. A polar coordinate power amplifier, the polar coordinate power amplifier comprising: A first transistor having a gate terminal for receiving a positive clock signal; The second transistor has a gate terminal for receiving a negative clock signal, and the first transistor and the second transistor have source terminals coupled to a power supply input; A third transistor having a source terminal coupled to the drain terminal of the first transistor; A fourth transistor having a source terminal coupled to the drain terminal of the second transistor, and the third and fourth transistors having gate terminals coupled to a circuit node; A first capacitor is coupled in series between the power input and the circuit node; A first inverter, the first inverter having a power terminal coupled between the power input and the circuit node; A second inverter, the second inverter having a power terminal coupled between the power input and the circuit node; A third inverter has an input that receives the positive clock signal and an output that is communicatively coupled to the input of the first inverter and the output of the second inverter; as well as A fourth inverter has an input that receives the negative clock signal and an output that is communicatively coupled to the input of the second inverter and the output of the first inverter.

20. The polar coordinate power amplifier according to claim 19, further comprising: A second capacitor is coupled in series between the output of the third inverter and the input of the first inverter; A third capacitor is coupled in series between the output of the fourth inverter and the input of the second inverter, wherein the third inverter and the fourth inverter are powered by a bias voltage different from the power supply voltage received at the power supply input. A fifth transistor having a drain terminal coupled to the drain terminal of the third transistor; A sixth transistor having a drain terminal coupled to the drain terminal of the fourth transistor; A seventh transistor having a drain terminal coupled to the source terminal of the fifth transistor and a source terminal for receiving a reference voltage; The eighth transistor has a drain terminal coupled to the source terminal of the sixth transistor and a source terminal for receiving the reference voltage; A fourth capacitor couples the gate terminals of the seventh and eighth transistors to the reference voltage; as well as A radio frequency output is provided between the drain terminals of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

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