A 3.3V powered RS485 interface circuit

Abstract

The application discloses a 3.3V power supply RS485 interface circuit, and relates to the field of RS485 bus interface circuit driving, comprising: a high-level short-circuit protection unit for outputting a constant limited current when short-circuiting to ground; a low-level short-circuit protection unit for outputting a constant limited current when short-circuiting to a power supply. The output port of an output stage unit is connected with RS485 differential bus pins, and can switch output signals through conduction and shutdown according to a driving signal while bearing bus high voltage or negative voltage. A dynamic bias voltage node is formed inside the output stage unit, so that the substrate of the first PMOS tube is always connected with a higher potential, and the body diode is prevented from being turned on. The application adopts a high-voltage PMOS single tube and a high-voltage NMOS series diode structure, simultaneously meeting the requirements of bus-7V to +12V voltage resistance and RS485 protocol requirements under 3.3V; and the short-circuit current can be kept constant at a threshold order when short-circuiting to ground and short-circuiting to a power supply, so that constant current protection is realized.

Description

Technical Field

[0001] This application relates to the field of RS485 bus interface circuit drivers, and in particular to a 3.3V powered RS485 interface circuit. Background Technology

[0002] To address the potential difference issue in long-distance communication in industrial settings, according to the RS485 standard, the normal common-mode input voltage range of its transceivers is -7V to +12V. To prevent large current and breakdown issues when the bus interface is connected to voltages exceeding the power supply voltage or negative voltage, 5V RS485 drivers typically employ a MOSFET and diode series configuration. Figure 5 As shown, the RS485 driver with a 3.3V power supply cannot meet the RS485 standard requirements due to the limitations of differential swing and power supply voltage. Therefore, only a stacked MOS structure or a single-transistor MOS driver structure can be used.

[0003] In chip fabrication, while SOI technology simplifies circuit design and effectively isolates current leakage through the insulating layer, high-voltage BCD technology offers a more significant cost advantage. Because BCD technology uses well isolation, the substrate is typically P-type grounded. When high or negative voltage is applied to the device ports, leakage current or parasitic device conduction may occur, easily leading to circuit failure and burnout. Furthermore, RS485 circuits in industrial applications may experience problems such as A / B line short circuits or short circuits to power or ground, causing chip damage. Therefore, dedicated short-circuit protection functions must be designed. Traditional design methods, such as... Figure 6 As shown, PMOS and NMOS are designed with two groups of short-circuit current protection, m:n. When a short-circuit fault occurs, n groups of drive transistors with a fixed ratio are turned off to limit the current. Therefore, the traditional method generates a large transient current change on the bus near the short-circuit detection threshold. Summary of the Invention

[0004] The purpose of this application is to provide a 3.3V powered RS485 interface circuit that can simultaneously meet the bus voltage withstand of -7V to +12V and the RS485 protocol requirements at 3.3V. It can keep the short-circuit current constant at the threshold level when short-circuited to ground or to the power supply, thus achieving constant current protection.

[0005] To achieve the above objectives, this application provides the following solution: This application provides a 3.3V powered RS485 interface circuit, comprising: an output stage unit, a high-level short-circuit protection unit, and a low-level short-circuit protection unit; the high-level short-circuit protection unit and the low-level short-circuit protection unit are respectively connected to the first input port and the second input port of the output stage unit, and the output port of the output stage unit is connected to an external RS485 differential bus pin; the high-level short-circuit protection unit is used to constantly limit the current and automatically adjust the drive signal when the output is short-circuited to ground; the low-level short-circuit protection unit is used to constantly limit the current and automatically adjust the drive signal when the output is short-circuited to the power supply. The output stage unit adjusts the drive signal; it is used to output a signal to the RS485 differential bus pin by switching between on and off according to the drive signal provided by the high-level short-circuit protection unit or the low-level short-circuit protection unit while withstanding the high voltage or negative voltage of the RS485 bus; wherein, the output stage unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a first transistor, a first resistor, and a second resistor; the gate (G) of the first PMOS transistor is connected to the output terminal of the high-level short-circuit protection unit and the drain (D) of the fourth PMOS transistor, respectively, and the first PMOS transistor's... The source (S) terminal of the first PMOS transistor is connected to the external VCC pin. The base (B) of the first PMOS transistor is connected to the base (B) of the fourth PMOS transistor, the source (S) of the fourth PMOS transistor, the base (B) of the second PMOS transistor, the source (S) of the second PMOS transistor, the base (B) of the third PMOS transistor, and the source (S) of the third PMOS transistor, forming a dynamic bias voltage node. The drain (D) of the first PMOS transistor is connected to the drain (D) of the third PMOS transistor, the emitter of the first PMOS transistor, and the external RS485 differential bus pin. The drain (D) of the second PMOS transistor is connected to the external VCC pin, and the gate (G) of the second PMOS transistor is connected to one end of the first resistor. The first resistor is connected to an external RS485 differential bus pin; the gate (G) of the third PMOS transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the external VCC terminal; the gate (G) of the fourth PMOS transistor is connected to the external Vdrive_c terminal; the base, collector, and drain (D) of the first transistor are all connected to the external OUT_fbn terminal; the gate (G) of the first NMOS transistor is connected to the output terminal of the low-level short-circuit protection unit, and the base (B) and source (S) of the first NMOS transistor are both connected to the external VSS terminal.

[0006] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application designs an output stage unit, a high-level short-circuit protection unit, and a low-level short-circuit protection unit. The high-level short-circuit protection unit is used to maintain a constant current limit when the output is short-circuited to ground; the low-level short-circuit protection unit is used to maintain a constant current limit when the output is short-circuited to the power supply. The output port of the output stage unit is connected to the RS485 differential bus pin, and can withstand high or negative bus voltage while switching the output signal by turning it on and off according to the drive signal. A dynamic bias voltage node is formed inside the output stage unit, so that the substrate of the first PMOS transistor is always connected to a higher potential, avoiding the body diode from conducting. This application adopts a high-voltage PMOS single transistor and a high-voltage NMOS series diode structure, which simultaneously meets the bus voltage withstand of -7V to +12V and the RS485 protocol requirements at 3.3V; and can keep the short-circuit current constant at the threshold level when short-circuited to ground and short-circuited to the power supply, thus achieving constant current protection. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the structural connection of a 3.3V powered RS485 interface circuit provided in an embodiment of this application.

[0009] Figure 2 The circuit diagram of the output stage unit provided in the embodiments of this application.

[0010] Figure 3 A circuit diagram of a high-level short-circuit protection unit provided in an embodiment of this application.

[0011] Figure 4 A circuit diagram of a low-level short-circuit protection unit provided in an embodiment of this application.

[0012] Figure 5 The conventional driver output stage structure provided in the embodiments of this application.

[0013] Figure 6 The present application provides a conventional driver output short-circuit protection structure.

[0014] Figure 7 This is an internal structure diagram of a computer system provided in an embodiment of this application.

[0015] Figure label: 1. High-level short-circuit protection unit; 2. Low-level short-circuit protection unit; 3. Output stage unit; M1, first PMOS transistor; M2, second PMOS transistor; M3, third PMOS transistor; M4, fourth PMOS transistor; M5, first NMOS transistor; M6, sixth NMOS transistor; M7, fourth NMOS transistor; M8, fifth NMOS transistor; M9, sixth PMOS transistor; M10, seventh PMOS transistor; M11, second NMOS transistor; M12, third NMOS transistor; M13, fifth PMOS transistor; M14, tenth PMOS transistor; M15, eleventh PMOS transistor M16, twelfth PMOS transistor; M17, eighth PMOS transistor; M18, ninth PMOS transistor; M19, seventh NMOS transistor; M20, eighth NMOS transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; Q1, first transistor; Q2, second transistor; Q3, third transistor; Q4, fourth transistor; NOR, NOR gate; OR, OR gate. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] Example 1, as Figures 1-4 As shown, this embodiment provides a 3.3V powered RS485 interface circuit, which includes: an output stage unit 3, a high-level short-circuit protection unit 1, and a low-level short-circuit protection unit 2.

[0019] The high-level short-circuit protection unit 1 and the low-level short-circuit protection unit 2 are respectively connected to the first input port and the second input port of the output stage unit 3. The output port of the output stage unit 3 is connected to an external RS485 differential bus pin. The high-level short-circuit protection unit 1 is used to constantly limit the current and automatically adjust the drive signal when the output is short-circuited to ground. The low-level short-circuit protection unit 2 is used to constantly limit the current and automatically adjust the drive signal when the output is short-circuited to the power supply. The output stage unit 3 is used to output the signal to the RS485 differential bus pin by switching between conduction and shutdown according to the drive signal provided by the high-level short-circuit protection unit 1 or the low-level short-circuit protection unit 2 while withstanding the high voltage or negative voltage of the RS485 bus.

[0020] The output stage unit 3 includes: a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a first NMOS transistor M5, a first transistor Q1, a first resistor R1, and a second resistor R2.

[0021] The gate (G) of the first PMOS transistor M1 is connected to the output terminal of the high-level short-circuit protection unit 1 and the drain (D) of the fourth PMOS transistor M4, respectively. The source (S) of the first PMOS transistor M1 is connected to the external VCC pin. The base (B) of the first PMOS transistor M1 is connected to the base (B) and source (S) of the fourth PMOS transistor M4, the base (B) and source (S) of the second PMOS transistor M2, the base (B) and source (S) of the third PMOS transistor M3, respectively, forming a dynamic bias voltage node. The drain (D) of the first PMOS transistor M1 is connected to the drain (D) of the third PMOS transistor M3, the emitter of the first transistor Q1, and the external RS485 differential bus pin, respectively.

[0022] The drain of the second PMOS transistor M2 is connected to the external VCC terminal, the gate of the second PMOS transistor M2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the external RS485 differential bus pin.

[0023] The gate of the third PMOS transistor M3 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the external VCC terminal.

[0024] The gate (G) of the fourth PMOS transistor M4 is connected to the external Vdrive_c terminal.

[0025] The base of the first transistor Q1, the collector of the first transistor Q1, and the drain of the first NMOS transistor M5 are all connected to the external OUT_fbn terminal.

[0026] The gate (G) of the first NMOS transistor M5 is connected to the output terminal of the low-level short-circuit protection unit 2, and both the base (B) and source (S) of the first NMOS transistor M5 are connected to the external VSS terminal.

[0027] In practical applications, such as Figure 2 The first PMOS transistor M1 shown is the output stage PMOS transistor, the first transistor Q1 is a transistor connected in the form of a diode, and the first NMOS transistor M5 is the output stage NMOS transistor. This structure is a single-sided stacked diode structure.

[0028] Meanwhile, to address the large current flowing into the substrate from the PMOS body diode when the OUT output voltage is higher than the power supply voltage, a dynamic bias voltage node (VB) for the high-voltage N-well of the PMOS transistor substrate is biased. When the OUT voltage is lower than the power supply voltage, the second PMOS transistor M2 provides a dynamic bias voltage node (VB) close to the VCC voltage value; when the OUT voltage is higher than VCC, the third PMOS transistor M3 provides a dynamic bias voltage node (VB) close to the OUT voltage value. Simultaneously, the OUT voltage is transmitted to the gate terminal of the first PMOS transistor M1 through the fourth PMOS transistor M4, providing a gate voltage close to the OUT voltage value to turn off the first PMOS transistor M1. When a negative voltage appears at the OUT terminal, since the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, and the fourth PMOS transistor M4 are all high-voltage transistors, their gate terminals and source / drain terminals can withstand high voltage.

[0029] In a single-sided stacked diode, when the OUT terminal is under forward high voltage, the voltage passes through the first transistor Q1 to the drain (D) of the first NMOS transistor M5. The first NMOS transistor M5 is a high voltage transistor, and its drain withstand voltage can ensure that it will not be broken down. When the OUT terminal is under negative voltage, the voltage passes through the first transistor Q1 under reverse bias. The negative voltage will not cause the body diode of the first NMOS transistor M5 to conduct.

[0030] The structure is designed for a 3.3V power supply with a maximum power supply deviation of 10%. When VCC is 3V, the maximum output differential voltage is (VCC-VD), which is approximately 2.4V. This fully meets the protocol requirement of a minimum differential voltage of 1.5V when the load is 54Ω, and the design margin is also relatively large.

[0031] Furthermore, the high-level short-circuit protection unit 1 specifically includes: The fifth PMOS transistor M13, the sixth PMOS transistor M9, the seventh PMOS transistor M10, the second NMOS transistor M11, the third NMOS transistor M12, the fourth NMOS transistor M7, the fifth NMOS transistor M8, the sixth NMOS transistor M6, the second transistor Q2, the NOR gate, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6.

[0032] The gate (G) of the fifth PMOS transistor M13 is connected to the external Vdrive_p terminal; the source (S) of the fifth PMOS transistor M13 is connected to the source (S) of the sixth PMOS transistor M9, the base (B) of the sixth PMOS transistor M9, and one end of the third resistor R3; the base (B) of the fifth PMOS transistor M13 is connected to the dynamic bias voltage node; the drain (D) of the fifth PMOS transistor M13 is connected to the external RS485 differential bus pin; and the other end of the third resistor R3 is connected to the external VCC terminal.

[0033] The gate (G) of the sixth PMOS transistor M9 is connected to one end of the fourth resistor R4 and the drain (D) of the second NMOS transistor M11, respectively; the drain (D) of the sixth PMOS transistor M9 is connected to the other end of the fourth resistor R4 and the gate (G) of the seventh PMOS transistor M10, respectively.

[0034] The source (S) and base (B) of the seventh PMOS transistor M10 are both connected to the external VCC terminal; the drain (D) of the seventh PMOS transistor M10 is connected to the drain of the third NMOS transistor M12, the first input terminal of the NOR gate, and the gate (G) of the sixth NMOS transistor M6.

[0035] The gate (G) of the second NMOS transistor M11 is connected to the gate (G) of the third NMOS transistor M12 and the external Vbias1 terminal, respectively; the source (S) and base (B) of the second NMOS transistor M11 are both connected to the external VSS terminal.

[0036] The source (S) and base (B) of the third NMOS transistor M12 are both connected to the external VSS terminal.

[0037] The second input terminal of the NOR gate is connected to the external Vdrive_c1 terminal, and the output terminal of the NOR gate is connected to the gate (G) terminal of the fourth NMOS transistor M7.

[0038] The drain of the fourth NMOS transistor M7 is connected to the base of the second transistor Q2, the collector of the second transistor Q2, the drain of the fifth NMOS transistor M8, and the first input port of the output stage unit 3, respectively; the source (S) and the base (B) of the fourth NMOS transistor M7 are both connected to the external VSS terminal.

[0039] The gate (G) of the fifth NMOS transistor M8 is connected to the external Vdrive_c1 terminal; both the source (S) and the base (B) of the fifth NMOS transistor M8 are connected to one end of the sixth resistor R6; the other end of the sixth resistor R6 is connected to the external VSS terminal.

[0040] The drain (D) of the sixth NMOS transistor M6 is connected to one end of the fifth resistor R5; the source (S) and base (B) of the sixth NMOS transistor M6 are both connected to the emitter of the second transistor Q2; the other end of the fifth resistor R5 is connected to the external VCC terminal.

[0041] In practical applications, such as Figure 3 As shown, the fourth NMOS transistor M7, the fifth NMOS transistor M8, the sixth NMOS transistor M6, and the second transistor Q2 form the pre-stage drive circuit for the output stage PMOS transistor.

[0042] The Vdrive_p signal drives the gate signal of the output stage PMOS transistors. During normal operation, the gate (G) voltage of the seventh PMOS transistor M10 is (VCC-VDSM), which is in the off state. The gate voltage of the sixth NMOS transistor M6 is 0V, which is also off. Vdrive_c1 is the data input. When Vdrive_c1 is high, the fourth NMOS transistor M7 and the fifth NMOS transistor M8 are simultaneously turned on, pulling the gates of the output stage PMOS transistors to 0V, resulting in a high-level OUT output. When Vdrive_c1 is low, both the fourth NMOS transistor M7 and the fifth NMOS transistor M8 are off. Figure 3 When the Vdrive_c signal is 0V, the fourth PMOS transistor M4 is turned on, and the output stage PMOS transistors are turned off. When a short circuit event occurs at the OUT terminal, Vdrive_p is at a low level of 0V, the fifth PMOS transistor M13 is turned on, and the short circuit voltage at the OUT terminal pulls down the gate voltage of the seventh PMOS transistor M10, causing the seventh PMOS transistor M10 to turn on and enter the saturation region. As a common-source amplifier, it adjusts the gate voltage of the sixth NMOS transistor M6. When the gate voltage of the sixth NMOS transistor M6 rises to a certain value, that is, when the short circuit voltage at the OUT terminal drops to the short circuit detection threshold, the fourth NMOS transistor M7 is turned off. At this time, when the voltage at the OUT terminal continues to decrease, the gate voltage of the sixth NMOS transistor M6 rises, and Vdrive_p follows the rise of the source voltage of the sixth NMOS transistor M6, stabilizing the output short circuit current of the output stage PMOS transistors at a constant value.

[0043] Furthermore, the low-level short-circuit protection unit 2 specifically includes: The PMOS transistors are: M17 (eighth), M18 (ninth), M14 (tenth), M15 (eleventh), M16 (twelfth), M19 (seventh), M20 (eighth), Q3 (third), Q4 (fourth), OR gate, R7 (seventh), R8 (eighth), R9 (ninth), R10 (tenth), and R11 (eleventh).

[0044] The gate (G) of the seventh NMOS transistor M19 is connected to the external Vdrive_n terminal; the drain (D) of the seventh NMOS transistor M19 is connected to the external OUT_fbn terminal; the source (S) and base (B) of the seventh NMOS transistor M19 are both connected to the emitter of the third transistor Q3 and one end of the ninth resistor R9; the other end of the ninth resistor R9 is connected to the external VSS terminal.

[0045] The gate (G) of the eighth PMOS transistor M17 is connected to the gate (G) of the ninth PMOS transistor M18 and the external Vbias2 terminal, respectively; the source (S) and base (B) of the eighth PMOS transistor M17 are both connected to the external VCC terminal; the drain (D) of the eighth PMOS transistor M17 is connected to the base of the third transistor Q3 and one end of the seventh resistor R7, respectively; the other end of the seventh resistor R7 is connected to the collector of the third transistor Q3 and one end of the eighth resistor R8, respectively; the other end of the eighth resistor R8 is connected to the base of the fourth transistor Q4.

[0046] The source (S) and base (B) of the ninth PMOS transistor M18 are both connected to the external VCC terminal; the drain (D) of the ninth PMOS transistor M18 is connected to the collector of the fourth transistor Q4, the first input terminal of the OR gate, and the gate (G) of the twelfth PMOS transistor M16; the emitter of the fourth transistor Q4 is connected to the external VSS terminal.

[0047] The second input terminal of the OR gate is connected to the external Vdrive_c2 terminal; the output terminal of the OR gate is connected to the gate (G) terminal of the tenth PMOS transistor M14.

[0048] The source (S) and base (B) of the tenth PMOS transistor M14 are both connected to the external VCC terminal; the drain (D) of the tenth PMOS transistor M14 is connected to the drain of the eleventh PMOS transistor M15, the source (S) of the twelfth PMOS transistor, the base (B) of the twelfth PMOS transistor, the drain of the eighth NMOS transistor M20, and the external Vdrive_n terminal.

[0049] The gate (G) of the eleventh PMOS transistor M15 is connected to the external Vdrive_c2 terminal; the source (S) and the base (B) of the eleventh PMOS transistor M15 are both connected to one end of the tenth resistor R10; the other end of the tenth resistor R10 is connected to the external VCC terminal.

[0050] The drain of the twelfth PMOS transistor M16 is connected to one end of the eleventh resistor R11; the other end of the eleventh resistor R11 is connected to the external VCC terminal.

[0051] The gate (G) of the eighth NMOS transistor M20 is connected to the external Vdrive_c2 terminal; the source (S) and base (B) of the eighth NMOS transistor M20 are both connected to the external VSS terminal.

[0052] Furthermore, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the first NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor are all high-voltage MOS transistors.

[0053] Furthermore, the voltage of the high-voltage MOSFET is greater than 5V.

[0054] Furthermore, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the sixth NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the eighth NMOS transistor are all standard MOS transistors.

[0055] Furthermore, the standard MOSFET is 5V.

[0056] Furthermore, the output stage unit 3 meets the withstand voltage requirements of RS485 bus -7V to +12V.

[0057] Furthermore, the VCC is powered by 3.3V, with a maximum power supply deviation of ±10%.

[0058] Furthermore, when the supply voltage of VCC is 3V, the maximum value of the output differential voltage is 2.4V.

[0059] In practical applications, such as Figure 4As shown, the tenth PMOS transistor M14, the eleventh PMOS transistor M15, the twelfth PMOS transistor M16, and the eighth NMOS transistor M20 form the pre-stage driver circuit for the output stage NMOS transistors. The Vdrive_n signal drives the gate of the output stage NMOS transistors. During normal operation, Q4 is off, the gate of the twelfth PMOS transistor M16 is off at the VCC voltage value, and Vdrive_c2 is the data input. When Vdrive_c2 is high, the tenth PMOS transistors M14 and M15 are off, the eighth NMOS transistor M20 is on, and Vdrive_n outputs a low level, driving the output stage NMOS transistors to be off. When Vdrive_c2 is low, the tenth PMOS transistors M14 and M15 are on, the eighth NMOS transistor M20 is off, Vdrive_n outputs a high level, driving the output stage NMOS transistors to be on, and the OUT terminal outputs a low level. When a short circuit occurs at the OUT terminal, Vdrive_n is at a high level, the seventh NMOS transistor M19 is turned on, and the output feedback voltage OUT_fbn pulls up the collector voltage of the third transistor Q3, turning on the fourth transistor Q4. As a common-emitter amplifier, Q4 adjusts the gate voltage of the twelfth PMOS transistor M16. When the gate voltage of the twelfth PMOS transistor M16 drops to a certain value, i.e., when the OUT short-circuit voltage is high enough to detect the short-circuit threshold, the tenth PMOS transistor M14 is turned off. At this time, when the voltage at the OUT terminal continues to rise, the gate voltage of the twelfth PMOS transistor M16 drops, and Vdrive_n follows the drop of the source voltage of the twelfth PMOS transistor M16, stabilizing the short-circuit current of the output NMOS at a constant value.

[0060] The technical effects of this application are as follows: This application simultaneously solves two technical problems: bus withstand voltage and short-circuit current protection. Specifically, the RS485 driver output stage structure uses a high-voltage PMOS single-transistor to drive the output high level and a high-voltage NMOS series diode to output the low level, meeting the bus withstand voltage requirements from -7V to +12V. Simultaneously, the differential voltage in the 3.3V voltage range is greater than 1.5V (load resistance 54Ω), meeting the RS485 protocol standard. Furthermore, this application also includes high-level and low-level short-circuit protection units. By detecting the voltage difference between the output voltage and the power supply or between the output voltage and ground, the gate voltages of the output stage PMOS and NMOS are adjusted to keep the short-circuit current constant at the detection threshold level, achieving the purpose of short-circuit protection.

[0061] In summary, this application adopts a high-voltage PMOS single-transistor and a high-voltage NMOS series diode structure, which simultaneously meets the bus voltage withstand of -7V to +12V and the RS485 protocol requirements at 3.3V; and can keep the short-circuit current constant at the threshold level when short-circuited to ground and short-circuited to the power supply, thus achieving constant current protection.

[0062] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0063] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A 3.3V powered RS485 interface circuit, characterized in that, The 3.3V powered RS485 interface circuit includes: an output stage unit, a high-level short-circuit protection unit, and a low-level short-circuit protection unit; The high-level short-circuit protection unit and the low-level short-circuit protection unit are respectively connected to the first input port and the second input port of the output stage unit. The output port of the output stage unit is connected to an external RS485 differential bus pin. The high-level short-circuit protection unit is used to constantly limit the current and automatically adjust the drive signal when the output is short-circuited to ground. The low-level short-circuit protection unit is used to constantly limit the current and automatically adjust the drive signal when the output is short-circuited to the power supply. The output stage unit is used to output a signal to the RS485 differential bus pin by switching between on and off according to the drive signal provided by the high-level short-circuit protection unit or the low-level short-circuit protection unit while withstanding the high voltage or negative voltage of the RS485 bus. The output stage unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a first transistor, a first resistor, and a second resistor; The gate (G) of the first PMOS transistor is connected to the output terminal of the high-level short-circuit protection unit and the drain (D) of the fourth PMOS transistor. The source (S) of the first PMOS transistor is connected to the external VCC pin. The base (B) of the first PMOS transistor is connected to the base (B) of the fourth PMOS transistor, the source (S) of the fourth PMOS transistor, the base (B) of the second PMOS transistor, the source (S) of the second PMOS transistor, the base (B) of the third PMOS transistor, and the source (S) of the third PMOS transistor, forming a dynamic bias voltage node. The drain (D) of the first PMOS transistor is connected to the drain (D) of the third PMOS transistor, the emitter of the first transistor, and the external RS485 differential bus pin. The drain of the second PMOS transistor is connected to the external VCC terminal, the gate of the second PMOS transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the external RS485 differential bus pin. The gate of the third PMOS transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the external VCC terminal. The gate of the fourth PMOS transistor is connected to the external Vdrive_c terminal; The base of the first transistor, the collector of the first transistor, and the drain of the first NMOS transistor are all connected to the external OUT_fbn terminal; The gate (G) of the first NMOS transistor is connected to the output terminal of the low-level short-circuit protection unit, and both the base (B) and source (S) of the first NMOS transistor are connected to the external VSS terminal.

2. The 3.3V powered RS485 interface circuit according to claim 1, characterized in that, The high-level short-circuit protection unit specifically includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a second transistor, a NOR gate, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; The gate (G) of the fifth PMOS transistor is connected to the external Vdrive_p terminal; the source (S) of the fifth PMOS transistor is connected to the source (S) of the sixth PMOS transistor, the base (B) of the sixth PMOS transistor, and one end of the third resistor; the base (B) of the fifth PMOS transistor is connected to the dynamic bias voltage node; the drain (D) of the fifth PMOS transistor is connected to the external RS485 differential bus pin; the other end of the third resistor is connected to the external VCC terminal. The gate (G) of the sixth PMOS transistor is connected to one end of the fourth resistor and the drain (D) of the second NMOS transistor; the drain (D) of the sixth PMOS transistor is connected to the other end of the fourth resistor and the gate (G) of the seventh PMOS transistor. The source (S) and base (B) of the seventh PMOS transistor are both connected to the external VCC terminal; the drain (D) of the seventh PMOS transistor is connected to the drain of the third NMOS transistor, the first input terminal of the NOR gate, and the gate (G) of the sixth NMOS transistor. The gate (G) of the second NMOS transistor is connected to the gate (G) of the third NMOS transistor and the external Vbias1 terminal, respectively; the source (S) and the base (B) of the second NMOS transistor are both connected to the external VSS terminal. The source (S) and base (B) of the third NMOS transistor are both connected to the external VSS terminal. The second input terminal of the NOR gate is connected to the external Vdrive_c1 terminal, and the output terminal of the NOR gate is connected to the gate of the fourth NMOS transistor. The drain (D) of the fourth NMOS transistor is connected to the base of the second transistor, the collector of the second transistor, the drain of the fifth NMOS transistor, and the first input port of the output stage unit, respectively; the source (S) and the base (B) of the fourth NMOS transistor are both connected to the external VSS terminal. The gate (G) of the fifth NMOS transistor is connected to the external Vdrive_c1 terminal; the source (S) and base (B) of the fifth NMOS transistor are both connected to one end of the sixth resistor; the other end of the sixth resistor is connected to the external VSS terminal. The drain (D) of the sixth NMOS transistor is connected to one end of the fifth resistor; the source (S) and base (B) of the sixth NMOS transistor are both connected to the emitter of the second transistor; the other end of the fifth resistor is connected to the external VCC terminal.

3. The RS485 interface circuit powered by 3.3V according to claim 2, characterized in that, The low-level short-circuit protection unit specifically includes: the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the third transistor, the fourth transistor, an OR gate, the seventh resistor, the eighth resistor, the ninth resistor, the tenth resistor, and the eleventh resistor. The gate (G) of the seventh NMOS transistor is connected to the external Vdrive_n terminal; the drain (D) of the seventh NMOS transistor is connected to the external OUT_fbn terminal; the source (S) and the base (B) of the seventh NMOS transistor are both connected to the emitter of the third transistor and one end of the ninth resistor; the other end of the ninth resistor is connected to the external VSS terminal. The gate (G) of the eighth PMOS transistor is connected to the gate (G) of the ninth PMOS transistor and the external Vbias2 terminal, respectively; the source (S) and base (B) of the eighth PMOS transistor are both connected to the external VCC terminal; the drain (D) of the eighth PMOS transistor is connected to the base of the third transistor and one end of the seventh resistor, respectively; the other end of the seventh resistor is connected to the collector of the third transistor and one end of the eighth resistor, respectively; the other end of the eighth resistor is connected to the base of the fourth transistor. The source (S) and base (B) of the ninth PMOS transistor are both connected to the external VCC terminal; the drain (D) of the ninth PMOS transistor is connected to the collector of the fourth transistor, the first input terminal of the OR gate, and the gate (G) of the twelfth PMOS transistor; the emitter of the fourth transistor is connected to the external VSS terminal. The second input terminal of the OR gate is connected to the external Vdrive_c2 terminal; the output terminal of the OR gate is connected to the gate of the tenth PMOS transistor. The source (S) and base (B) of the tenth PMOS transistor are both connected to the external VCC terminal; the drain (D) of the tenth PMOS transistor is connected to the drain of the eleventh PMOS transistor, the source (S) of the twelfth PMOS transistor, the base (B) of the twelfth PMOS transistor, the drain of the eighth NMOS transistor, and the external Vdrive_n terminal. The gate (G) of the eleventh PMOS transistor is connected to the external Vdrive_c2 terminal; the source (S) and the base (B) of the eleventh PMOS transistor are both connected to one end of the tenth resistor; the other end of the tenth resistor is connected to the external VCC terminal. The drain of the twelfth PMOS transistor is connected to one end of the eleventh resistor; the other end of the eleventh resistor is connected to the external VCC terminal. The gate (G) of the eighth NMOS transistor is connected to the external Vdrive_c2 terminal; the source (S) and the base (B) of the eighth NMOS transistor are both connected to the external VSS terminal.

4. The 3.3V powered RS485 interface circuit according to claim 3, characterized in that, The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the first NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor are all high-voltage MOS transistors.

5. The 3.3V powered RS485 interface circuit according to claim 3, characterized in that, The sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the sixth NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the eighth NMOS transistor are all standard MOS transistors.

6. The 3.3V powered RS485 interface circuit according to claim 4, characterized in that, The voltage of the high-voltage MOSFET is greater than 5V.

7. The 3.3V powered RS485 interface circuit according to claim 5, characterized in that, The standard MOSFET is 5V.

8. The 3.3V powered RS485 interface circuit according to claim 1, characterized in that, The output stage unit meets the withstand voltage requirements of RS485 bus -7V to +12V.

9. The 3.3V powered RS485 interface circuit according to claim 1, characterized in that, The VCC is powered by 3.3V, and the maximum power supply deviation is ±10%.

10. The 3.3V powered RS485 interface circuit according to claim 9, characterized in that, When the supply voltage of VCC is 3V, the maximum value of the output differential voltage is 2.4V.

Images