A calibration method for inter-stage gain mismatch of a split-column pipelined ADC

Abstract

This invention provides a calibration method for inter-stage gain mismatch in a discrete pipelined ADC, relating to the field of semiconductor technology. The method includes: injecting a first DC bias into the pre-stage quantizer of the stage to be calibrated in the first sub-channel, and injecting different second DC biases into the same pre-stage quantizer in the second sub-channel, causing the two sub-channels to generate different transmission curves; using the two sub-channels to sample, quantize, and digitally concatenate the same input signal, calculating the difference between the concatenated digital output codes to obtain a concatenated output error value; under the condition that the pre-stage quantization code value of one sub-channel is within a preset reference region, the pre-stage quantization code value of the other sub-channel is flipped, and the residual quantization signal of its subsequent stage is within a preset interval, classifying and statistically averaging this error value to extract a transition error value; finally, iteratively updating the digital compensation gain based on this transition error value until convergence. This invention features simple digital processing, low resource consumption, and fast convergence speed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a calibration method for interstage gain mismatch in a discrete pipeline ADC. Background Technology

[0002] With the rapid development of integrated circuit technology, analog signal processing technology and digital signal processing technology are also gradually maturing. The surge in demand for high-precision ADCs in communication electronics, the Internet of Things, medical electronics, radar and other fields makes high-speed and high-resolution ADCs indispensable.

[0003] Furthermore, with the continuous advancement of process nodes in the semiconductor industry, analog ADC devices require more digital calibration to increase their performance and reduce their power consumption. High-performance ADCs rely even more heavily on various calibration techniques to correct errors and improve performance. The split-ADC architecture, consisting of two identical sub-ADCs, is a high-speed, high-performance, low-complexity, easy-to-model physical architecture that can achieve good digital calibration, detailed below. Figure 1 As shown, two sub-ADCs repeatedly sample the same analog signal, and the quantized signals from the last two sub-ADCs are averaged, resulting in a performance improvement of at least 3dB compared to a single ADC. The pipelined linear architecture of the ADC enables high-speed, high-bit-precision quantization in analog implementations. After each pipeline stage quantizes the high-order bits, the remaining low-order bits are time-delayed and quantized by the second stage, ..., the Nth stage ADC. Details as follows Figure 2 As shown, each stage of the analog stgADC can be either a flash ADC or a Sar ADC, selected based on the ADC architecture's maximum sampling rate and power consumption. The split-pipeline architecture is currently an important architecture for achieving high speed and high precision. While split ADCs offer significant performance improvements, the use of two sub-ADCs is not optimal in terms of overall system power consumption and hardware resource overhead. Therefore, simplifying the ADC's analog / digital calibration resources is crucial. Theoretically, there are many mature calibration schemes for split-ADCs that can calibrate capacitors to optimal performance. However, the interstage gain introduced by the pipeline structure ADC (introduced by the interstage amplifier OP) is dynamically unstable due to factors such as process technology, temperature, and voltage. This cannot be resolved through analog or digital domain front-end calibration techniques and will severely affect the ADC's linearity.

[0004] Currently, there is a common calibration method for interstage gain calibration of Pipeline-ADCs, which involves injecting a known pseudo-random sequence of PN into the quantizer of the preceding stgADC stage. This PN sequence is then quantized and output after being amplified by the interstage gain of the operating system (OP). Finally, on the digital side, the statistical amplitude of PN in the subsequent quantized signal is extracted by detecting the autocorrelation sequence of PN. This amplitude changes with the PVT, which can provide real-time feedback on the interstage gain of the ADC. However, this method extracts the PN amplitude from the existing mixed traffic signal, which requires a large amount of statistical sample convergence time for calibration. The calibration accuracy is limited by a certain amplitude of PN injected by the preceding ADC (too large will cause saturation in the subsequent stage, and too small will result in insufficient calibration accuracy). The digital side needs to generate a high-speed pseudo-random sequence of PN to send to the analog stage, and the high-speed interface is also a design challenge and risk. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the purpose of this invention is to provide a calibration method for interstage gain mismatch in a pipelined ADC. This invention solves the problems in the prior art where general interstage gain calibration methods require a large number of statistical samples and convergence time, the calibration accuracy is limited by the magnitude of the injected pseudo-random sequence, and the challenges and risks of high-speed interface design brought about by generating a high-speed pseudo-random sequence on the digital side and sending it to the analog end.

[0006] To achieve the above objectives, the present invention provides the following solution: A calibration method for interstage gain mismatch in a discrete pipelined ADC includes: A first DC bias is injected into the pre-amplifier of the stage to be calibrated in the first sub-channel, and a different second DC bias is injected into the pre-amplifier of the second sub-channel, so that the two sub-channels produce different transmission curves. The first sub-channel and the second sub-channel are used to sample and quantize the same input signal, and output the first pre-stage quantization code value and the first post-stage residual quantization signal, as well as the second pre-stage quantization code value and the second post-stage residual quantization signal, respectively. Based on the current calibration digital compensation gain of the stage to be calibrated, the quantization code values ​​of the previous stage and the residual quantization signal of the next stage output from the two sub-channels are digitally concatenated to obtain the first concatenated digital output code and the second concatenated digital output code. Calculate the difference between the first concatenated digital output code and the second concatenated digital output code to obtain the concatenation output error value corresponding to the same input signal; When the preset conditions are met, the splicing output error value is classified, statistically averaged, and the jump error value representing the inter-stage gain mismatch is extracted; the preset conditions are: the quantization code value of the pre-stage of one sub-channel is in a preset reference area, the quantization code value of the pre-stage of another sub-channel is flipped, and the residual quantization signal of the post-stage of the other sub-channel is within a preset quantization threshold range. Based on the amplitude and sign characteristics of the jump error value, the current calibration digital compensation gain is iteratively updated based on a preset convergence step factor until the amplitude of the jump error value decreases and converges, so as to complete the calibration of the interstage gain mismatch.

[0007] The present invention discloses the following technical effects: This invention provides a calibration method for interstage gain mismatch in split-pipeline ADCs. The invention demonstrates that the break characteristic of this statistical method for split-ADCs is essentially achieved by cleverly combining the distributed probability continuity of the ADC input signal within the split-ADC architecture for calibration. This method is highly suitable for tracking the interstage gain of split-ADCs affected by environmental factors such as PVT. This calibration scheme conditionally classifies and statistically analyzes the error between the two sub-ADCs. Digital implementation resources are relatively simple, and interstage gain error can be obtained without multipliers. Furthermore, the entire calibration only requires configuring two split ADCs, with a fixed DC injection into the preceding ADC, or utilizing the DC bias inherent in the analog ADC to effectively create an equivalent DC injection function. This simplifies analog circuit design and eliminates the need for an additional PN high-speed pseudo-random code, effectively solving the interstage gain problem. Overall, this invention provides a relatively simple solution to the interstage gain problem with minimal resource consumption for both digital and analog circuits, making it highly suitable for interstage gain calibration in split-pipeline ADC architectures. The structure of the Split-Pipeline-ADC allows for efficient interstage gain calibration between the two sub-ADCs, significantly reducing the resource consumption and complexity of analog ADC design. It also minimizes the resource consumption of digital design, while offering high calibration accuracy, fast convergence time, simple digital processing, and low resource consumption. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of the physical architecture of a discrete analog-to-digital converter provided in an embodiment of the present invention; Figure 2 A schematic diagram of the architecture of a pipelined analog-to-digital converter provided in an embodiment of the present invention; Figure 3 A flowchart of a calibration method for interstage gain mismatch in a pipelined ADC provided in this embodiment of the invention; Figure 4 A schematic diagram of the overall circuit architecture of the interstage gain calibration scheme of the present invention provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the DC bias injection position of the pre-stage quantizer when the interstage gain is at the quasi-kth stage, provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the pre-stage quantization transfer curves after DC bias is injected into the two separate sub-channels provided in an embodiment of the present invention; Figure 7 This is a schematic diagram illustrating the error characteristics of a transmission curve jump caused by interstage gain mismatch and a typical gain mismatch scenario, provided in an embodiment of the present invention. Figure 8 This is an overall structural block diagram of a discrete analog-to-digital converter provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the transmission curve statistical characteristics under the scenario of small interstage gain mismatch provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the transmission curve statistical characteristics under a scenario of large interstage gain mismatch provided in an embodiment of the present invention. Figure 11 This is a schematic diagram illustrating the statistical characteristics of transmission curves under different degrees of gain mismatch in two sub-channels, as provided in an embodiment of the present invention. Figure 12 A schematic diagram of the error convergence curves of the two sub-channels during the calibration process provided in an embodiment of the present invention; Figure 13 A schematic diagram of the Fast Fourier Transform performance of a split-type analog-to-digital converter before inter-stage gain calibration, provided in an embodiment of the present invention; Figure 14 A schematic diagram of the Fast Fourier Transform performance of the discrete analog-to-digital converter after interstage gain calibration provided in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] like Figure 1 As shown, this invention provides a calibration method for inter-stage gain mismatch applied to a discrete pipelined ADC, comprising: Step 100: Inject a first DC bias into the pre-amplifier of the stage to be calibrated in the first sub-channel, and inject a different second DC bias into the pre-amplifier of the second sub-channel, so that the two sub-channels produce different transmission curves. Step 200: Use the first sub-channel and the second sub-channel to sample and quantize the same input signal, and output the first pre-stage quantization code value and the first post-stage residual quantization signal, as well as the second pre-stage quantization code value and the second post-stage residual quantization signal, respectively. Step 300: Based on the current calibration digital compensation gain of the stage to be calibrated, the quantization code values ​​of the pre-stage output and the residual quantization signal of the post-stage output of the two sub-channels are digitally concatenated to obtain the first concatenated digital output code and the second concatenated digital output code. Step 400: Calculate the difference between the first concatenated digital output code and the second concatenated digital output code to obtain the concatenation output error value corresponding to the same input signal; Step 500: When the preset conditions are met, the splicing output error values ​​are classified, statistically averaged, and the jump error values ​​representing the inter-stage gain mismatch are extracted; the preset conditions are: the quantization code value of the preceding stage of one sub-channel is in a preset reference area, the quantization code value of the preceding stage of another sub-channel is flipped, and the residual quantization signal of the following stage of the other sub-channel is within a preset quantization threshold range; Step 600: Based on the amplitude and sign characteristics of the jump error value, iteratively update the current calibration digital compensation gain according to the preset convergence step factor until the amplitude of the jump error value decreases and converges, so as to complete the calibration of the interstage gain mismatch.

[0013] Specifically, such as Figure 4 As shown, the overall circuit consists of a set of split Pipeline-ADCA and Pipeline-ADCB on the analog side to complete the sampling and quantization of the same input signal, and on the digital side, each Pipeline-ADC has its own independent calibration compensation and data combination module, error classification statistics for the two channels, and calibration gain iteration module.

[0014] Furthermore, the step of injecting a first DC bias into the pre-amplifier of the stage to be calibrated in the first sub-channel, and injecting a different second DC bias into the pre-amplifier of the second sub-channel, so that the two sub-channels produce different transmission curves, includes: The first DC bias and the different second DC biases are configured by utilizing the comparator mismatch in the pre-amplifier for equivalent purposes, or by configuring a fixed deviation during front-end calibration to generate the first DC bias and the different second DC biases. The first DC bias is injected into the pre-amplifier of the first sub-channel to be calibrated, and the second DC bias is injected into the pre-amplifier of the second sub-channel. Injecting oppositely oriented DC offsets into the multiplication digital-to-analog converter of the stage to be calibrated causes the two sub-channels to produce the differential transmission curves.

[0015] Furthermore, the interstage gain of this invention requires two identical sub-channels, Pipeline-ADCA and Pipeline-ADCB, in the analog-side circuit to acquire the same sampling point for quantization. This necessitates that the two sub-channels' preceding stgADCs can flexibly inject different DC biases. See details... Figure 5 The diagram shows the DC injection point of the simulated Stgk-ADC when calibrating the interstage gain of the k-th stage (equivalent to adding DC to the CADC branch from the In signal). If the preceding stgADC uses a flash ADC or sar ADC, its comparator mismatch can be equivalent to a natural injected DC bias function. Alternatively, the bias can be fixed during the foreground comparator calibration, equivalent to the DC bias injected by the preceding stgADC. The goal is to ensure that the two sub-channels have two or more different quantization code values ​​representing the same sampled signal in the preceding quantization output region, i.e., the two split channels output the k-th stage quantization code value d for the same sampled point value. k Theoretically, there are differences, or rather, there are two different transmission curves for the two sub-ADCs in the split configuration. These two transmission curves exhibit vertical shifts due to the injected DC bias of their respective ADCs. The feature of this invention is that different DC offsets need to be injected into the two sub-channels on the analog side. The purpose is to change the different transmission curves of the two identical sub-ADCs (ADCA and ADCB) when sampling the same signal. This requires injection into the preceding stgADC of the OP to be calibrated, thereby affecting the quantization d of the preceding stgADC. k As a result, considering the system, injecting a positive DC quantity at CADC will lead to a larger change in the residual quantized signal of the subsequent stage, i.e., res 实际 =res 理想 -DC(res) 理想 (In the case of no offset DC injection), the res signal overflows beyond the range during the subsequent ADC conversion; therefore Figure 5 The diagram shows the addition of a reverse-sized DC offset at the MDAC to ensure that the quantization of the subsequent ADC does not exceed its range. This patent does not restrict whether the pair of positive and negative DC offsets are the same size; the purpose is simply to ensure that the subsequent ADC does not saturate within its range. Even injecting a single positive DC at the CADC is possible. The DC offset can be flexibly set according to the reference voltage of the actual ADC architecture and the reserved dynamic range of the subsequent ADC.

[0016] The two split sub-channels of the CDAC are each injected with DC bias as follows: Figure 6 The example illustrates in detail the quantization transfer curve consisting of a 3-bit stg ADC in the front stage and a rear stage. The Pipeline-ADCA / B transfer curves are injected with two different DC biases relative to the ideal transfer curve. The injected DC bias causes ADCA and ADCB to have different code values ​​when acquiring the same signal. The figure illustrates that when the front stage code value d=0 (binary encoding is 100) of ADCB in the ghost area, the front stage output of ADCA has two code values ​​d=0 / 1 to simulate the requirements.

[0017] Furthermore, based on the current calibration digital compensation gain of the stage to be calibrated, the preceding quantization code values ​​output from the two sub-channels are digitally concatenated with the subsequent residual quantization signal to obtain a first concatenated digital output code and a second concatenated digital output code, including: Obtain the current calibration digital compensation gain of the level to be calibrated; Based on the current calibration digital compensation gain, the digital domain concatenation of the pre-stage quantization code value and the post-stage residual quantization signal output from the two sub-channels is performed using the data concatenation formula. After completing the digital field concatenation, the first concatenated digital output code and the second concatenated digital output code are obtained respectively. The expression of the data concatenation formula is as follows: ; Where, d a1 d a2 d represents the pre- and post-stage quantization values ​​of ADCA. b1 d b2 X represents the pre- and post-quantization values ​​of ADCB. a X is the concatenated data value of ADCA. b This is the concatenated data value of ADCB. , These are the inter-stage gains to be calibrated for ADCA and B, respectively.

[0018] Specifically, the interstage gain calibration and number concatenation module of this invention digitally implements the calibration and number concatenation of the quantization code value of the input Vin signal, as described in the reference. Figure 4 As shown, the outputs of the two split sub-ADCs are quantized, and the inter-stage gains of the analog operating system between each stage are G1, G2, ..., G... N-1 ADC concatenation requires digital domain compensation using the latest gain from calibration iterations to simulate non-ideal G gain. The concatenation and compensation of any one of the two ADC channels is achieved using the following formula: Where X is the multi-level concatenated digital code output from the Vin quantization of the analog signal, d1, d2, d3, ..., d N The quantization outputs of the sub-stgN-ADCs, in order, are stg1, stg2, stg3, ..., g, and the calibrated digital compensation gains are g1, g2, ..., g, respectively. N-1 The detailed calibration values ​​for ADCA can be labeled as ga1, ga2, ..., ga N-1 Detailed ADCB calibration values ​​can be labeled as gb1, gb2, ..., gb N-1 Theoretically, any single or multiple interstage gain values ​​can be selected for calibration, and the patent does not impose any restrictions. The concatenation module mainly completes the integrity concatenation of multiple gain coefficients generated by calibration into a single signal X. Actual ADC concatenation involves encoding and decoding, as well as other concatenations such as capacitance calibration. The formula in this module only provides one method of pipeline concatenation and is not intended to limit the uniqueness of the compensation formula and structure of this invention.

[0019] Furthermore, the step of classifying and statistically averaging the splicing output error values ​​when the preset conditions are met, and extracting the jump error value characterizing the inter-stage gain mismatch, includes: Configure the quantization code value range where the small signal is located as the preset reference region, and configure the range between the upper threshold and the lower threshold based on the common mode position of the subsequent output as the preset quantization threshold range; Determine whether the preset conditions are met, that is, confirm that the pre-stage quantization code value of one of the sub-channels is in the preset reference area, confirm that the pre-stage quantization code value of the other sub-channel has undergone code value inversion, and confirm that the post-stage residual quantization signal of the other sub-channel is within the preset quantization threshold range. When the preset conditions are met, the splicing output error value is averaged using a classification statistical formula to extract the jump error value representing the inter-stage gain mismatch.

[0020] Specifically, the error statistics module for interstage gain calibration in this invention is a key implementation of this patent. This module obtains the interstage gain error to be calibrated through conditional error classification and accumulation. Then, adjustment is completed based on the calibration gain iteration module, thus achieving the gain calibration of this patent. The error statistics are based on the difference between the two split-ADC channels, ADCA and ADCB, i.e., the statistics of err = Xa - Xb. The classification method is based on the principle that the two channels of the Split-ADC acquire the same reference point, and the mismatch in their interstage gain will cause the ADC to break at the position where the code value of the previous stage changes, as detailed below. Figure 7 As illustrated in the example, assuming ADCA is injected with a negative DC bias of a certain magnitude (approximately MSB / 2) and ADCB is injected with a positive bias of a certain magnitude (approximately MSB / 2), the inter-stage gain mismatch causes a large jump (or INL break) in the transmission curve of the entire ADC before and after the code value inversion of the previous stage. Then, the G in the Split structure is listed... a / G b Compared to the ideal gain G, gain mismatch presents a typical 6-gain mismatch scenario, and the statistical error signal err=Xa-Xb exhibits different characteristics in each scenario: 1) G b =G Ideal scenario, pre-stage quantization value d a The interval at point j will have d. b =j-1 flipped to j, no gain mismatch will cause the ADCB's transmission curve to be linear, then err is ideal DC, that is, DC bias injection will not cause err to have a break jump. 2) G a =G ideal scenario, d b The interval at point j will have d. a =J flipped to j+1, no gain mismatch will cause the ADCA transfer curve to be linear, then err is ideal DC, that is, DC bias injection will not cause err to have a break jump. 3) G b >G is more suitable for large scenes, d a The interval at =j-1 will have d b = flip j-2 to j-1, G b Gain deviation causes the ADCB's transfer curve to be non-linear, and its DC bias injection causes a break transition in err, with the transition position being d. b =j-2 flipped to j-1, approximately at Figure 7 The statistical interval that was selected; 4) G a >G is more suitable for large scenes, d b The interval at =j-1 will have d a =j-1 flipped to j, Ga The gain deviation causes the transfer curve of ADCA not to be linear, and its DC bias injection causes a break jump in err, and the jump position is d a flips from j - 1 to j, approximately at Figure 7 the calibrated statistical interval in the middle, and with G b >G, the flip sign of err is reversed; 5) G b <G small scenario, d a =j + 1 interval will have d b =j flips to j + 1, G b The gain deviation causes the transfer curve of ADCB not to be linear, and its DC bias injection causes a break jump in err, and the jump position is d b =j flips to j + 1, approximately at Figure 7 the calibrated statistical interval in the middle; 6) G a <G small scenario, d b =j + 1 interval will have d a =j + 1 flips to j + 2, G a The gain deviation causes the transfer curve of ADCA not to be linear, and its DC bias injection causes a break jump in err, and the jump position is d a =j + 1 flips to j + 2, approximately at Figure 7 the calibrated statistical interval in the middle, and with G b <G, the flip sign of err is reversed.

[0021] The err error classification and statistical method for the inter - stage gain of this patent observes the distribution law of err = X a -X b when observing the previous - stage code value flip of another channel according to the transfer curve of one ADC channel. The break jump of err will be eliminated only when the inter - stage gain of the ADC is calibrated to the optimal target value. The implementation requirements state that in the Split structure, the inter - stage gain error of the channel to be calibrated selects the error value of err = Xa - Xb according to the corresponding conditions: To calibrate the inter - stage gain of ADCA, first select the error err under the condition that the previous - stage ADCB quantization code value is d b =j, and on the basis of d b =j, it is also necessary to classify the previous - stage output code value d a =p, d a =q (note that p and q are the previous - stage quantization values of ADCA under the condition of d b =j, affected by various mismatches of the ADC, not necessarily as Figure 7 shown as p = q ± 1) two error values erra p and erraq , in order to capture the break jump characteristics most accurately, finally erra p and erra q The statistical error also requires the post-stage residual THL <res of the post-ADCA channel a <THH, where res a is the post-stage quantization value of ADCA, and THH / THL is the post-stage ADC quantization threshold setting. The conventional configuration is to add and subtract the common-mode position of the post-stage output to cover the quantization interval of a transmission curve. For detailed reference Figure 7 of the shaded area; calibrate the inter-stage gain of ADCB. First, select the error err when the pre-stage ADCA quantization code value is d a =j. On d a =j, it is also necessary to classify the pre-stage output code value d b= p, d b= q (note that p and q are the pre-stage quantization values of ADCB under the condition of d a =j. Affected by various mismatches of the ADC, they are not necessarily as Figure 7 shown as p = q ± 1) two error values errb p and errb q , in order to capture the break jump characteristics most accurately, finally errb p and errb q The statistical error also requires the post-stage residual THL <res of the post-ADCB channel b <THH, where res b is the post-stage quantization value of ADCB, and THH / L is the post-stage ADC quantization threshold setting. The conventional configuration is to add and subtract the common-mode position of the post-stage output to cover the quantization interval of a transmission curve. For detailed reference Figure 7 of the shaded area; the induction formula (classification statistics) is: ; where err = X a -X b the error value between the same sampling signals, E{ } is the statistical average of a segment of data, E{ }| represents the statistical average of a segment based on a preset condition, A break 、B break respectively represent the inter-stage gain error values of ADCA / B, with certain sign characteristics, which can be used to judge whether the inter-stage gain is too large or too small and are used for subsequent inter-stage gain iteration. For detailed examples Figure 7 described by the characteristic formula shown: ; Figure 6 It can be seen from the above formula that G a>Below G <0, G a <Below G >0, G b >Below G >0, G b <Below G <0.

[0022] For a multi-stage Pipeline-ADC, the gain between any two stages can be statistically calculated according to the previous-stage ADC and the subsequent-stage ADC. If stg1 is calibrated, then for the subsequent stage ; if stg2 is calibrated, then for the subsequent stage , ……, calibration of more subsequent stages will not be described. For the gain between stages of the entire ADC in multiple stages, it is recommended to proceed from the previous stage to the subsequent stage. The previous stage is the quantization information of the high-order bits, and the break error information of its gain between stages is more significant.

[0023] Further, based on the amplitude characteristic and sign characteristic of the jump error value, iteratively updating the current calibrated digital compensation gain according to a preset convergence step factor until the amplitude of the jump error value decreases and converges to complete the calibration of the gain mismatch between stages includes: Extracting the amplitude characteristic and the sign characteristic of the jump error value; Implementing multiplication of the preset convergence step factor and the jump error value through digital domain shift operation, and determining the adjustment direction in combination with the sign characteristic; Calculating the adjustment amount using a calibration iteration formula, and performing the iterative update on the current calibrated digital compensation gain according to the adjustment amount; Repeating the iterative update until the amplitude of the jump error value decreases and converges to complete the calibration of the gain mismatch between stages; Further, using the first sub-channel and the second sub-channel to sample and quantize the same input signal, and respectively outputting the first previous-stage quantization code value and the first subsequent-stage residual quantization signal, as well as the second previous-stage quantization code value and the second subsequent-stage residual quantization signal, includes: Using the first sub-channel and the second sub-channel to synchronously perform the sampling and quantization on the same input signal; Outputting the high-order quantization results of the current stage to be calibrated as the first previous-stage quantization code value and the second previous-stage quantization code value respectively; Outputting the concatenation value of the multi-stage combined quantization data after the current stage to be calibrated as the first subsequent-stage residual quantization signal and the second subsequent-stage residual quantization signal respectively.

[0024] Specifically, the calibration iteration module performs calibration on A obtained by the statistical module break , Bbreak Explanation of LMS iterative calibration for error information: The typical calibration iteration formula for ADCA / ADCB is: ; Or according to A break B break The iterative formula for symbol information change is: ; Among them, g a For the interstage gain of the stage to be calibrated in ADCA, g b The interstage gain of the ADCA stage to be calibrated is given by sign(u), where u is the convergence step factor, which can be set to a power of 2. In digital implementation, this is simplified by left and right shifts to save resources. The sign value is determined by the data. The dual-channel gain of the split-ADC can be calibrated simultaneously or independently, and the two channels will not affect each other. invs = 1 controls whether the iterative formula is reversed, allowing for flexible control of the injection into the ADC system. The entire calibration iterative formula can theoretically be implemented without a multiplier, saving hardware overhead.

[0025] Furthermore, this invention and its implementation steps are further explained in detail by using a Split-ADC with a 4-bit front-end and multiple stages combined into a 12-bit back-end as an example. For details on the ADC, please refer to [link to ADC documentation]. Figure 8 block diagram.

[0026] Before calibration, the ADC has completed certain pre-calibration and basic calibration such as capacitance calibration. Before calibration, a negative DC bias is injected into the preceding stage of ADCA, with the bias amplitude being 1 / 2 MSB relative to the preceding stage; a positive DC bias is injected into the preceding stage of ADCB, with the bias amplitude being 1 / 2 MSB relative to the preceding stage. The calibration and data concatenation module enables data concatenation between the pre-stage and post-stage, and the concatenation process is as follows: ; Where, d a1 d a2 d represents the pre- and post-stage quantization values ​​of ADCA. b1 d b2 X represents the pre- and post-quantization values ​​of ADCB. a X is the concatenated data value of ADCA. b This is the concatenated data value of ADCB. , These are the interstage gains to be calibrated for ADCA and B, respectively. To cover both large and small signals, select d a=0 is used as the reference area. Gain error classification statistics, d b =0 is used as the reference area. The gain error classification statistics show that the subsequent ADC is 12-bit with 1 bit of redundant width. The subsequent quantization code value ranges from -2048 to 2048, with THL=-1024 and THH=1024. The detailed classification statistics formula is as follows: ; This configuration formula is an example, with the ADC input being a single tone of fin=2.318MHz, the ADC sampling rate being 250MHz, and the default ideal interstage gain of the ADC being 8 times. The statistical characteristics of the transmission curves of ADCA and ADCB under the following six interstage gains are listed below. Figure 9 As shown, its [g a ,g b In the two gain mismatch scenarios [7.6, 8] and [8, 7.6], a clear break transition phenomenon can be observed near res=0 of the subsequent signal. However, this break transition does not exist in the ideal 8x gain channel. Furthermore, the break transition of ADCA is reversed compared to that of ADCB. Figure 9 The left side also indicates "erra". p erra q errb p errb q Of the four characteristic regions, only the err signal in the statistical characteristic region can clearly distinguish the magnitude of the gain mismatch between the OP stages. The greater the deviation of the mismatch gain from the ideal, the stronger the break jump amplitude.

[0027] See Figure 10 As shown, its [g a ,g b [8.4, 8] and [8, 8.4] represent two scenarios with significant gain mismatch, combined with... Figure 9 The break direction clearly shows a pattern: when the channel ADCA gain is too high, the break jumps downwards, and when the gain is too low, the break jumps upwards; when the channel ADCB gain is too high, the break jumps upwards, and when the gain is too low, the break jumps downwards.

[0028] and Figure 11 As shown, its [g a ,g b The two gain mismatch scenarios [8.4, 8.4] and [8.4, 7.4] demonstrate that the break of ADCA and the break of ADCB are not correlated; they can independently calibrate their respective gain mismatches. Finally, combining... Figures 9-11The results show that the gain deviation between the front and rear stages of the Split-ADC architecture can be characterized in detail by a classification statistical method under certain conditions, which can also be used to determine the magnitude and direction of the gain error.

[0029] Calibration coefficient , Iteration can be performed in the foreground to find the initial iteration, or in the background to track the fluctuations of the analog stage gain with PVT in real time, thereby improving the overall performance limit of the Split-ADC. The actual convergence process of ADCA and ADCB using this scheme is shown in [link to documentation]. Figure 12 As shown, the err convergence process between the two split ADCs during ADC calibration is illustrated. The Abreak / Bbreak jump amplitude gradually decreases with convergence. The convergence time depends on the selected u step factor; currently, u=0.5 is used, and the calibration convergence time is less than ms, far exceeding the speed requirement for tracking PVT. The FFT performance of the Split-ADC with inter-stage gain before two-channel calibration is shown in [reference needed]. Figure 13 The performance after interstage gain calibration is shown in [link to performance chart]. Figure 14 In theory, the gain compensation value can be calibrated to the level of the noise floor.

[0030] Combination Figure 9 As can be seen, this invention requires the appropriate selection of the ranges of THL and THH so that they fall within the break toggling position of the ADC, which can accurately find the most precise interstage gain. The characteristic of this method is that it requires a certain injection signal. It is recommended that the quantization code value range of the previous stage ADC be selected as the range where the small signal falls, which can well ensure that the break of the previous stage code value toggling can be counted.

[0031] Furthermore, the following example demonstrates a Split-ADC with a 4-bit front-end and multiple stages combined to a 12-bit back-end. This implementation method modifies only the conditions of the classification statistical formula used in this invention. The detailed implementation is as follows: ; Where err=X a -X b The error value between the same sampled signals, E{ } represents the statistical average of a data set, E{ }| represents a statistical average based on preset conditions, A break B break The interstage gain error values ​​of ADCA / B are respectively represented by d. a d b These are the pre-quantization values ​​of ADCA and ADCB, respectively, res a ,res bThese are the quantization values ​​of ADCA and ADCB, or the concatenation of multiple subsequent quantization values. THH, THL, and THB are the quantization threshold settings for the subsequent ADC stages. The THB target is the break transition position of the subsequent quantization output. Figures 8-10 The THB values ​​shown are all 0. In reality, the THB setting can be affected by different comparator offsets and other factors under different inter-stage gain calibrations of the ADC.

[0032] Incorporating actual implementation parameters: To cover both large and small signals, select d. a =0 is used as the reference area. Gain error classification statistics, d b =0 is used as the reference area. The gain error classification statistics are as follows: the subsequent ADC is 12-bit, the quantization code value ranges from -2048 to 2048, and its THL=-1024, THH=1024, and THB=0. Therefore, the classification statistics formula is: ; This patent utilizes Split-ADC and Pipeline-ADC structures to characterize the gain deviation between ADC stages. This deviation leads to the statistical analysis of the linearity break location. There are many implementation formulas or statistical classification conditions for this type of method. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of this invention.

[0033] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0034] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A calibration method for interstage gain mismatch applied to a discrete pipelined ADC, characterized in that, include: A first DC bias is injected into the pre-amplifier of the stage to be calibrated in the first sub-channel, and a different second DC bias is injected into the pre-amplifier of the second sub-channel, so that the two sub-channels produce different transmission curves. The first sub-channel and the second sub-channel are used to sample and quantize the same input signal, and output the first pre-stage quantization code value and the first post-stage residual quantization signal, as well as the second pre-stage quantization code value and the second post-stage residual quantization signal, respectively. Based on the current calibration digital compensation gain of the stage to be calibrated, the quantization code values ​​of the previous stage and the residual quantization signal of the next stage output from the two sub-channels are digitally concatenated to obtain the first concatenated digital output code and the second concatenated digital output code. Calculate the difference between the first concatenated digital output code and the second concatenated digital output code to obtain the concatenation output error value corresponding to the same input signal; When the preset conditions are met, the splicing output error value is classified, statistically averaged, and the jump error value representing the inter-stage gain mismatch is extracted; the preset conditions are: the quantization code value of the pre-stage of one sub-channel is in a preset reference area, the quantization code value of the pre-stage of another sub-channel is flipped, and the residual quantization signal of the post-stage of the other sub-channel is within a preset quantization threshold range. Based on the amplitude and sign characteristics of the jump error value, the current calibration digital compensation gain is iteratively updated based on a preset convergence step factor until the amplitude of the jump error value decreases and converges, so as to complete the calibration of the interstage gain mismatch.

2. The calibration method for interstage gain mismatch applied to a discrete pipelined ADC according to claim 1, characterized in that, The process of injecting a first DC bias into the pre-amplifier of the stage to be calibrated in the first sub-channel, and injecting a different second DC bias into the pre-amplifier of the second sub-channel, so that the two sub-channels produce different transmission curves, includes: The first DC bias and the different second DC biases are configured by utilizing the comparator mismatch in the pre-amplifier for equivalence, or by configuring a fixed deviation during front-end calibration to generate the first DC bias and the different second DC biases. The first DC bias is injected into the pre-amplifier of the first sub-channel to be calibrated, and the second DC bias is injected into the pre-amplifier of the second sub-channel. Injecting oppositely oriented DC offsets into the multiplication digital-to-analog converter of the stage to be calibrated causes the two sub-channels to produce the differential transmission curves.

3. The calibration method for interstage gain mismatch applied to a discrete pipelined ADC according to claim 1, characterized in that, The current calibration digital compensation gain based on the stage to be calibrated involves digitally concatenating the pre-stage quantization code values ​​and the post-stage residual quantization signal output from the two sub-channels to obtain a first concatenated digital output code and a second concatenated digital output code, including: Obtain the current calibration digital compensation gain of the level to be calibrated; Based on the current calibration digital compensation gain, the digital domain concatenation of the pre-stage quantization code value and the post-stage residual quantization signal output from the two sub-channels is performed using the data concatenation formula. After completing the digital field concatenation, the first concatenated digital output code and the second concatenated digital output code are obtained respectively. The expression of the data concatenation formula is as follows: ； Where, d a1 d a2 d represents the pre- and post-stage quantization values ​​of ADCA. b1 d b2 X represents the pre- and post-quantization values ​​of ADCB. a X is the concatenated data value of ADCA. b This is the concatenated data value of ADCB. , These are the inter-stage gains to be calibrated for ADCA and B, respectively.

4. The calibration method for interstage gain mismatch applied to a discrete pipelined ADC according to claim 1, characterized in that, The step of classifying and statistically averaging the splicing output error values ​​when the preset conditions are met, and extracting the jump error value characterizing the inter-stage gain mismatch, includes: Configure the quantization code value range where the small signal is located as the preset reference region, and configure the range between the upper threshold and the lower threshold based on the common mode position of the subsequent output as the preset quantization threshold range; Determine whether the preset conditions are met, that is, confirm that the pre-stage quantization code value of one of the sub-channels is in the preset reference area, confirm that the pre-stage quantization code value of the other sub-channel has undergone code value inversion, and confirm that the post-stage residual quantization signal of the other sub-channel is within the preset quantization threshold range. When the preset conditions are met, the splicing output error value is averaged using a classification statistical formula to extract the jump error value representing the inter-stage gain mismatch. The expression of the classification statistical formula is: ； Where err=X a -X b The error value between the same sampled signals, E{ } represents the statistical average of a set of data, E{ }| represents a statistical average based on preset conditions, A break B break These are represented as the interstage gain error values ​​for ADCA / B, respectively.

5. A calibration method for interstage gain mismatch in a pipelined ADC according to claim 3, characterized in that, The step of iteratively updating the current calibration digital compensation gain based on a preset convergence step factor, according to the amplitude and sign characteristics of the jump error value, until the amplitude of the jump error value decreases and converges, to complete the calibration of the inter-stage gain mismatch, includes: Extract the amplitude feature and the sign feature of the jump error value; The preset convergence step factor is multiplied by the jump error value through digital domain shift operation, and the adjustment direction is determined by combining the sign feature; The adjustment amount is calculated using the calibration iteration formula, and the current calibration digital compensation gain is iteratively updated based on the adjustment amount; Repeat the iterative update until the magnitude of the jump error value decreases and converges, to complete the calibration of the interstage gain mismatch. The expression for the calibration iteration formula is as follows: ； Where u is the convergence step factor, A break B break These are the inter-stage gain error values ​​of ADCA and B, respectively, in the classification statistical formula.

6. The calibration method for interstage gain mismatch applied to a discrete pipelined ADC according to claim 1, characterized in that, The step of sampling and quantizing the same input signal using the first sub-channel and the second sub-channel, and outputting the first pre-stage quantization code value and the first post-stage residual quantization signal, as well as the second pre-stage quantization code value and the second post-stage residual quantization signal, includes: The sampling and quantization of the same input signal are performed synchronously using the first sub-channel and the second sub-channel; The high-order quantization result of the current level to be calibrated is used as the first pre-stage quantization code value and the second pre-stage quantization code value for output; The concatenated value of the multi-level joint quantization data after the current calibration level is used as the first post-stage residual quantization signal and the second post-stage residual quantization signal, respectively, for output.

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