Parallel implementation method and system of quantum-resistant encryption algorithm based on hardware acceleration

Abstract

The application relates to the field of information security and anti-quantum computing, and discloses a kind of parallel implementation method and system of anti-quantum encryption algorithm based on hardware acceleration.The method comprises the following steps: configuring parallel anti-quantum encryption core operation array; deploying pulse neural network control module simulating the random discharge behavior of biological neurons, and connecting power consumption compensation execution unit; monitoring the key operation period and activating the module; using the non-periodic random pulse generated to drive power consumption disturbance, deeply integrating transient power consumption and noise; dynamically adjusting the neuron parameters through the feedback mechanism, so that the total power consumption presents the random characteristics of biological neural electrical signals. Through the above scheme, the encryption power consumption trajectory is disguised as random noise, and without sacrificing the operation efficiency, the differential power analysis and other physical attacks are resisted, and the physical layer security and energy efficiency ratio of the anti-quantum encryption system are improved.

Description

Technical Field

[0001] This invention belongs to the field of information security and quantum-resistant computing, specifically relating to a hardware-accelerated parallel implementation method and system for quantum-resistant encryption algorithms. Background Technology

[0002] With the rapid evolution of quantum computing technology, traditional public-key cryptography faces severe security threats. Quantum-resistant encryption algorithms, as a core pillar of future security defense systems, have become crucial for ensuring information security through their deployment in various communication protocols and high-performance computing platforms. Quantum-resistant encryption technology not only encompasses complex mathematical models and multi-dimensional logical operations but also involves high-performance deployment in various computing terminals and cloud facilities. The robustness of its algorithm implementation directly relates to the long-term security of massive amounts of sensitive data.

[0003] Parallelization based on hardware accelerators is the mainstream trend in the deployment of quantum-resistant encryption algorithms. By introducing massively parallel processing units and highly optimized pipeline architectures, the computational throughput of complex algorithms such as lattice cryptography can be improved. This hardware acceleration mode aims to leverage the computing power of application-specific integrated circuits (ASICs) to achieve efficient parallel processing of key generation and data encryption / decryption processes, meeting the stringent requirements of real-time encryption performance in modern high-frequency trading and massive data interaction scenarios.

[0004] Existing technologies in pursuing higher hardware acceleration performance for quantum-resistant encryption suffer from several drawbacks: Synchronization logic flips during high-speed operation of parallel computing units lead to excessively significant instantaneous power consumption characteristics, easily leaking core operational states and intermediate variables; traditional side-channel defense mechanisms often employ masking techniques or redundant operations, introducing substantial additional computational overhead and reducing the parallel processing gain of hardware accelerators; the inherent repetitive algebraic structure of quantum-resistant algorithms makes their physical signals highly identifiable, allowing attackers to easily extract valid information from environmental noise using differential analysis; and existing power smoothing methods lack the ability to adapt to complex computational environments, making it difficult to achieve deep masking of physical layer power consumption characteristics while ensuring system energy efficiency. These issues collectively contribute to the lack of a balance between physical security and computational performance in quantum-resistant encryption systems. To address the shortcomings of existing technologies, such as power consumption information leakage, excessive defense overhead, obvious computational characteristics, and a lack of adaptability in protection mechanisms, this invention proposes a hardware-accelerated parallel implementation method and system for quantum-resistant encryption algorithms, which is of great importance. Summary of the Invention

[0005] The purpose of this invention is to provide a hardware-accelerated parallel implementation method and system for quantum-resistant encryption algorithms, which can solve the problems mentioned in the background. Addressing the technical challenges of hardware acceleration of quantum-resistant encryption algorithms, such as significant power consumption characteristics due to synchronization logic flipping of massively parallel computing units, vulnerability to differential power analysis attacks, and physical side-channel information leakage, this invention integrates neuromorphic computing and side-channel defense mechanisms. This allows for deep masking of the physical characteristics of encryption operations without sacrificing hardware computing performance, ensuring the physical security of the quantum-resistant encryption system in complex electromagnetic environments.

[0006] To achieve the above objectives, the technical solution adopted by this invention is: a hardware-accelerated parallel implementation method for quantum-resistant encryption algorithms, comprising the following steps: S1. Initialize the hardware acceleration environment and configure the quantum-resistant encryption core operation array, wherein the core operation array is configured to perform polynomial modular multiplication and matrix operations in the quantum-resistant encryption algorithm in parallel. S2. Deploy a spiking neural network control module in the non-computational region of the hardware accelerator, and connect the output of the spiking neural network control module to the power compensation execution unit, wherein the spiking neural network control module simulates the random firing behavior of biological neurons; S3. Real-time monitoring of the task scheduling status of the core computing array. When the core computing array enters a preset critical computing cycle involving key information or intermediate variable processing, the spiking neural network control module is activated. S4. The non-periodic random pulse sequence generated by the spiking neural network control module drives the power compensation execution unit to generate neural pulse-like power disturbances, and deeply fuses the instantaneous power trajectory of the core computing array with random noise signals. S5. Based on the feedback control mechanism, the neuron excitation parameters of the spiking neural network are dynamically adjusted to ensure that the total power consumption of the synthesized system exhibits random characteristics similar to biological neural electrical signals in both the time and frequency domains.

[0007] Preferably, step S1 specifically includes the following steps: 1. Construct a parallelized acceleration architecture consisting of multiple independent computing units, each of which has local memory and arithmetic logic processing capabilities; 2. Decompose the lattice cryptographic operation logic in the adversarial quantum encryption algorithm and transform it into a vectorized operator stream suitable for parallel processing; 3. Preset task distribution strategies in the global control unit of the hardware accelerator to achieve pipelined scheduling of large-scale parallel data streams.

[0008] Preferably, step S2 specifically includes the following steps: 1. Integrate a hardware neuron circuit based on a leakage current integral triggering model within the idle silicon area of ​​a hardware accelerator; 2. Configure the synaptic weight matrix and membrane potential decay constant of the hardware neuron to enable it to have nonlinear dynamic characteristics that generate random spike discharges; 3. Design the power compensation execution unit as a dummy load consisting of multiple sets of transistor load arrays of preset size, and establish its electrical control connection with the pulse neural network control module.

[0009] Preferably, step S3 specifically includes the following steps: 1. Capture the status of the instruction register inside the core arithmetic array using hardware monitoring probes to identify the type of microinstruction currently being executed; 2. Establish a key operation identification model to mark instruction sequences involving sensitive mathematical operations, including but not limited to number theory transformation operations and discrete Gaussian sampling operations; 3. Before the critical operation instructions enter the pipeline execution stage, send an enable trigger signal to the spiking neural network control module.

[0010] Preferably, step S4 specifically includes the following steps: 1. After receiving the enable trigger signal, the spiking neural network control module starts the membrane potential integration process of the internal neuron model; 2. When the membrane potential exceeds a preset threshold at a preset random time point, a random pulse signal with a steep rising edge and a slow falling edge is generated; 3. The power consumption compensation execution unit generates controlled instantaneous current fluctuations on the power bus by rapidly switching the conduction state of the internal load array based on the amplitude and frequency of the random pulse signal.

[0011] Preferably, step S5 specifically includes the following steps: 1. The built-in current sampling module collects the sum current waveform of the core computing array and the power compensation execution unit in real time; 2. Calculate the similarity index between the current total current waveform and the power consumption characteristics of standard encryption operations using a cross-correlation analysis algorithm; 3. Adjust the refractory period parameter of the hardware neuron based on the similarity index feedback to correct the random distribution of power consumption disturbance in real time, ensuring that attackers cannot extract effective computational features through statistical means.

[0012] Preferably, the neuron model in the spiking neural network control module adopts an improved leakage current integral triggering architecture, and its mathematical description logic is as follows: within each preset sampling interval, the membrane potential of the neuron spontaneously decays according to a preset decay coefficient and accumulates external excitation from a random number generator or a task load monitor; when the accumulated potential exceeds a preset dynamic threshold, the neuron generates a spike pulse and immediately resets the membrane potential to a preset level.

[0013] Preferably, the refractory period characteristic of the neuron is configured such that: within a preset time period after the generation of the spike pulse, the neuron is in an inhibited state and does not respond to any external input; the duration of the refractory period is dynamically mapped according to the parallelism of the core computing array, aiming to break any potential phase-locked relationship between power consumption disturbances and computing cycles.

[0014] Preferably, the power consumption compensation execution unit includes a multi-level adjustable capacitor charging and discharging circuit to simulate the smooth transition effect of biological synaptic signals, so that the generated power consumption disturbance is closer to the shot noise characteristics of real circuit operation at the physical level.

[0015] Preferably, when the core computing array performs polynomial modular multiplication, it adopts a specific memory access mode. This memory access mode is configured to distribute the polynomial coefficients in different physical storage units to reduce the instantaneous power density change per unit area, and to achieve a better shading effect in conjunction with the spiking neural network control module.

[0016] Preferably, the amplitude range of the power consumption disturbance is limited to a predetermined proportion of the normal operating power consumption of the core computing array, so as to achieve a balance between ensuring side channel security and system energy efficiency.

[0017] Preferably, the hardware accelerator integrates an independent clock distribution network, and the spiking neural network control module adopts a clock domain asynchronous with the core computing array. This cross-clock domain design further eliminates feature correlations in the time domain.

[0018] A hardware-accelerated parallel implementation system for quantum-resistant encryption algorithms, used to implement the aforementioned method, includes: a quantum-resistant encryption acceleration core for parallel execution of lattice cryptography operations and related algebraic transformations, the output of which is connected to a system bus; the acceleration core is configured as a high-throughput pipeline structure; a spiking neural network controller deployed in a non-critical logic area of ​​a hardware chip, comprising multiple coupled hardware neuron units for generating random trigger sequences conforming to biomimetic characteristics; a power perturbation execution module electrically connected to the spiking neural network controller, consisting of an adjustable dummy load array, for introducing non-periodic power consumption fluctuations in the system power supply circuit according to the random trigger sequences; and a state monitoring and feedback component connected to both the acceleration core and the spiking neural network controller, for real-time analysis of power consumption waveforms and dynamic adjustment of neuron firing control parameters.

[0019] Preferably, the quantum-resistant encryption acceleration core includes multiple processing unit arrays, a dedicated number theory transformation accelerator, and highly parallel matrix multipliers, and the processing unit arrays exchange data through a high-speed interconnection network.

[0020] Preferably, the spiking neural network controller integrates a hardware random number generator to provide random initialization parameters and excitation sources for neurons, ensuring that power consumption disturbances do not have statistical reproducibility over long periods of time.

[0021] Preferably, the power consumption perturbation execution module adopts a distributed layout, distributing the dummy load array around the acceleration core to homogenize the power consumption radiation characteristics in physical space and counteract local near-field electromagnetic analysis.

[0022] Preferably, the status monitoring and feedback component includes a high-precision instantaneous current sensing circuit and fast Fourier transform processing logic, used to evaluate the entropy change of power consumption information at the hardware level.

[0023] Compared with the prior art, the present invention has the following beneficial effects: This invention introduces the neuronal excitation and refractory period characteristics from neuroscience into the field of hardware side-channel defense, constructing a biomimetic-based intelligent power consumption perturbation mechanism. Utilizing the non-periodic random discharge characteristics of spiking neural networks, this invention breaks the inherent power consumption regularity in the parallel hardware implementation of quantum-resistant encryption algorithms, successfully solving the side-channel information leakage problem caused by the synchronous flipping of large-scale computing units. Furthermore, since the spiking neural network module does not directly participate in encryption operations and the power consumption perturbation is random, this "dummy load" scheme avoids the huge computational overhead and hardware resource waste caused by traditional masking techniques, significantly improving the overall energy efficiency of the system.

[0024] This invention disguises the originally highly identifiable anti-quantum encryption computation power consumption trajectory as random noise similar to biological neural signals, making it impossible for attackers to separate the effective computation power consumption from the interference power consumption at the physical level, even through differential power analysis or related power analysis. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention; Figure 2 This is a schematic diagram of the core principle framework of biomimetic power consumption masking based on spiking neural networks in this invention; Figure 3 This is a logical flowchart of the identification and pulse enable scheduling of key operations against quantum encryption in this invention; Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow between the acceleration core, neural network controller and power compensation unit in this invention; Figure 5 This is a schematic diagram of the feedback control principle framework based on real-time current sampling and cross-correlation analysis in this invention. Detailed Implementation

[0026] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following description is provided in conjunction with the appendix. Figure 1 To be continued Figure 5 The following is a detailed description of the specific implementation methods, structures, features, and effects of the present invention, as well as preferred embodiments.

[0027] Example 1: This example provides a hardware-accelerated parallel implementation method for quantum-resistant encryption algorithms, primarily applied to quantum-resistant accelerator card environments for high-performance data center servers. This quantum-resistant accelerator card environment possesses large-scale programmable logic resources and high-speed data exchange bandwidth, capable of supporting complex lattice cryptographic operations.

[0028] Step S1, initializing the hardware acceleration environment and configuring the quantum-resistant encryption core computing array, is the foundation of the entire acceleration architecture. During implementation, a parallelized acceleration architecture consisting of a large number of independent computing units needs to be constructed first. Each independent computing unit integrates a dedicated arithmetic logic processing array at the physical layer and is equipped with an independent local cache memory. These memories are configured as a dual-port static random access memory structure to achieve parallel processing of data read and write operations, eliminating waiting cycles during data access.

[0029] When decomposing the lattice cryptographic operation logic in adversarial quantum encryption algorithms, this embodiment focuses on vectorizing the modular multiplication operation of polynomials. By decomposing high-order polynomials into multiple smaller-scale vector operator streams, these operators can be distributed to different computing units for simultaneous execution. To ensure the orderly scheduling of large-scale parallel data streams, a multi-level pipeline distribution strategy is preset in the global control unit of the hardware accelerator. This multi-level pipeline distribution strategy dynamically maps complex matrix operation tasks to physical computing arrays based on the current hardware resource load rate and task priority, ensuring that there is effective data flowing in the pipeline in each clock cycle, achieving extremely high instruction throughput.

[0030] For step S2, deploying the spiking neural network control module in the non-computational region of the hardware accelerator is crucial for achieving biomimetic power masking. This region is selected at the chip edge or within a free silicon area, away from high-speed signal transmission lines, to reduce electromagnetic interference to the main operational logic. In this embodiment, the core of the spiking neural network control module is a hardware neuron circuit built based on a leakage current integral triggering model. This hardware neuron circuit utilizes the subthreshold leakage current characteristics of transistors to simulate the spontaneous decay process of the membrane potential of biological neurons over time. The circuit includes a charge accumulation unit for accumulating charge excitation signals from an internal random number generator or an external task monitor. Simultaneously, a slow decrease in membrane potential is achieved through a preset discharge branch. During the configuration phase, technicians write preset parameters into the synaptic weight matrix through a configuration register; these parameters determine the sensitivity of the neuron to different input stimuli.

[0031] The membrane potential decay constant is set to an adjustable analog bias voltage to control the nonlinear dynamic frequency of random spike discharges generated by neurons. The power-compensated execution unit is designed as multiple transistor load arrays of varying sizes, which act as "dummy loads" connected to the main power line. Control signals sent via the spiking neural network control module precisely drive these transistor arrays to rapidly switch between on and off states.

[0032] For step S3, real-time monitoring of the task scheduling status of the core computing array is a prerequisite for ensuring the accurate triggering of the defense mechanism. This embodiment deploys hardware monitoring probes along the instruction distribution path within the core computing array to achieve real-time capture of microinstruction codes in the instruction register. The monitoring probes pre-decode each instruction entering the execution phase to identify its instruction type. By establishing a key operation identification model, the system can accurately pinpoint instruction sequences involving key-sensitive information or intermediate variable processing. For example, when performing number theory transformation operations or discrete Gaussian sampling operations, these operations are typically accompanied by specific memory access patterns and frequent flips of arithmetic logic units, resulting in highly identifiable power consumption trajectories. To counteract this identifiability, the monitoring component sends a high-level enable trigger signal to the spiking neural network control module one clock cycle before the key operation instruction officially enters the execution pipeline, ensuring that power consumption disturbances are fully aligned in the time domain with the actual encryption operation and achieve deep coverage.

[0033] In step S4, the power compensation process is driven by a generated non-periodic random pulse sequence, reflecting the randomness characteristic of biomimetic masking. Upon receiving the enable trigger signal, the spiking neural network control module immediately initiates the charge integration process of its internal neuron model. Since the input excitation source comes from a hardware random number generator, and the initial level state of each neuron is random, the time point when the membrane potential exceeds the preset trigger threshold exhibits high indeterminism. When the potential exceeds the threshold, the pulse generation circuit generates a pulse signal with specific waveform characteristics. This pulse signal has an extremely steep rising edge, capable of rapidly increasing the instantaneous current, and then exhibits a slowly declining edge characteristic through a controlled discharge circuit. Upon receiving these random pulses, the power compensation execution unit drives the internal power transistor array to switch at high speed. The instantaneous current fluctuations generated by this switching are superimposed on the actual power consumption trajectory generated by the core computing array on the power bus. Because the pulse signal is non-periodic and has variable waveforms, the synthesized total system power consumption trajectory is severely disrupted in physical characteristics, and the originally clear encrypted computing features are masked by background noise resembling bioelectrical signals.

[0034] For step S5, dynamically adjusting parameters based on a feedback control mechanism is the core of ensuring long-term security. The system integrates a high-bandwidth current sampling module, which captures minute changes in the total system current in real time through a precision sampling resistor connected in series with the main power supply. The sampled data is sent to the back-end digital signal processing unit, where a cross-correlation analysis algorithm is used to perform in-depth analysis of the current total current waveform. The algorithm compares the real-time waveform with a pre-stored standard encrypted operation power consumption template and calculates their similarity index. If the similarity index exceeds a preset security threshold, it indicates that the current power consumption disturbance is insufficient in strength or too regular, making it easy for attackers to crack using statistical methods. At this point, the feedback mechanism automatically adjusts the refractory period parameter of the hardware neurons. By extending or shortening the inhibition time of the neurons after generating a pulse, the frequency distribution and phase characteristics of the power consumption disturbance can be effectively changed, thereby correcting the random distribution in real time, breaking any potential correlation between the interference signal and the main operation clock, and ensuring that attackers cannot extract valid key information through differential analysis or correlation analysis.

[0035] The spiking neural network control module in this embodiment employs an improved leakage current integral triggering architecture. Within each preset micro-sampling interval, the virtual membrane potential of the neuron is subtracted by a certain proportion according to a preset attenuation coefficient, simulating the spontaneous reset characteristics of biological neurons. Simultaneously, the accumulation unit continuously receives external stimuli from the hardware entropy source, which are stored in the integrator in the form of discrete charges. When the accumulated potential value in the integrator crosses a dynamically adjusted voltage threshold, the neuron instantaneously releases a logic spike, completely discharging the charge in the integrator and resetting the potential to the reference level. This physical process does not involve any algebraic formula calculations and is entirely implemented by analog circuits or customized hard-core logic circuits.

[0036] Furthermore, the refractory period of neurons is a key means of combating temporal alignment attacks in this embodiment. After generating a spike pulse, the neuron automatically enters an inhibition state controlled by a hardware timer. During this specific time period, even if the external stimulus signal is very strong, the neuron will not fire a second time. The duration of this refractory period is not fixed, but dynamically mapped according to the current parallel execution dimension of the core computing array. For example, when the number of processing units participating in parallel computing increases, the refractory period adjustment logic automatically increases the range of its random fluctuations to generate a perturbation signal with a higher entropy value. This design can physically eliminate periodic power consumption peaks caused by clock synchronization, making the overall power consumption performance of the system closer to disordered shot noise.

[0037] Furthermore, the power compensation execution unit incorporates a multi-level adjustable capacitor array in its physical structure. These capacitors smooth current steps during charging and discharging, ensuring that the generated disturbance signal is no longer a harsh square wave at the physical observation level, but rather a continuous pulse waveform with biomimetic characteristics and a natural transition. This design not only enhances the shielding effect but also reduces the power integrity risks caused by high-speed current switching, ensuring the stability of the hardware accelerator at extreme operating frequencies.

[0038] This embodiment also employs a specific memory access mode designed for polynomial modular multiplication operations. To reduce instantaneous power density per unit area, the polynomial coefficients are interleaved and stored in different physically dispersed memory banks. When the acceleration core reads this data in parallel, the physical sources of current are uniformly distributed across the chip space. This, combined with the distributed disturbances generated by the spiking neural network control module, constructs a three-dimensional power consumption characteristic barrier.

[0039] Example 2: This example provides a hardware-accelerated parallel implementation system for quantum-resistant encryption algorithms, which is integrated into a security chip used in IoT terminals. Because IoT devices are extremely sensitive to power consumption, this example achieves high energy efficiency through fine-grained resource scheduling while maintaining strong side-channel defense capabilities.

[0040] The system described in this embodiment includes a quantum-resistant encryption acceleration core, which internally employs a streamlined array of parallel processing units. To achieve efficient lattice cryptography within a limited chip area, the acceleration core is specifically configured with a highly parallel matrix multiplier, which is directly connected to a number theory transformation accelerator via a multi-stage pipeline architecture. The output of the acceleration core interacts with other components of the system through a dedicated secure bus, ensuring data integrity during transmission.

[0041] The spiking neural network controller is deployed in the non-critical timing region of the chip and contains an array of multiple interconnected hardware neurons. Unlike Embodiment 1, lateral inhibition connections are established between the neurons here. This structure allows the generated pulse sequences to maintain randomness while possessing richer frequency components. The controller integrates a true random number generator based on physical thermal noise, which provides the neurons with initial firing excitation and dynamic threshold parameters. This injection of randomness at the physical level ensures that the generated power perturbations do not possess any statistically significant reproducibility over long time scales, blocking statistical attack paths based on multiple sampling.

[0042] The power consumption perturbation execution module employs a distributed layout. In this embodiment, the dummy load array is divided into dozens of tiny current-consuming units, evenly distributed among the computational logic units of the quantum encryption-resistant acceleration core. When the spiking neural network controller issues a trigger command, these distributed dummy loads perform differentiated current compensation according to preset weights. This spatially distributed perturbation can counteract near-field electromagnetic analysis attacks targeting the chip surface. Even if an attacker uses a high-resolution electromagnetic probe, it is difficult to accurately locate the specific physical location of the computational core and its execution state from the complex electromagnetic radiation background.

[0043] The status monitoring and feedback component implements closed-loop control at the hardware level. This component includes a high-precision instantaneous current sensing circuit capable of capturing nanosecond-level current pulses. Through internally integrated Fast Fourier Transform processing logic, the system can evaluate the entropy of the current system's total power consumption in the frequency domain in real time at the hardware level. If an abnormal energy concentration is detected at a specific frequency point, the feedback loop quickly issues instructions to adjust the discharge control parameters of the pulse neural network controller, eliminating these vulnerable frequency features by introducing more spectral dispersion characteristics.

[0044] In the application scenario of this embodiment, a parallel implementation method for a hardware-accelerated quantum-resistant encryption algorithm is executed in the following details. At the initial stage of system startup, the initialization module performs a physical self-test on the entire acceleration array and sets an upper limit for the power consumption perturbation based on the current battery level and ambient temperature. This range is strictly limited to within 15% of the normal operating power consumption of the acceleration core, thereby maximizing the device's battery life while ensuring physical security.

[0045] When the critical subroutine involved in key generation is initiated, the status monitoring probe quickly identifies the specific prefetch instruction for this type of task. Subsequently, the spiking neural network controller enters a high-frequency activation mode. The generated pulse signal at this time is not only random on the time axis, but its amplitude also varies with the level of the neuron's integral. This multi-dimensional randomness gives the current fluctuations generated by the power compensation execution unit extremely high information entropy.

[0046] To further enhance defense depth, the hardware accelerator in this embodiment employs a clock domain design that is completely asynchronous with the spiking neural network controller. The accelerator core operates at a clock frequency of several hundred megahertz, while the controller is driven by an independent on-chip oscillator with frequency jitter characteristics. This cross-clock domain architecture eliminates the synchronization between power consumption noise and the computation cycle, rendering the power trace superposition processing performed by attackers through clock alignment techniques meaningless.

[0047] In the polynomial operation processing flow, this embodiment introduces a data masquerading strategy. A certain proportion of pseudo-random interference data is inserted into the real vector data stream, and processed simultaneously by the acceleration core. Because the background noise generated by the spiking neural network control module and the power consumption generated by these pseudo-random operations intertwine, a physically robust shielding layer is constructed. This synergistic effect of algorithm-level pseudo-operations and physical-level biomimetic pulse perturbations enhances the system's robustness in complex electromagnetic environments.

[0048] Example 3: This example focuses on describing the optimization strategy of the parallelization implementation method of the quantum-resistant encryption algorithm when dealing with ultra-large-scale matrix operations, as well as its technical details in dealing with high-order differential power analysis attacks.

[0049] In step S1, for ultra-large-scale lattice cryptography operations, this embodiment introduces a multi-level distributed storage architecture to support parallelization acceleration. Each processing unit in the core computing array not only has a local cache but can also access a globally shared vector storage area through a high-speed interconnect network. When performing large-scale matrix multiplication, the system divides the original matrix into multiple sub-blocks and uses spatial permutation logic to map these sub-blocks to processing units that are not physically adjacent. The purpose of this operation is to disperse the current concentration caused by large-scale data flipping at the source and reduce the risk of side-channel leakage due to local power consumption abrupt changes.

[0050] In step S2, the spiking neural network control module introduces a dynamic synaptic evolution mechanism. The connection weights between hardware neurons are reconstructed in real time according to the task intensity of the acceleration core. When the system detects that a high-dimensional encryption operation is being performed, the control module automatically increases the activation density of the neuron array. At this time, multiple sets of transistor loads in the power compensation execution unit are turned on in a more complex combination mode. These load arrays adopt a special layout design, and their parasitic inductance and capacitance parameters are precisely matched to simulate the combined inductive and capacitive load characteristics of real logic gate circuits during switching. In this way, the generated interference current is not only close to the magnitude of the real power consumption, but its AC impedance characteristics are also highly consistent with those of the computing core.

[0051] For step S3, the key operation identification model is upgraded in this embodiment to a state machine-based deep feature comparison engine. This deep feature comparison engine can identify complex continuous instruction flow patterns, not just single sensitive instructions. For example, it can accurately predict upcoming modular exponentiation operations related to Fermat's Little Theorem. Several clock cycles before these operations begin, the identification engine activates pre-charging logic, allowing the spiking neural network control module to enter a warm-start state in advance, eliminating the delay when the defense mechanism is activated and ensuring the continuity and integrity of power masking.

[0052] In step S4, the generated biomimetic pulse waveform is further refined. Through multi-level bias voltage adjustment, the peak width, rise slope, and recovery time of the pulse signal all exhibit random distribution characteristics. This multi-parameter randomized pulse current drives the power compensation unit, forming a background substrate on the power line similar to the discharge of a complex biological neural network. This substrate signal has an extremely wide spectral coverage range, effectively burying all characteristic harmonic components generated by encryption operations below the noise floor level.

[0053] For step S5, the feedback control logic incorporates environmentally sensitive parameters. The system not only monitors the internal current but also acquires the chip's real-time temperature rise via a built-in temperature sensor. Since temperature changes affect transistor switching speed and leakage current, the feedback algorithm adjusts the neuron's firing threshold and refractory period based on a temperature compensation factor. This dynamic compensation mechanism ensures that, regardless of whether the environment is extremely cold or hot, the power consumption disturbances generated by the system are always maintained at an optimal level of statistical independence, preventing attackers from using ambient temperature as an auxiliary means to strip away interference signals.

[0054] Furthermore, the core computing array in this embodiment employs an asymmetric distribution of computational logic when performing specific transformation operations. Complex arithmetic logic operations are decomposed into multiple micro-operations triggered at different times, and these micro-operations are distributed across different regions in physical space. In conjunction with this, the spiking neural network controller prioritizes activating power compensation units physically closer to the currently active computing area based on spatial mapping relationships. This spatially dynamic following defense strategy further enhances the system's ability to resist local power consumption analysis by micro-probes.

[0055] The hardware acceleration system in this embodiment also possesses self-evolution capabilities. By periodically updating the neuron configuration parameters stored in non-volatile memory, the system's side-channel defense characteristics can be changed periodically. This means that even if an attacker establishes a certain level of power consumption prediction using a complex mathematical model over a period of time, these predictions will quickly become invalid as the system parameters are updated. This dynamically changing physical security boundary provides a solid guarantee for the long-term security of quantum-resistant encryption algorithms.

[0056] At the hardware implementation level, this system employs a multi-layered power distribution network. Although the acceleration core and power compensation unit share the main power input, they are locally isolated within the chip through a decoupling filter network. The disturbance current generated by the pulse neural network is introduced into the power network through a specially designed injection channel. This structure prevents high-frequency interference signals from flowing back into the operational logic, avoiding the negative impact of the defense mechanism on the accuracy of encryption operations. This ingenious circuit design achieves a harmonious balance between enhanced security and electrical performance.

[0057] In handling specific quantum-resistant algorithm steps such as number-theoretic transformations, this embodiment also employs instruction-level obfuscation technology. By inserting no-operation instructions or pseudo-computation instructions that do not change the logical result between critical computation instructions, and in conjunction with high-entropy power consumption perturbations synchronously generated by the spiking neural network control module, even the most advanced simple power analysis attacks cannot accurately delineate the instruction boundaries. This comprehensive protection from the microscopic instruction level to the macroscopic system level represents the deep application of this invention in the field of hardware security.

[0058] In summary, through meticulous optimization of the hardware architecture, algorithm flow, and physical layer defense mechanism in different embodiments, this invention not only solves the performance problem of quantum-resistant encryption algorithms in parallel implementation, but also constructs an adaptive, high-strength, and low-overhead side-channel defense system by introducing a biomimetic spiking neural network mechanism.

[0059] In this invention, the description of the pulse neural network control module relies entirely on the hardware units of integrated circuits, such as operational amplifiers, charge storage units, and logic gate arrays. These units perform predetermined logical functions through physical connections and the interaction of voltage and current. In all embodiments, the computation process, data processing, and logical judgment are described using purely technical language. For example, the process of potential change is described as the accumulation and discharge of charge and the crossing of logic thresholds; the analysis of signals is described as sampling of current waveforms, hardware comparison of similarity features, and register correction of feedback parameters. This approach clearly and accurately discloses the technical solution of this invention without using any mathematical formulas, which is sufficient for those skilled in the art to understand and implement it.

[0060] This invention successfully transforms complex mathematical defense logic into achievable hardware physical behavior through specific circuit structures and methodologies. This transformation not only enhances system security but also demonstrates the invention's advanced capabilities in electromechanical and software system integration. Through this in-depth technical disclosure, this invention provides a novel approach and reliable engineering path for physical layer security in the field of quantum-resistant encryption.

[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A hardware-accelerated parallel implementation method for quantum-resistant encryption algorithms, characterized in that, Includes the following steps: Step S1. Initialize the hardware acceleration environment and configure the quantum-resistant encryption core computing array. Construct a parallelized acceleration architecture consisting of multiple independent computing units with local memory and arithmetic logic processing capabilities. Perform vectorized decomposition on the lattice cryptographic operation logic in the quantum-resistant encryption algorithm to configure the core computing array to perform polynomial modular multiplication and matrix operations in parallel. Step S2. Integrate a hardware neuron circuit based on a leakage current integral triggering model in the non-computational region of the hardware accelerator to deploy a spiking neural network control module, and connect the output of the spiking neural network control module to a power-compensated execution unit containing multiple transistor load arrays, wherein the spiking neural network control module simulates the random firing behavior of biological neurons. Step S3. Capture the state of the instruction register inside the core computing array through a hardware monitoring probe, mark the sensitive mathematical operation instruction sequence involving key information or intermediate variable processing using a key operation identification model, and send an enable trigger signal to the spiking neural network control module to activate it when a preset key operation cycle is identified. Step S4. Using the non-periodic random pulse sequence generated by the spiking neural network control module, drive the power compensation execution unit to generate neural pulse-like power disturbances by switching the conduction state of the transistor load array, and deeply fuse the instantaneous power consumption trajectory of the core computing array with the random noise signal; Step S5. The total current waveform of the core computing array and the power compensation execution unit is collected in real time through the built-in current sampling module. The similarity index between the total current waveform and the power consumption characteristics of the standard encryption operation is calculated using the cross-correlation analysis algorithm. Based on the feedback control mechanism, the excitation parameters of the hardware neuron circuit are dynamically adjusted according to the similarity index to ensure that the total power consumption of the synthesized system presents the random characteristics of biological neural electrical signals in both the time domain and the frequency domain.

2. The method for parallelizing the hardware-accelerated quantum-resistant encryption algorithm according to claim 1, characterized in that, Step S1 specifically includes: configuring a dual-port static random access memory structure in the independent computing unit to perform parallel processing of data read and write operations; decomposing the polynomial modular multiplication operation into multiple vector operator streams and distributing the vector operator streams to different independent computing units; configuring a multi-level pipeline distribution strategy in the global control unit of the hardware accelerator to dynamically map matrix operation tasks to physical computing arrays according to the real-time load rate and task priority of hardware resources, so as to ensure that data flows in the pipeline in each clock cycle.

3. The method for parallelizing a hardware-accelerated quantum-resistant encryption algorithm according to claim 1, characterized in that, Step S2 specifically includes: integrating the hardware neuron circuit in the chip edge region far from the high-speed signal transmission line; constructing a charge accumulation unit using the subthreshold leakage current characteristics of transistors to simulate the spontaneous decay process of the membrane potential of biological neurons over time; writing preset weight parameters into the synaptic weight matrix through a configuration register and setting a membrane potential decay constant as a simulated bias voltage to control the nonlinear dynamic frequency of random spike discharges generated by the hardware neuron circuit; and connecting the transistor load array of the power compensation execution unit as a dummy load to the system main power line.

4. The method for parallelizing the hardware-accelerated quantum-resistant encryption algorithm according to claim 1, characterized in that, Step S3 specifically includes: deploying the hardware monitoring probe on the instruction distribution path inside the core computing array; pre-decoding the instructions entering the execution stage to identify the instruction type; the key operation identification model performing feature locking on the instruction sequences involved in number theory transformation operations and discrete Gaussian sampling operations; and triggering the enable trigger signal one clock cycle before the key operation instruction officially enters the execution pipeline to achieve time-domain alignment and coverage of the power consumption disturbance generated by the power compensation execution unit and the computing power consumption generated by the core computing array.

5. The method for parallelizing a hardware-accelerated quantum-resistant encryption algorithm according to claim 1, characterized in that, Step S4 specifically includes: after receiving the enable trigger signal, the spiking neural network control module starts the charge integration process of the internal neuron model; it uses a hardware random number generator to inject randomness into the initial level state of each neuron, so that the time point when the membrane potential exceeds the preset trigger threshold presents a non-deterministic distribution; when the potential exceeds the threshold, a random pulse signal with steep rising edge and slow falling edge characteristics is generated by the pulse generation circuit; the power compensation execution unit drives the internal power transistor array to switch rapidly between the on state and the off state, introducing non-periodic instantaneous current fluctuations on the power bus.

6. The method for parallelizing a hardware-accelerated quantum-resistant encryption algorithm according to claim 1, characterized in that, Step S5 specifically includes: the current sampling module captures the total current change of the system through a precision sampling resistor connected in series on the main power supply circuit; the digital signal processing unit performs in-depth analysis on the acquired current waveform and compares the real-time waveform with the stored encrypted computing power consumption template; when the similarity index exceeds a preset security threshold, the feedback control mechanism adjusts the refractory period parameter of the hardware neuron circuit; by changing the suppression duration of the hardware neuron circuit after generating a pulse, the frequency distribution and phase characteristics of the power consumption disturbance are corrected, and the phase-locked correlation between the power consumption disturbance and the main computing clock of the core computing array is eliminated.

7. The method for parallelizing a hardware-accelerated quantum-resistant encryption algorithm according to claim 1, characterized in that, The hardware neuron circuit adopts a leakage current integral triggering architecture. Within a preset sampling interval, the virtual membrane potential of the neuron is subtracted according to a preset attenuation coefficient to simulate spontaneous reset characteristics. The accumulation unit receives external charge stimulation from the hardware entropy source and stores it in the integrator. When the accumulated potential value in the integrator exceeds the dynamically adjusted voltage threshold, a logic spike is generated and the charge in the integrator is completely discharged to the reference level. The refractory period of the hardware neuron circuit is dynamically mapped according to the parallel execution dimension of the core computing array, and the spiking neural network control module adopts a clock domain asynchronous with the core computing array.

8. The method for parallelizing a hardware-accelerated quantum-resistant encryption algorithm according to claim 1, characterized in that, The power consumption compensation execution unit includes a multi-level adjustable capacitor array, which smooths the current step through the capacitor charging and discharging process and generates a continuous pulse waveform. When the core computing array performs polynomial modular multiplication, it adopts a polynomial coefficient interleaved storage mode, distributing the coefficients in multiple storage banks that are not physically adjacent. The power consumption disturbance generated by the spiking neural network control module adopts a spatially distributed layout. Based on the spatial mapping relationship of the active computing units in the core computing array, the power consumption compensation execution unit that is physically close to the active computing unit is activated, thus constructing a power consumption feature shielding barrier in the spatial dimension.

9. A hardware-accelerated parallel implementation system for quantum-resistant encryption algorithms, characterized in that, include: The quantum-resistant encryption acceleration core includes multiple processing unit arrays, a number theory transformation accelerator, and a parallel matrix multiplier. The acceleration core is configured with a pipelined structure for parallel execution of lattice cryptography operations and algebraic transformations, and the processing unit arrays exchange data through a high-speed interconnect network. The spiking neural network controller is deployed in a non-critical logic area of ​​a hardware chip and contains multiple mutually coupled hardware neuron units. The spiking neural network controller integrates a hardware random number generator to provide random initialization parameters and excitation sources for the hardware neuron units in order to generate non-periodic random trigger sequences. The power consumption perturbation execution module, which is electrically connected to the pulse neural network controller, consists of multiple adjustable dummy load arrays distributed around the anti-quantum encryption acceleration core. It is used to introduce non-periodic power consumption fluctuations in the system power supply circuit according to the random trigger sequence and to homogenize the power consumption radiation characteristics in physical space. The status monitoring and feedback component, connected to the quantum-resistant encryption acceleration core and the spiking neural network controller respectively, includes an instantaneous current sensing circuit and fast Fourier transform processing logic, used to analyze the entropy change of the synthesized total power consumption waveform in real time and dynamically adjust the discharge control parameters of the hardware neuron unit.

10. The hardware-accelerated parallel implementation system for quantum-resistant encryption algorithms according to claim 9, characterized in that, The hardware neuron units are configured with lateral suppression connections, and the spiking neural network controller is driven by an independent on-chip oscillator with frequency jitter characteristics. The state monitoring and feedback component also includes a temperature sensor, and the feedback control logic corrects the discharge threshold and refractory period of the hardware neuron units according to a temperature compensation factor. When performing computational tasks, the quantum-resistant encryption acceleration core inserts a predetermined proportion of pseudo-random interference data into the vector data stream, which is processed synchronously by the acceleration core. The power consumption generated by the pseudo-random interference data and the power consumption perturbation generated by the power consumption perturbation execution module are intertwined to form a shielding layer against physical side-channel attacks.

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