Oscillator control method and apparatus, computer device and medium

Abstract

This application discloses a control method, apparatus, computer device, and medium for an oscillator. The method includes: controlling a reconfigurable oscillator unit to switch between a physically non-cloning function (PCF) operating mode and a true random number generator (PRG) operating mode according to a received operation command; in PCF operating mode, controlling the delay path selection of the reconfigurable oscillator unit according to an externally input challenge configuration, and measuring the oscillation frequency of the reconfigurable oscillator unit under the challenge configuration and the complementary challenge configuration; comparing the oscillation frequency under the challenge configuration and the oscillation frequency under the complementary challenge configuration to generate a PCF response; and after generating the PCF response, restoring the configuration parameters of the reconfigurable oscillator unit in the previous PRG operating mode, so that the reconfigurable oscillator unit returns to the PRG operating mode.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of chip technology, and in particular to a method, apparatus, computer device, and medium for controlling an oscillator. Background Technology

[0002] In the field of hardware security, Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) are two core security primitives that are widely used in security scenarios such as device authentication, key generation, and random number generation.

[0003] A Programmable Fingerprint Function (PUF) is a circuit that utilizes unavoidable microscopic process variations in semiconductor manufacturing to generate a unique and difficult-to-clone "hardware fingerprint" for each chip. When a specific challenge is applied, the PUF generates a corresponding response based on its unique internal physical characteristics. One variation, the Loop-RO PUF, is a PUF based on a ring oscillator that enhances the uniqueness and reconfigurability of the response through a configurable loop delay structure. Specifically, the LOOP-RO PUF consists of multiple delay units connected in series to form a closed-loop oscillation loop. Each delay unit contains two selectable paths with random, small delay differences, selected by a multiplexer; this selection signal is the PUF's challenge bit. After applying a specific challenge, the LOOP-RO PUF generates a corresponding oscillation frequency. By measuring and comparing this frequency with the frequency of its complementary challenge, the bit sequence serving as the PUF response can be extracted. A TRNG (Transient Generator Number) is used to generate a bitstream with high randomness. Coherent sampling true random number generator is a commonly used structure that uses the phase jitter between two ring oscillators with similar frequencies as an entropy source. It has the advantages of simple structure and low power consumption, and is suitable for deployment in resource-constrained embedded systems.

[0004] In security chips, PUF and TRNG are typically implemented as two separate modules. While this discrete design has clear functions, it leads to problems such as low hardware resource utilization, increased chip area and power consumption, and increased system integration complexity. Especially in scenarios such as IoT devices and edge computing nodes that are sensitive to cost, area, and power consumption, this resource redundancy has become a bottleneck restricting the improvement of their security performance. Summary of the Invention

[0005] In view of this, embodiments of this application provide at least one control method, apparatus, computer device, and medium for an oscillator.

[0006] The technical solution of this application embodiment is implemented as follows: On one hand, embodiments of this application provide a method for controlling an oscillator, the method comprising: According to the received operation command, the reconfigurable oscillator unit is controlled to switch between a physically non-cloning function operating mode and a true random number generator operating mode, wherein the reconfigurable oscillator unit has a configurable delay path, and the operation command includes a physically non-cloning function mode command and a true random number generator mode command. In the physically unclonable operating mode, the delay path selection of the reconfigurable oscillator unit is controlled according to the challenge configuration of the external input, and the oscillation frequency of the reconfigurable oscillator unit is measured under the challenge configuration and the complementary challenge configuration. Compare the oscillation frequency under the challenge configuration with the oscillation frequency under the complementary challenge configuration to generate a physically unclonable functional response; After generating the physically unclonable function response, the configuration parameters of the reconfigurable oscillator unit in the previous true random number generator operating mode are restored, so that the reconfigurable oscillator unit returns to the true random number generator operating mode.

[0007] On the other hand, embodiments of this application provide a control device for an oscillator, the device comprising: A switching module is used to control a reconfigurable oscillator unit to switch between a physically non-cloning function operating mode and a true random number generator operating mode according to the received operation command, wherein the reconfigurable oscillator unit has a configurable delay path, and the operation command includes a physically non-cloning function mode command and a true random number generator mode command. The response module is configured to control the delay path selection of the reconfigurable oscillator unit according to an externally input challenge configuration in the physically unclonable function operating mode, measure the oscillation frequency of the reconfigurable oscillator unit under the challenge configuration and the complementary challenge configuration, and compare the oscillation frequency under the challenge configuration with the oscillation frequency under the complementary challenge configuration to generate a physically unclonable function response. The recovery module is used to restore the configuration parameters of the reconfigurable oscillator unit in the previous true random number generator operating mode after generating the physical unclonable function response, so that the reconfigurable oscillator unit returns to the true random number generator operating mode.

[0008] In another aspect, embodiments of this application provide a computer device, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the control method for the oscillator described above.

[0009] In another aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the control method for the oscillator described above.

[0010] In another aspect, embodiments of this application provide a computer program including computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps in the control method for implementing the above-described oscillator.

[0011] In another aspect, embodiments of this application provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the control method for the oscillator described above.

[0012] This application embodiment, through a reconfigurable oscillator hardware array and under unified state machine control, achieves dynamic reuse and on-demand switching of two security primitives: physically unclonable functionality and a true random number generator. After generating the PUF mode for unique device identity response, it can automatically recover and continue in the TRNG mode for high-entropy random number generation, thus completing two core security functions on a single hardware circuit. This deep reuse architecture significantly improves the utilization of hardware resources, effectively reduces chip area and power consumption, and reduces system integration complexity through standardized interfaces and automated mode management. It is particularly suitable for cost-, area-, and power-sensitive IoT and edge computing devices.

[0013] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0015] Figure 1 A schematic diagram illustrating the implementation flow of an oscillator control method provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the implementation process of device power-on and initialization provided in an embodiment of this application; Figure 3 This application provides a schematic diagram of a PUF command processing flow as an embodiment of the present application. Figure 4 A schematic diagram of a configurable ring oscillator structure provided in an embodiment of this application; Figure 5This application provides a schematic diagram of the composition structure of a control device for an oscillator. Figure 6 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0018] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0020] This application provides a method for controlling an oscillator. Figure 1 This is a schematic diagram illustrating the implementation flow of an oscillator control method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method includes: Step 101: According to the received operation command, control the reconfigurable oscillator unit to switch between a physically non-cloning function operating mode and a true random number generator operating mode, wherein the reconfigurable oscillator unit has a configurable delay path, and the operation command includes a physically non-cloning function mode command and a true random number generator mode command.

[0021] In this embodiment, an operation command refers to an instruction signal sent by an external host or processor to the control unit, used to instruct the system to perform a specific function. The physically unclonable function operating mode is a circuit operating state in which the system utilizes inherent hardware process variations to generate a digital fingerprint uniquely corresponding to the device. The true random number generator operating mode is another circuit operating state in which the system utilizes random physical noise of the circuit to generate a random bit sequence with high entropy. A reconfigurable oscillator unit is an electronic circuit module containing a closed-loop oscillation loop formed by multiple delay units connected in series, and each delay unit contains different delay paths selectable by configuration signals, thereby allowing the oscillation frequency of the entire oscillator to be adjusted.

[0022] The system drives a dual-mode control state machine to switch operating modes based on operation commands received from a unified interface. When the operation command is a physically non-cloning function mode command, the state machine switches the system from the current true random number generator operating mode to the physically non-cloning function mode. When the operation command is a true random number generator mode command, the state machine switches the system from the physically non-cloning function mode back to the true random number generator operating mode. The mode switching process is controlled by a hardware state machine, which selects different delay paths by configuring a multiplexer within the reconfigurable oscillator unit, thereby changing the oscillator's operating characteristics to adapt to the requirements of different modes.

[0023] Step 102: In the physically unclonable function operating mode, the delay path selection of the reconfigurable oscillator unit is controlled according to the challenge configuration of the external input, and the oscillation frequency of the reconfigurable oscillator unit under the challenge configuration and the complementary challenge configuration is measured.

[0024] In this embodiment, the challenge configuration refers to a set of externally input binary control signals used to specify the specific path selection for each delay unit in the reconfigurable oscillator unit. The complementary challenge configuration refers to another set of binary control signals that are logically opposite to the challenge configuration, i.e., the configuration formed by inverting each challenge bit. The oscillation frequency refers to the rate at which the reconfigurable oscillator unit generates a periodic electrical signal under a specific configuration, typically measured in Hertz.

[0025] In physically non-cloning operating mode, the system drives the reconfigurable oscillator unit based on an external challenge configuration received via the interface register. The system loads the challenge configuration signal into the multiplexer of each delay unit in the oscillator unit, thereby selecting a specific set of delay path combinations. Subsequently, the system activates the frequency measurement module, which uses a high-precision counter to count the periods of the oscillator output within a fixed time window determined by the system clock, thereby calculating the oscillation frequency under the challenge configuration. After completing this measurement, the system applies a complementary challenge configuration to the same oscillator unit and repeats the above counting process to measure the oscillation frequency under the complementary challenge configuration.

[0026] Step 103: Compare the oscillation frequency under the challenge configuration with the oscillation frequency under the complementary challenge configuration to generate a physically unclonable functional response.

[0027] In this embodiment, the physically unclonable function response refers to a sequence of binary bits generated by the system by comparing two oscillation frequencies. This sequence is unique and unclonable, and can be used for device authentication or key generation.

[0028] After obtaining the measured values ​​of the oscillation frequencies under the challenge configuration and the complementary challenge configuration, the system calls a comparator circuit to process these two frequency values. The comparator circuit performs a differential operation, specifically determining whether the frequency value under the challenge configuration is greater than the frequency value under its complementary challenge configuration. If it is greater, it outputs bit 1; if it is less, it outputs bit 0. This process is performed in parallel for each pair of oscillator units in the oscillator array, ultimately combining all comparison results into a complete, physically unclonable functional response bit sequence of predetermined length.

[0029] Step 104: After generating the physically unclonable function response, restore the configuration parameters of the reconfigurable oscillator unit in the previous true random number generator operating mode, so that the reconfigurable oscillator unit returns to the true random number generator operating mode.

[0030] In this embodiment, the configuration parameter refers to a set of values ​​stored in a register that defines the specific path selection state required by the reconfigurable oscillator unit to achieve the target oscillation frequency in true random number generator operating mode. The previous true random number generator operating mode refers to the operating state of the system before performing physically unclonable functions, used for generating random numbers.

[0031] After generating a physically unclonable function response and outputting the result, the system automatically triggers the mode recovery process. The dual-mode control state machine reads the previously saved configuration parameters for the true random number generator operating mode from a dedicated storage register. The state machine reloads these configuration parameters into the control ports of the reconfigurable oscillator units, restoring the path selection of each delay unit to its state before the physically unclonable function operation. Once the configuration recovery is complete, the state machine restarts the monitoring functions of the coherent sampling circuit and the automatic calibration module, enabling the system to seamlessly switch back to the true random number generator operating mode and continue generating true random numbers.

[0032] This application embodiment, through a reconfigurable oscillator hardware array and under unified state machine control, achieves dynamic reuse and on-demand switching of two security primitives: physically unclonable functionality and a true random number generator. After generating the PUF mode for unique device identity response, it can automatically recover and continue in the TRNG mode for high-entropy random number generation, thus completing two core security functions on a single hardware circuit. This deep reuse architecture significantly improves the utilization of hardware resources, effectively reduces chip area and power consumption, and reduces system integration complexity through standardized interfaces and automated mode management. It is particularly suitable for cost-, area-, and power-sensitive IoT and edge computing devices.

[0033] Optionally, the reconfigurable oscillator unit is configured in the following manner: Step 201: Connect multiple configurable delay units in series to form a closed-loop oscillation circuit to constitute the reconfigurable oscillator unit, wherein each configurable delay unit contains at least two paths with different delay characteristics.

[0034] In this application embodiment, a configurable delay unit is an electronic circuit module whose function is to introduce a specific time delay; delay characteristic refers to the length of time required for a signal to pass through the unit path; closed-loop oscillation circuit refers to a circuit structure formed by connecting multiple delay units end to end to form a loop, which can generate a periodic oscillation signal; reconfigurable oscillator unit refers to an oscillator circuit module whose internal connections or parameters can be changed through configuration, thereby adjusting its output oscillation characteristics.

[0035] The system first constructs multiple configurable delay units. Each configurable delay unit has at least two signal transmission paths, which have different inherent delay times due to differences in physical design or manufacturing processes. These configurable delay units are connected in series, meaning the output of the first delay unit is connected to the input of the second, and so on, until the output of the last delay unit is fed back to the input of the first delay unit, thus forming a complete closed-loop oscillation circuit where the signal can cyclically repeat. This closed-loop structure forms the basis of a reconfigurable oscillator unit, whose oscillation frequency is determined by the total delay of all delay units in the loop.

[0036] Step 202: Configure a path selector for each configurable delay unit, wherein the control signal of the path selector is used to select a specific delay path for the configurable delay unit.

[0037] In the embodiments of this application, the path selector is a digital logic circuit or multiplexer, whose function is to select one path from multiple input paths and connect it to the output terminal according to the input control signal.

[0038] The system equips each configurable delay unit with a path selector. The inputs of these path selectors are connected to at least two different delay paths within the delay unit. The output of the path selector serves as the overall output of the configurable delay unit. The system precisely specifies which delay path is currently active and connected by applying an independent control signal to each path selector. This control signal directly determines the specific delay time experienced by the signal flowing through the delay unit, thus becoming a key control point for subsequently adjusting the oscillation characteristics of the entire oscillator unit.

[0039] Step 203: Assemble multiple reconfigurable oscillator units into an oscillator array and configure a unified control state machine for the oscillator array. The control state machine is used to manage the state switching of the oscillator array between the physically unclonable function working mode and the true random number generator working mode.

[0040] In this embodiment, an oscillator array refers to a collection of multiple independent oscillator units arranged according to certain rules and working together; a control state machine is a digital logic circuit that switches between a finite number of states based on the current input and preset state transition rules to control the system's workflow; a physically unclonable function operating mode refers to a state in which the circuit is configured to generate a unique response using inherent physical differences in the hardware; a true random number generator operating mode refers to a state in which the circuit is configured to generate a random bit sequence using physical noise sources.

[0041] Multiple reconfigurable oscillator units fabricated by the system are combined to form an oscillator array. A unified control state machine is designed and configured for this oscillator array. This control state machine is programmed to manage the core operating mode of the entire array. Based on external commands or internal conditions, it issues control signals to synchronously switch all oscillator units in the array between a physically non-cloning function operating mode and a true random number generator operating mode. In the physically non-cloning function mode, the state machine controls the path selector to be configured according to an externally provided challenge bit; in the true random number generator mode, the state machine controls the path selector to be set according to the configuration derived from an internal calibration algorithm and manages the random number generation process, including coherent sampling.

[0042] This application embodiment achieves dynamic reuse and seamless switching between two functions—physical non-cloning functionality and true random number generator—through configurable delay paths and unified state machine control. This significantly reduces the number of independent circuit modules required in the chip, lowers the overall hardware area and power consumption, and simplifies system integration complexity.

[0043] Optionally, step 101 includes: Step 1011: Upon receiving a physical non-cloning function operation command through the unified interface, pause the random number generation process in the current true random number generator operating mode of the reconfigurable oscillator unit.

[0044] In this embodiment, the unified interface refers to the control and status register interface provided by the system, which conforms to the RISC-VK standard and extends with custom encoding, for receiving commands and data from the host. The Physically Unclonable Function (PUF) operation command is a format-specific instruction transmitted through this interface, instructing the system to perform PUF-related operations, such as generating a device uniqueness response. The reconfigurable oscillator unit refers to a closed-loop oscillation circuit composed of multiple delay units connected in series, where each delay unit contains a hardware circuit structure that can select different paths via a multiplexer. This structure can operate in PUF mode or TRNG mode depending on external configuration. The true random number generator operating mode is a system operating state in which the reconfigurable oscillator unit is configured to use phase jitter for coherent sampling to continuously generate a high-entropy random bit stream.

[0045] The system continuously listens for commands from an external host through its unified interface, which conforms to the RISC-VK standard and extends PUF-related coding. When the system detects that the interface has received a specifically coded instruction whose format is recognized as a physically unclonable functional operation command, the system's control unit immediately responds. The control unit then generates control signals and sends them to the dual-mode control state machine responsible for managing the reconfigurable oscillator array and the associated measurement and interface units. These control signals instruct the coherent sampling circuit to stop its phase comparison and counting operations and instruct the automatic calibration module to pause its continuous monitoring and adjustment activities. This process ensures that the phase jitter-based random number sampling and generation process currently being performed by the reconfigurable oscillator unit is forcibly interrupted, preparing for the subsequent switching of operating modes.

[0046] Step 1012: Save the current configuration parameters of the reconfigurable oscillator unit in the true random number generator operating mode to the specified storage area.

[0047] In this embodiment, configuration parameters refer to a set of values ​​or states that define the operating characteristics of the reconfigurable oscillator unit. In TRNG operating mode, these parameters are determined after optimization through an automatic calibration process to ensure that the frequency difference of each pair of oscillators meets the requirements for high-quality random number generation. Specifically, these parameters may include the path selection state of the multiplexer in each delay unit and other control bits that affect the oscillation frequency. The designated storage area is a pre-allocated non-volatile or volatile memory space within the system, specifically used for temporarily storing context information during operating mode switching, such as a dedicated configuration register file or a specific address range of on-chip SRAM.

[0048] After successfully pausing the TRNG's random number generation process, the system's control unit initiates a configuration saving routine. The control unit first reads all active configuration parameters related to the TRNG's operating mode from the configuration registers of the reconfigurable oscillator array. These parameters precisely describe the path selection state of each delay unit in each oscillator cell and are crucial for maintaining the current TRNG output entropy quality and performance. Subsequently, the control unit writes the entire set of configuration parameters to a predefined, designated storage area via the internal data bus. This storage process ensures that the TRNG's precise operating state is completely backed up, enabling accurate reconstruction of the pre-interruption operating environment when the TRNG mode needs to be restored later.

[0049] Step 1013: Switch the state of the control state machine from the true random number generator working state to the physical non-cloning function working state.

[0050] In this embodiment, the control state machine is a hardware logic unit within the system. Based on the input command and the current state, it outputs a corresponding sequence of control signals according to a predefined state transition diagram to coordinate the behavior of the entire system under different operating modes. The True Random Number Generator (TRNG) operating state is a stable state of the control state machine. In this state, the state machine outputs control signals to maintain various operations in TRNG mode, such as calibration monitoring, coherent sampling, and random number output. The Physically Unclonable Function (PUF) operating state is another stable state of the control state machine. In this state, the state machine outputs control signals to drive various operations in PUF mode, such as configuring the oscillator according to the challenge, performing frequency measurement, and response comparison.

[0051] After saving the configuration parameters, the system's control unit sends a clear state transition trigger signal to the dual-mode control state machine. Upon receiving this trigger signal, the control state machine's internal logic, based on the pre-designed state transition conditions, executes a transition from the true random number generator operating state to the physically unclonable function (PUF) operating state. With the state machine's state transition, the control signals output to various system modules also change. These new control signals reconfigure the functions of the measurement and interface unit: stopping TRNG-related health checks and preparing to start the PUF frequency measurement module; simultaneously, the state machine's output signals also indicate that the system is ready to receive and apply the upcoming PUF challenge configuration to the reconfigurable oscillator array. At this point, the system's global operating mode has completed the transition from random number generation to device authentication.

[0052] This application embodiment receives commands through a unified hardware interface, enabling dynamic and seamless pausing of the ongoing true random number generation service, complete preservation of its precise runtime configuration, and rapid switching of the entire hardware architecture to a physically unclonable functional operating mode. This series of operations is automatically completed by the hardware state machine without deep software intervention, achieving time-division multiplexing of PUF and TRNG functions on the same set of shared reconfigurable oscillator hardware.

[0053] Optionally, step 101 further includes: Step 1014: Based on the challenge configuration data contained in the physical non-cloning function operation command, decode the challenge configuration data into a path selection control signal for each of the reconfigurable oscillator units.

[0054] In this embodiment, the system receives and temporarily stores physically unclonable function operation commands from the host through its unified interface register. The command parsing unit extracts the "challenge configuration data" field from the command. Subsequently, the system's control logic decodes the challenge configuration data according to predefined encoding rules. The decoding process maps and splits the global configuration data into a set of independent path selection control signals for each reconfigurable oscillator unit in the array. These control signals are output to the corresponding oscillator unit control port, providing direct input for the execution of step 1015.

[0055] Step 1015: Reconfigure the path selector inside each of the reconfigurable oscillator units using the decoded path selection control signal to set a specific delay path combination for the reconfigurable oscillator unit in the physically unclonable function operating mode.

[0056] In this embodiment, a specific delay path combination refers to a specific set of signal transmission paths formed in the entire oscillator array after all reconfigurable oscillator units in the system have been configured according to their respective path selection control signals. This combination directly determines the overall oscillation frequency characteristics of the entire array in the physically non-cloning functional mode.

[0057] The system decodes the path selection control signal and sends it in parallel via the internal bus to each corresponding reconfigurable oscillator unit in the oscillator array. Each oscillator unit's internal path selector receives its own dedicated control signal. Based on the signal's level, the path selector performs a switching action, activating one of its two or more selectable delay paths while deactivating the others. After this configuration process, the selected delay paths within all oscillator units together form a specific combination of delay paths tailored to the current physically unclonable functional challenge. This hardware configuration allows the oscillator array to switch from a true random number generator operating mode to a physically unclonable functional operating mode, providing the circuitry basis for generating a unique frequency response corresponding to the current challenge.

[0058] This application embodiment precisely decodes and applies the high-level abstract challenge configuration data to the reconfigurable hardware circuit. The system can dynamically and accurately control the internal structure of the oscillator array, enabling it to quickly adapt to the requirements of the physically unclonable function mode. This is the foundation for ensuring the uniqueness and reliability of the physically unclonable function response. It is also the core technology for achieving efficient and flexible reuse of the same hardware resource between the two security primitives of physically unclonable function and true random number generator. This achieves the overall technical effect of saving chip area, reducing power consumption, and simplifying system integration complexity.

[0059] Optionally, step 102 includes: Step 1021: Use the system clock as a reference signal to drive the counter.

[0060] In this embodiment, the system clock is a periodic, highly stable timing signal generated within a computer or digital system, providing a time reference for the synchronized operation of various components within the system. A counter is a digital circuit or logic unit whose function is to increment or decrement its count upon receiving a trigger signal.

[0061] The system uses an internally generated system clock signal with a fixed frequency as its reference timing source. This system clock signal is directly connected to the clock input of the counter circuit in the frequency measurement module, providing drive pulses for the counter's operation. This configuration ensures that the counter's clock cycle is synchronized with the system master clock, providing a stable and predictable time reference for subsequent frequency measurements.

[0062] Step 1022: Under the challenge configuration, start the counter to count the oscillation cycles of a first specified number of the reconfigurable oscillator units, stop counting after a fixed first time window, and convert the count value into a first frequency measurement value.

[0063] In this embodiment, the challenge configuration is a set of control signals or data used to select a specific delay path within the reconfigurable oscillator unit. The reconfigurable oscillator unit is a ring oscillator circuit whose oscillation frequency can be adjusted by an external configuration signal. The oscillation period refers to the time it takes for the oscillator output signal to complete one full cycle.

[0064] Based on the received challenge configuration data, the system uses control logic to configure a specified number of reconfigurable oscillator units into corresponding internal delay path combinations. After configuration, the system simultaneously starts these oscillator units to begin oscillation. Simultaneously, the system activates a counter driven by the system clock and begins counting the edges of the oscillation periods output by the specified oscillator units. The system presets a fixed time window length. When the counter starts and passes through this preset first time window, the system control logic issues a stop signal, and the counter stops counting. The system then reads the final count value of the counter within this time window and, based on the relationship frequency = count value / time window length, converts this count value into a first frequency measurement representing the oscillation frequency.

[0065] Step 1023: Under the complementary challenge configuration, restart the counter to count the oscillation periods of the first specified number of reconfigurable oscillator units, stop counting after the same first time window, and convert the count value into a second frequency measurement value.

[0066] In the embodiments of this application, the complementary challenge configuration is a set of control signals or data that are the opposite of the original challenge configuration logic. It is usually obtained by inverting each bit of the original challenge configuration and is used to select another delay path in the oscillator unit that was not selected by the original challenge.

[0067] The system switches the configuration of the reconfigurable oscillator unit from the original challenge configuration to its corresponding complementary challenge configuration. After the configuration update, the system restarts the counter and resets it to zero. The counter begins a new round of counting for the oscillation cycles of the same set of specified number of oscillator units already in complementary configurations. The system uses the exact same fixed time window length as in step 1022 as the counting duration. When the first time window is reached again, the system stops the counter. The system reads the count value and uses the same conversion method to calculate the second frequency measurement value.

[0068] Step 1024: Repeat the acquisition process of the first frequency measurement value and the second frequency measurement value a second specified number of times, and calculate the average value of the first frequency measurement value and the second frequency measurement value respectively to eliminate the influence of instantaneous jitter.

[0069] In this embodiment, the first frequency measurement value refers to the frequency value obtained from a single measurement under the original challenge configuration. The second frequency measurement value refers to the frequency value obtained from a single measurement under the complementary challenge configuration. The average value is the result of dividing the sum of a set of values ​​by the number of values ​​in the set, and is used to characterize the central tendency of the set of data.

[0070] The system control logic repeatedly executes the complete measurement process described in steps 1022 and 1023, with the number of repetitions determined by a preset second specified number. In each loop, the system records the obtained first frequency measurement value and the second frequency measurement value, respectively. After completing all specified number of loops, the system sums all recorded first frequency measurement values ​​and divides by the number of loops to calculate the average value of the first frequency measurement values. Simultaneously, the system sums all recorded second frequency measurement values ​​and divides by the number of loops to calculate the average value of the second frequency measurement values. This averaging process effectively filters out instantaneous frequency jitter caused by factors such as circuit noise and power supply fluctuations, obtaining measurement values ​​that stably reflect the inherent frequency characteristics of the oscillator under both configurations, laying the foundation for the subsequent reliable generation of PUF response bits.

[0071] This application embodiment achieves digital frequency measurement by counting the periods of a configurable oscillator within a fixed time window, using a highly stable system clock as a reference. By performing symmetrical measurements under challenging and complementary challenges and averaging multiple samples, the system can effectively eliminate the influence of environmental noise and transient circuit jitter on the measurement results, thereby extracting stable and unique frequency difference information determined by chip manufacturing process deviations.

[0072] Optionally, step 103 includes: Step 1031: Input the average value of the first frequency measurement and the average value of the second frequency measurement into the comparator.

[0073] In this embodiment, the system uses the average value of the calculated first frequency measurement and the average value of the second frequency measurement as two input signals, which are simultaneously transmitted to the two data input ports of the comparator. This operation completes the loading of data required for the comparison process, preparing for subsequent logical judgment and bit output. The system completes this data transmission through an internal data bus or a dedicated connection path.

[0074] Step 1032: If the average value of the first frequency measurement is greater than the average value of the second frequency measurement, the comparator outputs a first logic value as a physical non-cloning function response for the current bit.

[0075] In this embodiment, the comparator's internal circuitry continuously monitors the values ​​of its two input ports. When the comparator detects that the value at its first input port is consistently greater than the value at its second input port, its internal logic is triggered. The system controls the comparator to output an electrical signal representing the greater than relationship from its output port; this signal is encoded as a predefined first logic value. This output value is latched by the system and recorded as the PUF response bit corresponding to the currently processed reconfigurable oscillator unit.

[0076] Step 1033: If the average value of the first frequency measurement is less than the average value of the second frequency measurement, the comparator outputs a second logic value as a physical non-cloning function response for the current bit.

[0077] In this embodiment, the comparator's internal circuitry continuously monitors the values ​​of its two input ports. When the comparator detects that the value at its first input port is consistently less than the value at its second input port, another set of internal logic is triggered. The system controls the comparator to output an electrical signal representing a "less than" relationship from its output port; this signal is encoded as a predefined second logic value. This output value is latched by the system and recorded as the PUF response bit corresponding to the currently processed reconfigurable oscillator unit.

[0078] Step 1034: Traverse all the reconfigurable oscillator units in the oscillator array, generate the response bits corresponding to each reconfigurable oscillator unit in sequence, and combine all the response bits into a complete physically unclonable functional response sequence.

[0079] In this embodiment, the system's control unit sequentially selects the next reconfigurable oscillator cell in the oscillator array according to a preset index order. For each selected cell, the system repeatedly executes the frequency average comparison and bit generation process described in steps 1031 to 1033. Each time a response bit is generated, the system stores it in a designated register or memory buffer. After all oscillator cells have been processed, the system concatenates or combines all the sequentially arranged response bits in the storage area to form a complete binary bit stream with a length related to the number of cells in the oscillator array. This bit stream is the complete physically unclonable functional response sequence generated by this PUF operation.

[0080] This application embodiment deterministically transforms frequency differences caused by minute, random process variations into binary response bits of 0 or 1 by comparing the average oscillation frequency of each reconfigurable oscillator unit under two different challenge configurations. By traversing the entire array and performing this operation on all units, the system can efficiently generate a sizable PUF response sequence with high uniqueness and randomness. This sequence can be directly used for device authentication or key generation, and the entire process is automatically completed by hardware logic, ensuring the reliability and speed of response generation.

[0081] Optionally, step 104 includes: Step 1041: After the physical unclonable function response is read externally or after a third specified time, a mode recovery event is triggered.

[0082] In this embodiment, the mode recovery event is an internal signal generated by system hardware or control logic to indicate that the system needs to switch back from the current physically non-clonable function operating mode to the previous true random number generator operating mode. The triggering condition of this event is determined by preset logic rules.

[0083] The system continuously monitors the status of the output interfaces related to the Physically Unclonable Function Response (PUNCR) and an internal timer. When the system detects that an external device has successfully read the generated PUNCR data through a standard interface, or when the internal timer reaches a preset third specified time threshold, the system hardware control logic automatically generates a mode recovery event signal. This signal is sent to the system's core control state machine as a trigger instruction to initiate the mode recovery process.

[0084] Step 1042: Read the previously saved configuration parameters of the true random number generator operating mode from the specified storage area.

[0085] In this embodiment, the designated storage area is a segment of address space pre-allocated within or outside the system's non-volatile or volatile memory for temporary storage of specific data. In this step, this area is specifically used to store key configuration parameters in the true random number generator's operating mode.

[0086] Upon receiving a mode recovery event signal, the system's control unit performs a read operation. Based on a predefined address mapping, the control unit generates address and control signals to access the specified storage area. In response to this access request, the storage controller reads a set of configuration parameter data previously saved when switching to the physically non-cloneable mode from the physical address of the specified storage area. This configuration parameter data is then transmitted back to the system's control unit or configuration register loading module via the data bus.

[0087] Step 1043: Reload the read configuration parameters into the path selector of the reconfigurable oscillator unit to restore the original working state of the reconfigurable oscillator unit in the true random number generator working mode.

[0088] In this embodiment, the configuration parameter data read by the system is distributed to each reconfigurable oscillator unit via an internal configuration bus. Each oscillator unit's internal configuration register receives and latches the corresponding parameter bits. These parameter bits, as control signals, are directly input to the path selector of each oscillator unit. Based on these control signals, the path selector switches its internal switch to the corresponding connection state, thereby restoring the delay path configuration of the oscillator loop to a state completely consistent with the previous true random number generator operating mode. This process restores the electrical characteristics and operating points of all oscillator units.

[0089] Step 1044: Switch the state of the control state machine from the physically unclonable function working state back to the true random number generator working state, and restart the random number generation process.

[0090] In this embodiment, after the oscillator configuration is restored, the system control logic sends a state switching command to the control state machine. The control state machine, based on its internal state transition diagram, changes its current state from representing the operation of the physically non-cloning function back to representing the operation of the true random number generator. Along with the state switch, the state machine outputs a corresponding sequence of control signals. These signals re-enable the functional circuits related to the true random number generator, including the coherent sampling circuit and the health monitoring counter, and initiate the control timing for the random number generation process. The system then begins, based on the restored oscillator configuration, to continuously acquire phase jitter and generate a true random number bit stream, providing services externally through a unified interface.

[0091] This application embodiment ensures the continuity of TRNG's working state by saving and restoring key configuration parameters and precisely controlling the switching of the hardware state machine. Its entropy source quality and randomness are not affected by PUF operations, thereby realizing the efficient and reliable dynamic reuse of two security primitives on a single hardware platform, significantly improving hardware resource utilization and reducing the overall power consumption and area of ​​the system.

[0092] Optionally, the method further includes: Step 301: In the physically unclonable function operating mode, keep the health monitoring circuit of the true random number generator in the on state.

[0093] In this embodiment, the true random number generator is a circuit module that uses physical noise sources to generate bit sequences with unpredictable statistical characteristics. The health monitoring circuit is a functional unit within the system used to continuously monitor and evaluate the randomness quality of the true random number generator's output signal. It ensures the health of the entropy source by analyzing the statistical characteristics of the output signal.

[0094] When the system performs authentication operations in the physically unclonable operating mode, its control unit maintains the power supply and clock signal to the true random number generator health monitoring circuit, ensuring that the circuit is active and operational. The system does not disable the health monitoring function due to mode switching; this circuit continues to run in the background, providing a foundation for subsequent security attack detection.

[0095] Step 302: The output signal of the reconfigurable oscillator unit is continuously sampled by the health monitoring circuit.

[0096] In this embodiment, the system continuously captures and digitizes the periodic electrical signals generated by the reconfigurable oscillator unit operating in a physically non-cloning functional mode through a sampling module within the health monitoring circuit, using a fixed sampling rate driven by the system clock. The sampling process is uninterrupted, continuously acquiring signal sample sequences reflecting the current operating state of the oscillator.

[0097] Step 303: Calculate the real-time statistical characteristics of the sampled data and compare the real-time statistical characteristics with the baseline statistical characteristics established in the working mode of the true random number generator.

[0098] In this embodiment, real-time statistical characteristics refer to the quantified feature values ​​obtained after calculating a continuous data sample obtained from the latest sampling, such as the variance and mean of the data sequence. Benchmark statistical characteristics are a set of reference feature value ranges established and stored by the system in true random number generator mode after a calibration process, through long-term sampling and analysis of the output of the healthy oscillator; these represent the statistical characteristics under normal, interference-free conditions.

[0099] The system's health monitoring circuit's internal computing unit segments the continuously sampled data stream into fixed window lengths. For each data window, the computing unit executes a predetermined statistical algorithm to calculate the real-time statistical characteristic parameters of the data within that window. Subsequently, the comparison unit compares these real-time calculated parameter values ​​with a reference statistical characteristic parameter range pre-stored in non-volatile memory or registers to determine whether the real-time values ​​deviate from the reference range.

[0100] Step 304: If the deviation between the real-time statistical characteristics and the baseline statistical characteristics exceeds a preset security threshold, a potential security attack is determined, a security fault signal is generated, and the current physical unclonable function response is stopped.

[0101] In this embodiment, the safety threshold is a predefined and stored numerical limit used to quantify the allowable range of statistical characteristic deviations. The safety fault signal is a logic level signal or interrupt signal generated by the system when an anomaly is detected, used to report the safety event to other control modules of the system.

[0102] When the system's comparison unit detects that the absolute value of the deviation between the calculated real-time statistical characteristic parameter value and the stored baseline statistical characteristic parameter value exceeds a preset safety threshold, the judgment logic confirms a safety anomaly event. The system then triggers the safety protocol, generates a high-level safety fault signal, and sends it to the control unit. Simultaneously, the system control unit immediately terminates the output flow of the current physically unclonable function response, clears the output buffer, and may notify the upper-layer host via an interrupt mechanism, thereby preventing potentially tampered or unreliable device authentication information from being used.

[0103] This application embodiment can effectively detect oscillator behavior anomalies caused by malicious attacks such as external signal injection by comparing the differences between the current signal statistical characteristics and known normal benchmarks. Once a deviation exceeding the safety threshold is detected, the system can react quickly, interrupt the output of unreliable authentication information and issue an alarm, thereby enhancing the active defense capability and anti-attack resistance of the entire security primitive module at the hardware level and ensuring the reliability of security functions under the dynamic reuse architecture.

[0104] Optionally, refer to Figure 2 The specific power-on and initialization process of the device in this embodiment is as follows: Step S1: After the system is powered on and reset, the control unit automatically enters the default TRNG mode; Step S2: Start the automatic calibration process; Step S3: Measure the variance and mean of the random number output of each pair of oscillators and calculate the required configuration range; Step S4: Verify that the output entropy quality meets the RISC-VK standard by measuring the mean / variance of random numbers; Step S5: Store the optimal TRNG configuration parameters; Step S6: Use the calibrated configuration to continuously generate random numbers. The 16 oscillator groups can generate 16-bit random numbers at a time. Step S7: Perform light health checks periodically; Step S8: Provide random number output through a unified interface.

[0105] Optionally, refer to Figure 3 The PUF command processing flow in this embodiment is as follows: Step P1: The host initiates a PUF operation by sending a PUF command through a unified interface and entering the PDF state machine. Step P2: Pause the current TRNG operation; Step P3: Reconfigure the 16 oscillators according to the challenge configuration; Step P4: Start the frequency measurement module. The specific measurement method is to use a counter to measure the number of cycles of the oscillator within a fixed clock interval, perform 1024 consecutive measurements, take the average to remove the influence of randomness, and obtain its stable frequency value. Step P5: Perform complementary challenge measurements for differential processing; Step P6: Extract 32-bit (16 groups, 2 in each group) response sequences (e.g., the comparison result of challenge frequency and complementary challenge frequency is greater than 1 and less than 0). Step P7: Write the PUF response to the output register; Step P8: After the result is read, the previously saved TRNG configuration is automatically restored; Step P9: Restart TRNG and seamlessly switch back to random number generation.

[0106] Optionally, refer to Figure 4 The reconfigurable LOOP-RO oscillator array consists of 16 groups (32 units) of configurable LOOP-RO oscillator elements, each 32 units long. Its configuration includes: PUF mode selects a specific latency path based on the challenge configuration; TRNG mode is configured as a fixed frequency mode based on the calibration results; The dual-mode control state machine includes: managing the switching between PUF mode and TRNG mode.

[0107] The measurement and interface unit includes: a PUF frequency measurement module that measures the average oscillation period under a 32-bit PUF challenge and its complementary challenge based on the system clock, compares the two, and outputs a 32-bit PUF response; a coherent sampling circuit is a dedicated phase comparator and counter for COSOTRNG, and an automatic calibration module; automatic TRNG calibration is performed upon power-up, and environmental changes and performance indicators are continuously monitored in TRNG mode. The unified interface register provides a CSR interface compliant with the RISC-V K standard, while adding custom encoding to support the transmission of PUF challenges and responses.

[0108] Based on the foregoing embodiments, this application provides a control device for an oscillator. The device includes various units and modules included in each unit, which can be implemented by a processor in a computer device; of course, it can also be implemented by specific logic circuits. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0109] Figure 5 This is a schematic diagram of the composition structure of a control device for an oscillator provided in an embodiment of this application, as shown below. Figure 5 As shown, the device includes: The switching module 401 is used to control the reconfigurable oscillator unit to switch between a physically non-cloning function operating mode and a true random number generator operating mode according to the received operation command, wherein the reconfigurable oscillator unit has a configurable delay path, and the operation command includes a physically non-cloning function mode command and a true random number generator mode command. The response module 402 is configured to, in the physically unclonable function operating mode, control the delay path selection of the reconfigurable oscillator unit according to the challenge configuration input by an external input, measure the oscillation frequency of the reconfigurable oscillator unit under the challenge configuration and the complementary challenge configuration, and compare the oscillation frequency under the challenge configuration with the oscillation frequency under the complementary challenge configuration to generate a physically unclonable function response. Recovery module 403 is used to restore the configuration parameters of the reconfigurable oscillator unit in the previous true random number generator operating mode after generating the physical unclonable function response, so that the reconfigurable oscillator unit returns to the true random number generator operating mode.

[0110] Optionally, the reconfigurable oscillator unit is configured in the following manner: Multiple configurable delay units are connected in series to form a closed-loop oscillation circuit to constitute the reconfigurable oscillator unit, wherein each configurable delay unit contains at least two paths with different delay characteristics; A path selector is configured for each configurable delay unit, and the control signal of the path selector is used to select a specific delay path for the configurable delay unit; Multiple reconfigurable oscillator units are combined into an oscillator array, and a unified control state machine is configured for the oscillator array. The control state machine is used to manage the state switching of the oscillator array between a physically non-cloning function operating mode and a true random number generator operating mode.

[0111] Optionally, the switching module 401 is further configured to: Upon receiving a physical non-cloning function operation command through the unified interface, the random number generation process of the reconfigurable oscillator unit in its current true random number generator operating mode is paused. Save the current configuration parameters of the reconfigurable oscillator unit in the true random number generator operating mode to the specified storage area; The state of the control state machine is switched from the true random number generator operating state to the physical non-cloning function operating state.

[0112] Optionally, the switching module 401 is further configured to: Based on the challenge configuration data contained in the physical non-cloning function operation command, the challenge configuration data is decoded into a path selection control signal for each of the reconfigurable oscillator units; The path selection control signal obtained from the decoding is used to reconfigure the path selector inside each of the reconfigurable oscillator units to set a specific combination of delay paths for the reconfigurable oscillator units in the physically unclonable function operating mode.

[0113] Optionally, the response module 402 is further configured to: The system clock is used as a reference signal to drive the counter; Under the challenge configuration, the counter is started to count the oscillation cycles of a first specified number of the reconfigurable oscillator units, and the counting stops after a fixed first time window, and the count value is converted into a first frequency measurement value; Under the complementary challenge configuration, the counter is restarted to count the oscillation periods of the first specified number of reconfigurable oscillator units, and the counting is stopped after the same first time window, and the count value is converted into a second frequency measurement value. The process of acquiring the first frequency measurement value and the second frequency measurement value is repeated a second specified number of times, and the average value of the first frequency measurement value and the second frequency measurement value is calculated respectively to eliminate the influence of instantaneous jitter.

[0114] Optionally, the response module 402 is further configured to: The average value of the first frequency measurement and the average value of the second frequency measurement are input into the comparator; If the average value of the first frequency measurement is greater than the average value of the second frequency measurement, the comparator outputs a first logic value as a physical non-cloning function response for the current bit. If the average value of the first frequency measurement is less than the average value of the second frequency measurement, the comparator outputs a second logic value as a physical non-cloning function response for the current bit. Traverse all the reconfigurable oscillator units in the oscillator array, generate the response bits corresponding to each reconfigurable oscillator unit in sequence, and combine all the response bits into a complete physically unclonable functional response sequence.

[0115] Optionally, the recovery module 403 is further configured to: A mode recovery event is triggered after the physical unclonable function response is read externally or after a third specified time. Read the previously saved configuration parameters of the true random number generator in its operating mode from the specified storage area; The read configuration parameters are reloaded into the path selector of the reconfigurable oscillator unit to restore the original working state of the reconfigurable oscillator unit in the true random number generator working mode. Switch the state of the control state machine from the physically unclonable function working state back to the true random number generator working state, and restart the random number generation process.

[0116] Optionally, the device further includes: The detection module is used for: In the physically unclonable function operating mode, the health monitoring circuit of the true random number generator is kept in the on state; The health monitoring circuit continuously samples the output signal of the reconfigurable oscillator unit. Calculate the real-time statistical characteristics of the sampled data and compare the real-time statistical characteristics with the baseline statistical characteristics established in advance under the working mode of the true random number generator; If the deviation between the real-time statistical characteristics and the baseline statistical characteristics exceeds a preset security threshold, a potential security attack is determined, a security fault signal is generated, and the current physical unclonable function response is stopped.

[0117] This application embodiment, through a reconfigurable oscillator hardware array and under unified state machine control, achieves dynamic reuse and on-demand switching of two security primitives: physically unclonable functionality and a true random number generator. After generating the PUF mode for unique device identity response, it can automatically recover and continue in the TRNG mode for high-entropy random number generation, thus completing two core security functions on a single hardware circuit. This deep reuse architecture significantly improves the utilization of hardware resources, effectively reduces chip area and power consumption, and reduces system integration complexity through standardized interfaces and automated mode management. It is particularly suitable for cost-, area-, and power-sensitive IoT and edge computing devices.

[0118] The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided in this application can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0119] It should be noted that, in the embodiments of this application, if the above-described oscillator control method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0120] This application provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0121] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0122] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0123] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0124] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0125] It should be noted that, Figure 6 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this application, such as... Figure 6 As shown, the hardware entity of the computer device 700 includes: one or more processors 701, a communication interface 702, and a memory 703, wherein: Processor 701 typically controls the overall operation of computer device 700.

[0126] Communication interface 702 enables computer devices to communicate with other terminals or servers over a network.

[0127] The memory 703 is configured to store instructions and applications executable by the processor 701, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 701 and various modules in the computer device 700. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 701, the communication interface 702, and the memory 703 can be performed via bus 704. Only one processor is shown in the figure; each processor 700 includes one or more cores.

[0128] It should be noted that the computer device may include multiple processors 701, and each processor 701 can interact with each other through aggregated communication methods such as all-to-all, all-gather, or all-reduce. The processors 701 may be central processing units (CPUs), graphics processing units (GPUs), embedded neural network processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), accelerated processing units (APUs), floating-point processing units (FPUs), or application-specific integrated circuits (ASICs). The processors may also be single-core or multi-core processors. The processor may consist of a CPU and hardware chips. The hardware chips may be ASICs, PLDs, or combinations thereof. The PLDs may be complex programmable logic devices (CPLDs), FPGAs, generic array logic (GALs), or any combination thereof. The processor can also be implemented using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs).

[0129] The communication interface 702 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0130] Memory 703 can be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 703 can also be volatile memory, which can be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synclink dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM), direct rambus DRAM (DRDRAM), and rambus DRAM.

[0131] The 704 bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc.

[0132] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0133] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0134] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0135] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0136] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0137] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0138] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0139] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A control method for an oscillator, characterized in that, The method includes: When a command to operate a physically unclonable function is received through a unified interface, the random number generation process of the reconfigurable oscillator unit in its current true random number generator operating mode is paused. Save the current configuration parameters of the reconfigurable oscillator unit in the true random number generator operating mode to the specified storage area; The control state machine switches from a true random number generator operating state to a physically unclonable function operating state. The reconfigurable oscillator unit has a configurable delay path, and the operation commands include a physically unclonable function mode command and a true random number generator mode command. The reconfigurable oscillator unit is formed by multiple configurable delay units connected in series to form a closed-loop oscillation circuit. Each configurable delay unit is equipped with a path selector. Multiple reconfigurable oscillator units utilize the control state machine to form an oscillator array. In the physically unclonable operating mode, the delay path selection of the reconfigurable oscillator unit is controlled according to the challenge configuration of the external input, and the oscillation frequency of the reconfigurable oscillator unit is measured under the challenge configuration and the complementary challenge configuration. Compare the oscillation frequency under the challenge configuration with the oscillation frequency under the complementary challenge configuration to generate a physically unclonable functional response; After generating the physically unclonable function response, the configuration parameters of the reconfigurable oscillator unit in the previous true random number generator operating mode are restored, so that the reconfigurable oscillator unit returns to the true random number generator operating mode.

2. The method according to claim 1, characterized in that, The reconfigurable oscillator unit is configured in the following manner: Multiple configurable delay units are connected in series to form a closed-loop oscillation circuit to constitute the reconfigurable oscillator unit, wherein each configurable delay unit contains at least two paths with different delay characteristics; A path selector is configured for each configurable delay unit, and the control signal of the path selector is used to select a specific delay path for the configurable delay unit; Multiple reconfigurable oscillator units are combined into an oscillator array, and a unified control state machine is configured for the oscillator array. The control state machine is used to manage the state switching of the oscillator array between a physically non-cloning function operating mode and a true random number generator operating mode.

3. The method according to claim 1, characterized in that, The method further includes: Based on the challenge configuration data contained in the physical non-cloning function operation command, the challenge configuration data is decoded into a path selection control signal for each of the reconfigurable oscillator units; The path selection control signal obtained from the decoding is used to reconfigure the path selector inside each of the reconfigurable oscillator units to set a specific combination of delay paths for the reconfigurable oscillator units in the physically unclonable function operating mode.

4. The method according to claim 1, characterized in that, The step of controlling the delay path selection of the reconfigurable oscillator unit according to the challenge configuration of the external input, and measuring the oscillation frequency of the reconfigurable oscillator unit under the challenge configuration and the complementary challenge configuration, includes: The system clock is used as a reference signal to drive the counter; Under the challenge configuration, the counter is started to count the oscillation cycles of a first specified number of the reconfigurable oscillator units, and the counting stops after a fixed first time window, and the count value is converted into a first frequency measurement value; Under the complementary challenge configuration, the counter is restarted to count the oscillation periods of the first specified number of reconfigurable oscillator units, and the counting is stopped after the same first time window, and the count value is converted into a second frequency measurement value. The process of acquiring the first frequency measurement value and the second frequency measurement value is repeated a second specified number of times, and the average value of the first frequency measurement value and the second frequency measurement value is calculated respectively to eliminate the influence of instantaneous jitter.

5. The method according to claim 4, characterized in that, The step of comparing the oscillation frequency under the challenge configuration with the oscillation frequency under the complementary challenge configuration to generate a physically unclonable functional response includes: The average value of the first frequency measurement and the average value of the second frequency measurement are input into the comparator; If the average value of the first frequency measurement is greater than the average value of the second frequency measurement, the comparator outputs a first logic value as a physical non-cloning function response for the current bit. If the average value of the first frequency measurement is less than the average value of the second frequency measurement, the comparator outputs a second logic value as a physical non-cloning function response for the current bit. Traverse all the reconfigurable oscillator units in the oscillator array, generate the response bits corresponding to each reconfigurable oscillator unit in sequence, and combine all the response bits into a complete physically unclonable functional response sequence.

6. The method according to claim 1, characterized in that, The process of restoring the configuration parameters of the reconfigurable oscillator unit in its previous true random number generator operating mode includes: A mode recovery event is triggered after the physical unclonable function response is read externally or after a third specified time. Read the previously saved configuration parameters of the true random number generator in its operating mode from the specified storage area; The read configuration parameters are reloaded into the path selector of the reconfigurable oscillator unit to restore the original working state of the reconfigurable oscillator unit in the true random number generator working mode. Switch the state of the control state machine from the physically unclonable function working state back to the true random number generator working state, and restart the random number generation process.

7. The method according to claim 1, characterized in that, The method further includes: In the physically unclonable function operating mode, the health monitoring circuit of the true random number generator is kept in the on state; The health monitoring circuit continuously samples the output signal of the reconfigurable oscillator unit. Calculate the real-time statistical characteristics of the sampled data and compare the real-time statistical characteristics with the baseline statistical characteristics established in advance under the working mode of the true random number generator; If the deviation between the real-time statistical characteristics and the baseline statistical characteristics exceeds a preset security threshold, a potential security attack is determined, a security fault signal is generated, and the current physical unclonable function response is stopped.

8. A control device for an oscillator, characterized in that, The device includes: The switching module is used to pause the random number generation process of the reconfigurable oscillator unit in its current true random number generator operating mode when a physical non-cloning function operation command is received through a unified interface. Save the current configuration parameters of the reconfigurable oscillator unit in the true random number generator operating mode to the specified storage area; The control state machine switches from a true random number generator operating state to a physically unclonable function operating state. The reconfigurable oscillator unit has a configurable delay path, and the operation commands include a physically unclonable function mode command and a true random number generator mode command. The reconfigurable oscillator unit is formed by multiple configurable delay units connected in series to form a closed-loop oscillation circuit. Each configurable delay unit is equipped with a path selector. Multiple reconfigurable oscillator units utilize the control state machine to form an oscillator array. The response module is configured to control the delay path selection of the reconfigurable oscillator unit according to an externally input challenge configuration in the physically unclonable function operating mode, measure the oscillation frequency of the reconfigurable oscillator unit under the challenge configuration and the complementary challenge configuration, and compare the oscillation frequency under the challenge configuration with the oscillation frequency under the complementary challenge configuration to generate a physically unclonable function response. The recovery module is used to restore the configuration parameters of the reconfigurable oscillator unit in the previous true random number generator operating mode after generating the physical unclonable function response, so that the reconfigurable oscillator unit returns to the true random number generator operating mode.

9. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the control method of the oscillator according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps in the control method of the oscillator according to any one of claims 1 to 7.

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