Multi-protocol intelligent adaptive communication switching system and method for four-way vehicle

Abstract

This invention discloses a multi-protocol intelligent adaptation communication switching system and method for four-way vehicles, belonging to the field of four-way vehicle communication technology. The system includes: acquiring communication signal characteristics and bus status data of the on-board perception module of the four-way vehicle; generating protocol adaptation configuration data through multi-protocol blind identification and virtual address mapping; iteratively optimizing the bus using a double-buffered ping-pong architecture and FPGA scheduling logic until the signal collision rate, bit error rate, and switching latency meet the standards, and outputting a protocol adaptation ready signal; performing seamless multi-protocol switching and bus transmission according to a time slot allocation strategy and polling priority, and collecting frame-level transmission data in real time. This invention solves the problems of heterogeneous communication protocols, bus conflicts, and high latency of multiple types of perception modules in four-way vehicles, achieving multi-protocol adaptive adaptation and seamless switching, and improving communication reliability and real-time performance.

Description

Technical Field

[0001] This invention belongs to the field of four-way vehicle communication technology, specifically a multi-protocol intelligent adaptation communication switching system and method for four-way vehicles. Background Technology

[0002] As a core piece of equipment in warehouse logistics automation, the four-way vehicle is equipped with multiple types of onboard sensing modules and needs to be compatible with various communication protocols to achieve data interaction. Current four-way vehicle communication systems have several shortcomings: First, protocol heterogeneity is prominent; different sensing modules use different protocols such as CAN and RS485, lacking a unified adaptation mechanism, leading to difficulties in protocol identification and poor compatibility. Second, bus conflicts are severe; parallel transmission by multiple modules easily causes signal collisions, resulting in increased bit error rates and insufficient transmission stability. Third, switching latency is high and real-time performance is weak; traditional communication switching mechanisms have simple scheduling logic, making it difficult to adapt to dynamic loads, and the switching latency cannot meet the high-speed scheduling requirements of four-way vehicles. Fourth, address management is chaotic; physical addresses are scattered and lack a unified addressing scheme, reducing bus resource utilization. Existing technologies mostly use single protocol adaptation or static configuration methods, which cannot achieve blind multi-protocol identification, dynamic address mapping, and seamless switching, making it difficult to balance communication reliability, real-time performance, and compatibility. Therefore, there is an urgent need for a multi-protocol intelligent adaptation communication switching method for four-way vehicles to solve problems such as protocol heterogeneity, bus conflict, high switching latency and chaotic address management, and improve the overall performance of the four-way vehicle on-board communication system. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention proposes a multi-protocol intelligent adaptation communication switching system and method for four-way vehicles. The system acquires communication signal characteristics and bus status data from the vehicle's onboard perception module; generates protocol adaptation configuration data through multi-protocol blind identification and virtual address mapping; iteratively optimizes the bus using a double-buffered ping-pong architecture and FPGA scheduling logic until signal collision rate, bit error rate, and switching latency meet standards, outputting a protocol adaptation ready signal; and performs seamless multi-protocol switching and bus transmission based on time slot allocation strategies and polling priorities, while simultaneously collecting frame-level transmission data in real time. This invention solves the problems of heterogeneous communication protocols, bus conflicts, and high latency in four-way vehicle perception modules, achieving multi-protocol adaptive adaptation and seamless switching, thus improving communication reliability and real-time performance.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A multi-protocol intelligent adaptation communication handover method for four-way vehicles includes:

[0006] The system acquires communication signal characteristics and bus status data of the multi-type sensing modules on the four-way vehicle. The communication signal characteristics include level characteristics, frame header characteristics, baud rate characteristics, and protocol type identifiers. The bus status data includes bus load rate, signal bit error rate, transmission delay, and module address mapping relationship.

[0007] Based on the communication signal characteristics and bus status data, multi-protocol blind identification and virtual address mapping are performed to obtain protocol adaptation configuration data; the protocol adaptation configuration data includes protocol type, global virtual ID, address translation list, verification parameters and time slot allocation strategy;

[0008] According to the protocol adaptation configuration data, the double-buffered ping-pong architecture and FPGA scheduling logic are invoked to perform iterative optimization of the bus until the signal collision rate and bit error rate in the current transmission cycle are both lower than the preset threshold and the switching delay is less than the preset delay limit, and then the protocol adaptation ready signal is output.

[0009] According to the protocol adaptation ready signal, multi-protocol seamless switching and bus transmission are performed based on the time slot allocation strategy and the polling priority of the global virtual ID planning. In the communication process, frame-level transmission data of each of the four-way vehicle-mounted multi-type perception modules are collected in real time. The frame-level transmission data includes response data, verification results, fault identifiers and link status identifiers.

[0010] Specifically, based on the communication signal characteristics and bus status data, multi-protocol blind identification and virtual address mapping are performed to obtain protocol adaptation configuration data, including:

[0011] Based on the characteristics of communication signals, a protocol feature matrix is ​​constructed by calling a variable step-size sliding window protocol feature matching algorithm; the row vectors of the protocol feature matrix correspond to the time window indexes, and the column vectors correspond to the candidate sets of protocol types.

[0012] Based on the protocol feature matrix, the posterior probability values ​​of each column vector are normalized into a protocol confidence vector, and the protocol type corresponding to the maximum value in the protocol confidence vector is taken as the real-time protocol type of the current four-way vehicle on-board multi-type perception module.

[0013] Based on the real-time protocol type and the module address mapping relationship, a hash mapping algorithm is invoked to map the physical address to a global virtual ID;

[0014] Based on the mapping relationship between the global virtual ID and the module address, an address translation linked list is constructed;

[0015] Based on the address translation linked list, the initial vector of cyclic redundancy check is extracted, and check parameters are generated.

[0016] Based on the bus load rate and the transmission delay, a dynamic time window cutting algorithm is used to divide the bus cycle into multiple equal-length time slots, and a dedicated time slot and a shared time slot are allocated to each global virtual ID to obtain a time slot allocation strategy.

[0017] Integrate the real-time protocol type, the global virtual ID, the address translation list, the verification parameters, and the time slot allocation strategy to output protocol adaptation configuration data.

[0018] Specifically, the step-size sliding window protocol feature matching algorithm for constructing the protocol feature matrix includes:

[0019] Extract a continuous sampling sequence of communication signal features, initialize the start pointer and step counter of the sliding window based on the continuous sampling sequence, and dynamically adjust the window length of the sliding window according to the parity of the step counter. When the step counter is even, the window length is set to an integer multiple of the number of frame header feature bytes. When the step counter is odd, the window length is set to the product of the reciprocal of the baud rate feature and the preset sampling multiple.

[0020] Based on the level characteristics in the communication signal features, the number of signal edge transitions is detected within the adjusted sliding window, and the number of signal edge transitions is matched with the preset standard protocol edge template using Hamming distance to obtain the matching distance value. If the matching distance value is less than the preset distance threshold, feature vector extraction is triggered, and the frame header feature byte sequence and protocol type identifier field are extracted within the adjusted sliding window.

[0021] The row number of the protocol feature matrix is ​​determined by the starting pointer and step counter of the sliding window. The extracted frame header feature byte sequence and protocol type identifier field are used as the feature data of the row vector. The row vector of the protocol feature matrix is ​​constructed and stored in the first-in-first-out buffer queue. The column vector is constructed with the preset protocol type candidate set to form the protocol feature matrix.

[0022] Specifically, based on the protocol feature matrix, the posterior probability values ​​of each column vector are normalized into a protocol confidence vector, including:

[0023] Obtain the prior probability distribution of the protocol type candidate set corresponding to each column vector in the protocol feature matrix; the prior probability distribution is dynamically updated based on historical adaptation records;

[0024] Based on the column vectors of the protocol feature matrix within the current sampling period, the likelihood function value of each candidate protocol type under a given observation feature is calculated; the observation feature is the level feature and the frame header feature in the communication signal features; the likelihood function value is obtained by fitting the joint distribution of the level feature and the frame header feature using the Gaussian kernel density estimation method.

[0025] Multiplying the prior probability distribution by the likelihood function value yields the unnormalized posterior probability value.

[0026] Based on the sum of the unnormalized posterior probability values ​​of all candidate protocol types, a normalized division is performed on each unnormalized posterior probability value to obtain a posterior probability value. The posterior probability values ​​are then arranged in the order of the candidate protocol type set, and a protocol confidence vector is output.

[0027] Specifically, based on the protocol adaptation configuration data, the double-buffered ping-pong architecture and FPGA scheduling logic are invoked to perform iterative optimization of the bus, including:

[0028] Based on the protocol adaptation configuration data, initialize the first and second buffers of the dual-buffered ping-pong architecture; the first and second buffers share the same physical storage medium but independently control the read and write pointers.

[0029] Based on FPGA scheduling logic, three independent state machines are assigned to handle different optimization tasks, namely the first state machine, the second state machine, and the third state machine;

[0030] Based on the time slot allocation strategy, the first state machine generates a time slot synchronization pulse, and the rising edge of the time slot synchronization pulse triggers the switching of the current active buffer;

[0031] Based on the verification parameters, the second state machine adopts a parallel cyclic redundancy check mechanism to synchronously calculate the verification value during the process of writing data into the first buffer or the second buffer.

[0032] Based on the global virtual ID and the address translation linked list, the third state machine uses a dynamic priority queue algorithm to calculate the polling priority of each four-way vehicle-mounted multi-type perception module; the priority weight factor of the dynamic priority queue algorithm is determined by the weighted sum of the signal bit error rate and the bus load rate.

[0033] Specifically, the dual-buffered ping-pong architecture includes a first buffer and a second buffer, which alternately serve as the write buffer and the read buffer, with the specific switching logic as follows:

[0034] Within a preset first time period, the first buffer is configured as a write buffer, and the second buffer is configured as a read buffer;

[0035] The buffer switching signal is triggered when the write completion signal of the first buffer is set and the read completion signal of the second buffer is set.

[0036] In response to the buffer switching signal, the first buffer is reconfigured as a read buffer and the second buffer is reconfigured as a write buffer;

[0037] Meanwhile, a buffer switching mutex is set in the FPGA scheduling logic. The buffer switching mutex is locked when the buffer switching signal is triggered and released after the configuration switching of the first buffer and the second buffer is completed and the read / write pointers are returned to zero.

[0038] Specifically, the step of outputting a protocol adaptation ready signal when the signal collision rate and bit error rate are both below a preset threshold and the switching delay is less than a preset delay limit during the current transmission cycle includes:

[0039] Based on the verification mechanism, polling priority, and bus transmission timing generated by the first state machine based on the time slot allocation strategy, all four-way vehicle-mounted multi-type perception modules corresponding to the global virtual ID are polled sequentially in the current transmission cycle according to the time slot allocation strategy, and the collision event count and error frame count are collected in each polling process.

[0040] The signal collision rate is obtained based on the ratio of the collision event count to the total number of polling iterations.

[0041] The bit error rate is obtained based on the ratio of the number of erroneous frames to the total number of transmitted frames.

[0042] The switching delay is obtained based on the difference between the time when the first state machine generates the time slot synchronization pulse and the actual time when the first buffer and the second buffer complete the switching.

[0043] Determine whether the signal collision rate is lower than the collision rate threshold in the preset threshold, whether the bit error rate is lower than the bit error rate threshold in the preset threshold, and whether the switching delay is less than the preset delay upper limit; when all conditions are met, trigger the generation of a protocol adaptation ready signal; when any condition is not met, adjust the time slot length of the time slot allocation strategy, the priority weight factor of the dynamic priority queue algorithm, or the polynomial order of the parallel cyclic redundancy check mechanism, and repeat iterative optimization until the conditions are met.

[0044] Specifically, based on the protocol adaptation ready signal, and according to the polling priority of the time slot allocation strategy and the global virtual ID planning, seamless switching of multiple protocols and bus transmission are performed, including:

[0045] Based on the protocol adaptation ready signal, the iteratively optimized polling priority is written into the priority register of the FPGA scheduling logic;

[0046] Based on the iteratively optimized polling priority, the third state machine generates a polling sequence; each element in the polling sequence is a global virtual ID;

[0047] Based on the polling sequence, the first state machine sequentially sends request frames within the exclusive time slot allocated by the time slot allocation strategy for the corresponding global virtual ID, and listens for response frames from the physical address corresponding to the module address mapping relationship; the response frame contains a checksum and a payload; the payload is the service transmission data collected by the four-way vehicle-mounted multi-type perception module;

[0048] During the protection interval between the end of the exclusive time slot and the start of the next exclusive time slot, the second state machine performs a verification comparison, comparing the checksum carried in the response frame with the calculation result of the parallel cyclic redundancy check mechanism to determine consistency. If the consistency determination passes, the first state machine writes the payload of the response frame into the current active buffer of the double-buffered ping-pong architecture. If the consistency determination fails, the third state machine triggers a retransmission mechanism, retransmitting the request frame in the next shared time slot allocated by the time slot allocation strategy.

[0049] Specifically, the real-time acquisition of frame-level transmission data from the multi-type sensing modules on each of the four-way vehicles during communication includes:

[0050] Based on each successfully received response frame during the bus transmission process, the frame sequence number field is extracted from the header of the response frame, the payload field is extracted from the payload field of the response frame, and the check field is extracted from the tail of the response frame. The frame sequence number field, the payload field, and the check field are then merged into response data for frame-level transmission data.

[0051] Based on the result of the consistency decision, if the check code matches the calculation result, a successful check is generated; if they do not match, a failed check is generated. The successful check or the failed check is recorded as the check result in the frame-level transmission data.

[0052] Based on the error flag bit carried in the response frame, the fault identifier in the frame-level transmission data is obtained; the error flag bit is a built-in identifier bit in the response frame used to characterize the abnormality of the four-way vehicle's on-board multi-type perception module and communication; the fault identifier includes internal communication faults, sensor faults and power supply faults of the four-way vehicle's on-board multi-type perception module.

[0053] Based on the link status bits carried in the response frame, the link status identifier in the frame-level transmission data is obtained; the link status identifier includes link connected state, link idle state, and link interrupted state.

[0054] A multi-protocol intelligent adaptation communication switching system for four-way vehicles includes:

[0055] The signal and status acquisition module is used to acquire the communication signal characteristics and bus status data of the four-way vehicle's on-board multi-type sensing modules;

[0056] The virtual address mapping module performs multi-protocol blind identification and virtual address mapping based on the collected communication signal characteristics and bus status data, and generates protocol adaptation configuration data.

[0057] The iterative optimization module, based on the protocol adaptation configuration data, calls the double-buffered ping-pong architecture and FPGA scheduling logic, iteratively optimizes the bus transmission process through three independent state machines, and outputs a protocol adaptation ready signal.

[0058] The multi-protocol seamless switching module generates a polling sequence by the FPGA state machine based on the protocol adaptation ready signal, time slot allocation strategy and global virtual ID planning polling priority. It sends request frames, listens for response frames and performs verification in the exclusive time slot. If the verification fails, it triggers retransmission in the shared time slot to complete multi-protocol seamless switching and bus transmission.

[0059] The frame-level data acquisition module collects frame-level transmission data in real time during communication, including response data, verification results, fault identifiers, and link status identifiers.

[0060] Compared with the prior art, the beneficial effects of the present invention are:

[0061] 1. This invention proposes a multi-protocol intelligent adaptation communication switching method for four-way vehicles. Through multi-protocol blind identification, virtual address mapping, and FPGA scheduling optimization, it effectively solves problems such as heterogeneous protocols, bus conflicts, and chaotic address management of multiple types of onboard perception modules in four-way vehicles, significantly reducing signal collision rate and bit error rate, and greatly improving communication stability and reliability. At the same time, the dual-buffered ping-pong architecture combined with dynamic time slot allocation and priority scheduling realizes seamless switching of multiple protocols, effectively shortens the switching latency, ensures real-time data transmission, and adapts to the needs of high-speed dynamic scheduling scenarios for four-way vehicles.

[0062] 2. This invention proposes a multi-protocol intelligent adaptation communication switching method for four-way vehicles. It adopts dynamic address mapping, parallel verification and real-time frame-level data acquisition mechanism to achieve efficient utilization of bus resources and real-time monitoring of communication status. It can quickly locate module faults and link anomalies, improve the convenience of system operation and maintenance and fault tolerance, and enhance the compatibility, scalability and overall performance of the four-way vehicle on-board communication system. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the multi-protocol intelligent adaptation communication switching method for four-way vehicles according to the present invention;

[0064] Figure 2 This is a flowchart illustrating the principle of the multi-protocol intelligent adaptation and communication switching method for four-way vehicles according to the present invention.

[0065] Figure 3This is a diagram of the multi-protocol intelligent adaptation communication switching system architecture for four-way vehicles according to the present invention. Detailed Implementation

[0066] Example 1:

[0067] Please see Figure 1 and Figure 2 The present invention provides an embodiment of a multi-protocol intelligent adaptation communication switching method for four-way vehicles, the method comprising S1~S4, including the following steps:

[0068] S1: Acquire the communication signal characteristics and bus status data of the four-way vehicle's onboard multi-type perception modules; the communication signal characteristics include level characteristics, frame header characteristics, baud rate characteristics, and protocol type identifier; the bus status data includes bus load rate, signal bit error rate, transmission delay, and module address mapping relationship;

[0069] Furthermore, level characteristics refer to the manifestation of the module's communication signal at high and low levels, including the duration of high level, duration of low level, level transition mode, and stable level range. The level characteristics of different protocols and different hardware interfaces are significantly different and can be used to initially distinguish signal types. Frame header characteristics refer to the fixed feature sequence at the very beginning of the data frame sent by the module, including frame header length, frame header byte composition, frame header encoding rules, and frame header occurrence period. The frame header is a key basis for identifying the protocol type. Baud rate characteristics refer to the signal transmission rate performance, obtained by statistically analyzing the number of signal transitions per unit time, effective pulse interval, and stable signal segment length, and are used to determine the actual transmission rate of the module. Protocol type identifiers refer to protocol-related marking information implicitly or explicitly carried in the signal, including fixed feature codes, protocol-specific fields, manufacturer identification codes, and module type codes, and are used to assist in confirming the protocol type.

[0070] Furthermore, the bus load rate refers to the degree to which the vehicle bus is occupied by valid data at the current moment. It is obtained by statistically analyzing the proportion of the bus time occupied by signals to the total bus time over a period of time. An excessively high load rate can easily cause signal congestion, increased latency, and a higher probability of collisions. The signal bit error rate refers to the proportion of erroneous data frames that occur during transmission. It is obtained by statistically analyzing the relationship between the number of erroneous frames and the total number of transmitted frames. A high bit error rate indicates poor link quality, high interference, and unstable signals. Transmission latency refers to the time required for the module to send data to the main control unit for complete reception and parsing. This includes physical transmission time, bus forwarding time, and parsing processing time. Excessive latency affects real-time control and sensing response. The module address mapping relationship refers to the correspondence between the physical address, device number, hardware ID, and bus interface number configured at the factory for each sensing module. This is used for subsequent address translation and virtual mapping.

[0071] S2: Based on the communication signal characteristics and bus status data, perform multi-protocol blind identification and virtual address mapping to obtain protocol adaptation configuration data; the protocol adaptation configuration data includes protocol type, global virtual ID, address translation list, verification parameters and time slot allocation strategy;

[0072] Based on the communication signal characteristics and bus status data, multi-protocol blind identification and virtual address mapping are performed to obtain protocol adaptation configuration data, including:

[0073] S2.1: Based on the characteristics of communication signals, a protocol feature matrix is ​​constructed by calling a variable step-size sliding window protocol feature matching algorithm; the row vectors of the protocol feature matrix correspond to the time window indexes, and the column vectors correspond to the protocol type candidate set.

[0074] The construction of the protocol feature matrix by invoking the variable step-size sliding window protocol feature matching algorithm includes:

[0075] S2.1.1: Extract a continuous sampling sequence of communication signal features, initialize the start pointer and step counter of the sliding window based on the continuous sampling sequence, and dynamically adjust the window length of the sliding window according to the parity of the step counter. When the step counter is even, the window length is set to an integer multiple of the number of frame header feature bytes. When the step counter is odd, the window length is set to the product of the reciprocal of the baud rate feature and the preset sampling multiple.

[0076] Furthermore, in actual execution, the sampling frequency of the sampling sequence is uniformly set to one million times per second, and each sampling records a level state value.

[0077] Furthermore, the start pointer is used to mark the starting position of the current sliding window in the entire continuous sampling sequence. During initialization, the start pointer is directly set to zero, which means that the window starts from the very beginning of the sampling sequence. The step counter is used to record the number of times the sliding window has slid on the sampling sequence. During initialization, the step counter is also directly set to zero, which means that the window has not yet performed any sliding action. The entire sliding process starts from zero slides and gradually progresses.

[0078] Furthermore, when the current value of the step counter is even, the window length setting logic of the even branch is executed, including: firstly, reading the number of frame header feature bytes of the current module data frame from the extracted communication signal features. In the parameter setting of this embodiment, after statistical analysis of various industrial protocol frame structures, the number of frame header feature bytes is set to 8 bytes, which is suitable for the communication frame format of most vehicle sensing modules; then, the window length is directly set to an integer multiple of the number of frame header feature bytes. In this embodiment, 2 times is uniformly selected as the fixed multiple parameter, that is, the window length is set to 16 sampling points, which can ensure that the sliding window completely covers two consecutive frame headers. It will not cause the frame header features to be truncated due to the window being too small, nor will it introduce too much irrelevant data due to the window being too large, thus ensuring the accuracy and stability of feature extraction.

[0079] Furthermore, when the current value of the step counter is odd, the window length setting logic for the odd branch is executed, including: firstly, reading the baud rate feature value of the current module from the extracted communication signal features. The baud rate feature value is obtained by the system in real time. In automotive application scenarios, the baud rate feature value is usually set to 9600 baud per second, which is the most commonly used standard baud rate in industrial communication and can adapt to most automotive serial communication modules; calculating the reciprocal of the baud rate feature, which represents the time required for the transmission of a single signal bit; setting the sampling multiple to 10, and then multiplying the reciprocal of the baud rate feature by the sampling multiple to obtain the sliding window length in the odd state. Such a window length can accurately adapt to high-speed signal transmission scenarios and effectively capture rapidly changing level transition features.

[0080] S2.1.2: Based on the level characteristics in the communication signal features, the number of signal edge transitions is detected within the adjusted sliding window, and the number of signal edge transitions is matched with a preset standard protocol edge template using Hamming distance to obtain a matching distance value. If the matching distance value is less than a preset distance threshold, feature vector extraction is triggered, and the frame header feature byte sequence and protocol type identifier field are extracted within the adjusted sliding window. The frame header feature byte sequence includes complete frame header information such as frame header start byte, frame header length byte, frame header check byte, and frame header end byte. The protocol type identifier field includes protocol-specific marking information implicitly or explicitly carried in the signal.

[0081] Furthermore, the specific steps in S2.1.2 include:

[0082] (1) After the sliding window length is dynamically adjusted, enter the currently adjusted sliding window and perform a complete scan and point-by-point analysis of the communication signal level data contained in the window. The scanning process is carried out in the order of sampling points, starting from the first sampling point at the beginning of the window and scanning until the last sampling point at the end of the window, to ensure that all level changes in the window are completely covered and no signal change details are missed. At the same time, during the scan, it is necessary to focus on the position where the level state changes, that is, the position where the signal switches from high level to low level or from low level to high level, that is, the position where the signal edge transition occurs.

[0083] (2) When counting, start from the beginning of the window. Each time a level state change is detected, increment the count variable of the number of transitions by 1 until all sampling points in the window are scanned. Count the number of edge transitions. In the whole statistical process, only the number of transitions is recorded, and the specific location and time of the transition are not recorded.

[0084] (3) Read the preset standard protocol edge templates stored in the system in advance. The standard protocol edge templates are constructed in advance based on the typical signal edge characteristics of various mainstream industrial communication protocols. The standard protocol edge templates store the edge transition number sequence corresponding to various protocols in the standard communication state. Each protocol type corresponds to an independent standard template. The number of templates is determined according to the actual supported protocol types. In this method, the number of preset standard protocol edge templates is set to 8, which correspond to 8 common vehicle communication protocols. The length of the standard edge transition number sequence stored in each standard protocol edge template is uniformly set to 20 units to ensure that the template can completely cover the edge feature changes of a standard data frame.

[0085] (4) Calculate the total number of different values ​​at corresponding positions between the actual edge transition count sequence obtained in the current sliding window and the standard edge transition count sequence stored in the standard protocol edge template. The total number is the final matching distance value.

[0086] (5) Compare the matched distance value with the preset distance threshold. In this embodiment, the distance threshold is set to 5. When the judgment result is that the matched distance value is less than the distance threshold, the execution instruction for feature vector extraction is triggered, and the feature vector extraction process is entered. The trigger instruction is directly generated by the internal logic of the system and does not require manual intervention. The extraction process is started immediately after the instruction is generated.

[0087] (6) After triggering the feature vector extraction instruction, the frame header feature byte sequence is extracted within the currently adjusted sliding window range. The extraction process starts from the beginning of the sliding window and reads the frame header data bytes contained in the window in the order of data transmission. The length of the frame header feature byte sequence is set to 8 bytes according to the standard protocol frame format. During extraction, it is strictly truncated according to the length of 8 bytes, starting from the frame header start marker byte and ending at the frame header end marker byte, to ensure that the extracted byte sequence is complete and continuous frame header data, without containing any data content outside the frame header.

[0088] (7) After the frame header feature byte sequence is extracted, the protocol type identifier field is extracted within the same adjusted sliding window. The protocol type identifier field is a fixed-length marker data located after the frame header data and before the effective data payload. It is used to identify the specific protocol type corresponding to the current communication signal. The length of this field is set to 2 bytes. When extracting, start from the next byte after the end of the frame header data and read 2 bytes of data continuously. The combination of these 2 bytes of data is the complete protocol type identifier field. The extraction process is strictly limited to the current sliding window and does not cross the window boundary to read data, so as to ensure that the extracted identifier field accurately corresponds to the communication signal in the current window.

[0089] (8) Integrate the extracted frame header feature byte sequence with the protocol type identifier field to form feature vector data.

[0090] S2.1.3: The row number of the protocol feature matrix is ​​determined by the starting pointer and step counter of the sliding window. The extracted frame header feature byte sequence and protocol type identifier field are used as the feature data of the row vector. The row vector of the protocol feature matrix is ​​constructed and stored in the first-in-first-out buffer queue. The column vector is constructed with the preset protocol type candidate set to form the protocol feature matrix.

[0091] S2.2: Based on the protocol feature matrix, the posterior probability values ​​of each column vector are normalized into a protocol confidence vector, and the protocol type corresponding to the maximum value in the protocol confidence vector is taken as the real-time protocol type of the current four-way vehicle on-board multi-type perception module.

[0092] Based on the protocol feature matrix, the posterior probability values ​​of each column vector are normalized into a protocol confidence vector, including:

[0093] S2.2.1: Obtain the prior probability distribution of the protocol type candidate set corresponding to each column vector in the protocol feature matrix; the prior probability distribution is dynamically updated based on historical adaptation records;

[0094] Furthermore, the specific steps in S2.2.1 include:

[0095] (1) Obtain the protocol feature matrix and the candidate set of protocol types;

[0096] (2) Retrieve and read the historical adaptation record database stored in the system. The historical adaptation record database is automatically accumulated during the long-term operation of the system. It is used to record complete information such as protocol identification results, identification time, module type, runtime, and communication stability when all vehicle-mounted sensing modules access the bus in the past. The database is stored in a structured manner, and each record corresponds to a complete protocol identification event.

[0097] (3) Select valid and complete protocol identification records from the historical adaptation record database. During the screening, exclude identification failure or invalid records caused by signal interference, module failure, or communication interruption. Only retain valid records that are successfully identified, have complete data, and have reliable results. After the screening is completed, the total number of valid records obtained is stable at more than 10,000 under normal operating conditions.

[0098] (4) The effective historical adaptation records obtained by screening are classified and statistically analyzed according to the eight protocol categories in the protocol type candidate set. During the statistical analysis, all effective historical adaptation records are traversed, and the protocol type that was finally successfully identified in each effective historical adaptation record is extracted one by one. The effective historical adaptation records are assigned to the corresponding protocol category statistical items, and the number of times the effective historical adaptation records corresponding to each protocol category are counted to obtain the historical occurrence frequency of each of the eight protocols.

[0099] (5) Add up the historical occurrence frequencies of all 8 protocols to get the total frequency of all valid historical adaptation records. Then divide the historical occurrence frequency of each protocol by the total frequency to get the initial prior probability of the protocol. The sum of the initial prior probabilities of all protocols is fixed to 1 to ensure that the probability distribution conforms to the basic probability rules.

[0100] (6) Set the dynamic update cycle parameter of the prior probability distribution. The dynamic update cycle determines how often the system re-statistics historical data and updates the prior probability. In this embodiment, the update cycle is set to 24 hours. That is, the system will automatically trigger a historical data re-statistics and prior probability update operation every 24 hours.

[0101] (7) Set the smooth update weight parameter of the prior probability distribution to avoid the probability value from changing abruptly in a single update. The smooth update weight is used to balance the influence of historical cumulative data and the latest statistical data on the prior probability. In this embodiment, the smooth update weight parameter is set to 0.2. The smaller the weight value, the greater the influence of historical data and the smoother the probability change; the larger the weight value, the greater the influence of the latest data and the more sensitive the probability change.

[0102] (8) Construct a dynamic update algorithm for the prior probability distribution. Specifically, each time an update is performed, a set of temporary prior probabilities is recalculated using the latest valid historical adaptation records within the last 24 hours. Then, the smooth update weight parameter is subtracted from 1 to obtain the weighting coefficient of the historical probability. Subsequently, the weighting coefficient is multiplied by the currently stored old prior probability, and the smooth update weight parameter is multiplied by the temporary prior probability. The two sets of weighted results are added together to obtain the final prior probability after the update. This algorithm ensures that each update can smoothly integrate the old and new data and maintain the stability of the probability distribution.

[0103] (9) The prior probabilities corresponding to the 8 protocols that have been calculated and updated are arranged in the order of the protocol type candidate set to form a complete prior probability distribution vector. The prior probability distribution vector contains 8 probability values, each of which corresponds to the prior probability of a protocol type in the protocol type candidate set. The order of the values ​​is completely consistent with the order of the column vectors of the protocol feature matrix, ensuring that each column vector can accurately match the corresponding prior probability. After the vector is arranged, it is stored in the probability storage area specified by the system.

[0104] (10) Bind each column vector of the protocol feature matrix to the corresponding probability value in the prior probability distribution vector. During mapping, the column vectors are arranged in order, from column 1 to column 8, corresponding to the first to eighth values ​​in the prior probability distribution vector. After the binding relationship is established, the corresponding prior probability can be quickly located and obtained by directly using the index position of the column vector when performing probability calculation.

[0105] S2.2.2: Based on the column vectors of the protocol feature matrix within the current sampling period, calculate the likelihood function value of each candidate protocol type under a given observation feature; the observation feature is the level feature and frame header feature in the communication signal features; the likelihood function value is obtained by fitting the joint distribution of the level feature and the frame header feature using the Gaussian kernel density estimation method;

[0106] Furthermore, the specific steps in S2.2.2 include:

[0107] (1) Determine the range of the current sampling period and read each column vector of the protocol feature matrix. In this embodiment, the duration of each sampling period is set to 10ms.

[0108] (2) Extract the observation features required for this calculation from the communication signal features collected in the current sampling period. The observation features are clearly divided into two categories: level features and frame header features. Level features include specific information such as the duration of high and low signal levels, level transition intervals, and level stability intervals. Each sampling will generate a set of corresponding level feature data. Frame header features include specific information such as the frame header byte sequence, frame header length, and frame header encoding rules. Each complete data frame corresponds to a set of frame header feature data. In the current sampling period, the system collects multiple sets of level feature data and frame header feature data, and selects the most stable set of data without noise interference and abnormal fluctuations as the observation features used in this calculation.

[0109] (3) Retrieve historical feature sample library; It should be noted that the system will store the valid level feature samples and frame header feature samples collected in all past sampling periods for a long time, thereby forming a historical feature sample library. Each record in the historical feature sample library corresponds to a set of synchronously collected level feature data and frame header feature data, and the total number of samples is fixed at more than 100,000.

[0110] (4) Construct a two-dimensional joint sample space of level features and frame header features. The joint sample space consists of all sample data in the historical feature sample library. Each sample corresponds to a data point in the two-dimensional space. One dimension corresponds to the quantized value of the level feature and the other dimension corresponds to the quantized value of the frame header feature. When constructing, each record in the historical sample library is first quantized. The multi-dimensional information of the level feature is integrated into a normalized value, and the multi-dimensional information of the frame header feature is also integrated into a normalized value. The range of the normalized value is uniformly set between 0 and 1 to ensure that the numerical scale of the two dimensions is consistent. After quantization, the two normalized values ​​corresponding to each record are used as coordinate points in the two-dimensional space and all are entered into the joint sample space to form a complete two-dimensional joint sample distribution.

[0111] (5) Determine the number of Gaussian kernel functions and the bandwidth parameter. In this embodiment, the number of Gaussian kernel functions is set to 200, which are evenly distributed in the two-dimensional joint sample space to ensure that the sample distribution area can be fully covered. The bandwidth parameter controls the influence range of each Gaussian kernel function. In this embodiment, the Silverman rule is used to determine the bandwidth parameter. For the two-dimensional joint sample distribution, the bandwidth parameter is uniformly set to 0.15, which can accurately adapt to the distribution characteristics of the vehicle communication signal feature samples.

[0112] (6) Arrange 200 Gaussian kernel functions evenly in the two-dimensional coordinate range from 0 to 1 according to the principle of uniform distribution. The center coordinates of each Gaussian kernel function are randomly selected but the distribution is uniform to avoid the kernel functions being too dense or sparse in the local area. Set its own influence radius according to the bandwidth parameter of 0.15. At the same time, initialize the weight coefficient of the Gaussian kernel function. The initial weight coefficient of all Gaussian kernel functions is uniformly set to the same value to ensure that the contribution of each Gaussian kernel function to the fitting result is equal in the initial state.

[0113] (7) Input the level feature value and frame header feature value corresponding to the current observation feature, and calculate the output value of each Gaussian kernel function at the observation point. Specifically, first normalize the level feature and frame header feature in the current observation feature and convert them into values ​​in the range of 0 to 1 to form the two-dimensional coordinates of the observation point. Then, traverse 200 Gaussian kernel functions and calculate the distance from the observation point to the center coordinates of each Gaussian kernel function. Then, combine the bandwidth parameter 0.15 and substitute it into the Gaussian kernel function formula to calculate the output value of the Gaussian kernel function at the observation point. This output value reflects the degree of matching between the current observation feature and the sample area corresponding to the Gaussian kernel function. The larger the value, the higher the degree of matching. After traversing, the set of output values ​​corresponding to 200 Gaussian kernel functions is obtained.

[0114] (8) Summarize the output values ​​of all Gaussian kernel functions at the observation point and calculate the global probability density value corresponding to the current observation feature. Specifically, add up all the output values ​​of 200 Gaussian kernel functions at the observation point and then normalize them. The final value is the global probability density value of the current observation feature under the joint distribution of level feature and frame header feature, which directly reflects the probability of the current observation feature appearing in the historical feature distribution.

[0115] (9) For each column vector in the protocol feature matrix, a candidate protocol type is corresponding to it. All synchronous sample data belonging to the candidate protocol type are selected from the historical feature sample library. According to the construction rules in (4), the selected synchronous sample data is normalized and quantized to generate a two-dimensional joint sample distribution exclusive to the candidate protocol type. Finally, 8 independent sub-joint sample spaces are obtained, each space corresponding to a candidate protocol type.

[0116] (10) Repeat (5)-(8) for each sub-joint sample space to obtain the probability density value specific to the candidate protocol type. The probability density value is the likelihood function value corresponding to the candidate protocol type under the current observation feature. After completing the calculation of all candidate protocol types, 8 likelihood function values ​​are obtained.

[0117] (11) Arrange the likelihood function values ​​corresponding to the 8 candidate protocols in the order of the candidate protocol type set to form a likelihood function value sequence. Each value in the likelihood function value sequence corresponds to the likelihood of a candidate protocol type under the current observation feature. The larger the value, the higher the probability that the current observation feature belongs to the protocol type.

[0118] S2.2.3: Multiply the prior probability distribution by the likelihood function value to obtain the unnormalized posterior probability value. The posterior probability value takes into account both the historical access probability and the current feature matching probability, and more comprehensively and accurately reflects the true credibility of the current module belonging to a certain protocol type.

[0119] S2.2.4: Based on the sum of the unnormalized posterior probability values ​​of all candidate protocol types, perform normalization division on each unnormalized posterior probability value to map all posterior probability values ​​to the range of 0 to 1, obtain the posterior probability value, and arrange the posterior probability values ​​in the order of the candidate protocol type set to output the protocol confidence vector. Here, normalization is a prior art in this field and is not an inventive solution of this application, so it will not be described in detail here.

[0120] S2.3: Based on the real-time protocol type and the module address mapping relationship, a hash mapping algorithm is called to map the physical address to a global virtual ID; the bit length of the global virtual ID is dynamically expanded according to the number of four-way vehicle bus nodes;

[0121] Furthermore, when the hash mapping algorithm is executed, it first determines the real-time protocol type of the module based on the identified real-time protocol type. In this embodiment, the total number of protocol types supported by the system is fixed at 8, and the real-time protocol type of each module belongs to one of these 8 types. Next, it retrieves the module address mapping relationship. The module address mapping relationship is structured data automatically collected and stored by the system when the module accesses the bus. Each record corresponds to a physical module and includes information such as the module's factory physical address, model, hardware interface number, access time, and online status. In this embodiment, the mapping relationship database can store up to 1000 valid records, supporting multi-module access scenarios. Finally, it filters the modules currently in online status from the mapping relationship database. For modules that have completed protocol identification, the corresponding factory physical addresses are extracted to form a set of valid physical addresses to be mapped. These factory physical addresses include the module's factory hardware address, device serial number, interface number, and bus node number. The hash mapping algorithm parameters are initialized. The hash function uses an industrial-grade general-purpose hash algorithm, with an initial hash output length of 8 bits, supporting 256 virtual IDs. The total length of the consistent hash ring is fixed at 1000 units, and the number of virtual nodes is fixed at 200. Each virtual node corresponds to a global virtual ID for stable mapping. Based on the initialization parameters, a ring with a length of 1000 units is created. The structure is a ring-shaped network, evenly divided into 200 virtual node positions. Each position is assigned a unique global virtual ID, arranged sequentially. Each virtual node has a fixed position on the ring. After the hash ring is constructed, the structure and node allocation states are stored in a fixed manner, serving as the core carrier for mapping. The initialized hash function is used to perform a hash transformation on each selected valid physical address, obtaining a physical address hash value. Each generated physical address hash value is mapped one-to-one to a 1000-unit length of the consistent hash ring. Each hash value corresponds to a unique coordinate point on the ring, with all coordinate points evenly distributed on the ring to avoid local clustering. Then, the hash value of each physical address is mapped to a specific location on the ring. Starting from the mapped position on the hash ring, traverse the hash ring clockwise to find the virtual node closest to that mapped position. This virtual node is the matching node for the current physical address. Since the virtual nodes are evenly distributed, each physical address can be matched with a unique virtual node. After determining the closest virtual node corresponding to the physical address, directly assign the global virtual ID bound to that node to the current physical address, completing one-to-one mapping. After completing the mapping and assignment of all valid physical addresses, construct a doubly linked mapping list. Each record in the doubly linked mapping list contains information such as physical address, global virtual ID, real-time protocol type, and module online status, supporting bidirectional fast query between physical address and global virtual ID.When the number of connected modules increases and the existing virtual ID capacity is insufficient, the system automatically triggers bit length expansion. The initial bit length is 8 bits, supporting 256 virtual IDs. When the number of modules exceeds 200, it automatically expands to 16 bits, supporting 65,536 virtual IDs. When adding a module, only the physical address of the new module is hashed, mapped on the ring, matched with virtual nodes, and virtual IDs are assigned. The original module mapping relationship is not affected. When removing a module, only the virtual node corresponding to the module is marked as idle, and the global virtual ID is released for reuse. Only the local arc segment mapping relationship on the hash ring is adjusted. The overall hash ring structure is not changed, and the communication of other modules is not affected. The adjustment range is small and the impact is narrow, ensuring stable and continuous bus communication.

[0122] S2.4: Based on the mapping relationship between the global virtual ID and the module address, construct an address translation linked list;

[0123] Furthermore, in this embodiment, after completing the mapping from physical address to global virtual ID, an address translation list needs to be constructed to store, manage, and query the bidirectional mapping relationship between physical address and global virtual ID. When constructing the address translation list, the system traverses all sensing modules connected to the vehicle bus, extracting key information such as the global virtual ID, physical address, module type, protocol type, interface number, access time, online status, signal quality, and bus occupancy priority for each module, generating a linked list node record for each module. The linked list nodes adopt a doubly linked list structure, with each node containing a predecessor. The system uses a predecessor pointer to point to the previous node in the linked list and a successor pointer to point to the next node. It supports bidirectional traversal from the head to the tail and from the tail to the head, improving query efficiency and simplifying node addition and deletion operations, resulting in a well-constructed address translation linked list. After the address translation linked list is built, the head of the list stores the record of the first node connected to the bus module, and the tail stores the record of the last node connected to the bus module. All nodes are arranged in order according to the module access time or the global virtual ID, ensuring a well-organized, logically clear, and easily managed address translation linked list.

[0124] Furthermore, the address translation list supports multiple query methods. It can query the corresponding global virtual ID, module type, and protocol type through the physical address; it can query the corresponding physical address, online status, and signal quality through the global virtual ID; and it can query related module information in batches through module type and protocol type. The query process is fast and efficient with extremely short response time, meeting the needs of real-time communication, real-time scheduling, and real-time management of the vehicle bus.

[0125] Furthermore, the address translation list supports dynamic updates. When a new module is added to the vehicle bus, the system automatically generates a new list node, inserts it into the tail of the address translation list, and updates the tail pointer of the address translation list. When a module is removed from the vehicle bus, the system finds the corresponding list node, modifies the pointers of its predecessor and successor nodes, removes the list node from the address translation list, and releases storage space. When the module's online status, signal quality, or bus occupancy priority changes, the system directly locates the corresponding list node, modifies the corresponding field information within the node, and does not need to adjust the list structure.

[0126] S2.5: Based on the address translation linked list, extract the initial vector of cyclic redundancy check and generate the check parameters;

[0127] Furthermore, the specific steps of S2.5 include:

[0128] (1) Iterate through each node of the address translation linked list in sequence, and extract the basic format information of the data frame of the module from each node record. The basic format information of the data frame includes the frame header length, data payload length, frame tail length, check field position, check field length and protocol default check rule. In this embodiment, the frame header length is uniformly set to 8 bytes, the data payload length is fixed at 32 bytes according to the module type, the frame tail length is uniformly set to 4 bytes, the check field position is fixed at the beginning of the frame tail, the check field length is uniformly set to two bytes, and the protocol default check rule is cyclic redundancy check.

[0129] (2) Summarize the basic format information of all module data frames obtained by traversing the address translation linked list, and count the length of the verification field. In this embodiment, the length of the verification field of all modules is uniformly set to 2 bytes, that is, 16 bits. After determining the uniform verification field length, it is used as the length benchmark of the cyclic redundancy check initial vector.

[0130] (3) Determine the polynomial order parameter of the cyclic redundancy check algorithm. In this embodiment, according to the requirements of the vehicle communication scenario, the polynomial order of the cyclic redundancy check algorithm is set to 16th order. This order is the standard order commonly used in vehicle bus communication, which is compatible with the length of the 2-byte check field and meets the requirements for data transmission error detection.

[0131] (4) Based on the determined order of the 16th order polynomial, generate the corresponding cyclic redundancy check standard initial vector template. The cyclic redundancy check standard initial vector template is the default initial state value of the algorithm. The template length is consistent with the length of the check field. In this embodiment, the template length is 16 bits.

[0132] (5) Traverse the address translation list, count the real-time protocol types corresponding to all modules, and filter out the mainstream protocol types with the highest proportion. In this embodiment, the mainstream protocol types are fixed to 2, which correspond to commonly used industrial communication protocols. According to the default verification configuration of the mainstream protocol types, determine the initial vector base value. The initial vector base value is consistent with the standard initial vector template length, which is 16 bits.

[0133] (6) The 16-bit standard initial vector template and the initial vector reference value corresponding to the mainstream protocol are fused bit-by-bit. The fusion method is bit-by-bit logical operation to generate a set of candidate initial vectors. In this embodiment, the candidate initial vector set contains 8 different initial vectors, each of which is 16 bits long.

[0134] (7) Iterate through the eight initial vectors in the candidate initial vector set in sequence and perform compatibility matching with the protocol default verification rules of all modules in the address translation chain. The matching process verifies whether the initial vector is compatible with the data frame format, verification field length and protocol verification logic of each module. Select the initial vector that is compatible with the protocol of all modules in the chain. In this embodiment, a unique compatible initial vector is obtained.

[0135] (8) The selected compatible initial vector is determined as the cyclic redundancy check initial vector with a length of 16 bits, which is suitable for the 16th order cyclic redundancy check algorithm.

[0136] (9) The determined initial vector of cyclic redundancy check is integrated with the determined polynomial order, check field length and check field position to generate complete check parameters. In this embodiment, the polynomial order is 16, the check field length is 2 bytes, and the check field position is located at the beginning of the frame end. After integration, the check parameters are stored in the system-specified configuration area.

[0137] S2.6: Based on the bus load rate and the transmission delay, a dynamic time window cutting algorithm is used to divide the bus cycle into multiple equal-length time slots, and an exclusive time slot and a shared time slot are allocated to each global virtual ID to obtain a time slot allocation strategy;

[0138] Furthermore, the process of dividing equal-length time slots includes:

[0139] (1) Calculate the proportion of time occupied by effective data transmission in each transmission cycle based on the bus load rate. Effective data transmission refers to useful data such as service data, control instructions, and status information sent by the module, excluding useless signals such as idle signals, noise signals, and invalid frames. The higher the bus load rate, the greater the proportion of time occupied by effective data, and the more strained the bus resources are.

[0140] (2) Calculate the minimum time interval required for each request frame to be sent to the response frame based on the transmission delay. The minimum time interval ensures that there is enough time to wait for the response frame to return after the request frame is sent, so as to avoid the overlap and conflict between the request frame and the response frame.

[0141] (3) Multiply the total duration of the bus cycle by the proportion of time occupied by the effective data transmission to obtain the effective transmission duration. The effective transmission duration is the total time available for the module to send effective data within the bus cycle, excluding idle time, guard interval, and redundant time.

[0142] (4) Divide the effective transmission duration by the total number of global virtual IDs to obtain the basic time slot length, wherein the basic time slot length is the time resource evenly allocated to each module;

[0143] (5) The larger of the basic time slot length and the minimum time interval is used as the unit for dividing the equal-length time slot, thereby dividing the bus cycle into multiple equal-length time slots.

[0144] Furthermore, after the time slots are divided, the system allocates exclusive time slots and shared time slots to each global virtual ID. Exclusive time slots are dedicated time slots specifically assigned to any given module. Within an exclusive time slot, only that module can send data, while other modules are prohibited from sending data, ensuring that the module's data transmission is interference-free, collision-free, and highly reliable. This is suitable for modules with high real-time requirements, important data, and high priority, such as LiDAR, inertial navigation, and battery management systems. Shared time slots are common time slots used by multiple modules. Within shared time slots, modules send data in an orderly manner according to preset rules. This is suitable for modules with low real-time requirements, small data volume, and low priority, such as temperature and humidity sensors, vibration sensors, and auxiliary cameras. The reasonable combination and flexible allocation of exclusive and shared time slots not only ensure the real-time communication needs of high-priority modules but also improve the overall utilization of bus resources, achieving optimal resource allocation.

[0145] S2.7: Integrate the real-time protocol type, the global virtual ID, the address translation list, the verification parameters, and the time slot allocation strategy to output protocol adaptation configuration data.

[0146] S3: According to the protocol adaptation configuration data, call the double-buffered ping-pong architecture and FPGA scheduling logic to perform iterative optimization on the bus until the signal collision rate and bit error rate in the current transmission cycle are both lower than the preset threshold and the switching delay is less than the preset delay limit, and output the protocol adaptation ready signal.

[0147] Based on the protocol adaptation configuration data, the double-buffered ping-pong architecture and FPGA scheduling logic are invoked to perform iterative optimization of the bus, including:

[0148] S3.1: Based on the protocol adaptation configuration data, initialize the first and second buffers of the dual-buffered ping-pong architecture; the first and second buffers share the same physical storage medium but independently control the read and write pointers;

[0149] The dual-buffered ping-pong architecture includes a first buffer and a second buffer, which alternately serve as the write buffer and the read buffer, with the specific switching logic as follows:

[0150] S3.1.1: Within a preset first time period, the first buffer is configured as a write buffer and the second buffer is configured as a read buffer. In this embodiment, the duration of the first time period is set to 10ms.

[0151] In this embodiment, the storage capacity of a single buffer is set to 1024 data units, and each data unit corresponds to the smallest data block of a single bus transmission; the buffer data bus width is set to 32 bits to adapt to the standard data transmission bit width of the vehicle bus; the buffer read / write response latency is set to 100ns to meet the requirements of high real-time communication; the two buffers adopt the same design specifications, and the storage capacity, bus width, and response latency parameters are completely identical.

[0152] Furthermore, when the system detects that the start time of the first time period has arrived, it immediately executes the write configuration operation of the first buffer. The specific configuration includes: setting the working mode register of the first buffer to write mode, enabling the write enable signal of the first buffer, disabling the read enable signal of the first buffer, locking the write pointer of the first buffer to the start position, allowing data frames sent by the vehicle bus sensing module to be written to the first buffer, and prohibiting any data from being read from the first buffer. After the configuration is completed, the first buffer officially enters the write working state, only responding to data write requests and not responding to data read requests.

[0153] Furthermore, while completing the write configuration of the first buffer, the read configuration operation of the second buffer is executed simultaneously. The specific configuration includes: setting the working mode register of the second buffer to read mode, enabling the read enable signal of the second buffer, disabling the write enable signal of the second buffer, locking the read pointer of the second buffer to the starting position, allowing buffered data to be read from the second buffer to the main control unit or other modules, and prohibiting any data from being written to the second buffer. After the configuration is completed, the second buffer officially enters the read working state, only responding to data read requests and not responding to data write requests.

[0154] S3.1.2: Based on the fact that the write completion signal of the first buffer is set and the read completion signal of the second buffer is set, a buffer switching signal is triggered;

[0155] S3.1.3: In response to the buffer switching signal, the first buffer is reconfigured as a read buffer and the second buffer is reconfigured as a write buffer;

[0156] S3.1.4: At the same time, a buffer switching mutex is set in the FPGA scheduling logic. The buffer switching mutex is locked when the buffer switching signal is triggered and released after the configuration switching of the first buffer and the second buffer is completed and the read / write pointer is returned to zero.

[0157] S3.2: Based on FPGA scheduling logic, the first state machine is assigned to generate bus transmission timing, the second state machine is assigned to calculate the verification mechanism, and the third state machine is assigned to arbitrate the polling priority.

[0158] S3.3: Based on the time slot allocation strategy, the first state machine generates a time slot synchronization pulse. The rising edge of the time slot synchronization pulse triggers the switching of the current active buffer. The time slot allocation strategy includes key configurations such as bus cycle duration, total number of time slots, duration of a single time slot, rules for dividing exclusive and shared time slots, time slot start offset, and synchronization pulse period. In this embodiment, the bus cycle duration is set to 10ms, the total number of time slots is set to 8, the duration of a single time slot is set to 1.25ms, the proportion of exclusive time slots is set to 75%, the proportion of shared time slots is set to 25%, the time slot start offset is set to zero microseconds, and the synchronization pulse period is set to 10ms.

[0159] In this embodiment, the first state machine is an independent timing control unit inside the FPGA, responsible for the generation and timing scheduling of time slot synchronization pulses. During initialization, a pulse generation counter, a pulse width register, a rising edge trigger register, and a synchronization enable register are configured. In this embodiment, the counting precision of the pulse generation counter is set to 100ns, the value of the pulse width register is set to 500ns, the initial state of the rising edge trigger register is set to low level, and the initial state of the synchronization enable register is set to on. After all hardware resources are initialized, the machine is in a ready and standby state.

[0160] Furthermore, the pulse generation counter is used for precise timing, gradually accumulating with an accuracy of 100ns. In this embodiment, the bus cycle duration is 10ms, and the upper limit of the pulse generation counter is set to 100,000 counting units. The counter starts from the initial value of zero and increments. Each time the upper limit of the count is reached, one bus cycle timing is completed, and the counter is automatically cleared and the next round of counting begins.

[0161] Furthermore, the currently active buffer refers to the buffer in the double-buffered ping-pong architecture that is performing a write or read operation. In this embodiment, the initial active buffer is the first buffer configured in write mode, and the inactive buffer is the second buffer configured in read mode.

[0162] Furthermore, the specific steps of S3.3 include:

[0163] (1) Based on a single time slot duration of 1.25ms and a timing accuracy of 100ns, the counter count value corresponding to a single time slot is determined to be 12,500 count units. The first state machine generates a synchronization pulse trigger signal at the beginning of each time slot according to this interval. The synchronization pulse trigger signal is used to mark the time slot boundary and provide timing nodes for the generation of synchronization pulses. The generation interval accurately matches the time slot division to ensure that the pulse and time slot correspond one-to-one. The time slot synchronization pulse adopts a standard digital pulse signal. In this embodiment, the duration of the low level of the pulse is set to 1.25ms, and the duration of the high level, i.e., the pulse width, is set to 500ns.

[0164] (2) Initialize the synchronization enable register and pulse generation counter of the first state machine. Specifically, the synchronization enable register is in the open state, and the pulse generation counter starts from 0 and increments with an accuracy of 100ns. When the pulse generation counter reaches the counting unit corresponding to the duration of a single time slot, the first state machine immediately sets the rising edge trigger register from low level to high level to generate a pulse rising edge. After maintaining the high level for 500ns, it is automatically pulled low to complete the output of a single time slot synchronization pulse. This process is repeated to continuously generate a synchronization pulse sequence that corresponds to each time slot.

[0165] (3) The internal signal monitoring module of the first state machine continuously scans the synchronous pulse output port, captures the level transition state in real time, focuses on identifying the rising edge signal that transitions from low level to high level, and sets the monitoring response delay to 100ns to ensure that the rising edge signal is captured instantly, without omission or delay.

[0166] (4) When the monitoring module captures the rising edge of the synchronization pulse, the first state machine immediately generates a buffer switching instruction. The buffer switching instruction includes a switching enable signal, a target buffer configuration signal, and a read / write pointer reset signal. The instruction generation delay is set to 200ns.

[0167] (5) The first state machine sends the buffer switching instruction to the double-buffered ping-pong architecture control unit in real time through the dedicated control bus inside the FPGA, and the transmission delay is set to 100ns;

[0168] (6) After receiving the buffer switching command, the dual-buffered ping-pong architecture control unit immediately performs the buffer mode switching, reverses the working mode, read / write enable, and pointer state of the original active buffer, switches the write buffer to the read buffer, and switches the read buffer to the write buffer. At the same time, the read / write pointer is reset to the starting position. The switching process is directly executed by the hardware logic. The switching delay is fixed at 300ns. After the switching is completed, the active buffer identifier is updated to complete a complete switching.

[0169] (7) The first state machine continuously generates time slot synchronization pulses. Each pulse rising edge triggers a buffer switch. The switching rhythm is strictly synchronized with the time slot division. Eight pulses are generated and eight buffer switches are completed within the entire bus cycle. The cyclic process is stable, the timing is accurate, and there is no deviation.

[0170] S3.4: Based on the verification parameters, the second state machine adopts a parallel cyclic redundancy check mechanism to synchronously calculate the verification value during the process of writing data into the first buffer or the second buffer. The cyclic redundancy check mechanism is a prior art in this field and is not an inventive solution of this application, so it will not be described in detail here.

[0171] Furthermore, during the process of writing data into the first buffer or the second buffer, a checksum is calculated synchronously, specifically including:

[0172] (1) Configure the data writing bus width as the parallel computing bit width, wherein the parallel computing bit width is equal to the data bus width of the first buffer;

[0173] (2) The parallel cyclic redundancy check calculation unit is divided into multiple parallel sub-computation units, and each sub-computation unit corresponds to a data bit segment in the parallel calculation bit width;

[0174] (3) Each sub-computing unit adopts a linear feedback shift register structure, and the tap coefficients of the linear feedback shift register are determined by the cyclic redundancy check polynomial in the verification parameters;

[0175] (4) When data is written to the first buffer or the second buffer, all sub-computing units simultaneously receive the corresponding data bit segment and synchronously update their respective linear feedback shift register states;

[0176] (5) After the data is written, the states of the linear feedback shift registers of all sub-computation units are XORed and merged to obtain the final verification value.

[0177] S3.5: Based on the global virtual ID and the address translation list, the third state machine uses a dynamic priority queue algorithm to calculate the polling priority of each four-way vehicle-mounted multi-type perception module; the priority weight factor of the dynamic priority queue algorithm is determined by the weighted sum of the signal bit error rate and the bus load rate.

[0178] Furthermore, a dynamic priority queue algorithm is used to calculate the polling priority of each of the four-way vehicle's onboard multi-type perception modules, including:

[0179] (1) Based on the signal bit error rate and the bus load rate, construct a priority weighting factor calculation formula. The priority weighting factor is equal to the preset first weighting coefficient multiplied by the signal bit error rate plus the preset second weighting coefficient multiplied by the bus load rate. In this embodiment, the first weighting coefficient is set to 0.6 and the second weighting coefficient is set to 0.4.

[0180] (2) Retrieve the historical transmission records of each vehicle-mounted sensing module, and extract the waiting time, retransmission count, and service time of each module based on the historical transmission records of each module; the waiting time is the time difference between the current time and the last successful transmission time; the retransmission count is the total number of times the request frame of the module is retransmitted within the current transmission cycle; the service time is the bus time occupied by the module to complete a complete request-response transaction.

[0181] (3) Based on the priority weight factor, the waiting time, the number of retransmissions, and the service time, a multi-level feedback queue scheduling algorithm is used to calculate the dynamic priority value of each module; the dynamic priority value is equal to: the basic priority value multiplied by the priority weight factor, plus the waiting time coefficient multiplied by the waiting time, minus the service time coefficient multiplied by the service time, plus the retransmission penalty term; the retransmission penalty term is equal to the number of retransmissions multiplied by the preset penalty factor. In this embodiment, the preset penalty factor is fixed at 1 to quantify the impact of retransmission behavior on priority. The basic priority value is preset to 100 as the priority calculation benchmark; the waiting time coefficient is preset to 0.5 to compensate for the module waiting time; the service time coefficient is preset to 0.3 to suppress modules that occupy the bus for a long time.

[0182] (4) Sort the dynamic priority values ​​of all modules from largest to smallest to obtain the polling priority.

[0183] The process of outputting a protocol adaptation ready signal until the signal collision rate and bit error rate are both below a preset threshold and the switching delay is less than a preset delay limit within the current transmission cycle includes:

[0184] S3.6: Based on the verification mechanism, polling priority, and bus transmission timing generated by the first state machine based on the time slot allocation strategy, all four-way vehicle-mounted multi-type perception modules corresponding to the global virtual ID are polled sequentially in the current transmission cycle according to the time slot allocation strategy, and the collision event count and error frame count are collected in each polling process.

[0185] S3.7: The signal collision rate is obtained based on the ratio of the collision event count to the total number of polling times;

[0186] S3.8: The bit error rate is obtained based on the ratio of the error frame count to the total number of transmitted frames;

[0187] S3.9: The switching delay is obtained based on the difference between the time when the first state machine generates the time slot synchronization pulse and the actual time when the first buffer and the second buffer complete the switching.

[0188] S3.10: Determine whether the signal collision rate is lower than the collision rate threshold in the preset threshold, whether the bit error rate is lower than the bit error rate threshold in the preset threshold, and whether the switching delay is less than the preset delay upper limit; when all conditions are met, trigger the generation of a protocol adaptation ready signal. In this embodiment, the collision rate threshold is set to 1%, the bit error rate threshold is set to 0.1%, and the delay upper limit is set to 500ns; when any condition is not met, adjust the time slot length of the time slot allocation strategy, the priority weight factor of the dynamic priority queue algorithm, or the polynomial order of the parallel cyclic redundancy check mechanism, and repeat iterative optimization until the conditions are met.

[0189] Further, adjusting the time slot length of the time slot allocation strategy specifically includes: calculating a collision concentration index based on the signal collision rate collected in the current transmission cycle, wherein the collision concentration index is equal to the variance of the collision events in the time domain divided by the mean of the collision events; when the collision concentration index is greater than a preset concentration threshold of 1.5, a non-uniform time slot allocation method is used to divide the bus cycle into multiple time slots of unequal length, wherein the length of each time slot is inversely proportional to the signal collision rate of the module corresponding to that time slot; when the collision concentration index is less than or equal to the concentration threshold, a uniform time slot allocation method is used to divide the bus cycle into time slots equal to the number of global virtual IDs; and regenerating the time slot allocation strategy based on the adjusted time slot length.

[0190] Further, adjusting the priority weight factor of the dynamic priority queue algorithm specifically includes: calculating a channel quality assessment index based on the signal bit error rate and the bus load rate in the current transmission cycle, wherein the channel quality assessment index is equal to a linear combination of the logarithm of the signal bit error rate and the bus load rate; using the channel quality assessment index as input to a fuzzy logic controller, and after fuzzification, fuzzy inference, and defuzzification steps, outputting adjusted values ​​of the first weighting coefficient and the second weighting coefficient; updating the first weighting coefficient and the second weighting coefficient in the priority weight factor calculation formula based on the adjusted values, thereby adjusting the priority weight factor.

[0191] Further, adjusting the polynomial order of the parallel cyclic redundancy check (CRC) calculation unit specifically includes: determining whether the bit error rate (BER) is located in a high BER range, a medium BER range, or a low BER range based on the BER within the current transmission cycle; when the BER is located in a high BER range, setting the polynomial order of the parallel CRC calculation unit to the first order and enabling dual-check mode, wherein the dual-check mode simultaneously calculates the CRC checksum; when the BER is located in a medium BER range, setting the polynomial order to the second order, wherein the second order is less than the first order, and maintaining single-check mode; when the BER is located in a low BER range, setting the polynomial order to the third order, wherein the third order is less than the second order, and disabling the check bypass.

[0192] S4: Based on the protocol adaptation ready signal, perform seamless switching of multiple protocols and bus transmission according to the time slot allocation strategy and the polling priority of the global virtual ID planning, and collect frame-level transmission data of each four-way vehicle on-board multi-type perception module in real time during the communication process; the frame-level transmission data includes response data, verification results, fault identifiers and link status identifiers.

[0193] Based on the protocol adaptation readiness signal, and according to the polling priority of the time slot allocation strategy and the global virtual ID planning, seamless multi-protocol switching and bus transmission are performed, including:

[0194] S4.1: Based on the protocol adaptation ready signal, write the iteratively optimized polling priority into the priority register of the FPGA scheduling logic;

[0195] S4.2: Based on the iteratively optimized polling priority, the third state machine generates a polling sequence; each element in the polling sequence is a global virtual ID;

[0196] Furthermore, the third state machine is an independent scheduling unit within the FPGA, responsible for polling sequence generation and priority management. During initialization, it configures the sequence buffer register, sequence index counter, and sequence generation enable register. In this embodiment, the sequence buffer register has a storage length of 8 units to store the complete polling sequence; the sequence index counter has a fixed counting range of 1 to 8 to iterate through the polling sequence elements; the sequence generation enable register is initially set to enabled, allowing the polling sequence generation process to start, and is in a ready-to-go state after all hardware resources are initialized.

[0197] Furthermore, the process of generating the polling sequence includes:

[0198] (1) Iterate through the priority sorting results in sequence and extract the global virtual ID corresponding to each position in turn. In this embodiment, the global virtual ID is a unique identifier uniformly assigned by the system. Each module corresponds to a unique global virtual ID. The 8 modules correspond to 8 different global virtual IDs. The extraction process is carried out in the sorting order to ensure that the element order is completely consistent with the priority order.

[0199] (2) Set the initial value of the sequence index counter to 1, and start traversing from the first position of the sorting result. The sequence index counter is used to mark the position of the currently extracted element.

[0200] (3) Starting from the first position of the sorting result, the extracted global virtual IDs are stored into the sequence cache register in sequence. The sequence cache register stores them in the order of storage. The first global virtual ID stored is located at the beginning of the sequence, and the rest are arranged in sequence until all 8 global virtual IDs are stored into the sequence cache register, thus completing the sequence element filling.

[0201] (4) After the sequence is filled, the third state machine automatically checks the contents of the sequence buffer register. The check contents include whether the total number of sequence elements is 8, whether each global virtual ID is unique, without duplication, and without missing. The check logic strictly matches the number of modules and the ID allocation rules to ensure that the sequence is complete and valid.

[0202] (5) After the verification is passed, the order of the global virtual IDs stored in the sequence buffer register is the final polling sequence. Each element in the polling sequence is a global virtual ID. The order is completely consistent with the polling priority after iterative optimization. The module ID with higher priority is located at the front of the sequence, and the module ID with lower priority is located at the back of the sequence.

[0203] S4.3: Based on the polling sequence, the first state machine sequentially sends request frames in the exclusive time slot allocated by the time slot allocation strategy for the corresponding global virtual ID, and listens for response frames from the physical address corresponding to the module address mapping relationship; the response frame includes a checksum and a payload; the payload is the service transmission data collected by the four-way vehicle-mounted multi-type perception module;

[0204] S4.4: During the protection interval between the end of the exclusive time slot and the start of the next exclusive time slot, the second state machine performs a fast check comparison, and makes a consistency decision between the check code carried in the response frame and the calculation result of the parallel cyclic redundancy check mechanism; if the consistency decision passes, the first state machine writes the payload of the response frame into the current active buffer of the double-buffered ping-pong architecture; if the consistency decision fails, the third state machine triggers a retransmission mechanism, and retransmits the request frame in the next shared time slot allocated by the time slot allocation strategy.

[0205] Furthermore, the third state machine triggers a retransmission mechanism to retransmit the request frame in the next shared time slot allocated by the time slot allocation strategy, including:

[0206] (1) Based on the result of the consistency decision failing, the third state machine writes the global virtual ID of the module into the retransmission queue, and the retransmission queue adopts a first-in-first-out structure;

[0207] (2) Based on the fact that the retransmission queue is not empty, the third state machine inserts a retransmission flag into the polling sequence and temporarily raises the priority of the global virtual ID at the head of the retransmission queue to the highest level.

[0208] (3) When the next shared time slot arrives, the first state machine sends the request frame corresponding to the global virtual ID of the queue head according to the retransmission flag bit.

[0209] (4) If the same global virtual ID triggers the retransmission mechanism three times in a row, the third state machine generates a module offline alarm signal and temporarily removes the global virtual ID from the polling sequence.

[0210] The real-time acquisition of frame-level transmission data from various four-way vehicle-mounted multi-type perception modules during communication includes:

[0211] S4.5: Based on each successfully received response frame during the bus transmission process, extract the frame sequence number field from the header of the response frame, extract the payload field from the payload field of the response frame, extract the check field from the tail of the response frame, and merge the frame sequence number field, the payload field and the check field into response data of frame-level transmission data.

[0212] S4.6: Based on the result of the consistency decision, if the check code carried in the response frame matches the calculation result of the parallel cyclic redundancy check mechanism, a check success identifier is generated; if they do not match, a check failure identifier is generated. The check success identifier or the check failure identifier is recorded as the check result in the frame-level transmission data. If all byte values ​​of the check code and the calculation result are completely consistent, the result is a match.

[0213] S4.7: Based on the error flag bit carried in the response frame, obtain the fault identifier in the frame-level transmission data; the error flag bit is a built-in identifier bit in the response frame used to characterize the abnormality of the four-way vehicle's on-board multi-type perception module and communication; the fault identifier includes internal communication faults, sensor faults, and power supply faults of the four-way vehicle's on-board multi-type perception module.

[0214] Furthermore, the response frame is a structured data frame returned by the vehicle-mounted sensing module. The frame format is uniformly defined by the protocol adaptation configuration data. The error flag bit is a preset dedicated status bit within the response frame, used to mark abnormalities in module operation and communication. In this embodiment, the position of the error flag bit in the response frame is fixed at the fourth byte from the end of the frame, and the bit width is fixed at 1 byte, containing 8 independent status bits. Each bit corresponds to a preset fault type. This position and bit width parameters are fixed configurations predefined in the protocol adaptation phase, used to clarify the reading basis of the error flag bit.

[0215] Furthermore, the 8 bits of the error flag are mapped one-to-one with preset fault types. In this embodiment, the 8 bits correspond sequentially from high to low to module power supply fault, sensor hardware fault, communication interface fault, data acquisition abnormality, module overheating fault, voltage abnormality, current abnormality, and module offline fault. Each bit represents only a single fault type, with no overlapping meaning, and the mapping relationship is clear and unique.

[0216] Furthermore, the read byte error flag data is parsed bit by bit to determine the level status. In this embodiment, the bit level status is divided into two types: high level and low level. A high level is fixed to indicate that the corresponding fault type has occurred, and a low level is fixed to indicate that the corresponding fault type has not occurred. The level determination threshold is a preset standard digital circuit level. The parsing process is performed bit by bit, covering 8 fault type bits.

[0217] Furthermore, based on the bit level analysis results, the fault type corresponding to each bit is checked one by one, and all fault types corresponding to the high level state are summarized to form the fault type set reported by the current module in this transmission cycle; if all bits are low level, it is determined that no fault has occurred in the current module, and the fault type set is an empty set. The identification process strictly follows the bit mapping rules to ensure accurate fault type identification.

[0218] Furthermore, the fault identifier field is fixed to a length of 4 bytes, uses a text encoding format, and is initially set to blank for writing fault description information. The format and length parameters are pre-defined. In this embodiment, according to the preset fault type name, the identified fault types are converted into standard Chinese fault description text one by one, such as power failure, sensor hardware failure, communication interface failure, etc. If the fault type set is empty, it is converted into standard description text without fault. The converted standard fault description text is completely written into the fault identifier field of the frame-level transmission data. After writing, the content of the fault identifier field is the module fault status record corresponding to the current response frame.

[0219] S4.8: Based on the link status bits carried in the response frame, obtain the link status identifier in the frame-level transmission data; the link status identifier includes link connected state, link idle state, and link interrupted state.

[0220] Example 2:

[0221] Please see Figure 3 Another embodiment of the present invention provides: a multi-protocol intelligent adaptation communication switching system for four-way vehicles, comprising:

[0222] The signal and status acquisition module 10 is used to acquire the communication signal characteristics and bus status data of the four-way vehicle on-board multi-type perception module. The communication signal characteristics include level characteristics, frame header characteristics, baud rate characteristics and protocol type identifier. The bus status data includes bus load rate, signal bit error rate, transmission delay and module address mapping relationship.

[0223] The virtual address mapping module 20, based on the collected communication signal characteristics and bus status data, performs multi-protocol blind identification and virtual address mapping through algorithms such as variable step-size sliding window protocol feature matching, confidence calculation, hash mapping and dynamic time window cutting. It generates protocol adaptation configuration data containing protocol type, global virtual ID, address translation list, verification parameters and time slot allocation strategy, so as to realize unified identification of heterogeneous protocols and standardized management of addresses.

[0224] The iterative optimization module 30, based on the protocol adaptation configuration data, calls the dual-buffered ping-pong architecture and FPGA scheduling logic, and manages time slot synchronization, parallel verification and dynamic priority scheduling through three independent state machines, iteratively optimizing the bus transmission process until the signal collision rate and bit error rate are lower than the preset threshold and the switching delay meets the upper limit requirement, and outputs the protocol adaptation ready signal to ensure stable and efficient bus transmission.

[0225] The multi-protocol seamless switching module 40 generates a polling sequence by the FPGA state machine based on the protocol adaptation ready signal, time slot allocation strategy and global virtual ID planning polling priority. It sends request frames, listens for response frames and performs fast verification in the exclusive time slot. If the verification fails, it triggers retransmission in the shared time slot to complete the multi-protocol seamless switching and reliable bus data transmission, adapting to the dynamic communication requirements of four-way vehicles.

[0226] The frame-level data acquisition module 50 extracts the frame sequence number field, payload field, and verification field from the successfully received response frame during the communication process to generate response data. Combined with the verification consistency judgment result, the fault flag bit of the response frame, and the link status bit, it collects frame-level transmission data containing response data, verification result, fault identifier, and link status identifier in real time to realize full-state monitoring of the communication process.

[0227] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the present invention. All of these variations are within the protection scope of the present invention.

Claims

1. A multi-protocol intelligent adaptation communication switching method for four-way vehicles, characterized in that, include: The system acquires communication signal characteristics and bus status data of the multi-type sensing modules on the four-way vehicle. The communication signal characteristics include level characteristics, frame header characteristics, baud rate characteristics, and protocol type identifiers. The bus status data includes bus load rate, signal bit error rate, transmission delay, and module address mapping relationship. Based on the communication signal characteristics and bus status data, multi-protocol blind identification and virtual address mapping are performed to obtain protocol adaptation configuration data; the protocol adaptation configuration data includes protocol type, global virtual ID, address translation list, verification parameters and time slot allocation strategy; According to the protocol adaptation configuration data, the double-buffered ping-pong architecture and FPGA scheduling logic are invoked to perform iterative optimization of the bus until the signal collision rate and bit error rate in the current transmission cycle are both lower than the preset threshold and the switching delay is less than the preset delay limit, and then the protocol adaptation ready signal is output. According to the protocol adaptation ready signal, multi-protocol seamless switching and bus transmission are performed based on the time slot allocation strategy and the polling priority of the global virtual ID planning. During the communication process, frame-level transmission data of each of the four-way vehicle's on-board multi-type perception modules are collected in real time. The frame-level transmission data includes response data, verification results, fault identifiers and link status identifiers. Based on the protocol adaptation configuration data, the double-buffered ping-pong architecture and FPGA scheduling logic are invoked to perform iterative optimization of the bus, including: Based on the protocol adaptation configuration data, initialize the first and second buffers of the dual-buffered ping-pong architecture; the first and second buffers share the same physical storage medium but independently control the read and write pointers. Based on FPGA scheduling logic, three independent state machines are assigned to handle different optimization tasks. The three independent state machines are the first state machine, the second state machine, and the third state machine. Based on the time slot allocation strategy, the first state machine generates a time slot synchronization pulse, and the rising edge of the time slot synchronization pulse triggers the switching of the current active buffer; Based on the verification parameters, the second state machine adopts a parallel cyclic redundancy check mechanism to synchronously calculate the verification value during the process of writing data into the first buffer or the second buffer. Based on the global virtual ID and the address translation list, the third state machine uses a dynamic priority queue algorithm to calculate the polling priority of each four-way vehicle-mounted multi-type perception module; the priority weight factor of the dynamic priority queue algorithm is determined by the weighted sum of the signal bit error rate and the bus load rate; Based on the protocol adaptation readiness signal, and according to the polling priority of the time slot allocation strategy and the global virtual ID planning, seamless multi-protocol switching and bus transmission are performed, including: Based on the protocol adaptation ready signal, the iteratively optimized polling priority is written into the priority register of the FPGA scheduling logic; Based on the iteratively optimized polling priority, the third state machine generates a polling sequence; each element in the polling sequence is a global virtual ID; Based on the polling sequence, the first state machine sequentially sends request frames within the exclusive time slot allocated by the time slot allocation strategy for the corresponding global virtual ID, and listens for response frames from the physical address corresponding to the module address mapping relationship; the response frame contains a checksum and a payload; the payload is the service transmission data collected by the four-way vehicle-mounted multi-type perception module; During the protection interval between the end of the exclusive time slot and the start of the next exclusive time slot, the second state machine performs a verification comparison, comparing the checksum carried in the response frame with the calculation result of the parallel cyclic redundancy check mechanism to determine consistency. If the consistency determination passes, the first state machine writes the payload of the response frame into the current active buffer of the double-buffered ping-pong architecture. If the consistency determination fails, the third state machine triggers a retransmission mechanism, retransmitting the request frame in the next shared time slot allocated by the time slot allocation strategy.

2. The multi-protocol intelligent adaptation communication switching method for four-way vehicles as described in claim 1, characterized in that, Based on the communication signal characteristics and bus status data, multi-protocol blind identification and virtual address mapping are performed to obtain protocol adaptation configuration data, including: Based on the characteristics of communication signals, a protocol feature matrix is ​​constructed by calling a variable step-size sliding window protocol feature matching algorithm; the row vectors of the protocol feature matrix correspond to the time window indexes, and the column vectors correspond to the candidate sets of protocol types. Based on the protocol feature matrix, the posterior probability values ​​of each column vector are normalized into a protocol confidence vector, and the protocol type corresponding to the maximum value in the protocol confidence vector is taken as the real-time protocol type of the current four-way vehicle on-board multi-type perception module. Based on the real-time protocol type and the module address mapping relationship, a hash mapping algorithm is invoked to map the physical address to a global virtual ID; Based on the mapping relationship between the global virtual ID and the module address, an address translation linked list is constructed; Based on the address translation linked list, the initial vector of cyclic redundancy check is extracted, and check parameters are generated. Based on the bus load rate and the transmission delay, a dynamic time window cutting algorithm is used to divide the bus cycle into multiple equal-length time slots, and a dedicated time slot and a shared time slot are allocated to each global virtual ID to obtain a time slot allocation strategy. Integrate the real-time protocol type, the global virtual ID, the address translation list, the verification parameters, and the time slot allocation strategy to output protocol adaptation configuration data.

3. The multi-protocol intelligent adaptation communication switching method for four-way vehicles as described in claim 2, characterized in that, The construction of the protocol feature matrix by invoking the variable step-size sliding window protocol feature matching algorithm includes: Extract a continuous sampling sequence of communication signal features, initialize the start pointer and step counter of the sliding window based on the continuous sampling sequence, and dynamically adjust the window length of the sliding window according to the parity of the step counter. When the step counter is even, the window length is set to an integer multiple of the number of frame header feature bytes. When the step counter is odd, the window length is set to the product of the reciprocal of the baud rate feature and the preset sampling multiple. Based on the level characteristics in the communication signal features, the number of signal edge transitions is detected within the adjusted sliding window, and the number of signal edge transitions is matched with the preset standard protocol edge template using Hamming distance to obtain the matching distance value. If the matching distance value is less than the preset distance threshold, feature vector extraction is triggered, and the frame header feature byte sequence and protocol type identifier field are extracted within the adjusted sliding window. The row number of the protocol feature matrix is ​​determined by the starting pointer and step counter of the sliding window. The extracted frame header feature byte sequence and protocol type identifier field are used as the feature data of the row vector. The row vector of the protocol feature matrix is ​​constructed and stored in the first-in-first-out buffer queue. The column vector is constructed with the preset protocol type candidate set to form the protocol feature matrix.

4. The multi-protocol intelligent adaptation communication switching method for four-way vehicles as described in claim 3, characterized in that, Based on the protocol feature matrix, the posterior probability values ​​of each column vector are normalized into a protocol confidence vector, including: Obtain the prior probability distribution of the protocol type candidate set corresponding to each column vector in the protocol feature matrix; the prior probability distribution is dynamically updated based on historical adaptation records; Based on the column vectors of the protocol feature matrix within the current sampling period, the likelihood function value of each candidate protocol type under a given observation feature is calculated; the observation feature is the level feature and the frame header feature in the communication signal features; the likelihood function value is obtained by fitting the joint distribution of the level feature and the frame header feature using the Gaussian kernel density estimation method. Multiplying the prior probability distribution by the likelihood function value yields the unnormalized posterior probability value. Based on the sum of the unnormalized posterior probability values ​​of all candidate protocol types, a normalized division is performed on each unnormalized posterior probability value to obtain a posterior probability value. The posterior probability values ​​are then arranged in the order of the candidate protocol type set, and a protocol confidence vector is output.

5. The multi-protocol intelligent adaptation communication switching method for four-way vehicles as described in claim 4, characterized in that, The dual-buffered ping-pong architecture includes a first buffer and a second buffer, which alternately serve as the write buffer and the read buffer, with the specific switching logic as follows: Within a preset first time period, the first buffer is configured as a write buffer, and the second buffer is configured as a read buffer; The buffer switching signal is triggered when the write completion signal of the first buffer is set and the read completion signal of the second buffer is set. In response to the buffer switching signal, the first buffer is reconfigured as a read buffer and the second buffer is reconfigured as a write buffer; Meanwhile, a buffer switching mutex is set in the FPGA scheduling logic. The buffer switching mutex is locked when the buffer switching signal is triggered and released after the configuration switching of the first buffer and the second buffer is completed and the read / write pointers are returned to zero.

6. The multi-protocol intelligent adaptation communication switching method for four-way vehicles as described in claim 5, characterized in that, The process of outputting a protocol adaptation ready signal until the signal collision rate and bit error rate are both below a preset threshold and the switching delay is less than a preset delay limit within the current transmission cycle includes: Based on the verification mechanism, polling priority, and bus transmission timing generated by the first state machine based on the time slot allocation strategy, all four-way vehicle-mounted multi-type perception modules corresponding to the global virtual ID are polled sequentially in the current transmission cycle according to the time slot allocation strategy, and the collision event count and error frame count are collected in each polling process. The signal collision rate is obtained based on the ratio of the collision event count to the total number of polling iterations. The bit error rate is obtained based on the ratio of the number of erroneous frames to the total number of transmitted frames. The switching delay is obtained based on the difference between the time when the first state machine generates the time slot synchronization pulse and the actual time when the first buffer and the second buffer complete the switching. Determine whether the signal collision rate is lower than the collision rate threshold in the preset threshold, whether the bit error rate is lower than the bit error rate threshold in the preset threshold, and whether the switching delay is less than the preset delay upper limit; when all conditions are met, trigger the generation of a protocol adaptation ready signal; when any condition is not met, adjust the time slot length of the time slot allocation strategy, the priority weight factor of the dynamic priority queue algorithm, or the polynomial order of the parallel cyclic redundancy check mechanism, and repeat iterative optimization until the conditions are met.

7. The multi-protocol intelligent adaptation communication switching method for four-way vehicles as described in claim 6, characterized in that, The real-time acquisition of frame-level transmission data from various four-way vehicle-mounted multi-type perception modules during communication includes: Based on each successfully received response frame during the bus transmission process, the frame sequence number field is extracted from the header of the response frame, the payload field is extracted from the payload field of the response frame, and the check field is extracted from the tail of the response frame. The frame sequence number field, the payload field, and the check field are then merged into response data for frame-level transmission data. Based on the result of the consistency decision, if the check code matches the calculation result, a successful check is generated; if they do not match, a failed check is generated. The successful check or the failed check is recorded as the check result in the frame-level transmission data. Based on the error flag bit carried in the response frame, the fault identifier in the frame-level transmission data is obtained; the error flag bit is a built-in identifier bit in the response frame used to characterize the abnormality of the four-way vehicle's on-board multi-type perception module and communication; the fault identifier includes internal communication faults, sensor faults and power supply faults of the four-way vehicle's on-board multi-type perception module. Based on the link status bits carried in the response frame, the link status identifier in the frame-level transmission data is obtained; the link status identifier includes link connected state, link idle state, and link interrupted state.

8. A multi-protocol intelligent adaptation communication switching system for four-way vehicles, used to implement the multi-protocol intelligent adaptation communication switching method for four-way vehicles as described in any one of claims 1-7, characterized in that, include: The signal and status acquisition module is used to acquire the communication signal characteristics and bus status data of the four-way vehicle's on-board multi-type sensing modules; The virtual address mapping module performs multi-protocol blind identification and virtual address mapping based on the collected communication signal characteristics and bus status data, and generates protocol adaptation configuration data. The iterative optimization module, based on the protocol adaptation configuration data, calls the double-buffered ping-pong architecture and FPGA scheduling logic, iteratively optimizes the bus transmission process through three independent state machines, and outputs a protocol adaptation ready signal. The multi-protocol seamless switching module generates a polling sequence by the FPGA state machine based on the protocol adaptation ready signal, time slot allocation strategy and global virtual ID planning polling priority. It sends request frames, listens for response frames and performs verification in the exclusive time slot. If the verification fails, it triggers retransmission in the shared time slot to complete multi-protocol seamless switching and bus transmission. The frame-level data acquisition module collects frame-level transmission data in real time during communication, including response data, verification results, fault identifiers, and link status identifiers.

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