Distributed wireless device nanosecond-level clock synchronization method based on preset trigger mechanism

Abstract

This invention discloses a nanosecond-level clock synchronization method for distributed wireless devices based on a preset triggering mechanism. The method includes: a parameter presetting stage: a master node sends synchronization parameters to multiple slave nodes, wherein the synchronization parameters include a target clock counter value T, a channel number, and a packet type. The target clock counter value T is calculated by the master node based on the current reference clock counter value and a set reservation time; in response to the received synchronization parameters, the slave nodes record their current local clock counter value and synchronously switch to a receiving and listening state; a trigger alignment stage: when time T arrives, the master node sends a synchronization beacon to each slave node on a predetermined channel; in response to the received synchronization beacon, each slave node generates a hardware interrupt at the physical layer, and each slave node forcibly sets its local clock counter to T, completing relative clock alignment. This invention can achieve a high-precision, low-cost, low-power, and scalable clock synchronization solution.

Description

Technical Field

[0001] This invention relates to the field of clock synchronization technology, and more specifically, to a nanosecond-level clock synchronization method for distributed wireless devices based on a preset triggering mechanism. Background Technology

[0002] Distributed wireless data acquisition systems have wide applications in clinical diagnosis, neuroscience research, and IoT monitoring. In these applications, multiple distributed acquisition nodes need to maintain strict timeline alignment to ensure the temporal consistency of data across nodes. Especially in distributed acquisition devices, the system requires a strict clock synchronization rate.

[0003] Clock synchronization is one of the core technologies of distributed systems. Traditional wired systems maintain strict synchronization between channels through a physical bus, but the cumbersome cabling limits the system's portability and application scenarios. While wireless systems have solved the cabling problem, the distributed architecture inevitably introduces clock drift and phase delay issues. Achieving high-precision clock phase synchronization among multiple devices in a wireless environment is a key technical challenge in this field.

[0004] Currently, the following technical solutions are mainly used for clock synchronization in wireless devices: (1) Synchronization method based on NTP (Network Time Protocol). NTP is a protocol for time synchronization in computer networks. It is based on UDP transmission and uses software timestamps to record the time of data packet transmission and reception, and calculates and compensates for network latency. The accuracy of this method is usually in the millisecond range, which is suitable for application scenarios where the synchronization accuracy requirement is not high, but cannot meet the nanosecond-level synchronization requirements.

[0005] (2) Synchronization method based on PTP (Precision Time Protocol). PTP is a precision clock synchronization protocol defined by the IEEE standard, which can achieve sub-microsecond synchronization accuracy through hardware timestamps. This method requires dedicated hardware support, has a high protocol stack complexity, consumes a lot of power, and performs well in wired Ethernet environments, but its accuracy in wireless environments is significantly affected by protocol stack jitter.

[0006] (3) Synchronization methods based on UWB (Ultra-Wideband). UWB technology utilizes the high temporal resolution of ultra-wideband signals to achieve ranging and synchronization accuracy at the nanosecond or even sub-nanosecond level. However, UWB modules have high power consumption, are expensive, and require additional hardware support, making them unsuitable for resource-constrained wearable devices and large-scale sensor network deployments.

[0007] (4) Master-slave synchronization method based on BLE (Bluetooth Low Energy). Existing commercial wireless electromyography (EMG) acquisition systems (such as Cometa PICO X) mostly use BLE for data transmission and synchronization. These systems typically employ a master-slave architecture, where the master device periodically sends synchronization packets to the slave device, and the slave device adjusts its local clock based on the received time. Due to jitter in the BLE protocol stack and the limited accuracy of the software timestamp, the synchronization error of this approach is typically in the microsecond to millisecond range, which cannot meet the nanosecond-level synchronization requirements.

[0008] In existing technologies, patent application CN202610049694.0 employs a classic master-slave architecture and a bidirectional timestamp exchange mechanism (similar to the PTP protocol). The master device obtains four key timestamps by sending synchronization request packets and receiving response packets from slave devices to calculate transmission delay and clock skew, thereby achieving clock synchronization among multiple slave devices. However, this scheme uses a continuous bidirectional handshake synchronization mode, requiring each slave device to frequently interact with the master device, resulting in significant communication overhead and the master node easily becoming a system bottleneck. Furthermore, this scheme relies on real-time measurement of network round-trip time, which limits synchronization accuracy and stability in complex wireless environments, and synchronization accuracy is affected by the protocol stack.

[0009] Patent application CN202010451060.0 employs a two-step synchronization strategy: first, it corrects clock frequency errors to align the slave and master devices' frequencies; then, it uses a broadcast packet to use the master device's transmission time as the slave device's reference time to achieve phase synchronization, thereby reducing the frequency of synchronization interactions between the master and slave devices. However, because this scheme uses a progressive frequency locking mechanism, it requires continuous detection and adjustment of frequency errors to achieve stability, resulting in a long convergence time and making it difficult to meet the need for rapid synchronization. Furthermore, this scheme uses the broadcast packet arrival time as the reference time, lacking a precise compensation mechanism for wireless transmission delays. Synchronization accuracy is significantly affected by network jitter, making it difficult to achieve nanosecond-level accuracy. It also still relies on the master device's periodic broadcasts to maintain synchronization, placing a heavy burden on the master node in a distributed architecture with a large number of devices, making it difficult to guarantee strict consistency of sampling times across multiple terminals.

[0010] Patent application CN202510096573.7 employs a time-slot allocation + passive monitoring mechanism: different transmission time slots are allocated to N UWB base stations. Each base station broadcasts signals according to its respective time slot. Tags are only responsible for monitoring all broadcast messages and calculating their location based on arrival time, without needing to communicate bidirectionally with the base stations. However, due to the numerous UWB protocol standards currently on the market, there is a lack of unified and mature protocol access and PHY facilities similar to BLE and Wi-Fi. Therefore, this solution has significant drawbacks in terms of cost and compatibility.

[0011] Patent application CN202510397196.0 utilizes existing 2.4GHz air signals (Wi-Fi, Bluetooth, ZigBee, etc.) as a clock reference source, receiving and down-converting them through a miniaturized ceramic antenna to achieve crystal-free clock calibration for SOC chips. However, the core objective of this scheme is not clock synchronization, but rather to use the vibration frequency of the 2.4GHz signal as a reference source for clock accuracy, thereby correcting the system's clock frequency.

[0012] Patent application CN202510964025.1 employs timestamp-free switching and EKF filtering to achieve multi-node clock synchronization, reducing wireless communication overhead through passive listening by silent nodes. The overall approach leans towards lightweight collaboration in low-speed wireless sensor networks. However, this scheme is prone to introducing uncontrollable delays due to MAC layer queuing and multipath effects. Furthermore, there is a significant tension between the computational overhead of EKF iteration and the low-power constraints of the terminal. The overall scheme is more suitable for sensor networks with low data rates and stable topologies, rather than high-real-time signal acquisition systems. Moreover, the synchronization in this scheme relies primarily on algorithmic compensation, depending on the stability of the air channel.

[0013] Analysis reveals that existing clock synchronization schemes have the following main drawbacks: (1) Software timestamp accuracy is limited: Traditional synchronization protocols (such as NTP, PTP, BLE synchronization) rely on software timestamps to record the time of data packet transmission and reception. Affected by factors such as operating system scheduling, protocol stack processing delay, and interrupt response time, the timestamp accuracy is usually at the microsecond level or even the millisecond level, which cannot meet the nanosecond level synchronization requirements.

[0014] (2) Impact of protocol stack jitter: The processing of wireless communication protocol stack has uncertain delays, including packet parsing, address filtering, CRC verification, etc., which cause random deviations between the actual reception time of the synchronization packet and the time recorded by the local clock, seriously affecting the synchronization accuracy.

[0015] (3) High hardware cost and high power consumption: Although high-precision synchronization schemes based on dedicated hardware such as UWB can achieve nanosecond-level accuracy, they require additional radio frequency modules and complex signal processing circuits, which leads to a significant increase in system cost and power consumption, making them unsuitable for large-scale sensor networks and wearable applications.

[0016] (4) Limited scalability: In the master-slave synchronization architecture, as the number of slave devices increases, the burden of sending synchronization packets by the master device increases, and the probability of collision increases due to multiple devices competing for the channel, resulting in a decrease in synchronization accuracy and reliability, making it difficult to support large-scale distributed networks. Summary of the Invention

[0017] The purpose of this invention is to overcome the shortcomings of the prior art and provide a nanosecond-level clock synchronization method for distributed wireless devices based on a preset triggering mechanism. This method includes: Parameter preset stage: The master node sends synchronization parameters to the corresponding multiple slave nodes. The synchronization parameters include the target clock counter value T, the channel number, and the packet type. The target clock counter value T is calculated by the master node based on the current reference clock counter value and the set reservation time. In response to the received synchronization parameters, the slave nodes record the current local clock counter value and synchronously switch to the receiving and listening state. Triggering Alignment Phase: When the master node arrives at time T, it sends a synchronization beacon to each slave node through a predetermined channel; in response to the received synchronization beacon, each slave node generates a hardware interrupt at the physical layer, and each slave node forces its local clock counter to T, thus completing relative clock alignment.

[0018] Compared with existing technologies, the advantages of this invention lie in its provision of a nanosecond-level clock phase synchronization method for distributed wireless devices based on a preset-trigger mechanism. This method achieves nanosecond-level hard synchronization among multiple devices without increasing additional hardware costs by leveraging the consistency of hardware interrupt responses at the BLE PHY layer. This invention, through a two-stage synchronization process involving parameter preset and broadcast triggering, avoids jitter handling in the protocol stack, providing a high-precision, low-power, and scalable clock synchronization solution for resource-constrained wireless sensor networks. It can meet the nanosecond-level synchronization accuracy requirements of applications such as high-precision physiological signal acquisition and distributed IoT monitoring.

[0019] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0021] Figure 1 This is a flowchart of a nanosecond-level clock synchronization method for distributed wireless devices based on a preset triggering mechanism according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the synchronous broadcast packet structure according to an embodiment of the present invention; Figure 3 This is a timing diagram of the synchronization process according to an embodiment of the present invention; Figure 4 This is a schematic diagram of synchronous verification according to an embodiment of the present invention; In the attached diagram, Preamble; Access Address; Data; System Tick; Type. Detailed Implementation

[0022] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0023] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0024] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0025] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0026] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0027] A distributed wireless device system consists of a master node (or central node, master device) and multiple slave nodes (or slave devices), with each master node having multiple slave nodes. This invention aims to achieve precise clock synchronization between distributed wireless device systems. Through a "preset-triggered" relative clock synchronization mechanism, nanosecond-level hard synchronization of multiple slave nodes can be achieved, with the number of slave nodes potentially exceeding 32. The master node is responsible for sending synchronization parameters and triggering broadcast packets (or synchronization beacons) as the system's reference clock source. Slave nodes perform the actual synchronization tasks; for example, the synchronization timing is triggered by a timer controlled by the CH585's clock counter. The following design primarily uses the CH585 chip as an example, utilizing its integrated system clock counter (the counter frequency is consistent with the system clock frequency, 78MHz) and PHY (physical layer) hardware interrupt mechanism to achieve nanosecond-level clock synchronization for distributed wireless devices. It should be understood that other chip models besides the CH585 can also be used.

[0028] See Figure 1 As shown, the provided method for nanosecond-level clock synchronization of distributed wireless devices based on a preset triggering mechanism mainly includes the following steps: Step S1, parameter preset stage: The master node sends synchronization parameters to the corresponding multiple slave nodes, wherein the synchronization parameters include the target clock counter value T, the channel number and the packet type. The target clock counter value T is calculated by the master node based on the current reference clock counter value and the set reservation time. In response to the received synchronization parameters, the slave nodes record the current local clock counter value and synchronously switch to the receiving and listening state. Specifically, the master node first calculates the target clock counter value T. For example, the calculation formula is T = current clock counter count + reserved time Δt. The reserved time Δt is usually 1 second, used to ensure that all slave nodes have enough time to complete parameter reception and state switching.

[0029] The master node sends synchronization parameters to the slave nodes via broadcast. These synchronization parameters include: target clock counter value T, broadcast channel number Ch, and packet type Type=0xFF, etc.

[0030] After all slave nodes receive the T value, they record the current local clock counter value and synchronously switch to the RX (receive) listening state, waiting for the arrival of time T.

[0031] This invention, through a parameter preset stage, ensures that all devices know the target time T in advance before triggering, and only need to wait for the trigger signal to arrive, without the need for complex parameter analysis and calculation at the triggering time.

[0032] Step S2, triggering the alignment phase: When the master node arrives at time T, it sends a synchronization beacon to each slave node on a predetermined channel; in response to the received synchronization beacon, each slave node generates a hardware interrupt at the physical layer, and each slave node forces its local clock counter to T, thus completing the relative clock alignment.

[0033] Specifically, when the local clock counter of the master node reaches the preset target value T, it immediately sends a synchronization broadcast packet on the designated channel Ch. Combined with... Figure 2 As shown, the synchronous broadcast packet format includes: a 32-bit address field, a 1-byte payload (0xFF), and a specific type identifier. Figure 3 This is a schematic diagram of the synchronous process.

[0034] Because wireless signals travel at the speed of light, the 32 slave devices (slave nodes) receive the broadcast packet almost simultaneously. When the RF module detects a valid data packet, a hardware interrupt (RF-IRQ) is generated at the PHY layer (physical layer). This interrupt is generated directly by the RF hardware, without being processed by the protocol stack, and the response time is deterministic and consistent.

[0035] Within the Interrupt Service Routine (ISR), each slave device immediately forces its local clock counter to the preset target value T, completing relative clock alignment. Since all devices generate PHY layer interrupts at the same RF reception time and the interrupt response code paths are consistent, the clock skew between devices is minimized.

[0036] In one embodiment, to ensure synchronization accuracy, the ISR code path is strictly controlled within 12 clock cycles (@78MHz ≈154 ns). Utilizing the interrupt response consistency of the CH585 chip, the differences between devices are compressed to 1-2 clock cycles (13-26 ns).

[0037] In summary, this invention decouples and coordinates the parameter presetting and trigger alignment stages, enabling the synchronization mechanism to effectively reduce latency and errors during time synchronization, improving the coordination efficiency and time accuracy of distributed systems. Furthermore, this modular design and broadcast triggering mechanism offer excellent scalability; by distributing synchronization parameters, the master node can simultaneously manage at least 32 slave nodes, and synchronization accuracy does not significantly decrease with the increase in the number of devices. The two stages of this invention's synchronization mechanism (parameter presetting + trigger alignment) are significantly superior to traditional real-time synchronization technologies through "advance distribution and timely triggering," achieving comprehensive optimization in response latency, computational load, and time accuracy. Compared to existing technologies, the core difference of this invention's synchronization mechanism lies in pre-positioning critical computation and communication, avoiding performance bottlenecks at the synchronization trigger moment. Traditional synchronization methods (such as real-time calibration based on broadcast timestamps) typically send time information only at the moment of triggering, requiring each node to complete reception, parsing, and local clock adjustment within a very short time, making them susceptible to network jitter and processing delays, leading to decreased synchronization accuracy.

[0038] To verify the effectiveness of the invention, further synchronization performance tests were conducted. See [link / reference] Figure 4 As shown, a synchronization accuracy test platform was established. An oscilloscope with a bandwidth of ≥250 MHz was used to monitor the PPS (Pulse Per Second) signal output from the GPIO of multiple nodes, directly measuring the clock deviation between nodes. A loopback test was designed to verify synchronization consistency. Verification results show that, in a static scenario, the clock deviation between nodes is ≤50 ns, and in a dynamic scenario (relative node speed ≤1 m / s), it is ≤100 ns.

[0039] It should be noted that, without departing from the spirit and scope of this invention, those skilled in the art can make appropriate changes or modifications to the above embodiments. For example, the preset parameter distribution method can adopt either broadcast distribution of synchronization parameters or BLE broadcast method, that is, the master node distributes synchronization parameters through the BLE broadcast channel, and the slave nodes receive them through BLE. This method is compatible with BLE mode and is more suitable for a fully wireless distributed architecture. Alternatively, periodic beacon triggering can be used, that is, the master node periodically sends beacon frames, and the slave nodes adjust their local clocks according to the reception time of the beacon frames. This method is suitable for scenarios requiring continuous synchronization.

[0040] In summary, compared to existing technologies, this invention designs a two-stage "preset-trigger" synchronization mechanism, achieving nanosecond-level hard synchronization of multiple devices through a two-stage synchronization process of "parameter preset + broadcast trigger". In the preset stage, the master node calculates the target clock counter value T and sends it to all slave nodes. Each device receives the T value in advance and switches to RX listening state. In the trigger stage, the master node sends an RF synchronization broadcast packet when the clock counter value equals T. All devices generate a PHY layer hardware interrupt at the same RF reception time, forcibly setting the clock counter to T within the interrupt service routine, thus completing the alignment. This mechanism avoids protocol stack jitter handling and utilizes the consistency of PHY layer interrupt responses to achieve nanosecond-level alignment. Furthermore, this invention utilizes the consistency of BLE PHY layer (physical layer) hardware interrupt responses to achieve nanosecond-level clock alignment of multiple devices. When the RF module detects a valid synchronization broadcast packet, it directly generates a hardware interrupt (RF-IRQ) at the PHY layer, bypassing the packet parsing, address filtering, and CRC check processing steps of the protocol stack. Interrupt Service Routine (ISR) code paths are strictly controlled within 12 clock cycles (@78MHz≈154ns). Leveraging the interrupt response consistency of the CH585 chip, inter-device differences are compressed to 1-2 clock cycles (13-26 ns). This design eliminates the need for an additional synchronization clock line, overcoming the accuracy bottleneck (typically >1 μs) of traditional PTP / FTSP protocols that rely on software timestamps. Compared to traditional software timestamp-based PTP protocols (sub-microsecond level) and BLE synchronization schemes (microsecond to millisecond level), it achieves a 2-3 order of magnitude improvement. In summary, this invention offers significant advantages in synchronization accuracy, hardware cost, power consumption control, and scalability, while significantly reducing system cost and power consumption. It overcomes the existing technological bottleneck in balancing accuracy and cost, making it particularly suitable for resource-constrained wearable devices and large-scale sensor networks.

[0041] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0042] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0043] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0044] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0045] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0046] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. It will be known to those skilled in the art that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are equivalent.

[0047] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.

Claims

1. A nanosecond-level clock synchronization method for distributed wireless devices based on a preset triggering mechanism, comprising: Parameter preset stage: The master node sends synchronization parameters to the corresponding multiple slave nodes. The synchronization parameters include the target clock counter value T, the channel number, and the packet type. The target clock counter value T is calculated by the master node based on the current reference clock counter value and the set reservation time. In response to the received synchronization parameters, the slave nodes record the current local clock counter value and synchronously switch to the receiving and listening state. Triggering Alignment Phase: When the master node arrives at time T, it sends a synchronization beacon to each slave node through a predetermined channel; in response to the received synchronization beacon, each slave node generates a hardware interrupt at the physical layer, and each slave node forces its local clock counter to T, thus completing relative clock alignment.

2. The method according to claim 1, characterized in that, Each slave node generates the hardware interrupt according to the following steps: When the RF module detects a valid synchronization beacon, it generates a hardware interrupt directly at the physical layer, bypassing the packet parsing, address filtering, and CRC check processing steps of the protocol stack. The interrupt service routine code path is strictly controlled within 12 clock cycles. By utilizing the interrupt response consistency of the CH585 chip, the differences between slave nodes are compressed to 1-2 clock cycles.

3. The method according to claim 1, characterized in that, The reserved time is set according to the time required for the slave node to complete the reception of synchronization parameters and state switching.

4. The method according to claim 1, characterized in that, The format of the synchronization beacon includes: a 32-bit address field, a 1-byte payload, and a specific type identifier.

5. The method according to claim 1, characterized in that, The master node sends the synchronization parameters to the corresponding multiple slave nodes via broadcast or BLE broadcast.

6. The method according to claim 1, characterized in that, Also includes: For scenarios requiring continuous synchronization, the master node periodically sends synchronization beacon frames, and each slave node adjusts its local clock according to the time of receiving the synchronization beacon frames.

7. The method according to claim 1, characterized in that, The number of slave nodes corresponding to the master node is greater than or equal to 32.

8. The method according to claim 3, characterized in that, Set the reserved time to 1 second.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

10. A computer device comprising a memory and a processor, wherein a computer program capable of running on the processor is stored in the memory, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

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