Sot-mram memory cell and method of fabricating the same

Abstract

This invention provides a SOT-MRAM memory cell and its fabrication method. The SOT-MRAM memory cell includes: a bottom electrode, a substrate, a seed layer, an SOT source layer, a fully antiferromagnetic tunnel junction, and a top electrode layer, stacked sequentially from bottom to top. The substrate is made of an amorphous dielectric material, the seed layer is made of an insulating cubic seed material, and the SOT source layer is made of a cubic non-collinear antiferromagnetic material. The lattice constant of the SOT source layer ranges from 3.8 Å to 4.4 Å, and the lattice constant of the antiferromagnetic material in the fully antiferromagnetic tunnel junction also ranges from 3.8 Å to 4.4 Å. The bottom electrode is located below or above the SOT source layer and is electrically connected to the SOT source layer. This invention can effectively reduce the current density when writing to the memory cell, break through the performance limits of ferromagnetic materials, and achieve sub-nanosecond high-speed writing of the memory cell.

Description

Technical Field

[0001] This invention relates to the field of magnetic random access memory (MRAM) technology, and more particularly to a SOT-MRAM memory cell and its fabrication method. Background Technology

[0002] Magnetic random access memory (MRAM) is a novel high-speed non-volatile memory technology. Currently, the industrialized magnetic memory product is STT-MRAM. SOT-MRAM, as a next-generation spin memory technology, uses spin-orbit materials to generate spin currents for data writing. Its read and write paths are separated, which is expected to achieve a comprehensive breakthrough in MRAM in terms of lifespan, speed, and power consumption. Current vertical SOT-MRAM memory cells all use a ferromagnetic tunnel junction structure composed of CoFeB / MgO / CoFeB. Its vertical magnetic anisotropy originates from the interface at the CoFeB and MgO interface. The free layer thickness needs to be controlled at around 1nm, and the spin precession frequency is on the order of GHz. Thus, when the write time of the SOT-MRAM memory cell is less than 5ns, it enters the precession-flip mode, and the required write power consumption surges, which cannot fully utilize the advantages of SOT technology. Summary of the Invention

[0003] To address the aforementioned issues, the SOT-MRAM memory cell and its fabrication method provided by this invention, by forming an insulating cubic seed layer, a cubic non-collinear antiferromagnetic material SOT source layer, and a fully antiferromagnetic tunnel junction on a substrate, can effectively reduce the current density for writing to the memory cell, break through the performance limits of ferromagnetic materials, and achieve sub-nanosecond-level high-speed writing of the memory cell.

[0004] In a first aspect, the present invention provides a SOT-MRAM memory cell, the SOT-MRAM memory cell comprising: a substrate, a bottom electrode, a seed layer, an SOT source layer, a fully antiferromagnetic tunnel junction, and a top electrode layer stacked sequentially from bottom to top;

[0005] The substrate is made of amorphous dielectric material, the seed layer is made of insulating cubic seed material, the SOT source layer is made of cubic non-collinear antiferromagnetic material, the lattice constant of the SOT source layer ranges from 3.8 Å to 4.4 Å, and the lattice constant of the antiferromagnetic material in the fully antiferromagnetic tunnel junction ranges from 3.8 Å to 4.4 Å. The bottom electrode is located below or above the SOT source layer and is electrically connected to the SOT source layer.

[0006] Optionally, the fully antiferromagnetic tunnel junction includes: a first antiferromagnetic electrode layer, a barrier layer, and a second antiferromagnetic electrode layer stacked sequentially from bottom to top; The lattice constants of both the first and second antiferromagnetic electrode layers range from 3.8 Å to 4.4 Å. The barrier layer is made of cubic dielectric material, and its thickness ranges from 0.5 nm to 2.5 nm. The thickness of the first antiferromagnetic electrode layer and the second antiferromagnetic electrode layer both range from 5 nm to 50 nm.

[0007] Optionally, the materials of the first antiferromagnetic electrode layer and the second antiferromagnetic electrode layer are at least one of cubic antiferromagnetic material and tetragonal antiferromagnetic material, respectively. Cubic antiferromagnetic materials include: Mn3Pt, Mn3Ir, Mn3Rh, Mn3GaN, Mn3NiN, and Mn3SnN; tetragonal antiferromagnetic materials include: Mn2Au, CuMnAs, and Mn2Au. 1.9 SbCr 0.1 ; In the SOT source layer, the first antiferromagnetic electrode layer, the barrier layer, and the second antiferromagnetic electrode layer, the lattice fit between adjacent layers is less than 5%.

[0008] Optionally, a lattice buffer layer is formed between at least one pair of adjacent functional layers, the functional layers including: an SOT source layer, a first antiferromagnetic electrode layer, a barrier layer, and a second antiferromagnetic electrode layer; The lattice constant of the lattice buffer layer is less than the largest lattice constant of the two functional layers adjacent to the lattice buffer layer, and greater than the smallest lattice constant of the two functional layers adjacent to the lattice buffer layer.

[0009] Optionally, a magnetic functional layer is stacked on top of the fully antiferromagnetic tunnel junction, and the magnetic functional layer is located below the top electrode layer. The bias field provided by the magnetic functional layer to the second antiferromagnetic electrode layer is greater than the coercive field of the second antiferromagnetic electrode layer.

[0010] Optionally, the resistivity of the seed layer is greater than or equal to ten times the resistivity of the SOT source layer.

[0011] Optionally, the thickness of the SOT source layer ranges from 3 nm to 25 nm; The materials for the SOT source layer include: Mn3Pt, Mn3Ir, Mn3Rh, Mn3GaN, Mn3NiN, Mn3SnN, Mn2Au, CuMnAs, and Mn. 1.9 SbCr 0.1 At least one of them.

[0012] Optionally, the thickness of the seed layer ranges from 1 nm to 100 nm; The seed layer material includes at least one of NiO, MgAl2O4, SrTiO3, BaTiO3, LaNiO3, LaMnO3, and MgO; Amorphous dielectric materials include at least one of silicon, silicon oxide, and silicon nitride.

[0013] Secondly, the present invention provides a method for fabricating a SOT-MRAM memory cell, the method comprising: A substrate is provided, and the substrate material is an amorphous dielectric material; A seed layer is grown on the upper surface of the substrate, and the material of the seed layer is an insulating cubic seed material; Pattern the seed layer and etch it to expose the substrate; The substrate is etched and filled with conductive material to form a bottom electrode prefabrication layer; Planarize the bottom electrode prefabrication layer to expose the seed layer and form the bottom electrode; A cubic non-collinear antiferromagnetic material is deposited on the upper surface of the seed layer and the bottom electrode to form the SOT source layer; A fully antiferromagnetic tunnel junction is formed on the upper surface of the SOT source layer; The lattice constants of the antiferromagnetic materials in the SOT source layer and the fully antiferromagnetic tunnel junction range from 3.8 Å to 4.4 Å.

[0014] Thirdly, the present invention provides a method for fabricating a SOT-MRAM memory cell, the method comprising: A substrate is provided, and the substrate material is an amorphous dielectric material; A seed layer and an SOT source layer are sequentially formed from bottom to top on the upper surface of the substrate; the seed layer is made of insulating cubic seed material, and the SOT source layer is made of cubic non-collinear antiferromagnetic material. Patterned SOT source layer; A bottom electrode and a fully antiferromagnetic tunnel junction are formed on the upper surface of the patterned SOT source layer; The bottom electrode is located on opposite sides of the fully antiferromagnetic tunnel junction; the lattice constants of the antiferromagnetic material in the SOT source layer and the fully antiferromagnetic tunnel junction are both in the range of 3.8 Å to 4.4 Å.

[0015] The SOT-MRAM memory cell and its fabrication method provided in this invention, by forming an insulating cubic seed layer, a cubic non-collinear antiferromagnetic material SOT source layer, and an epitaxial stack of a fully antiferromagnetic tunnel junction on a substrate, makes the magnetic storage coercivity of the memory cell adjustable in the range of 0.01 T to 2 T, and reduces the write current density to the range of 2 MA / cm² to 10 MA / cm², breaking through the performance limit of ferromagnetic materials and realizing sub-nanosecond-level high-speed writing. At the same time, it utilizes the z-spin of the non-collinear antiferromagnetic spin source to achieve deterministic flipping without magnetic field assistance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic structural diagram of a SOT-MRAM memory cell according to an embodiment of this application; Figure 2 This is a comparison diagram of the coercivity of antiferromagnetic material layers of different thicknesses in an embodiment of this application; Figure 3 This is a schematic diagram of research data on low-power flip-type antiferromagnetic materials and the anti-magnetic field interference characteristics of antiferromagnetic materials according to an embodiment of this application; Figure 4 This is a schematic structural diagram of a SOT-MRAM memory cell according to an embodiment of this application; Figures 5 to 11 This is a schematic structural diagram illustrating different stages of the fabrication of a SOT-MRAM memory cell according to an embodiment of this application.

[0018] Figure label: 1. Bottom electrode; 11. Bottom electrode prefabrication layer; 2. Substrate; 3. Seed layer; 4. SOT source layer; 5. Fully antiferromagnetic tunnel junction; 51. First antiferromagnetic electrode layer; 52. Barrier layer; 53. Second antiferromagnetic electrode layer; 6. Top electrode layer. Detailed Implementation

[0019] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0021] Spatial relation terms such as "below," "under," "below," "below," "above," and "above" are used here to describe the relationship between one element or feature shown in the figure and other elements or features. Similarly, "directly above" can be used here to describe an element or feature shown in the figure that coincides in a vertical straight line direction, which may be partial or complete, depending on the actual situation or the content of the illustration. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as "below," "below," or "below" of other elements will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0023] It should also be understood that the terms “including / comprise” or “have” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0024] In a first aspect, one embodiment of the present invention provides a SOT-MRAM memory cell, combined with Figure 1 The SOT-MRAM memory cell includes: a bottom electrode 1, a substrate 2 stacked from bottom to top, a seed layer 3, an SOT source layer 4, a fully antiferromagnetic tunnel junction 5, and a top electrode layer 6.

[0025] The substrate 2 is made of amorphous dielectric material, the seed layer 3 is made of insulating cubic seed material, and the SOT source layer 4 is made of cubic non-collinear antiferromagnetic material. The lattice constants a and b of the SOT source layer 4 range from 3.8 Å to 4.4 Å, and the lattice constants a and b of the antiferromagnetic material in the fully antiferromagnetic tunnel junction also range from 3.8 Å to 4.4 Å. In this embodiment, the relevant lattice constant c is not limited.

[0026] The bottom electrode 1 is located below the SOT source layer 4 and is electrically connected to the SOT source layer 4. The SOT source layer 4 can be composed of one or more layers of composite material, and its thickness can be set according to the actual situation. This embodiment does not limit this.

[0027] The SOT-MRAM memory cell provided in this embodiment achieves cubic non-collinear antiferromagnetic orientation epitaxy by forming a seed layer 3 of insulating cubic seed material on an amorphous dielectric substrate 2. A multilayer cubic non-collinear antiferromagnetic structure with adjustable thickness is designed to form the SOT source layer 4 and the fully antiferromagnetic tunnel junction 5, respectively. The magnetocrystalline anisotropy of the antiferromagnetic material replaces the interface anisotropy, allowing the size of the SOT-MRAM memory cell to be miniaturized to nodes below 20nm. Simultaneously, the increased adjustable thickness range of the SOT-MRAM memory cell improves process tolerance and enlarges the etch stop window. This results in deterministic flipping without external magnetic field assistance, support for sub-nanosecond ultrafast low-power writing, and natural resistance to magnetic field interference due to zero net magnetic moment.

[0028] The read / write circuit connection method of the SOT-MRAM memory cell provided in this embodiment is the same as that of traditional SOT-MRAM. The write current flows horizontally through the SOT source layer 4, and the read current flows vertically through the MTJ. There is no need to reconstruct the peripheral circuit or interconnect architecture. Existing layout and process equipment can be directly used to achieve rapid industrial deployment.

[0029] In a further optional embodiment of this example, the fully antiferromagnetic tunnel junction 5 includes: a first antiferromagnetic electrode layer 51, a barrier layer 52, and a second antiferromagnetic electrode layer 53 stacked sequentially from bottom to top. The lattice constants of the first antiferromagnetic electrode layer 51 and the second antiferromagnetic electrode layer 53 are both in the range of 3.8 Å to 4.4 Å, such as 4 Å or 4.2 Å.

[0030] The barrier layer 52 is made of a cubic dielectric material, and its thickness ranges from 0.5 nm to 2.5 nm, such as 0.8 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.2 nm, and 2.4 nm. The thicknesses of the first antiferromagnetic electrode layer 51 and the second antiferromagnetic electrode layer 53 both range from 5 nm to 50 nm, such as 10 nm, 15 nm, 20 nm, 30 nm, and 40 nm. When the first antiferromagnetic electrode layer 51 and the second antiferromagnetic electrode layer 53 are made of the same material, the thickness of 53 is greater than that of 51. When they are made of different materials, the coercive fields of 51 and 53 need to be tuned so that the coercive field of 53 is greater than that of 51. The barrier layer 52 and the antiferromagnetic electrode layers on both sides form a lattice-matched epitaxial heterostructure.

[0031] When the thickness of the first antiferromagnetic electrode is 25 nm, its coercivity H c>1.5 T, write current density J c ≈10MA / cm 2 When the thickness is 10nm, H c ≈200 Oe, J c 2MA / cm 2 Up to 3 MA / cm 2 At this point, the SOT-MRAM memory cell features an ultra-high-speed structure. The coercivity of antiferromagnetic material layers of varying thicknesses is described in [reference needed]. Figure 2 ,in, Figure 2 The two arrows indicate the vertical coordinates corresponding to the subsequent antiferromagnetic material layers. In this embodiment, the thickness of the first antiferromagnetic electrode layer 51 is 25 nm and the thickness of the second antiferromagnetic electrode layer 53 is 45 nm, as an example.

[0032] In a further optional embodiment of this embodiment, the first antiferromagnetic electrode layer 51 is at least one of cubic antiferromagnetic material and tetragonal antiferromagnetic material, and the material of the second antiferromagnetic electrode layer 53 is at least one of cubic antiferromagnetic material and tetragonal antiferromagnetic material.

[0033] Cubic antiferromagnetic materials include, but are not limited to: Mn3Pt, Mn3Ir, Mn3Rh, Mn3GaN, Mn3NiN, and Mn3SnN; tetragonal antiferromagnetic materials include, but are not limited to: Mn2Au, CuMnAs, and Mn 1.9 SbCr 0.1 The barrier layer 52 forms a lattice-matched epitaxial heterostructure with the antiferromagnetic electrodes on both sides. The material of the barrier layer 52 includes, but is not limited to, at least one of NiO, MgAl2O4, SrTiO3, BaTiO3, LaNiO3, LaMnO3, and MgO. In the SOT source layer 4, the first antiferromagnetic electrode layer 51, the barrier layer 52, and the second antiferromagnetic electrode layer 53, the lattice fit between adjacent layers is less than 5%.

[0034] It is understood that the materials of the first antiferromagnetic electrode layer 51 and the second antiferromagnetic electrode layer 53 can be the same or different. In this embodiment, the materials of both the first antiferromagnetic electrode layer 51 and the second antiferromagnetic electrode layer 53 are Mn3SnN. The material of the barrier layer 52 is MgO.

[0035] In a further optional embodiment of this example, a lattice buffer layer is formed between at least one pair of adjacent functional layers. The functional layers include: an SOT source layer 4, a first antiferromagnetic electrode layer 51, a barrier layer 52, and a second antiferromagnetic electrode layer 53. It is understood that a pair of adjacent functional layers refers to two functional layers that are closest to each other; for example, the SOT source layer 4 and the first antiferromagnetic electrode layer 51 are a pair of adjacent functional layers, and the first antiferromagnetic electrode layer 51 and the barrier layer 52 are a pair of adjacent functional layers.

[0036] The lattice constant of the lattice buffer layer is less than the largest lattice constant of the two adjacent functional layers, and greater than the smallest lattice constant of the two adjacent functional layers. For example, if the lattice constants of the SOT source layer 4 and the first antiferromagnetic electrode layer 51 are 3.8 Å and 4.4 Å, respectively, then the lattice constant of the lattice buffer layer can be in the range of greater than 3.8 Å and less than 4.4 Å, such as 3.9 Å, 4.3 Å, or 4.1 Å. The material of the lattice buffer layer can be a cubic antiferromagnetic material, and its thickness can be less than the thickness of either of the adjacent functional layers; this embodiment does not limit this.

[0037] In a further optional embodiment of this example, the first antiferromagnetic electrode layer 51 and the second antiferromagnetic electrode layer 53 are made of different materials. A magnetic functional layer is stacked on top of the all-antiferromagnetic tunnel junction 5, and the magnetic functional layer is located below the top electrode layer. The bias field provided by the magnetic functional layer to the second antiferromagnetic electrode layer 53 is greater than the coercive field of the second antiferromagnetic electrode layer 53.

[0038] The materials of the magnetic functional layer include, but are not limited to, collinear antiferromagnetic alloys such as PtMn and IrMn, or multilayer film structures composed of artificial antiferromagnetic Pt / Co. This embodiment does not limit the thickness of the magnetic functional layer. By setting the magnetic functional layer, the second antiferromagnetic electrode layer 53 can be pinned, thereby improving the stability of the all-antiferromagnetic tunnel junction 5.

[0039] In a further optional embodiment of this example, the resistivity of the seed layer 3 is greater than or equal to ten times the resistivity of the SOT source layer 4.

[0040] In a further optional embodiment of this embodiment, the thickness of the SOT source layer 4 ranges from 3nm to 25nm, such as 5nm, 8nm, 10nm, 15nm, 20nm, etc.

[0041] The materials for the SOT source layer 4 include: Mn3Pt, Mn3Ir, Mn3Rh, Mn3GaN, Mn3NiN, Mn3SnN, Mn2Au, CuMnAs, and Mn. 1.9 SbCr 0.1At least one of them. When the SOT source layer 4 includes multiple materials, the SOT source layer 4 is formed by alternating stacking of multiple cubic crystal system materials.

[0042] In a further optional embodiment of this embodiment, the thickness of the seed layer 3 ranges from 1 nm to 100 nm, such as 3 nm, 8 nm, 10 nm, 20 nm, 30 nm, 50 nm, 70 nm, 90 nm, etc.

[0043] The seed layer 3 is made of at least one of the following materials: NiO, MgAl2O4, SrTiO3, BaTiO3, LaNiO3, LaMnO3, and MgO. The amorphous dielectric material is made of at least one of the following materials: silicon, silicon oxide, and silicon nitride.

[0044] In this embodiment, the seed layer 3 is a composite layer composed of SrTiO3 / MgO; the substrate 2 is made of silicon.

[0045] It should be noted that the epitaxial orientation of the cubic antiferromagnetic material in this invention includes, but is not limited to, <001>, <011>, or <111> crystal orientations.

[0046] The first aspect provides a SOT-MRAM memory cell that realizes a fully epitaxial antiferromagnetic SOT-MRAM device, using antiferromagnetic material as the direct information storage medium to achieve lattice-matched epitaxial growth of the fully antiferromagnetic tunnel junction 5 and the SOT source layer 4; it can achieve a net magnetic moment close to zero overall, reducing the critical write current of the spin orbital moment to the range of 2MA / cm² to 10MA / cm², thus reducing the write power consumption of the SOT-MRAM memory cell; at the same time, this SOT-MRAM memory cell utilizes the characteristic of antiferromagnetic intrinsic precession frequency >10GHz, which can extend the thermally assisted flip-flop mode of the spin memory to the sub-nanosecond write range, thereby making the SOT-MRAM memory cell adaptable to sub-nanosecond ultrafast writing; this SOT-MRAM memory cell also utilizes non-collinearity The z-spin of the antiferromagnetic SOT source achieves deterministic flipping without external magnetic field assistance. Simultaneously, leveraging the natural magnetic field resistance of antiferromagnetism, a first antiferromagnetic electrode layer 51 and a second antiferromagnetic electrode layer 53 are formed, enabling the SOT-MRAM memory cell to possess both dynamic and static magnetic field resistance capabilities, with adjustable magnetic field resistance for data storage. Furthermore, the thickness of the first antiferromagnetic electrode layer 51 can be increased to reserve a larger etch stop window for the magnetic tunnel junction, improving the etching yield of the SOT-MRAM memory cell. In addition, the antiferromagnetic magnetic anisotropy contributes greater anisotropy to the SOT-MRAM memory cell, supporting smaller device miniaturization. Moreover, its read / write current path design is fully compatible with traditional SOT-MRAM devices, eliminating the need for interconnect architecture reconstruction.

[0047] During data reading, the SOT-MRAM memory cell uses a vertical current flowing through the all-antiferromagnetic tunnel junction 5. By distinguishing the resistance difference between the parallel and antiparallel states of the all-antiferromagnetic tunnel junction 5, the magnetic state of the first antiferromagnetic electrode layer 51 is read. The SOT-MRAM memory cell demonstrates strong feasibility during data reading, with the TMR (Tunnel Magnetoresistance) of the all-antiferromagnetic tunnel junction 5 exceeding 100%. During data writing, the SOT-MRAM memory cell uses a horizontal current flowing through the SOT source layer 4, inducing a spin current in the vertical direction. The SOT source layer 4 has a <001> crystal orientation, which can induce a z-direction (vertical) polarized spin current, achieving deterministic flipping of the first antiferromagnetic electrode layer 51 without magnetic field assistance. The SOT-MRAM memory cell also demonstrates strong feasibility during data writing.

[0048] Among them, the research data on low-power flipping antiferromagnetic and antiferromagnetic magnetic field interference characteristics are as follows: Figure 3 As shown, under an external magnetic field of ±3000 Oe, the flipping characteristics of the heterostructure remain unchanged, and the flipping current density is only 2.58 MA / cm². 2 .

[0049] Secondly, one embodiment of the present invention provides a SOT-MRAM memory cell, combined with Figure 4 The SOT-MRAM memory cell differs from the SOT-MRAM memory cell in the first aspect in that the bottom electrode 1 is located above the SOT source layer 4.

[0050] It should be noted that in this embodiment, the two bottom electrodes 1 are located on opposite sides of the fully antiferromagnetic tunnel junction 5 in the horizontal direction.

[0051] Thirdly, the present invention provides a method for preparing a SOT-MRAM memory cell as described in the first aspect, the method comprising steps S101 to S107.

[0052] Step S101: Provide substrate 2.

[0053] The substrate 2 is made of amorphous dielectric material.

[0054] Step S102: Grow a seed layer 3 on the upper surface of substrate 2, and combine it with... Figure 5 .

[0055] The seed layer 3 is made of insulating cubic seed material.

[0056] Step S103: Pattern the seed layer 3 and etch to expose the substrate 2, then combine... Figure 6 .

[0057] Step S103 includes using photoresist as a mask and low-energy IBE (Ion Beam Etching) to etch through the seed layer 3 to complete the patterning process of the seed layer 3.

[0058] Step S104: The substrate is etched a second time and filled with conductive material to form the bottom electrode prefabrication layer 11, combined with... Figure 7 and Figure 8 .

[0059] Step S104 includes etching a bottom electrode channel in the amorphous dielectric filling material using a RIE (Reactive Ion Etching) process, and then filling it with conductive material to cover the seed layer 3 and the photoresist directly above the seed layer 3. This embodiment does not limit the specific shape of the bottom electrode channel.

[0060] Step S105: Planarize the bottom electrode prefabrication layer 11 to expose the seed layer 3 and form the bottom electrode 1, combining Figure 9 .

[0061] It is understandable that exposing the seed layer 3 in step S105 does not mean that the seed layer 3 is not ground. While planarizing the bottom electrode prefabricated layer 11, the seed layer 3 is also planarized. Therefore, in step S102, a margin of about 5nm can be reserved for the thickness of the seed layer 3 so that it can be removed in step S105.

[0062] Step S106: Deposit cubic non-collinear antiferromagnetic material on the upper surface of seed layer 3 and bottom electrode 1 to form SOT source layer 4, combined with... Figure 10 .

[0063] Step S107: Form a fully antiferromagnetic tunnel junction 5 on the upper surface of the SOT source layer 4, and combine it with... Figure 10 and Figure 11 .

[0064] The lattice constants of the antiferromagnetic materials in the SOT source layer 4 and the fully antiferromagnetic tunnel junction 5 range from 3.8 Å to 4.4 Å.

[0065] It should be noted that after the formation of the fully antiferromagnetic tunnel junction 5, the subsequent process is basically the same as the back-end integration of general SOT-MRAM, and this embodiment does not limit it.

[0066] It should be noted that the etching and deposition processes involved in this embodiment are all performed at temperatures below those compatible with CMOS back-end processes. The planarization process uses chemical mechanical polishing and retains part of the seed layer 3 as a stop layer. The stacked layers in the fully antiferromagnetic tunnel junction 5 are formed by physical vapor deposition or other deposition methods to maintain lattice matching.

[0067] Fourthly, the present invention provides a method for fabricating a SOT-MRAM memory cell as described in the second aspect, combined with... Figure 4 The method includes steps S201 to S204.

[0068] Step S201: Provide substrate 2. The material of substrate 2 is an amorphous dielectric material.

[0069] Step S202: A seed layer 3 and an SOT source layer 4 are sequentially formed on the upper surface of the substrate 2, stacked from bottom to top. The seed layer 3 is made of insulating cubic seed material, and the SOT source layer 4 is made of cubic non-collinear antiferromagnetic material.

[0070] Step S203: Pattern SOT source layer 4.

[0071] In this embodiment, the steps of patterning the SOT source layer 4 are similar to those in the third aspect, and will not be described in detail here.

[0072] Step S204: A bottom electrode 1 and a fully antiferromagnetic tunnel junction 5 are formed on the upper surface of the patterned SOT source layer 4.

[0073] It is understood that step S204 includes forming a patterned photomask of the bottom electrode 1 on the upper surface of the patterned SOT source layer 4; after the patterned photomask of the bottom electrode 1 is patterned with photoresist, a conductive material is deposited to form a bottom electrode prefabrication layer; after planarization of the bottom electrode prefabrication layer, the bottom electrode 1 is formed, and then the photoresist on the SOT source layer 4 is removed; after the cylindrical patterned photomask of the total antiferromagnetic tunnel junction 5 is patterned with photoresist, it is deposited on the SOT source layer 4 to form the total antiferromagnetic tunnel junction 5. It is understood that the order of the multiple patterning steps in step S204 can be flexibly adjusted according to actual process requirements.

[0074] In this embodiment, the bottom electrode 1 is located on opposite sides of the antiferromagnetic tunnel junction 5; the lattice constants of the antiferromagnetic materials in the SOT source layer 4 and the fully antiferromagnetic tunnel 5 range from 3.8 Å to 4.4 Å. Compared to the preparation method in the third aspect, the preparation method in this embodiment is achieved by adjusting the patterned photomask, avoiding the risks of cross-contamination and planarization caused by CMP (Chemical Mechanical Polishing) grinding of the seed layer 3 and the bottom electrode 1.

[0075] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A SOT-MRAM memory cell, characterized in that, The SOT-MRAM memory cell includes: a bottom electrode, a substrate, a seed layer, an SOT source layer, a fully antiferromagnetic tunnel junction, and a top electrode layer, stacked sequentially from bottom to top. The substrate is made of an amorphous dielectric material, the seed layer is made of an insulating cubic seed material, the SOT source layer is made of a cubic non-collinear antiferromagnetic material, the lattice constant of the SOT source layer ranges from 3.8 Å to 4.4 Å, and the lattice constant of the antiferromagnetic material in the fully antiferromagnetic tunnel junction ranges from 3.8 Å to 4.4 Å. The bottom electrode is located below or above the SOT source layer and is electrically connected to the SOT source layer.

2. The SOT-MRAM memory cell according to claim 1, characterized in that, The fully antiferromagnetic tunnel junction comprises: a first antiferromagnetic electrode layer, a barrier layer, and a second antiferromagnetic electrode layer stacked sequentially from bottom to top; The lattice constants of both the first and second antiferromagnetic electrode layers range from 3.8 Å to 4.4 Å. The barrier layer is made of a cubic crystal medium and has a thickness ranging from 0.5 nm to 2.5 nm. The thicknesses of the first antiferromagnetic electrode layer and the second antiferromagnetic electrode layer both range from 5 nm to 50 nm.

3. The SOT-MRAM memory cell according to claim 2, characterized in that, The materials of the first antiferromagnetic electrode layer and the second antiferromagnetic electrode layer are at least one of cubic antiferromagnetic material and tetragonal antiferromagnetic material, respectively. The cubic antiferromagnetic materials include: Mn3Pt, Mn3Ir, Mn3Rh, Mn3GaN, Mn3NiN, and Mn3SnN; the tetragonal antiferromagnetic materials include: Mn2Au, CuMnAs, and Mn... 1.9 SbCr 0.1 ; In the SOT source layer, the first antiferromagnetic electrode layer, the barrier layer, and the second antiferromagnetic electrode layer, the lattice fit between adjacent layers is less than 5%.

4. The SOT-MRAM memory cell according to claim 2, characterized in that, A lattice buffer layer is formed between at least one pair of adjacent functional layers, the functional layers including: the SOT source layer, the first antiferromagnetic electrode layer, the barrier layer, and the second antiferromagnetic electrode layer; The lattice constant of the lattice buffer layer is less than the largest lattice constant among the two functional layers adjacent to the lattice buffer layer, and greater than the smallest lattice constant among the two functional layers adjacent to the lattice buffer layer.

5. The SOT-MRAM memory cell according to claim 2, characterized in that, A magnetic functional layer is formed on the top of the fully antiferromagnetic tunnel junction, and the magnetic functional layer is located below the top electrode layer; The bias field provided by the magnetic functional layer to the second antiferromagnetic electrode layer is greater than the coercive field of the second antiferromagnetic electrode layer.

6. The SOT-MRAM memory cell according to claim 1, characterized in that, The resistivity of the seed layer is greater than or equal to ten times the resistivity of the SOT source layer.

7. The SOT-MRAM memory cell according to claim 1, characterized in that, The thickness of the SOT source layer ranges from 3 nm to 25 nm; The materials of the SOT source layer include: Mn3Pt, Mn3Ir, Mn3Rh, Mn3GaN, Mn3NiN, Mn3SnN, Mn2Au, CuMnAs, and Mn. 1.9 SbCr 0.1 At least one of them.

8. The SOT-MRAM memory cell according to claim 1, characterized in that, The thickness of the seed layer ranges from 1 nm to 100 nm; The seed layer material includes at least one of NiO, MgAl2O4, SrTiO3, BaTiO3, LaNiO3, LaMnO3, and MgO. The amorphous dielectric material includes at least one of silicon, silicon oxide, and silicon nitride.

9. A method for fabricating a SOT-MRAM memory cell, characterized in that, The method includes: A substrate is provided, wherein the substrate is made of an amorphous dielectric material; A seed layer is grown on the upper surface of the substrate, and the seed layer is made of an insulating cubic seed material. The seed layer is patterned, and the substrate is etched to expose it; The substrate is etched and filled with conductive material to form a bottom electrode prefabrication layer; The bottom electrode prefabrication layer is planarized to expose the seed layer and form the bottom electrode; A cubic non-collinear antiferromagnetic material is deposited on the upper surface of the seed layer and the bottom electrode to form an SOT source layer; A fully antiferromagnetic tunnel junction is formed on the upper surface of the SOT source layer; The lattice constants of the antiferromagnetic material in the SOT source layer and the fully antiferromagnetic tunnel junction range from 3.8 Å to 4.4 Å.

10. A method for fabricating a SOT-MRAM memory cell, characterized in that, The method includes: A substrate is provided, wherein the substrate is made of an amorphous dielectric material; A seed layer and an SOT source layer are sequentially formed from bottom to top on the upper surface of the substrate; the seed layer is made of insulating cubic seed material, and the SOT source layer is made of cubic non-collinear antiferromagnetic material. Pattern the SOT source layer; A bottom electrode and a fully antiferromagnetic tunnel junction are formed on the upper surface of the patterned SOT source layer; The bottom electrode is located on opposite sides of the fully antiferromagnetic tunnel junction; the lattice constant of the SOT source layer and the antiferromagnetic material in the fully antiferromagnetic tunnel junction both range from 3.8 Å to 4.4 Å.

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