Silicon carbide mos integrated circuit process and structure

Abstract

This invention addresses the technical shortcomings of existing silicon carbide high-voltage discrete devices and silicon-based low-voltage CMOS driving architectures, such as large parasitic parameters and bulky system size. It aims to solve the technical problem of their inability to meet the stringent power density and reliability requirements of high-end applications by proposing a silicon carbide MOS integrated circuit process and structure. This process can stably fabricate high-voltage VDMOS devices and low-voltage CMOS circuits, and can integrate passive components such as well resistors, poly resistors, MOS capacitors, and diodes with the aforementioned devices and circuits to form a fully functional integrated circuit. This invention not only fully integrates the high switching speed, high voltage withstand, and high temperature resistance of high-voltage VDMOS devices with the high integration and low static power consumption advantages of low-voltage CMOS circuits, but also uses fewer mask layers and provides great flexibility for power circuit design. Based on this process, this invention also provides a silicon carbide MOS integrated circuit structure with advantages such as low parasitic parameters, high temperature resistance, high power density, and fast circuit response speed.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, specifically relating to a silicon carbide MOS integrated circuit process and structure. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, possesses superior properties such as a large bandgap, high breakdown electric field, high thermal conductivity, and fast saturated electron drift velocity. It holds irreplaceable advantages in high-frequency, high-voltage, high-temperature, and high-efficiency power conversion systems and has been widely applied in key areas such as new energy vehicles, photovoltaic inverters, rail transportation, and server power supplies. Current power semiconductor devices and power integration technologies are developing towards monolithic integration, high power density, high reliability, and stable operation across the entire temperature range. Integrating silicon carbide high-voltage power devices with low-voltage control, drive, and protection circuits on the same chip can significantly reduce parasitic parameters, lower packaging complexity, and improve system dynamic performance and high-temperature reliability, representing a significant development trend in the field of silicon carbide power devices.

[0003] The core of power integration technology lies in achieving process compatibility between high-voltage and low-voltage devices, with the appropriate selection of isolation technology being particularly crucial. As the demands of electronic system applications continue to upgrade, not only are more low-voltage circuits and protection modules required to achieve complex intelligent control functions, but harsh application environments also place higher demands on the performance stability and reliability of devices. Therefore, power integration technology must balance multiple requirements within a limited chip area, including high- and low-voltage process compatibility, high performance, high efficiency, and high reliability. However, traditional silicon carbide discrete devices and silicon-based driver architectures have inherent defects: large parasitic parameters, limited high-temperature resistance, and poor reliability, failing to fully utilize the core high-speed switching characteristics of silicon carbide (SiC) devices. Furthermore, the discrete layout of traditional silicon-based driver chips and silicon carbide power devices results in large lead inductance, limiting the dynamic performance of the devices. Silicon-based devices struggle to operate stably for extended periods in environments above 200°C, further restricting the full release of the high-temperature advantages of SiC materials. While all-silicon carbide integrated circuits can effectively solve the aforementioned problems, existing silicon carbide high- and low-voltage device integration technologies still face numerous insurmountable bottlenecks. Achieving process compatibility between high and low voltage devices requires a large number of additional photomasks and special process steps, directly leading to a significant increase in manufacturing costs, reduced product yield, and increased difficulty in mass production. In summary, developing a silicon carbide MOS integrated circuit process and structure that can achieve monolithic integration of high-voltage VDMOS, low-voltage CMOS, capacitors, resistors, and diodes, and possesses excellent process compatibility and stable performance, has become a key technical problem urgently needing to be solved in this field. Summary of the Invention

[0004] This invention aims to solve the technical problems of incompatibility between silicon carbide high-voltage power devices and low-voltage control circuit processes, as well as the cumbersome process steps in the prior art. By optimizing the process steps, it achieves monolithic integration of high-voltage VDMOS, low-voltage NMOS, low-voltage PMOS, capacitors, resistors, and diodes, thereby improving the stability, reliability, and integration of integrated circuits, simplifying the process flow, reducing manufacturing costs, and adapting to the application requirements of power integrated circuits.

[0005] This invention provides a process for silicon carbide MOS integrated circuits, comprising the following steps:

[0006] Step 1: Select N-type 4H-SiC as substrate 1, with substrate doping of 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 ;

[0007] Step 2: An N-type buffer layer 2 is epitaxially grown on the N-type substrate 1, with a doping concentration of 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 The thickness ranges from 0.3 μm to 1.5 μm;

[0008] Step 3: An N-type epitaxial layer 3 is epitaxially grown on the N-type buffer layer 2, with a doping concentration of 1×10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3 ;

[0009] Step 4: Deposit to form a thick field oxygen isolation layer 4 with a thickness of 0.5 μm to 2 μm, and remove the oxide layer on the surface of the active region;

[0010] Step 5: Ion implant N-type impurities into the N-type epitaxial layer 3 to adjust the doping of the JFET region 5 of the VDMOS device and to fabricate the N-well region 6 of the PMOS device, thereby better adjusting the electrical performance of the VDMOS and PMOS devices. The implantation is performed 2 to 5 times, with a total implantation dose of 1 × 10⁻⁶. 12 cm -3 Up to 1×10 13 cm -3 ;

[0011] Step 6: Ion implant P-type impurities into the N-type epitaxial layer 3 to form the first P-well region 7, the second P-well region 8, the third P-well region 9 of the NMOS device, the fourth P-well region 10, the fifth P-well region 11 of the PMOS device, the sixth P-well region 12 of the trap resistor, the seventh P-well region 13 of the capacitor, and the eighth P-well region 14 of the diode. The implantation is performed 2 to 5 times, with a total implantation dose of 5 × 10⁻⁶. 13 cm -3 Up to 2×10 14 cm -3 ;

[0012] Step 7: Ion implant N-type impurities into N-well region 6 and P-well regions 7-9 (7-9) and P-well regions 12-14 (12-14) to form the first N+ region 15, the second N+ region 16 of the VDMOS device, the third N+ region 17, the fourth N+ region 18 of the NMOS device, the fifth N+ region 19 of the PMOS device, the sixth N+ region 20 of the well resistor, the seventh N+ region 21, the eighth N+ region 22 of the capacitor, and the ninth N+ region 23 of the diode. The number of implantation cycles is 2 to 5, and the total implantation dose is 1 × 10⁻⁶. 15 cm -3 Up to 3×10 15 cm -3 ;

[0013] Step 8: Ion implant P-type impurities into the N-type epitaxial layer 3 and the seventh to fourteenth P-well regions 7-14 to form the first P+ region 24, the second P+ region 25 of the VDMOS device, the third P+ region 26 of the NMOS device, the fourth P+ region 27, the fifth P+ region 28, the sixth P+ region 29, the seventh P+ region 30 of the PMOS device, the eighth P+ region 31 of the well resistor, the ninth P+ region 32 of the capacitor, and the tenth P+ region 33 of the diode. The number of implantation times is 2 to 5, and the total implantation dose is 5 × 10⁻⁶. 13 cm -3 Up to 1×10 15 cm -3 ;

[0014] Step 9: After completing all ion implantation steps, remove the adhesive and clean the device surface. Then, a dense carbon film is formed to prevent Si atoms from sublimating and causing surface roughness.

[0015] Step 10: Perform high-temperature annealing at 1600-1900℃ in Ar or vacuum atmosphere to activate the implanted impurities and repair lattice damage, then remove the carbon film and wet clean to remove residues.

[0016] Step 11: Generate a sacrificial oxide layer and remove it by wet process to remove the surface damage layer caused by implantation and annealing steps. A gate oxide layer with a thickness of 30 nm to 60 nm is grown on a clean SiC surface by thermal oxidation process and annealed in a nitrogen or inert gas atmosphere to stabilize the charge of the gate oxide layer.

[0017] Step 12: Deposit a polycrystalline silicon thin film with a thickness of 300 nm to 500 nm, and heavily dope the polycrystalline silicon by ion implantation or in-situ doping.

[0018] Step 13: Dry etching of polysilicon to define the gate pattern, which can be used for the gate 35 of VDMOS devices, PMOS devices, NMOS devices, and capacitor devices, and to form a poly resistor 35 on the thick field oxide 4, and can assist the single-layer metal in connecting device electrodes.

[0019] Step 14: Deposit SiO2 to form dielectric layer 36 and reflow to achieve planarization;

[0020] Step 15: Perform contact hole etching to complete the ohmic contact fabrication. Then, sputter metal to form the first source metal 37, the second source metal 38, and the first VP electrode metal 39 and the second VP electrode metal 40 of the body region of the VDMOS device; the drain metal 41, the source metal 42, and the VP electrode metal 43 of the body region of the NMOS device; the drain metal 44, the source metal 45, the VN electrode metal 46 of the body region, and the first P+ region metal 47 and the second P+ region metal 48 of the PMOS device; the positive electrode metal 49, the negative electrode metal 50, and the VP electrode metal 51 of the body region of the well resistor; the drain metal 52, the source metal 53, and the VP electrode metal 54 of the body region of the capacitor; and the cathode metal 55 and the anode metal 56 of the diode.

[0021] Step 16: Perform poly contact hole etching to create ohmic contacts at the contact holes. Then, sputter metal to form the gate metal 57 of the VDMOS device, the gate metal 58 of the NMOS device, the gate metal 59 of the PMOS device, the gate metal 60 of the capacitor, and the positive electrode metal 61 and negative electrode metal 62 of the poly resistor. Simultaneously, steps 15 and 16 also achieve electrode bridging and local interconnection through a single layer of metal with the assistance of the poly layer.

[0022] Step 17: Backside thinning and metallization to form the drain metal 63 of the VDMOS device.

[0023] The above process steps successfully enable the fabrication of one or more silicon carbide VDMOS, NMOS, PMOS, well resistors, poly resistors, capacitors, and diodes on the same N-type 4H-SiC substrate and N-type epitaxial layer, without requiring additional photomasks compared to the silicon carbide VDMOS process. Interconnection of all devices can be achieved using a polysilicon layer combined with a single metal layer. The polysilicon layer can also serve as an auxiliary interconnect jumper, which is crucial for simplifying device interconnect wiring. High-voltage and low-voltage devices are electrically isolated by forming a PN junction isolation structure within the N-type epitaxial layer through the P-well and P+ implantation processes described in steps 6 and 8.

[0024] Furthermore, the N-type impurity is nitrogen or phosphorus, and the P-type impurity is aluminum or boron.

[0025] Furthermore, step 3 can form a superjunction structure through multiple epitaxial and implantation processes to better optimize the electrical characteristics of the VDMOS device.

[0026] Furthermore, step 5 can be used to meet the on-resistance and breakdown voltage requirements of different VDMOS and PMOS devices by adjusting the N-type impurity injection energy, dose, and number of times.

[0027] Furthermore, step 6 can be implemented by adjusting the different P-type impurity injection energies, doses, and number of injections to meet the threshold voltage, on-resistance, and breakdown voltage requirements of different VDMOS and NMOS.

[0028] Furthermore, step 9 can be used to fabricate a dense carbon film by direct deposition or high-temperature carbonization of photoresist.

[0029] Furthermore, after depositing the polycrystalline silicon thin film in step 12, the resistance forming region of the polycrystalline silicon thin film may not be subjected to ion implantation and in-situ doping to form a high-resistance poly resistor.

[0030] Furthermore, step 13 can utilize a poly layer as an auxiliary interconnect lead to achieve bridging and local interconnection of device electrodes under single-layer metal wiring process conditions.

[0031] Furthermore, steps 15 and 16 can be used to fabricate multilayer metal interconnect structures to achieve more complex circuit wiring.

[0032] Based on the above process, high-voltage silicon carbide VDMOS devices, low-voltage silicon carbide NMOS devices, low-voltage silicon carbide PMOS devices, trap resistor devices, poly resistor devices, MOS capacitor devices, diode devices, and other structures can be formed on a monolithic N-type 4H-SiC substrate and N-type epitaxial layer.

[0033] The high-voltage silicon carbide VDMOS device includes a drain electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3. On top of the N-type epitaxial layer 3, a JFET region 5, a first P-well region 7, a second P-well region 8, a first N+ region 15, a second N+ region 16, a first P+ region 24, and a second P+ region 25 are distributed. The first N+ region 15, the second N+ region 16, and the first P+ region 24 and the second P+ region 25 are located inside the first P-well region 7 and the second P-well region 8, while the JFET region 5 is located between the first P-well region 7 and the second P-well region 8. Above the JFET region 5 is a gate oxide layer 34, covering the channel region formed by the nesting of the first P-well region 7, the second P-well region 8, and the first N+ region 15 and the second N+ region 16. Above the first N+ region 15 and the second N+ region 16 are the first source metal 37 and the second source metal 38, respectively. Above the first P+ region 24 and the second P+ region 25 are the first VP electrode metal 39 and the second VP electrode metal 40 of the body region. Above the gate oxide layer 34 is a poly gate 35, and above the poly gate 35 is a gate electrode 57. In addition, there is an isolation dielectric layer 36 on the top of the device.

[0034] The low-voltage silicon carbide NMOS device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3. On top of the N-type epitaxial layer 3, a third P-well region 9, a third N+ region 17, a fourth N+ region 18, and a third P+ region 26 are distributed. The third N+ region 17, the fourth N+ region 18, and the third P+ region 26 are located inside the third P-well region 9. Above the epitaxial layer between the third N+ region 17 and the fourth N+ region 18 is a gate oxide layer 34, covering the channel region of the NMOS device. Above the third N+ region 17 and the fourth N+ region 18 are a drain electrode 41 and a source electrode 42. Above the third P+ region 26 is a body region VP electrode 43. Above the gate oxide layer 34 is a poly gate 35, and above the poly gate 35 is a gate electrode 58. In addition, an isolation layer 36 is located on top of the device.

[0035] The low-voltage silicon carbide PMOS device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3. On top of the N-type epitaxial layer 3, N-well regions 6, a fourth P-well region 10, a fifth P-well region 11, a fifth N+ region 19, a fourth P+ region 27, a fifth P+ region 28, a sixth P+ region 29, and a seventh P+ region 30 are distributed. A gate oxide layer 34 is located above the epitaxial layer between the fifth P+ regions 28 and the sixth P+ regions 29, covering the channel region of the PMOS device. A source electrode 44 and a drain electrode 45 are located above the fifth P+ regions 28 and 29. A first P+ region metal 47 and a second P+ region metal 48 are located above the fourth P+ regions 27 and 30. A body region VN electrode 46 is located above the fifth N+ region 19. A poly gate 35 is located above the gate oxide layer 34, and a gate electrode 59 is located above the poly gate 35. In addition, there is an isolation layer 36 on top of the device.

[0036] The described well resistor device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3, sequentially arranged on top of the substrate. On top of the N-type epitaxial layer 3, a sixth P-well region 12, a sixth N+ region 20, and an eighth P+ region 31 are distributed. The sixth N+ region 20 is located within the sixth P-well region 12. Above the sixth N+ region 20 are the positive electrode metal 49 and the negative electrode metal 50 of the well resistor, and above the eighth P+ region 31 is the VP electrode metal 51. Furthermore, an isolation layer 36 is present on top of the device.

[0037] The poly resistor device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3, which are sequentially placed on top of the substrate. Above the N-type epitaxial layer 3 is a field oxide layer 4, above the field oxide layer 4 is a poly resistor 35, and above the poly resistor 35 are the positive electrode metal 61 and the negative electrode metal 62 of the poly resistor 35. Additionally, an isolation layer 36 is located on top of the device.

[0038] The capacitor device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3, all sequentially arranged on top of the substrate. On top of the N-type epitaxial layer 3, a seventh P-well region 13, a seventh N+ region 21, an eighth N+ region 22, and a ninth P+ region 32 are distributed. The seventh N+ region 21, the eighth N+ region 22, and the ninth P+ region 32 are located within the seventh P-well region 13. Above the epitaxial layer between the seventh N+ region 21 and the eighth N+ region 22 is a gate oxide layer 34, covering the channel region of the capacitor device. Above the seventh N+ region 21 and the eighth N+ region 22 are a drain electrode 52 and a source electrode 53. Above the ninth P+ region 32 is a body region VP electrode 54. Above the gate oxide layer 34 is a poly gate 35, and above the poly gate 35 is a gate electrode 60. Furthermore, an isolation layer 36 is located on top of the device.

[0039] The diode device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3, all sequentially arranged on top of the substrate. On top of the N-type epitaxial layer 3, an eighth P-well region 14, a ninth N+ region 23, and a tenth P+ region 33 are distributed. The ninth N+ region 23 and the tenth P+ region 33 are located inside the eighth P-well region 14. Above the tenth P+ region 33 is a positive electrode 56, and above the ninth N+ region 23 is a negative electrode 55. Furthermore, an isolation layer 36 is present on top of the device.

[0040] Furthermore, the high-voltage VDMOS device shares the same P-well injection, P+ injection, and N+ injection as the low-voltage PMOS device, low-voltage NMOS device, well resistor device, poly resistor device, capacitor device, and diode device, and uses the same gate oxide layer thickness.

[0041] Furthermore, the fifth P+ region 28 and the sixth P+ region 29 of the PMOS device are surrounded by the fourth P-well region 10 and the fifth P-well region 11, and the terminal protection ring of the VDMOS device is extended to the periphery of all devices, uniformly protecting the entire chip edge and achieving auxiliary withstand voltage for the entire integrated chip.

[0042] Furthermore, according to the integrated silicon carbide MOS integrated circuit process of claim 1, after step 8, an N-type impurity implantation process is introduced in the channel region below the gate oxide layer of the high-voltage VDMOS device region and the low-voltage NMOS device region to form an N-type electron accumulation layer as a conductive channel, thereby completing the fabrication of the high-voltage depletion-type VDMOS device and the low-voltage depletion-type NMOS device, and then proceeding to step 9.

[0043] Furthermore, according to the integrated silicon carbide MOS integrated circuit process of claim 1, after step 8, additional N-type or P-type impurity implantation is introduced into the channel region below the gate oxide layer of the low-voltage NMOS device region and the low-voltage PMOS device region to adjust the threshold voltage of the two devices, and then proceeds to step 9.

[0044] Furthermore, according to the integrated silicon carbide MOS integrated circuit process of claim 1, after the gate oxide layer is grown in step 11, the gate oxide layer of the low-voltage NMOS device region and the low-voltage PMOS device region is removed by photolithography and wet etching, and then the photoresist is retained in the exposed area for a second thermal oxidation to form a thin gate oxide layer of 10nm to 20nm, and then the process proceeds to step 12.

[0045] On the other hand, this invention proposes a silicon carbide MOS integrated circuit structure, fabricated using the above-mentioned process, comprising:

[0046] PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, NMOS transistor M11, NMOS transistor M12, NMOS transistor M13, PMOS transistor M14, NMOS transistor M15, PMOS transistor M16, NMOS transistor M17, NMOS transistor M18, NMOS transistor M19, PMOS transistor M20, NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24, NMOS transistor M25, PMOS transistor M26, NMOS transistor M27 Transistor M27, PMOS transistor M28 (28th), NMOS transistor M29 (29th), PMOS transistor M30 (30th), NMOS transistor M31 (31st), PMOS transistor M32 (32nd), NMOS transistor M33 (33rd), PMOS transistor M34 (34th), NMOS transistor M35 (35th), NMOS transistor M36 (36th), NMOS transistor M37 (37th), Resistor R1 (1st), Resistor R2 (2nd), Resistor R3 (3rd), Resistor R4 (4th), Resistor R5 (5th), Resistor R6 (6th), Resistor R7 (7th), Resistor R8 (8th), Resistor R9 (9th), Resistor R10 (10th), Resistor R11 (11th), Resistor R12 (12th), Resistor R13 (13th), Resistor R14 (14th), Resistor R15 (15th), Resistor R16 (16th), Resistor R17 (17th), Resistor R18 (18th), Resistor R19 (19th), Capacitor C1 (1st), Capacitor C2 (2nd).

[0047] The sources of the first PMOS transistor M1, the third PMOS transistor M3, the fourth PMOS transistor M4, and the seventh PMOS transistor M7 are all connected to the input voltage VIN, and their gates are all connected to the drain of the fourth PMOS transistor M4. The drain of the first PMOS transistor M1 is connected to the gate of the second PMOS transistor M2. The source of the second PMOS transistor M2 is grounded to GND through the first resistor R1, and its drain is connected to the gate of the fifth NMOS transistor M5. The drain of the third PMOS transistor M3 is connected to the drain and gate of the fifth NMOS transistor M5. The drain of the fourth PMOS transistor M4 is connected to the drain of the sixth NMOS transistor M6. The source of the fifth NMOS transistor is grounded to GND, and the source of the sixth NMOS transistor is grounded to GND through the second resistor R2. The drain of the seventh PMOS transistor is connected to the first connection node through the third resistor R3. The first connection node is grounded to GND through the first capacitor C1, the fourth resistor R4, and the fifth resistor R5.

[0048] The gate of the eighth NMOS transistor M8 is connected to the first connection node, and its drain is connected to the input voltage VIN via the sixth resistor R6; the gate of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8, its source is grounded to GND, and its drain is connected to the input voltage VIN via the seventh resistor R7; the source of the tenth NMOS transistor M10 is grounded to GND, and its drain is connected to the connection node of the fourth resistor R4 and the fifth resistor R5; the gate of the twenty-second NMOS transistor M22 is connected to the drain of the ninth NMOS transistor M9, its source is grounded to GND, and its drain is connected to the gate of the twenty-fifth NMOS transistor M25.

[0049] The upper ends of the eighth resistor R8, the ninth resistor R9, and the twelfth resistor R12 are all connected to the input voltage VIN. The lower end of the eighth resistor R8 is connected to the second connection node, which is grounded to GND via the second capacitor C2, and also grounded to GND via the tenth resistor R10 and the eleventh resistor R11 in series. The series connection node of the tenth resistor R10 and the eleventh resistor R11 is connected to the drain of the eleventh NMOS transistor M11. The source of the eleventh NMOS transistor M11 is grounded to GND, and its gate is connected to the drain of the thirteenth NMOS transistor M13. The gate of the twelfth NMOS transistor M12 is connected to the second connection node, and its drain is connected to the input voltage VIN via the ninth resistor R9. The gate of the thirteenth NMOS transistor M13 is connected to the drain of the twelfth NMOS transistor M12, its source is grounded to GND, and its drain is connected to the input voltage VIN via the twelfth resistor R12.

[0050] The sources of the fourteenth PMOS transistor M14, the sixteenth PMOS transistor M16, the eighteenth PMOS transistor M18, and the twentieth PMOS transistor M20 are connected to the input voltage VIN; the sources of the fifteenth NMOS transistor M15, the seventeenth NMOS transistor M17, the nineteenth NMOS transistor M19, and the twenty-first NMOS transistor M21 are connected to ground GND.

[0051] Drive stage 1: The drain of the fourteenth PMOS transistor M14 and the drain of the fifteenth NMOS transistor M15 are connected together to form the output terminal of the drive stage 1, and their gates are connected together as the drive input terminal.

[0052] Drive the second stage: The drain of the sixteenth PMOS transistor M16 and the drain of the seventeenth NMOS transistor M17 are connected together to form the output terminal of the second stage driver. The gates of the two transistors are connected together to drive the output terminal of the first stage driver.

[0053] Drive stage 3: The drain of the eighteenth PMOS transistor M18 and the drain of the nineteenth NMOS transistor M19 are connected together to form the output terminal of drive stage 3, and their gates are connected together to drive stage 2 output terminal;

[0054] Drive stage four: The drain of the twentieth PMOS transistor M20 and the drain of the twenty-first NMOS transistor M21 are connected together to form the output terminal of drive stage four.

[0055] The 24th NMOS transistor M24 is a current sampling transistor M24, and the 25th NMOS transistor M25 is a power transistor M25; the drains of both are connected to the output node OUT; the source of the 24th NMOS transistor M24 is grounded to GND through the 13th resistor R13; the gate of the 23rd NMOS transistor M23 is connected to the source of the 24th NMOS transistor M24, the drain is connected to the gate of the 24th NMOS transistor M24, and the source is grounded to GND; the gate of the 25th NMOS transistor M25 is connected to the gate of the 24th NMOS transistor M24, and the source is grounded to GND.

[0056] The sources of the 26th PMOS transistor M26, the 28th PMOS transistor M28, the 30th PMOS transistor M30, and the 32nd PMOS transistor M32 are connected to the input voltage VIN; the sources of the 27th NMOS transistor M27, the 29th NMOS transistor M29, the 31st NMOS transistor M31, and the 33rd NMOS transistor M33 are connected to ground GND.

[0057] Segmented Stage 1: The drain of the 26th PMOS transistor M26 and the drain of the 27th NMOS transistor M27 are connected together to form the segmented stage 1 output terminal. The gates of both are connected to the second connection node as the segmented drive stage 1 input terminal.

[0058] Segmented two-stage: The drain of the twenty-eighth PMOS transistor M28 and the drain of the twenty-ninth NMOS transistor M29 are connected together to form the segmented two-stage output terminal, and their gates are connected together to the segmented first-stage output terminal;

[0059] Three-stage segmentation: The drain of the 30th PMOS transistor M30 and the drain of the 31st NMOS transistor M31 are connected together to form a three-stage segmented output terminal, and their gates are connected together to form a two-stage segmented output terminal.

[0060] Segmented four stages: The drain of the thirty-second PMOS transistor M32 and the drain of the thirty-third NMOS transistor M33 are connected together to form a segmented four-stage output terminal;

[0061] The source of the thirty-fourth PMOS transistor M34 is connected to the four-stage drive output terminal, the drain is connected to the four-stage segmented output terminal, and the gate is connected to the drain of the thirty-seventh NMOS transistor M37.

[0062] The upper ends of the fourteenth resistor R14, the seventeenth resistor R17, and the eighteenth resistor R18 are connected to the output terminals of the four-stage drive, and are connected to the gate of the twenty-fifth NMOS transistor M25 via the nineteenth resistor R19; the lower end of the fourteenth resistor R14 is connected to the third connection node, and the third connection node is connected to ground GND via the fifteenth resistor R15 and the sixteenth resistor R16 in series; the series node of the fifteenth resistor R15 and the sixteenth resistor R16 is connected to the drain of the thirty-fifth NMOS transistor M35, the source of the thirty-fifth NMOS transistor M35 is grounded to GND, and the gate is connected to the drain of the thirty-sixth NMOS transistor M36;

[0063] The gate of the thirty-sixth NMOS transistor M36 is connected to the third connection node, and the drain is connected to the gate of the twenty-fifth NMOS transistor M25 via the seventeenth resistor R17; the gate of the thirty-seventh NMOS transistor M37 is connected to the drain of the thirty-sixth NMOS transistor M36, the source is grounded to GND, and the drain is connected to the nineteenth resistor R19.

[0064] The reference circuit operates as follows: The third PMOS transistor M3 and the fourth PMOS transistor M4 form a current mirror with a 1:1 area ratio, ensuring that the current flowing through them is equal during normal operation. The fifth NMOS transistor M5 and the sixth NMOS transistor M6 are set with a 1:K area ratio. Under the clamping effect of the third PMOS transistor M3 and the fourth PMOS transistor M4, the operating currents of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are forced to be equal, thereby making their VL equal. GS There is a voltage difference, and this voltage drop is applied across the second resistor R2 to form a temperature-dependent reference current.

[0065] The fourth PMOS transistor M4 and the seventh PMOS transistor M7 further form a current mirror, which mirrors the above reference current to the first connection node, forming a stable reference voltage at the first connection node.

[0066] The startup circuit works as follows: The second PMOS transistor M2 and the first resistor R1 constitute the startup circuit. When the input voltage VIN rises, the gate voltage of the second PMOS transistor M2 is pulled down to a low level through the first resistor R1, turning on the second PMOS transistor M2 and causing the gate voltage of the fifth NMOS transistor M5 to rise and turn on. Under the action of the positive feedback loop, the entire circuit gradually enters the normal operating state. Subsequently, the first PMOS transistor M1 mirrors the reference current to the first resistor R1 and forms a voltage drop, turning off the second PMOS transistor M2. After power-on, this startup branch no longer affects the normal operation of the circuit.

[0067] Temperature sensing characteristics of silicon carbide devices: Silicon carbide material has a large bandgap (approximately 3.26 eV), allowing devices to operate stably in the range of -40℃ to 175℃ or even higher. Silicon carbide NMOS devices exhibit a strong negative temperature characteristic in relation to their threshold voltage.

[0068] The threshold voltage of a silicon carbide NMOS can be expressed as: ,

[0069] Where T0 represents room temperature, and the threshold voltage of silicon carbide is V. T The temperature coefficient of the threshold voltage of silicon carbide NMOS can be expressed as: α≈-0.4×10 -3 V / ℃, where T represents the junction temperature.

[0070] Over-temperature detection and protection principle: The gate of the eighth NMOS transistor M8 is connected to the reference voltage of the first connection node, and its VGS is approximately constant. When the temperature has not reached the over-temperature threshold, the threshold voltage of the eighth NMOS transistor M8 is greater than its VGS. GS When the transistor is cut off, the drain is pulled high by the sixth resistor R6, the ninth NMOS transistor M9 is turned on, and the eleventh resistor R11 is shorted. At this time, the gate voltage bias is I. REF • R4. When the temperature rises to the over-temperature threshold, the threshold voltage of the eighth NMOS transistor M8 is:

[0071] The threshold voltage of the eighth NMOS transistor M8 is lower than V. GS The transistor turns on and pulls down the gates of the ninth NMOS transistor M9 and the tenth NMOS transistor M10 to cut off. The seventh resistor R7 pulls up the gate of the twenty-second NMOS transistor M22 to turn it on. The twenty-second NMOS transistor M22 pulls down the gate voltage of the sampling transistor M24 and the power transistor M25, realizing gate voltage clamping protection under over-temperature conditions.

[0072] Meanwhile, since the tenth NMOS transistor M10 is turned off, the fifth resistor R5 is connected to the branch, causing the gate voltage to rise and achieving temperature hysteresis. When the temperature drops to the threshold voltage V of the eighth NMOS transistor M8... T (T rel) for:

[0073] V REF This indicates the reference voltage for over-temperature protection detection.

[0074] When the temperature drops to a level that causes the threshold voltage of the eighth NMOS transistor M8 to be higher than... When the voltage is adjusted, the circuit returns to normal operation.

[0075] Undervoltage and hysteresis control principle: The twelfth NMOS transistor M12 detects the voltage of the voltage divider network formed by the eighth resistor R8, the tenth resistor R10, and the eleventh resistor R11 at the second connection node. When the voltage at the second connection node is higher than the threshold voltage of the twelfth NMOS transistor M12, the release voltage V input VIN is released. ON for:

[0076]

[0077] The twelfth NMOS transistor M12 is turned on, pulling down the gates of the eleventh NMOS transistors M11 and M13 to cutoff. Resistor R11 is connected, further increasing the voltage at the second connection node to achieve hysteresis comparison characteristics. Resistor R12 pulls high the input terminals of the first-stage driver and the first-stage segment, causing the output terminals of the fourth-stage driver and the fourth-stage segment to output high levels. Through resistor R19, the gate capacitance of sampling transistor M24 and power transistor M25 is charged, enabling power transistor M25 to operate in the linear region. When the input voltage VIN decreases and the voltage at the second connection node falls below the threshold voltage of the twelfth NMOS transistor M12, the undervoltage protection voltage V of the input VIN is activated. OFF for:

[0078]

[0079] The twelfth NMOS transistor M12 is cut off, and the gate of the thirteenth NMOS transistor M13 is pulled up and turned on through the ninth resistor R9, pulling the input terminals of the first stage of the driver and the first stage of the segment low. This causes the output terminals of the fourth stage of the driver and the fourth stage of the segment to output a low level, pulling down the gate voltage of the power transistor M25, keeping it off under low input voltage and reducing conduction losses.

[0080] Gate voltage segmented charge / discharge control principle: During the turn-on of power transistor M25 and the rise of VIN, the 36th NMOS transistor M36 detects the voltage divider formed by resistors R14, R15, and R16 at the third connection node, thus indirectly detecting the gate voltage of power transistor M25. When the voltage at the third connection node is higher than the threshold voltage of the 36th NMOS transistor M36, the gate charging release voltage V... on_pl for:

[0081]

[0082] The 36th NMOS transistor M36 is turned on, pulling down the gates of the 35th NMOS transistor M35 and the 37th NMOS transistor M37 to cutoff. Resistor R16 is connected, increasing the voltage at the third connection node and creating hysteresis. Resistor R18 pulls up the gate of the 34th PMOS transistor M34, disconnecting the segmented four-stage output from resistor R19, reducing the gate capacitor charging current, and achieving soft-start.

[0083] During the turn-off of power transistor M25 and the decrease of VIN, the voltage at the third connection node is lower than the threshold voltage of the thirty-sixth NMOS transistor M36. At this time, the detection voltage V for gate discharge is... off_pl for:

[0084]

[0085] The 36th NMOS transistor M36 is off. The gates of the 35th NMOS transistor M35 and the 37th NMOS transistor M37 are pulled up and turned on through the 17th resistor R17. The 16th resistor R16 is short-circuited, reducing the voltage at the third connection node and creating reverse hysteresis. The 37th NMOS transistor M37 turns on and pulls the gate of the 34th PMOS transistor M34 low, connecting the segmented four-stage output terminal to the 19th resistor R19, increasing the gate capacitor discharge current and achieving fast turn-off.

[0086] Overcurrent protection principle: When power transistor M25 operates in the linear region, sampling transistor M24 and power transistor M25 are mirror images with a 1:N area ratio, then the sampling current I... S satisfy:

[0087]

[0088] Where I LOAD The load current of the main power transistor is measured by a sampling resistor connected in series in the current path of the current sensing transistor. This directly acquires and converts the operating current signal flowing through the power device, transforming the current information into a voltage signal that can be recognized by subsequent comparison and control circuits. The sampling voltage V generated across the thirteenth resistor R13 is then used. S for:

[0089]

[0090] When the sampling voltage exceeds the threshold voltage of the 23rd NMOS transistor M23, the 23rd NMOS transistor M23 turns on and pulls down the gate voltage of the sampling transistor M24 and the power transistor M25 to achieve overcurrent turn-off and prevent the power transistor M25 from burning out due to overcurrent.

[0091] Finally, the overcurrent protection detection threshold I is obtained. OCP formula:

[0092] First preferred embodiment: Based on the silicon carbide MOS integrated circuit described above, the circuit power consumption is further optimized by replacing the sixth resistor R6 and the seventh resistor R7 with the first power dissipation diode D1 and the second power dissipation diode D2; the drains of the first power dissipation diode D1 and the second power dissipation diode D2 are connected to the input voltage VIN, and after the gate and source are shorted, they are connected to the drains of the eighth NMOS transistor M8 and the ninth NMOS transistor M9, respectively.

[0093] Replace the ninth resistor R9 and the twelfth resistor R12 with the third power dissipation diode D3 and the fourth power dissipation diode D4; connect the drains of the third power dissipation diode D3 and the fourth power dissipation diode D4 to VIN, and after shorting the gate and source, connect them to the drains of the twelfth NMOS transistor M12 and the thirteenth NMOS transistor M13, respectively.

[0094] Replace the seventeenth resistor R17 and the eighteenth resistor R18 with the fifth power dissipation diode D5 and the sixth power dissipation diode D6; connect the drains of the fifth power dissipation diode D5 and the sixth power dissipation diode D6 to VIN, and after shorting the gate and source, connect them to the drains of the thirty-sixth NMOS transistor M36 and the thirty-seventh NMOS transistor M37, respectively.

[0095] Although the current-limiting resistor can be operated as a constant current source, it can precisely limit the operating current of the eighth NMOS transistor M8, the ninth NMOS transistor M9, the twelfth NMOS transistor M12, the thirteenth NMOS transistor M13, the thirty-sixth NMOS transistor M36, and the thirty-seventh NMOS transistor M37, avoiding the extra power consumption caused by high current and significantly improving the circuit's energy efficiency. At the same time, large-value current-limiting resistors occupy a large layout area; replacing them with the current-limiting resistor can effectively reduce the overall chip area.

[0096] Second preferred embodiment: Based on the above-mentioned silicon carbide MOS integrated circuit, to further improve the over-temperature detection accuracy, the structure connected to the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the fourth PMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh PMOS transistor M7, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the first capacitor C1 is replaced with the following structure:

[0097] This includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a first PNP transistor, a second PNP transistor, a first operational amplifier I1, and a first inverter A1. The sources of the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are connected to the input voltage VIN, and their gates are connected to the output of the first operational amplifier and the drain of the fourth NMOS transistor M4. The source of the fourth NMOS transistor M4 is grounded to GND. The drain of the first PMOS transistor M1 is connected to the non-inverting input of the first operational amplifier I1, the emitter of the first PNP transistor Q1, and grounded to GND through the first resistor R1. The drain of the second PMOS transistor M2 is connected to the inverting input of the first operational amplifier and grounded to GND through the third resistor R3. The drain of the third PMOS transistor M3 is connected to the first connection node, and the first connection node is grounded to GND through the first capacitor C1; the first connection node is grounded to GND through the fourth resistor R4 and the fifth resistor R5 connected in series; the base and collector of the first PNP transistor Q1 and the second PNP transistor Q2 are both grounded to GND, and the emitter of the second PNP transistor Q2 is connected to the inverting input terminal of the first operational amplifier I1 through the second resistor R2; the input terminal of the first inverter A1 is connected to the drain of the third PMOS transistor M3, and the output terminal of the first inverter A1 is connected to the gate of the fourth NMOS transistor M4.

[0098] The first inverter A1 and the fourth NMOS transistor M4 constitute the startup circuit.

[0099] When the input VIN voltage increases, the input voltage of the first inverter A1 is zero, and the high-level output turns on the fourth NMOS transistor M4, causing the gate of the first PMOS transistor M1 to be pulled down. This turns on the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3. The first PMOS transistor M1 and the second PMOS transistor M2 form a matched PMOS current mirror. The first operational amplifier I1 achieves virtual short characteristics through negative feedback, forcing the emitter voltages of the first PNP transistor Q1 and the second PNP transistor Q2 to be equal.

[0100] The first PNP transistor Q1 and the second PNP transistor Q2 are a pair of transistors with an emitter area ratio of 1:K, which, together with the second resistor R2, generate a positive temperature coefficient current PTAT.

[0101] The emitter-junction voltage V generated across the third resistor R3 is the same as that of the first PNP transistor Q1. BEQ1 The relevant negative temperature coefficient current.

[0102] By canceling out the positive temperature coefficient current and the negative temperature coefficient current, and after being mirrored by the third PMOS transistor M3, a zero temperature coefficient reference current is output, and a reference voltage can be obtained at the first connection node.

[0103] When the first connection node receives the reference voltage, the input voltage of the first inverter A1 can be considered as high level, turning off the fourth NMOS transistor M4. This startup circuit does not affect the normal operation of the overall circuit.

[0104] Third preferred embodiment: Based on the above silicon carbide MOS integrated circuit, to further improve the circuit's operational stability, the first power dissipation transistor D1 and the second power dissipation transistor D2 are replaced with the thirty-eighth PMOS transistor M38 and the thirty-ninth PMOS transistor M39. The sources of the thirty-eighth PMOS transistor M38 and the thirty-ninth PMOS transistor M39 are connected to the input voltage VIN, and their gates are connected to the gate of the third PMOS transistor M3. The drain of the thirty-eighth PMOS transistor M38 is connected to the drain of the twelfth NMOS transistor M12, and the drain of the thirty-ninth PMOS transistor M39 is connected to the drain of the thirteenth NMOS transistor M13. The third power dissipation transistor D3 and the fourth power dissipation transistor D4 are replaced with the fortieth PMOS transistor M40 and the forty-first PMOS transistor M41. The sources of the fortieth PMOS transistor M40 and the forty-first PMOS transistor M41 are connected to the input voltage VIN, and their gates are connected to the gate of the third PMOS transistor M3. The drain of the fortieth PMOS transistor M40 is connected to the drain of the eighth NMOS transistor M8, and the drain of the forty-first PMOS transistor is connected to the ninth NMOS transistor M13. The drain of tube M9.

[0105] The third PMOS transistor M3, the thirty-eighth PMOS transistor, the thirty-ninth PMOS transistor, the fortieth PMOS transistor M40, and the forty-first PMOS transistor M41 together form a high-precision current mirror, which accurately mirrors the zero-temperature coefficient reference current to each control branch, making the current of key nodes such as the eighth NMOS transistor M8 and the ninth NMOS transistor M9 constant and with low temperature sensitivity, significantly improving the detection and control accuracy of the circuit.

[0106] Fourth preferred embodiment: Based on the above silicon carbide MOS integrated circuit, to further improve the driving reliability, it also includes a forty-second NMOS transistor M42; the source of the forty-second NMOS transistor M42 is connected to the drain of the thirty-fourth PMOS transistor M34, the drain is connected to the source of the thirty-fourth PMOS transistor M34, and the gate is connected to the drain of the thirty-sixth NMOS transistor M36.

[0107] The forty-second NMOS transistor M42 and the thirty-fourth PMOS transistor M34 complement each other to form a transmission gate structure. Compared with a single MOS transistor, it has a more stable on-resistance, better bidirectional current transmission symmetry, no current attenuation, and smaller turn-off leakage current in the entire voltage range. It is more suitable for the transmission and switching of precision current in the gate voltage control circuit, and improves the consistency and reliability of drive and protection actions.

[0108] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0109] (1) This invention provides a process for a silicon carbide MOS integrated circuit structure. Compared with the high voltage VDMOS process, no additional mask is required, which is beneficial to the control of manufacturing costs. It realizes the monolithic integration of high voltage VDMOS devices, low voltage CMOS devices, capacitors, resistors and diodes, so that each device can give full play to its own advantages. It solves the technical problem of incompatibility between silicon carbide power devices and low voltage control circuit processes in the prior art, and improves integration and reliability.

[0110] (2) The present invention can use the poly layer as an auxiliary interconnect lead to realize the bridging and local interconnection of device electrodes under the process conditions of single-layer metal wiring, thereby reducing process complexity and manufacturing cost.

[0111] (3) The fifth P+ region 28 and the sixth P+ region 29 of the PMOS device are surrounded by the fourth P-well region 10 and the fifth P-well region 11, and the termination protection ring of the VDMOS device is extended to the periphery of all devices, so as to uniformly protect the edge of the entire chip and achieve auxiliary withstand voltage for the entire integrated chip.

[0112] (4) The design of the integrated device of the present invention is conducive to achieving an excellent compromise in performance, function and cost, and is convenient for implementation.

[0113] The diversification of current products allows us to quickly meet the ever-growing market demand.

[0114] (5) In this invention, the monolithic integration of VDMOS, CMOS and passive devices significantly reduces the number of components, interconnects and solder joints in the system compared to the circuits composed of discrete devices, which in turn helps to reduce the size and weight of the system, reduce electromagnetic interfaces, and bring higher reliability to the system.

[0115] (6) The reference circuit of the present invention forms a stable reference current by clamping with a PMOS current mirror and matching the area of ​​an NMOS transistor. In subsequent improved embodiments, a structure combining a PNP transistor and an operational amplifier is further adopted. The positive temperature coefficient current and the negative temperature coefficient current of PTAT cancel each other out to generate a zero temperature coefficient reference voltage. With the selection of a low temperature coefficient polysilicon resistor, the reference voltage is ensured to maintain high stability in a wide temperature range of -40℃ to 175℃. At the same time, the startup circuit is designed to be simple and automatically shuts off after power-on, without affecting the normal operation of the circuit, effectively avoiding the problem of reduced control accuracy caused by reference drift.

[0116] (7) This invention utilizes the strong negative temperature characteristic of the threshold voltage of silicon carbide NMOS to achieve real-time detection of circuit temperature without the need for an additional independent temperature sensor. The temperature detection error is controlled within ±2℃, and the response speed can reach the microsecond level, which is far superior to traditional thermistors. It can quickly capture temperature changes and trigger the over-temperature protection mechanism. By clamping the power transistor with the gate voltage, it prevents the device from being damaged by high temperature. At the same time, through the temperature hysteresis design, it avoids the protection action from being frequently triggered, thus improving the stability of the circuit operation.

[0117] (8) The present invention has perfect undervoltage and overcurrent protection. When the input voltage VIN is low, the power transistor is kept in the off state, which effectively reduces the conduction loss. The overcurrent detection method adopts the area ratio mirror of the sampling transistor and the power transistor + small resistance sampling resistor, which does not lose the performance of the power path, has low conduction loss, strong anti-interference ability, high detection accuracy, good temperature drift characteristics, and simple circuit structure that is easy to integrate on the chip. It is more suitable for the high frequency, high voltage and wide temperature range working requirements of silicon carbide devices.

[0118] (9) When the power transistor is turned on, the gate capacitor charging current is reduced in segments by detecting the gate voltage to achieve soft turn-on and avoid the current surge at the moment of turn-on; when the power transistor is turned off, the gate capacitor discharge current is increased to achieve fast turn-off and reduce turn-off loss; at the same time, the gate voltage control stability is ensured by the hysteresis design, the response speed and control accuracy of the drive circuit are improved, and the working characteristics of silicon carbide power transistor are adapted.

[0119] (10) By replacing the large-value current-limiting resistor with the power dissipation resistor in the first improved embodiment, the operating current of key devices can be precisely limited, reducing additional power consumption and significantly reducing the chip layout area; in the third improved embodiment, a PMOS transistor is used to replace the power dissipation resistor to form a high-precision current mirror, further improving the current control accuracy, while simplifying the circuit structure and reducing the system integration cost.

[0120] (11) In the fourth improved embodiment, a transmission gate is used. Compared with a single MOS transistor, its on-resistance is more stable across the entire voltage range, its bidirectional current transmission symmetry is better, it has no current attenuation and its turn-off leakage current is smaller, which effectively improves the reliability of the transmission and switching of precision current in the gate voltage control circuit and ensures the consistency of drive and protection actions.

[0121] (12) The reference circuit, drive circuit, over-temperature, over-current, and under-voltage protection functions are integrated into a single chip, eliminating the need for additional independent components, simplifying the system structure and reducing system size and cost; at the same time, relying on the high bandgap characteristics of silicon carbide material, the device can work stably in the range of -40℃ to 175℃ or even higher temperatures, with strong radiation resistance and anti-interference capabilities, and is suitable for harsh working conditions such as industrial control, new energy, and aerospace. Attached Figure Description

[0122] Figure 1 This is a schematic flowchart of a silicon carbide MOS integrated circuit process according to Embodiment 1 of the present invention.

[0123] Figure 2 This is a schematic cross-sectional view of the silicon carbide integrated device implemented using the silicon carbide MOS integrated circuit process according to Embodiment 1 of the present invention.

[0124] Figure 3 This is a top view of the overall structure of the silicon carbide integrated device implemented by the silicon carbide MOS integrated circuit process in Embodiment 1 of the present invention.

[0125] Figure 4 This is a schematic diagram of a silicon carbide MOS integrated circuit provided in Embodiment 2 of the present invention.

[0126] Figure 5 This is a schematic diagram of another silicon carbide MOS integrated circuit provided in Embodiment 3 of the present invention.

[0127] Figure 6 This is a schematic diagram of another silicon carbide MOS integrated circuit provided in Embodiment 4 of the present invention.

[0128] Figure 7 This is a schematic diagram of another silicon carbide MOS integrated circuit provided in Embodiment 5 of the present invention.

[0129] Figure 8 This is a schematic diagram of another silicon carbide MOS integrated circuit provided in Embodiment 6 of the present invention. Detailed Implementation

[0130] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0131] Example 1;

[0132] like Figure 1 The diagram shows a schematic of the fabrication process of the silicon carbide MOS integrated circuit of the present invention, which specifically includes the following main process steps:

[0133] Step 1: A low-defect, high-crystal-quality N-type 4H-SiC single crystal wafer is selected as the device substrate 1. This substrate is heavily doped, possessing low resistivity, high thermal conductivity, and high structural stability. It provides a stable single-crystal substrate for subsequent epitaxial growth, ion implantation, and high-temperature annealing processes, while also serving as the drain current conduction path for the device, meeting the requirements of high-voltage power devices for substrate conductivity and mechanical strength. In this embodiment, the doping concentration is controlled at 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 Within the range.

[0134] Step 2: An N-type buffer layer 2 is epitaxially grown on the upper surface of the N-type 4H-SiC substrate 1. This N-type buffer layer reduces interface defects between the substrate and the epitaxial layer, suppresses epitaxial layer punch-through, improves the overall breakdown voltage and high-temperature operating stability of the device, and optimizes the trade-off between the device's on-resistance and breakdown voltage. In this embodiment, the buffer layer 2 uses high-concentration N-type doping, with the doping concentration controlled at 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 Within this range, the thickness is set from 0.3 μm to 1.5 μm.

[0135] Step 3: On top of the N-type buffer layer 2, an N-type 4H-SiC epitaxial layer 3 of a predetermined thickness is epitaxially grown using chemical vapor deposition. This epitaxial layer serves as the high-voltage withstand region and main current drift region of the device. It possesses low doping and high resistivity characteristics, enabling it to withstand reverse high voltage during device operation, ensuring sufficient breakdown voltage and blocking capability. Simultaneously, it provides a unified epitaxial support layer for high-voltage power devices and low-voltage control circuits, achieving voltage isolation and electrical compatibility between high- and low-voltage devices. In this embodiment, the doping concentration of epitaxial layer 3 is controlled at 1×10⁻⁶. 15 cm-3 Up to 1×10 17 cm -3 Within the range.

[0136] Step 4: A thick field oxygen isolation layer 4 is formed by deposition. The thickness of the thick field oxygen isolation layer 4 is 0.5 μm to 2 μm, which is used to achieve high voltage electrical isolation and surface passivation between devices. Then, the oxide layer above the active region is completely removed by photolithography and wet etching processes, retaining the thick field oxygen structure of the isolation region, so as to provide a clean active region surface for subsequent ion implantation and gate oxide layer growth.

[0137] Step 5: N-type impurity ion implantation is performed in the N-type epitaxial layer 3. This implantation step is used to precisely control the doping concentration and vertical distribution of the JFET region 5 of the VDMOS device, and also to ensure compatibility with the formation of the N-well region 6 of the PMOS device. By simultaneously achieving the doping requirements of high- and low-voltage devices through the same implantation process, the process flow is effectively simplified, process compatibility is improved, and the on-resistance and breakdown voltage characteristics of the VDMOS device are optimized, while the threshold voltage, leakage current, and other electrical properties of the PMOS device are improved. In this embodiment, the number of ion implantations is 2 to 5, and the total implantation dose is controlled at 1×10⁻⁶. 12 cm -3 Up to 1×10 13 cm -3 Within the range.

[0138] Step 6: In the N-type epitaxial layer 3, P-type impurities are implanted by ions to simultaneously form the first P-well region 7 of the VDMOS device, the second P-well region 8, the third P-well region 9 of the NMOS device, the fourth P-well region 10 and the fifth P-well region 11 of the PMOS device, the sixth P-well region 12 of the well resistor, the seventh P-well region 13 of the capacitor, and the eighth P-well region 14 of the diode. A single implantation process is used to fabricate the well structure of all devices, significantly simplifying the process flow and improving high- and low-voltage integration compatibility. In this embodiment, the number of ion implantations is 2 to 5, and the total implantation dose is controlled at 5 × 10⁻⁶. 13 cm -3 Up to 2×10 14 cm -3 Within the range.

[0139] Step 7: In N-well region 6 and P-well regions 7-9 (7-9) and P-well regions 12-14 (12-14), N-type high-energy impurities are introduced by ion implantation to simultaneously form the first N+ region 15, the second N+ region 16 of the VDMOS device, the third N+ region 17, the fourth N+ region 18 of the NMOS device, the fifth N+ region 19 of the PMOS device, the sixth N+ region 20 of the trap resistor, the seventh N+ region 21, the eighth N+ region 22 of the capacitor, and the ninth N+ region 23 of the diode. The above-mentioned N+ regions are heavily doped to form a low-resistance, steep, and uniform heavily doped layer, reducing ohmic contact resistance, improving the device's conduction, contact, and switching characteristics, and ensuring the electrical consistency and stability of the high- and low-voltage integrated structure. In this embodiment, the number of ion implantations is 2 to 5 times, and the total implantation dose is controlled at 1×10⁻⁶. 15 cm -3 Up to 3×10 15 cm -3 Within the range.

[0140] Step 8: Ion implant P-type impurities into the N-type epitaxial layer 3 and the seventh to fourteenth P-well regions 7-14 to form the first P+ region 24, the second P+ region 25 of the VDMOS device, the third P+ region 26 of the NMOS device, the fourth P+ region 27, the fifth P+ region 28, the sixth P+ region 29, the seventh P+ region 30 of the PMOS device, the eighth P+ region 31 of the well resistor, the ninth P+ region 32 of the capacitor, and the tenth P+ region 33 of the diode. The above P+ regions are heavily doped to reduce contact resistance, improve ohmic contact performance, and stabilize the body potential of each device, ensuring the reliability and electrical stability of the high-voltage integrated device. In this embodiment, the number of ion implantations is 2 to 5, and the total implantation dose is controlled at 5 × 10⁻⁶. 13 cm -3 Up to 1×10 15 cm -3 Within the range.

[0141] Step 9: After completing all ion implantation processes, the device surface undergoes comprehensive photoresist removal and deep cleaning to thoroughly remove residual photoresist, photolithography byproducts, particulate contaminants, and metal ion impurities, ensuring a clean and undamaged silicon carbide surface and providing clean interface conditions for subsequent high-temperature annealing. Subsequently, a dense and uniform amorphous carbon film is formed on the clean device surface. This carbon film serves as a high-temperature protective coating, effectively suppressing the high-temperature sublimation and decomposition of silicon atoms on the silicon carbide surface during subsequent ultra-high temperature annealing. This prevents problems such as surface roughening, lattice defects, and impurity spillover from the SiC surface, while ensuring stable doping distribution after ion implantation and improving the lattice repair effect and device surface quality after high-temperature annealing.

[0142] Step 10: Perform high-temperature annealing at 1600-1900℃ in a high-purity Ar atmosphere or vacuum environment to fully activate the doped impurities in each ion-implanted region, effectively repair lattice damage caused by ion implantation, and improve crystal quality and device electrical performance. After annealing, remove the surface carbon film by a combination of oxidation ashing and wet cleaning, and thoroughly clean away residual contaminants to obtain a clean device surface.

[0143] Step 11: First, a sacrificial oxide layer is formed, and then it is completely removed by wet etching to eliminate the damage and contamination caused by ion implantation and high-temperature annealing on the SiC surface. Subsequently, a high-quality gate oxide layer 34 is grown on the clean silicon carbide surface using a thermal oxidation process, with a thickness controlled between 30 nm and 60 nm. Annealing is then performed in a nitrogen or inert gas atmosphere to further stabilize the internal charge and interface characteristics of the gate oxide layer.

[0144] Step 12: Deposit a polycrystalline silicon thin film with a thickness of 300 nm to 500 nm on a clean device surface using a low-pressure chemical vapor deposition process, and then perform heavy doping treatment on it by high-precision ion implantation or high-temperature in-situ doping to significantly reduce the film resistivity and improve the conductivity uniformity, providing a stable and reliable material basis for subsequent gate electrodes or interconnect structures.

[0145] Step 13: The polysilicon thin film is patterned using a dry etching process to precisely define the gate pattern and form the gates 35 of VDMOS, PMOS, NMOS and capacitor devices respectively. At the same time, polysilicon resistors 35 are formed on top of the thick field oxygen isolation layer 4, realizing the integrated fabrication of polysilicon functional structures.

[0146] Step 14: Deposit SiO2 to form dielectric layer 36 and reflow to achieve planarization;

[0147] Step 15: Perform contact hole etching to complete the ohmic contact fabrication. Then, sputter metal to form the first source metal 37, the second source metal 38, and the first VP electrode metal 39 and the second VP electrode metal 40 of the body region of the VDMOS device; the drain metal 41, the source metal 42, and the VP electrode metal 43 of the body region of the NMOS device; the drain metal 44, the source metal 45, the VN electrode metal 46 of the body region, and the first P+ region metal 47 and the second P+ region metal 48 of the PMOS device; the positive electrode metal 49, the negative electrode metal 50, and the VP electrode metal 51 of the body region of the well resistor; the drain metal 52, the source metal 53, and the VP electrode metal 54 of the body region of the capacitor; and the cathode metal 55 and the anode metal 56 of the diode.

[0148] Step 16: Perform poly contact hole etching to create ohmic contacts at the contact holes. Then, sputter metal to form the gate metal 57 of the VDMOS device, the gate metal 58 of the NMOS device, the gate metal 59 of the PMOS device, the gate metal 60 of the capacitor, and the positive electrode metal 61 and negative electrode metal 62 of the poly resistor. Simultaneously, steps 15 and 16 also achieve electrode bridging and local interconnection through a single layer of metal with the assistance of the poly layer.

[0149] Step 17: Backside thinning and metallization to form the drain metal 63 of the VDMOS device.

[0150] Preferably, the N-type impurity is nitrogen or phosphorus, and the P-type impurity is aluminum or boron.

[0151] Preferably, step 3 can form a superjunction structure through multiple epitaxial and implantation processes to better optimize the electrical characteristics of the VDMOS device.

[0152] Preferably, step 5 can be implemented by adjusting the N-type impurity injection energy, dose, and number of times to meet the on-resistance and breakdown voltage requirements of different VDMOS and PMOS devices.

[0153] Preferably, step 6 can be performed by adjusting different P-type impurity implantation energies, doses, and number of times to meet the threshold voltage, on-resistance, and breakdown voltage requirements of different VDMOS and NMOS.

[0154] Preferably, step 9 can be achieved by direct deposition or high-temperature carbonization of photoresist to create a dense carbon film.

[0155] Preferably, after depositing the polycrystalline silicon thin film in step 12, the resistance forming region of the polycrystalline silicon thin film may not be subjected to ion implantation and in-situ doping to form a high-resistance poly resistor.

[0156] Preferably, step 13 can utilize a poly layer as an auxiliary interconnect lead to achieve bridging and local interconnection of device electrodes under single-layer metal wiring process conditions.

[0157] Preferably, steps 15 and 16 can fabricate a multilayer metal interconnect structure to achieve more complex circuit wiring.

[0158] Based on the complete silicon carbide integrated circuit process described above, various functional device structures can be integrated and formed on a monolithic N-type 4H-SiC substrate and an N-type epitaxial layer, such as... Figure 2Specifically, it includes high-voltage silicon carbide VDMOS devices, low-voltage silicon carbide NMOS devices, and low-voltage silicon carbide PMOS devices. Passive and active devices such as trap resistors, poly resistors, capacitors, and diodes are fabricated simultaneously, realizing monolithic integration of high- and low-voltage devices and passive components. This effectively simplifies the device fabrication process, improves integration, and reduces device packaging costs. Moreover, the structures of each device are compatible and matched, which can give full play to the advantages of silicon carbide material in terms of high voltage resistance, high thermal conductivity, and high frequency, and meet the integrated application requirements of high-voltage power control circuits.

[0159] The high-voltage silicon carbide VDMOS device includes a drain electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3. On top of the N-type epitaxial layer 3, a JFET region 5, a first P-well region 7, a second P-well region 8, a first N+ region 15, a second N+ region 16, a first P+ region 24, and a second P+ region 25 are distributed. The first N+ region 15, the second N+ region 16, and the first P+ region 24 and the second P+ region 25 are located inside the first P-well region 7 and the second P-well region 8, while the JFET region 5 is located between the first P-well region 7 and the second P-well region 8. Above the JFET region 5 is a gate oxide layer 34, covering the channel region formed by the nesting of the first P-well region 7, the second P-well region 8, and the first N+ region 15 and the second N+ region 16. Above the first N+ region 15 and the second N+ region 16 are the first source metal 37 and the second source metal 38, respectively. Above the first P+ region 24 and the second P+ region 25 are the first VP electrode metal 39 and the second VP electrode metal 40 of the body region. Above the gate oxide layer 34 is a poly gate 35, and above the poly gate 35 is a gate electrode 57. In addition, there is an isolation dielectric layer 36 on the top of the device.

[0160] The low-voltage silicon carbide NMOS device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3. On top of the N-type epitaxial layer 3, a third P-well region 9, a third N+ region 17, a fourth N+ region 18, and a third P+ region 26 are distributed. The third N+ region 17, the fourth N+ region 18, and the third P+ region 26 are located inside the third P-well region 9. Above the epitaxial layer between the third N+ region 17 and the fourth N+ region 18 is a gate oxide layer 34, covering the channel region of the NMOS device. Above the third N+ region 17 and the fourth N+ region 18 are a drain electrode 41 and a source electrode 42. Above the third P+ region 26 is a body region VP electrode 43. Above the gate oxide layer 34 is a poly gate 35, and above the poly gate 35 is a gate electrode 58. In addition, an isolation layer 36 is located on top of the device.

[0161] The low-voltage silicon carbide PMOS device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3. On top of the N-type epitaxial layer 3, N-well regions 6, a fourth P-well region 10, a fifth P-well region 11, a fifth N+ region 19, a fourth P+ region 27, a fifth P+ region 28, a sixth P+ region 29, and a seventh P+ region 30 are distributed. A gate oxide layer 34 is located above the epitaxial layer between the fifth P+ regions 28 and the sixth P+ regions 29, covering the channel region of the PMOS device. A source electrode 44 and a drain electrode 45 are located above the fifth P+ regions 28 and 29. A first P+ region metal 47 and a second P+ region metal 48 are located above the fourth P+ regions 27 and 30. A body region VN electrode 46 is located above the fifth N+ region 19. A poly gate 35 is located above the gate oxide layer 34, and a gate electrode 59 is located above the poly gate 35. In addition, there is an isolation layer 36 on top of the device.

[0162] The described well resistor device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3, sequentially arranged on top of the substrate. On top of the N-type epitaxial layer 3, a sixth P-well region 12, a sixth N+ region 20, and an eighth P+ region 31 are distributed. The sixth N+ region 20 is located within the sixth P-well region 12. Above the sixth N+ region 20 are the positive electrode metal 49 and the negative electrode metal 50 of the well resistor, and above the eighth P+ region 31 is the VP electrode metal 51. Furthermore, an isolation layer 36 is present on top of the device.

[0163] The poly resistor device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3, which are sequentially placed on top of the substrate. Above the N-type epitaxial layer 3 is a field oxide layer 4, above the field oxide layer 4 is a poly resistor 35, and above the poly resistor 35 are the positive electrode metal 61 and the negative electrode metal 62 of the poly resistor 35. Additionally, an isolation layer 36 is located on top of the device.

[0164] The capacitor device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3, all sequentially arranged on top of the substrate. On top of the N-type epitaxial layer 3, a seventh P-well region 13, a seventh N+ region 21, an eighth N+ region 22, and a ninth P+ region 32 are distributed. The seventh N+ region 21, the eighth N+ region 22, and the ninth P+ region 32 are located within the seventh P-well region 13. Above the epitaxial layer between the seventh N+ region 21 and the eighth N+ region 22 is a gate oxide layer 34, covering the channel region of the capacitor device. Above the seventh N+ region 21 and the eighth N+ region 22 are a drain electrode 52 and a source electrode 53. Above the ninth P+ region 32 is a body region VP electrode 54. Above the gate oxide layer 34 is a poly gate 35, and above the poly gate 35 is a gate electrode 60. Furthermore, an isolation layer 36 is located on top of the device.

[0165] The diode device includes a substrate electrode 63, an N-type substrate 1, an N-type buffer layer 2, and an N-type epitaxial layer 3, all sequentially arranged on top of the substrate. On top of the N-type epitaxial layer 3, an eighth P-well region 14, a ninth N+ region 23, and a tenth P+ region 33 are distributed. The ninth N+ region 23 and the tenth P+ region 33 are located inside the eighth P-well region 14. Above the tenth P+ region 33 is a positive electrode 56, and above the ninth N+ region 23 is a negative electrode 55. Furthermore, an isolation layer 36 is present on top of the device.

[0166] Preferably, the high-voltage VDMOS device involved in this invention shares the same P-well injection, P+ injection, and N+ injection with low-voltage PMOS devices, low-voltage NMOS devices, well resistor devices, poly resistor devices, capacitor devices, and diode devices, and uses the same gate oxide layer thickness.

[0167] Preferably, the fifth P+ region 28 and the sixth P+ region 29 of the PMOS device are surrounded by the fourth P-well region 10 and the fifth P-well region 11, and the terminal protection ring of the VDMOS device is extended to the periphery of all devices, so as to uniformly protect the entire chip edge and achieve auxiliary withstand voltage for the integrated chip as a whole.

[0168] Preferably, the integrated silicon carbide MOS integrated circuit process according to claim 1 further includes, after step 8, introducing an N-type impurity implantation process in the channel region below the gate oxide layer in the high-voltage VDMOS device region and the low-voltage NMOS device region to form a high-concentration N-type electron accumulation layer on the semiconductor surface below the gate oxide layer; this electron accumulation layer can provide a stable N-type conductive channel for the device under zero gate voltage or negative gate voltage, thereby simultaneously fabricating a high-voltage depletion-type VDMOS device and a low-voltage depletion-type NMOS device on the same chip, realizing the compatible integration of high-voltage power devices and low-voltage control devices in terms of process structure, and then proceeding to step 9.

[0169] Preferably, the integrated silicon carbide MOS integrated circuit process according to claim 1 further includes, after step 8, performing an additional ion implantation process by selectively implanting N-type impurities or P-type impurities in the channel region below the gate oxide layer of the low-voltage NMOS device region and the low-voltage PMOS device region, respectively, to precisely adjust and optimize the threshold voltage of the low-voltage NMOS device and the low-voltage PMOS device, so that the threshold voltage of the two devices meets the working requirements of the low-voltage CMOS circuit, and improves the turn-on consistency and working stability of the circuit under high temperature and high voltage conditions, before proceeding to step 9.

[0170] Preferably, the integrated silicon carbide MOS integrated circuit process according to claim 1 further includes, after the gate oxide layer growth in step 11, patterning the low-voltage NMOS device region and the low-voltage PMOS device region by photolithography processes such as spin coating photoresist, exposure, and development, so that the gate oxide layer in this region is exposed, while the high-voltage VDMOS device region and other high-voltage functional regions are covered and protected by photoresist; then, etching is performed on the exposed region to completely remove the gate oxide layer in the low-voltage NMOS device region and the low-voltage PMOS device region, so that the silicon carbide surface in this region is exposed again; on the basis of retaining the original photoresist mask, a second thermal oxidation process is performed on the wafer to grow a high-quality thin gate oxide layer with a thickness of 10nm to 20nm in the exposed low-voltage device region, while the high-voltage region protected by the photoresist and the original thick gate oxide layer no longer undergoes significant oxidation, thereby simultaneously forming a thick gate oxide layer adapted to the high-voltage device and a thin gate oxide layer adapted to the low-voltage device on the same chip, realizing differentiated preparation of gate oxide thickness for high and low voltage devices, and then proceeding to step 12.

[0171] Example 2:

[0172] This embodiment discloses a silicon carbide MOS integrated circuit structure, the overall structure of which is as follows: Figure 4 As shown, it includes:

[0173] PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, NMOS transistor M11, NMOS transistor M12, NMOS transistor M13, PMOS transistor M14, NMOS transistor M15, PMOS transistor M16, NMOS transistor M17, NMOS transistor M18, NMOS transistor M19, PMOS transistor M20, NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24, NMOS transistor M25, PMOS transistor M26, NMOS transistor M27 Transistor M27, PMOS transistor M28 (28th), NMOS transistor M29 (29th), PMOS transistor M30 (30th), NMOS transistor M31 (31st), PMOS transistor M32 (32nd), NMOS transistor M33 (33rd), PMOS transistor M34 (34th), NMOS transistor M35 (35th), NMOS transistor M36 (36th), NMOS transistor M37 (37th), Resistor R1 (1st), Resistor R2 (2nd), Resistor R3 (3rd), Resistor R4 (4th), Resistor R5 (5th), Resistor R6 (6th), Resistor R7 (7th), Resistor R8 (8th), Resistor R9 (9th), Resistor R10 (10th), Resistor R11 (11th), Resistor R12 (12th), Resistor R13 (13th), Resistor R14 (14th), Resistor R15 (15th), Resistor R16 (16th), Resistor R17 (17th), Resistor R18 (18th), Resistor R19 (19th), Capacitor C1 (1st), Capacitor C2 (2nd).

[0174] The sources of the first PMOS transistor M1, the third PMOS transistor M3, the fourth PMOS transistor M4, and the seventh PMOS transistor M7 are all connected to the input voltage VIN, and their gates are all connected to the drain of the fourth PMOS transistor M4. The drain of the first PMOS transistor M1 is connected to the gate of the second PMOS transistor M2. The source of the second PMOS transistor M2 is grounded to GND through the first resistor R1, and its drain is connected to the gate of the fifth NMOS transistor M5. The drain of the third PMOS transistor M3 is connected to the drain and gate of the fifth NMOS transistor M5. The drain of the fourth PMOS transistor M4 is connected to the drain of the sixth NMOS transistor M6. The source of the fifth NMOS transistor is grounded to GND, and the source of the sixth NMOS transistor is grounded to GND through the second resistor R2. The drain of the seventh PMOS transistor is connected to the first connection node through the third resistor R3. The first connection node is grounded to GND through the first capacitor C1, the fourth resistor R4, and the fifth resistor R5.

[0175] The gate of the eighth NMOS transistor is connected to the first connection node, and its drain is connected to the input voltage VIN via the sixth resistor R6; the gate of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8, its source is grounded to GND, and its drain is connected to the input voltage VIN via the seventh resistor R7; the source of the tenth NMOS transistor M10 is grounded to GND, and its drain is connected to the connection node of the fourth resistor R4 and the fifth resistor R5; the gate of the twenty-second NMOS transistor M22 is connected to the drain of the ninth NMOS transistor M9, its source is grounded to GND, and its drain is connected to the gate of the twenty-fifth NMOS transistor.

[0176] The upper ends of the eighth resistor R8, the ninth resistor R9, and the twelfth resistor R12 are all connected to the input voltage VIN. The lower end of the eighth resistor R8 is connected to the second connection node, which is grounded to GND via the second capacitor C2, and also grounded to GND via the tenth resistor R10 and the eleventh resistor R11 in series. The series connection node of the tenth resistor R10 and the eleventh resistor R11 is connected to the drain of the eleventh NMOS transistor. The source of the eleventh NMOS transistor is grounded to GND, and its gate is connected to the drain of the twelfth NMOS transistor. The gate of the twelfth NMOS transistor is connected to the second connection node, and its drain is connected to the input voltage VIN via the ninth resistor R9. The gate of the thirteenth NMOS transistor M13 is connected to the drain of the twelfth NMOS transistor M12, its source is grounded to GND, and its drain is connected to the input voltage VIN via the twelfth resistor R12.

[0177] The sources of the fourteenth, sixteenth, eighteenth, and twentieth PMOS transistors are connected to the input voltage VIN; the sources of the fifteenth, seventeenth, nineteenth, and twenty-first NMOS transistors are connected to ground GND.

[0178] Driver Stage 1: The drain of the fourteenth PMOS transistor and the drain of the fifteenth NMOS transistor are connected together to form the output terminal of the driver stage, and their gates are connected together as the driver input terminal.

[0179] Drive the second stage: The drain of the sixteenth PMOS transistor and the drain of the seventeenth NMOS transistor are connected together to form the output terminal of the second stage driver, and the gates of the two transistors are connected together to drive the output terminal of the first stage driver;

[0180] Drive stage 3: The drain of the eighteenth PMOS transistor and the drain of the nineteenth NMOS transistor are connected together to form the output terminal of drive stage 3, and the gates of the two transistors are connected together to drive stage 2 output terminal;

[0181] Drive stage four: The drain of the twentieth PMOS transistor and the drain of the twenty-first NMOS transistor are connected together to form the output terminal of drive stage four.

[0182] The 24th NMOS transistor is a current sampling transistor M24, and the 25th NMOS transistor is a power transistor M25; their drains are connected to the output node OUT; the source of the 24th NMOS transistor is grounded to GND through the 13th resistor R13; the gate of the 23rd NMOS transistor is connected to the source of the 24th NMOS transistor, the drain is connected to the gate of the 24th NMOS transistor, and the source is grounded to GND; the gate of the 25th NMOS transistor is connected to the gate of the 24th NMOS transistor, and the source is grounded to GND.

[0183] The sources of the 26th PMOS transistor M26, the 28th PMOS transistor M28, the 30th PMOS transistor M30, and the 32nd PMOS transistor M32 are connected to the input voltage VIN; the sources of the 27th NMOS transistor, the 29th NMOS transistor, the 31st NMOS transistor, and the 33rd NMOS transistor are connected to ground GND.

[0184] Segmented Stage 1: The drain of the 26th PMOS transistor and the drain of the 27th NMOS transistor are connected together to form the segmented stage 1 output terminal. The gates of both transistors are connected to the second connection node as the segmented drive stage 1 input terminal.

[0185] Segmented two-stage: The drain of the 28th PMOS transistor and the drain of the 29th NMOS transistor are connected together to form the segmented two-stage output terminal, and their gates are connected together to the segmented first-stage output terminal;

[0186] Three-stage segmentation: The drain of the 30th PMOS transistor and the drain of the 31st NMOS transistor are connected together to form a three-stage segmented output terminal, and their gates are connected together to form a two-stage segmented output terminal.

[0187] Segmented four stages: The drain of the thirty-second PMOS transistor and the drain of the thirty-third NMOS transistor are connected together to form a segmented four-stage output terminal;

[0188] The source of the thirty-fourth PMOS transistor is connected to the four-stage drive output terminal, the drain is connected to the four-stage segmented output terminal, and the gate is connected to the drain of the thirty-seventh NMOS transistor.

[0189] The upper ends of the fourteenth resistor R14, the seventeenth resistor R17, and the eighteenth resistor R18 are connected to the output terminals of the four-stage drive, and are connected to the gate of the twenty-fifth NMOS transistor M25 via the nineteenth resistor R19; the lower end of the fourteenth resistor R14 is connected to the third connection node, and the third connection node is connected to ground GND via the fifteenth resistor R15 and the sixteenth resistor R16 in series; the series node of the fifteenth resistor R15 and the sixteenth resistor R16 is connected to the drain of the thirty-fifth NMOS transistor M35, the source of the thirty-fifth NMOS transistor M35 is grounded to GND, and the gate is connected to the drain of the thirty-sixth NMOS transistor M36;

[0190] The gate of the thirty-sixth NMOS transistor M36 is connected to the third connection node, and the drain is connected to the gate of the twenty-fifth NMOS transistor M25 via the seventeenth resistor R17; the gate of the thirty-seventh NMOS transistor M37 is connected to the drain of the thirty-sixth NMOS transistor M36, and the source is grounded to GND. The nineteenth resistor R19 is connected to the common node of the gate of the power transistor M25.

[0191] The reference circuit operates as follows: The third PMOS transistor M3 and the fourth PMOS transistor M4 form a current mirror with a 1:1 area ratio, ensuring that the current flowing through them is equal during normal operation. The fifth NMOS transistor M5 and the sixth NMOS transistor M6 are set with a 1:K area ratio. Under the clamping effect of the third PMOS transistor M3 and the fourth PMOS transistor M4, the operating currents of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are forced to be equal, thereby making their VL equal. GS There is a voltage difference, and this voltage drop is applied across the second resistor R2, forming a temperature-dependent reference current I. REF .

[0192] Where μn represents electron mobility, C OX W / L represents the capacitance per unit area of ​​the gate oxide layer of a MOSFET, where W / L is the width-to-length ratio of the MOSFET.

[0193] The fourth PMOS transistor M4 and the seventh PMOS transistor M7 further form a current mirror, mirroring the aforementioned reference current to the first connection node, thereby forming a stable reference voltage V independent of the input voltage VIN at the first connection node. REF .

[0194]

[0195] The startup circuit works as follows: The second PMOS transistor M2 and the first resistor R1 constitute the startup circuit. When the input voltage VIN rises, the gate voltage of the second PMOS transistor M2 is pulled down to a low level through the first resistor R1, turning on the second PMOS transistor M2 and causing the gate voltage of the fifth NMOS transistor M5 to rise and turn on. Under the action of the positive feedback loop, the entire circuit gradually enters the normal operating state. Subsequently, the first PMOS transistor M1 mirrors the reference current to the first resistor R1 and forms a voltage drop, turning off the second PMOS transistor M2. After power-on, this startup branch no longer affects the normal operation of the circuit.

[0196] Silicon carbide (SiC) device temperature detection characteristics: Silicon carbide has a large bandgap (approximately 3.26 eV), allowing devices to operate stably in the range of -40℃ to 175℃ and even higher. SiC NMOS devices exhibit a strong negative temperature characteristic in relation to threshold voltage and temperature, with good linearity of temperature drift and a stable temperature coefficient. Their detection sensitivity is significantly higher than that of silicon-based devices, and the temperature detection error can be controlled within ±2℃. The response speed of its threshold voltage to temperature changes can reach the microsecond level, far faster than traditional thermistors (millisecond level), enabling real-time capture of temperature abrupt changes and timely triggering over-temperature shutdown and other protection mechanisms. Furthermore, this temperature detection function can be monolithically integrated with multi-level drive and segmented drive structures, eliminating the need for an additional independent temperature sensor, simplifying the system structure, and reducing chip area and cost.

[0197] The threshold voltage of a silicon carbide NMOS can be expressed as:

[0198] Where T0 represents room temperature, and the threshold voltage of silicon carbide is V. T The temperature coefficient of the threshold voltage of silicon carbide NMOS can be expressed as: α≈-0.4×10 -3 V / ℃, where T represents the junction temperature.

[0199] Over-temperature detection and protection principle: The gate of the eighth NMOS transistor M8 is connected to the reference voltage of the first connection node, and its VGS is approximately constant. When the temperature has not reached the over-temperature threshold, the threshold voltage of the eighth NMOS transistor M8 is greater than its VGS. GS When the transistor is cut off, the drain is pulled high by the sixth resistor R6, the ninth NMOS transistor M9 is turned on, and the eleventh resistor R11 is shorted. At this time, the gate voltage bias is I. REF• R4. When the temperature rises to the over-temperature threshold, the threshold voltage of the eighth NMOS transistor M8 is: :

[0200] V REF T represents the over-temperature protection detection reference voltage. det This is the junction temperature at which over-temperature protection is triggered.

[0201] The threshold voltage of the eighth NMOS transistor M8 is lower than V. GS The transistor turns on and pulls down the gates of the ninth NMOS transistor M9 and the tenth NMOS transistor M10 to cut off. The seventh resistor R7 pulls up the gate of the twenty-second NMOS transistor M22 to turn it on. The twenty-second NMOS transistor M22 pulls down the gate voltage of the sampling transistor M24 and the power transistor M25, realizing gate voltage clamping protection under over-temperature conditions.

[0202] Meanwhile, since the tenth NMOS transistor M10 is turned off, the fifth resistor R5 is connected to the branch, causing the gate voltage to rise and achieving temperature hysteresis. When the temperature drops to the threshold voltage of the eighth NMOS transistor M8, :

[0203] T rel This is the junction temperature when over-temperature protection is applied.

[0204] When the temperature drops to a level that causes the threshold voltage of the eighth NMOS transistor M8 to be higher than... When the voltage is applied, the circuit returns to normal operation.

[0205] Undervoltage and hysteresis control principle: The twelfth NMOS transistor M12 detects the voltage of the voltage divider network formed by the eighth resistor R8, the tenth resistor R10, and the eleventh resistor R11 at the second connection node. When the voltage at the second connection node is higher than the threshold voltage of the twelfth NMOS transistor M12, the input VIN voltage is V. ON :

[0206]

[0207] The twelfth NMOS transistor M12 is turned on, pulling down the gates of the eleventh NMOS transistors M11 and M13 to cutoff. Resistor R11 is connected, further increasing the voltage at the second connection node to achieve hysteresis comparison characteristics. Resistor R12 pulls high the input terminals of the first-stage driver and the first-stage segment, causing the output terminals of the fourth-stage driver and the fourth-stage segment to output a high level. Resistor R19 charges the gate capacitance of sampling transistor M24 and power transistor M25, enabling power transistor M25 to operate in the linear region. When the input voltage VIN decreases and the voltage at the second connection node falls below the threshold voltage of the twelfth NMOS transistor M12, the input VIN voltage is V. OFF :

[0208]

[0209] The twelfth NMOS transistor M12 is cut off, and the gate of the thirteenth NMOS transistor M13 is pulled up and turned on through the ninth resistor R9, pulling the input terminals of the first stage of the driver and the first stage of the segment low. This causes the output terminals of the fourth stage of the driver and the fourth stage of the segment to output a low level, pulling down the gate voltage of the power transistor M25, keeping it off under low input voltage and reducing conduction losses.

[0210] Gate voltage segmented charge / discharge control principle: During the turn-on of power transistor M25 and the rise of VIN, the 36th NMOS transistor M36 detects the voltage divider formed by resistors R14, R15, and R16 at the third connection node, thus indirectly detecting the gate voltage of power transistor M25. When the voltage at the third connection node is higher than the threshold voltage of the 36th NMOS transistor M36, the detected voltage is... :

[0211]

[0212] The 36th NMOS transistor M36 is turned on, pulling down the gates of the 35th NMOS transistor M35 and the 37th NMOS transistor M37 to cutoff. Resistor R16 is connected, increasing the voltage at the third connection node and creating hysteresis. Resistor R18 pulls up the gate of the 34th PMOS transistor M34, disconnecting the segmented four-stage output from resistor R19, reducing the gate capacitor charging current, and achieving soft-start.

[0213] During the process of power transistor M25 being turned off and VIN decreasing, the voltage at the third connection node is lower than the threshold voltage of the thirty-sixth NMOS transistor M36. At this time, the detected voltage is... :

[0214]

[0215] The 36th NMOS transistor M36 is off. The gates of the 35th NMOS transistor M35 and the 37th NMOS transistor M37 are pulled up and turned on through the 17th resistor R17. The 16th resistor R16 is short-circuited, reducing the voltage at the third connection node and creating reverse hysteresis. The 37th NMOS transistor M37 turns on and pulls the gate of the 34th PMOS transistor M34 low, connecting the segmented four-stage output terminal to the 19th resistor R19, increasing the gate capacitor discharge current and achieving fast turn-off.

[0216] Overcurrent protection principle: When power transistor M25 operates in the linear region, sampling transistor M24 and power transistor M25 are mirror images with a 1:N area ratio, then the sampling current I... S satisfy:

[0217]

[0218] A sampling resistor is connected in series in the current path of the current sensing tube to directly acquire and convert the operating current signal flowing through the power device. This current information is then converted into a voltage signal that can be recognized by subsequent comparison and control circuits. The sampling voltage generated across the thirteenth resistor R13 is V. S :

[0219]

[0220] When the sampling voltage exceeds the threshold voltage of the 23rd NMOS transistor M23, the 23rd NMOS transistor M23 turns on and pulls down the gate voltage of the sampling transistor M24 and the power transistor M25 to achieve overcurrent turn-off and prevent the power transistor M25 from burning out due to overcurrent.

[0221] The final formula for the overcurrent protection detection threshold is:

[0222] Example 3:

[0223] Overall structure as Figure 5 As shown, this embodiment is based on embodiment 2, but replaces the sixth resistor R6 and the seventh resistor R7 with the first power dissipation diode D1 and the second power dissipation diode D2; the drains of the first power dissipation diode D1 and the second power dissipation diode D2 are connected to the input voltage VIN, and after the gate and source are shorted, they are connected to the drains of the eighth NMOS transistor M8 and the ninth NMOS transistor M9, respectively.

[0224] Replace the ninth resistor R9 and the twelfth resistor R12 with the third power dissipation diode D3 and the fourth power dissipation diode D4; connect the drains of the third power dissipation diode D3 and the fourth power dissipation diode D4 to VIN, and after shorting the gate and source, connect them to the drains of the twelfth NMOS transistor M12 and the thirteenth NMOS transistor M13, respectively.

[0225] Replace the seventeenth resistor R17 and the eighteenth resistor R18 with the fifth power dissipation diode D5 and the sixth power dissipation diode D6; connect the drains of the fifth power dissipation diode D5 and the sixth power dissipation diode D6 to VIN, and after shorting the gate and source, connect them to the drains of the thirty-sixth NMOS transistor M36 and the thirty-seventh NMOS transistor M37, respectively.

[0226] Although the current-limiting resistor can be operated as a constant current source, it can precisely limit the operating current of the eighth NMOS transistor M8, the ninth NMOS transistor M9, the twelfth NMOS transistor M12, the thirteenth NMOS transistor M13, the thirty-sixth NMOS transistor M36, and the thirty-seventh NMOS transistor M37, avoiding the extra power consumption caused by high current and significantly improving the circuit's energy efficiency. At the same time, large-value current-limiting resistors occupy a large layout area; replacing them with the current-limiting resistor can effectively reduce the overall chip area.

[0227] Example 4:

[0228] Overall structure as Figure 6 As shown, this embodiment is based on embodiment 3, but the structure connected to the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the fourth PMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh PMOS transistor M7, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the first capacitor C1 is replaced with the following structure:

[0229] This includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a first PNP transistor, a second PNP transistor, a first operational amplifier I1, and a first inverter A1. The sources of the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are connected to the input voltage VIN, and their gates are connected to the output of the first operational amplifier and the drain of the fourth NMOS transistor M4. The source of the fourth NMOS transistor M4 is grounded to GND. The drain of the first PMOS transistor M1 is connected to the non-inverting input of the first operational amplifier I1, the emitter of the first PNP transistor Q1, and grounded to GND through the first resistor R1. The drain of the second PMOS transistor M2 is connected to the inverting input of the first operational amplifier and grounded to GND through the third resistor R3. The drain of the third PMOS transistor M3 is connected to the first connection node, and the first connection node is grounded to GND through the first capacitor C1; the first connection node is grounded to GND through the fourth resistor R4 and the fifth resistor R5 connected in series; the base and collector of the first PNP transistor Q1 and the second PNP transistor Q2 are both grounded to GND, and the emitter of the second PNP transistor Q2 is connected to the inverting input terminal of the first operational amplifier I1 through the second resistor R2; the input terminal of the first inverter A1 is connected to the drain of the third PMOS transistor M3, and the output terminal of the first inverter A1 is connected to the gate of the fourth NMOS transistor M4.

[0230] The first inverter A1 and the fourth NMOS transistor M4 constitute the startup circuit.

[0231] When the input VIN voltage increases, the input voltage of the first inverter A1 is zero, and the high-level output turns on the fourth NMOS transistor M4, causing the gate of the first PMOS transistor M1 to be pulled down. This turns on the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3. The first PMOS transistor M1 and the second PMOS transistor M2 form a matched PMOS current mirror. The first operational amplifier I1 achieves virtual short characteristics through negative feedback, forcing the emitter voltages of the first PNP transistor Q1 and the second PNP transistor Q2 to be equal.

[0232]

[0233] Among them, the first PNP tube Q1 and the second PNP tube Q2 are a pair of tubes with an emission area ratio of 1:K, V T The thermal equivalent voltage combined with the second resistor R2 generates a positive temperature coefficient current I at PTAT. R2 :

[0234]

[0235] The voltage V generated across the third resistor R3 is the same as the emitter-junction voltage V of the first PNP transistor Q1. BEQ1The relevant negative temperature coefficient current I R3 :

[0236]

[0237] By canceling out the positive temperature coefficient current and the negative temperature coefficient current, and after being mirrored by the third PMOS transistor M3, a zero temperature coefficient reference current I is output. REF :

[0238]

[0239] The reference voltage V can be obtained at the first connection node. REF :

[0240]

[0241] According to the above formula, R4 and R5 are low temperature coefficient polycrystalline resistors. By adjusting the resistance values ​​of R2, R3, R4 and R5, a high-stability reference voltage across the entire temperature range can be obtained.

[0242] When the first connection node receives the reference voltage, the input voltage of the first inverter A1 can be considered as high level, turning off the fourth NMOS transistor M4. This startup circuit does not affect the normal operation of the overall circuit.

[0243] Example 5:

[0244] Overall structure as Figure 7 As shown, this embodiment is based on Embodiment 4. The first power dissipation transistor D1 and the second power dissipation transistor D2 are replaced with the thirty-eighth PMOS transistor M38 and the thirty-ninth PMOS transistor M39. The source of the thirty-eighth PMOS transistor M38 and the thirty-ninth PMOS transistor M39 is connected to the input voltage VIN, and the gate is connected to the gate of the third PMOS transistor M3. The drain of the thirty-eighth PMOS transistor M38 is connected to the drain of the twelfth NMOS transistor M12, and the drain of the thirty-ninth PMOS transistor M39 is connected to the drain of the thirteenth NMOS transistor M13. The third power dissipation transistor D3 and the fourth power dissipation transistor D4 are replaced with the fortieth PMOS transistor M40 and the forty-first PMOS transistor M41. The source of the fortieth PMOS transistor M40 and the forty-first PMOS transistor M41 is connected to the input voltage VIN, and the gate is connected to the gate of the third PMOS transistor M3. The drain of the fortieth PMOS transistor M40 is connected to the drain of the eighth NMOS transistor M8, and the drain of the forty-first PMOS transistor is connected to the drain of the ninth NMOS transistor M9.

[0245] The third PMOS transistor M3, the thirty-eighth PMOS transistor, the thirty-ninth PMOS transistor, the fortieth PMOS transistor M40, and the forty-first PMOS transistor M41 together form a high-precision current mirror, which accurately mirrors the zero-temperature coefficient reference current to each control branch, making the current of key nodes such as the eighth NMOS transistor M8 and the ninth NMOS transistor M9 constant and with low temperature sensitivity, significantly improving the detection and control accuracy of the circuit.

[0246] Example 6:

[0247] Overall structure as Figure 8 As shown, this embodiment is based on embodiment 5 and also includes the forty-second NMOS transistor M42; the source of the forty-second NMOS transistor M42 is connected to the drain of the thirty-fourth PMOS transistor M34, the drain is connected to the source of the thirty-fourth PMOS transistor M34, and the gate is connected to the drain of the thirty-sixth NMOS transistor M36.

[0248] The 42nd NMOS transistor and the 34th PMOS transistor M34 complement each other to form a transmission gate structure. Compared with a single MOS transistor, it has a more stable on-resistance, better bidirectional current transmission symmetry, no current attenuation, and smaller turn-off leakage current in the entire voltage range. It is more suitable for the transmission and switching of precision current in the gate voltage control circuit, and improves the consistency and reliability of drive and protection actions.

[0249] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A process for a silicon carbide MOS integrated circuit, characterized in that, Includes the following steps: Step 1: Select N-type 4H-SiC as the substrate, with a substrate doping degree of 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 ; Step 2: Epitaxially grow an N-type buffer layer on an N-type substrate with a doping concentration of 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 The thickness ranges from 0.3 μm to 1.5 μm; Step 3: Epitaxially grow an N-type epitaxial layer of a certain thickness on the N-type buffer layer, with a doping concentration of 1×10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3 ; Step 4: Deposit to form a thick field oxygen isolation layer with a thickness of 0.5 μm to 2 μm, and remove the oxide layer on the surface of the active region; Step 5: Ion implant N-type impurities into the N-type epitaxial layer to adjust the JFET region doping of the VDMOS device and to fabricate the N-well region of the PMOS device, so as to better adjust the electrical performance of the VDMOS and PMOS devices. The implantation is performed 2 to 5 times, and the total implantation dose is 1×10⁻⁶. 12 cm -3 Up to 1×10 13 cm -3 ; Step 6: Ion implant P-type impurities into the N-type epitaxial layer to form the P-well regions of the VDMOS device, NMOS device, trap resistor, capacitor, and diode. The implantation is performed 2 to 5 times, with a total implantation dose of 5 × 10⁻⁶. 13 cm -3 Up to 2×10 14 cm -3 ; Step 7: Ion implant N-type impurities into the N-type epitaxial layer and P-well region to form the N+ regions of VDMOS devices, NMOS devices, PMOS devices, well resistors, capacitors, and diodes. The implantation is performed 2 to 5 times, with a total implantation dose of 1 × 10⁻⁶. 15 cm -3 Up to 3×10 15 cm -3 ; Step 8: Ion implant P-type impurities in the N-well and P-well regions to form the P+ regions of VDMOS devices, NMOS devices, PMOS devices, well resistors, capacitors, and diodes. The implantation is performed 2 to 5 times, with a total implantation dose of 5 × 10⁻⁶. 13 cm -3 Up to 1×10 15 cm -3 ; Step 9: After completing all ion implantation steps, remove the adhesive and clean the device surface. Then, a dense carbon film is formed to prevent SiC atoms from sublimating and causing surface roughness. Step 10: Perform high-temperature annealing at 1600-1900℃ in Ar or vacuum atmosphere to activate the implanted impurities and repair lattice damage, then remove the carbon film and wet clean to remove residues. Step 11: Generate a sacrificial oxide layer and remove it by wet process to remove the surface damage layer caused by implantation and annealing steps. A gate oxide layer with a thickness of 30 nm to 60 nm is grown on a clean SiC surface by thermal oxidation process and annealed in a nitrogen or inert gas atmosphere to stabilize the charge of the gate oxide layer. Step 12: Deposit a polycrystalline silicon thin film with a thickness of 300 nm to 1000 nm, and heavily dope the polycrystalline silicon by ion implantation or in-situ doping; Step 13: Dry etching of polysilicon to define gate patterns for VDMOS devices, PMOS devices, NMOS devices, and capacitor gates, and to form poly resistors on thick field oxide, which can also assist in the connection of device electrodes by a single layer of metal. Step 14: Deposit SiO2 to form a dielectric layer and reflow to achieve planarization; Step 15: Perform contact hole etching to complete the fabrication of ohmic contacts. Then, sputter metal to form the source metal and body region VP electrode metal of VDMOS device, drain metal, source metal and body region VP electrode metal of NMOS device, drain metal, source metal and body region VN electrode metal of PMOS device, contact electrode metal and body region VP electrode metal of well resistor, drain metal, source metal and body region VP electrode metal of capacitor device, and cathode metal and anode metal of diode. Step 16: Perform poly contact hole etching to complete the ohmic contact fabrication at the contact hole. Then, sputter metal to form the gate metal of VDMOS device, NMOS device, PMOS device, capacitor device, and contact electrode metal of poly resistor. At the same time, steps 15 and 16 also realize the bridging and local interconnection of device electrodes with the assistance of poly layer through single layer metal. Step 17: Backside thinning and metallization to form the drain metal of the VDMOS device; The above process steps can successfully fabricate one or more of silicon carbide VDMOS, NMOS, PMOS, well resistors, poly resistors, capacitors, and diodes on the same N-type 4H-SiC substrate and N-type epitaxial layer. Compared with the silicon carbide VDMOS process, no additional mask is required. The interconnection of each device can be completed by using a poly layer in combination with a single metal layer. The poly layer can also serve as an auxiliary interconnect jumper, simplifying device wiring. High-voltage devices and low-voltage devices form a PN junction isolation structure in the N-type epitaxial layer through the P-well injection and P+ injection processes described in steps 6 and 8, thereby achieving electrical isolation between devices.

2. The integrated silicon carbide MOS integrated circuit process according to claim 1, characterized in that... The process also includes, after step 8, introducing an N-type impurity implantation process in the channel region below the gate oxide layer in the high-voltage VDMOS device region and the low-voltage NMOS device region to form an N-type electron accumulation layer as a conductive channel, thereby completing the fabrication of the high-voltage depletion-type VDMOS device and the low-voltage depletion-type NMOS device, and then proceeding to step 9.

3. The integrated silicon carbide MOS integrated circuit process according to claim 1, characterized in that... The method also includes, after step 8, introducing additional N-type or P-type impurities into the channel region below the gate oxide layer in the low-voltage NMOS device region and the low-voltage PMOS device region to adjust the threshold voltage of the two devices, before proceeding to step 9.

4. The integrated silicon carbide MOS integrated circuit process according to claim 1, characterized in that... The process also includes removing the gate oxide layers of the low-voltage NMOS device region and the low-voltage PMOS device region by photolithography and wet etching after the gate oxide layer is grown in step 11, and then leaving the photoresist in the exposed area for a second thermal oxidation to form a thin gate oxide layer of 10nm to 20nm before proceeding to step 12.

5. A silicon carbide MOS integrated circuit structure, fabricated using the process described in any one of claims 1 to 4, characterized in that, include: PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, NMOS transistor M11, NMOS transistor M12, NMOS transistor M13, PMOS transistor M14, NMOS transistor M15, PMOS transistor M16, NMOS transistor M17, NMOS transistor M18, NMOS transistor M19, PMOS transistor M20, NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24, NMOS transistor M25, PMOS transistor M26, NMOS transistor M27 Transistor M27, PMOS transistor M28 (28th), NMOS transistor M29 (29th), PMOS transistor M30 (30th), NMOS transistor M31 (31st), PMOS transistor M32 (32nd), NMOS transistor M33 (33rd), PMOS transistor M34 (34th), NMOS transistor M35 (35th), NMOS transistor M36 (36th), NMOS transistor M37 (37th), Resistor R1 (1st), Resistor R2 (2nd), Resistor R3 (3rd), Resistor R4 (4th), Resistor R5 (5th), Resistor R6 (6th), Resistor R7 (7th), Resistor R8 (8th), Resistor R9 (9th), Resistor R10 (10th), Resistor R11 (11th), Resistor R12 (12th), Resistor R13 (13th), Resistor R14 (14th), Resistor R15 (15th), Resistor R16 (16th), Resistor R17 (17th), Resistor R18 (18th), Resistor R19 (19th), Capacitor C1 (1st), Capacitor C2 (2nd). The sources of the first PMOS transistor M1, the third PMOS transistor M3, the fourth PMOS transistor M4, and the seventh PMOS transistor M7 are all connected to the input voltage VIN, and their gates are all connected to the drain of the fourth PMOS transistor M4. The drain of the first PMOS transistor M1 is connected to the gate of the second PMOS transistor M2. The source of the second PMOS transistor M2 is grounded to GND through the first resistor R1, and its drain is connected to the gate of the fifth NMOS transistor M5. The drain of the third PMOS transistor M3 is connected to the drain and gate of the fifth NMOS transistor M5. The drain of the fourth PMOS transistor M4 is connected to the drain of the sixth NMOS transistor M6. The source of the fifth NMOS transistor is grounded to GND, and the source of the sixth NMOS transistor is grounded to GND through the second resistor R2. The drain of the seventh PMOS transistor is connected to the first connection node through the third resistor R3. The first connection node is grounded to GND through the first capacitor C1, the fourth resistor R4, and the fifth resistor R5. The gate of the eighth NMOS transistor M8 is connected to the first connection node, and its drain is connected to the input voltage VIN via the sixth resistor R6; the gate of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8, its source is grounded to GND, and its drain is connected to the input voltage VIN via the seventh resistor R7; the source of the tenth NMOS transistor M10 is grounded to GND, and its drain is connected to the connection node of the fourth resistor R4 and the fifth resistor R5; the gate of the twenty-second NMOS transistor M22 is connected to the drain of the ninth NMOS transistor M9, its source is grounded to GND, and its drain is connected to the gate of the twenty-fifth NMOS transistor M25; The upper ends of the eighth resistor R8, the ninth resistor R9, and the twelfth resistor R12 are all connected to the input voltage VIN. The lower end of the eighth resistor R8 is connected to the second connection node, which is grounded to GND via the second capacitor C2, and also grounded to GND via the tenth resistor R10 and the eleventh resistor R11 in series. The series connection node of the tenth resistor R10 and the eleventh resistor R11 is connected to the drain of the eleventh NMOS transistor M11. The source of the eleventh NMOS transistor M11 is grounded to GND, and its gate is connected to the drain of the thirteenth NMOS transistor M13. The gate of the twelfth NMOS transistor M12 is connected to the second connection node, and its drain is connected to the input voltage VIN via the ninth resistor R9. The gate of the thirteenth NMOS transistor M13 is connected to the drain of the twelfth NMOS transistor M12, its source is grounded to GND, and its drain is connected to the input voltage VIN via the twelfth resistor R12. The sources of the fourteenth PMOS transistor M14, the sixteenth PMOS transistor M16, the eighteenth PMOS transistor M18, and the twentieth PMOS transistor M20 are connected to the input voltage VIN; the sources of the fifteenth NMOS transistor M15, the seventeenth NMOS transistor M17, the nineteenth NMOS transistor M19, and the twenty-first NMOS transistor M21 are connected to ground GND. Drive stage 1: The drain of the fourteenth PMOS transistor M14 and the drain of the fifteenth NMOS transistor M15 are connected together to form the output terminal of the drive stage 1, and their gates are connected together as the drive input terminal. Drive the second stage: The drain of the sixteenth PMOS transistor M16 and the drain of the seventeenth NMOS transistor M17 are connected together to form the output terminal of the second stage driver. The gates of the two transistors are connected together to drive the output terminal of the first stage driver. Drive stage 3: The drain of the eighteenth PMOS transistor M18 and the drain of the nineteenth NMOS transistor M19 are connected together to form the output terminal of drive stage 3, and their gates are connected together to drive stage 2 output terminal; Drive stage four: The drain of the twentieth PMOS transistor M20 and the drain of the twenty-first NMOS transistor M21 are connected together to form the output terminal of drive stage four; The 24th NMOS transistor M24 is a current sampling transistor M24, and the 25th NMOS transistor M25 is a power transistor M25; the drains of both are connected to the output node OUT; the source of the 24th NMOS transistor M24 is grounded to GND through the 13th resistor R13; the gate of the 23rd NMOS transistor M23 is connected to the source of the 24th NMOS transistor M24, the drain is connected to the gate of the 24th NMOS transistor M24, and the source is grounded to GND; the gate of the 25th NMOS transistor M25 is connected to the gate of the 24th NMOS transistor M24, and the source is grounded to GND; The sources of the 26th PMOS transistor M26, the 28th PMOS transistor M28, the 30th PMOS transistor M30, and the 32nd PMOS transistor M32 are connected to the input voltage VIN; the sources of the 27th NMOS transistor M27, the 29th NMOS transistor M29, the 31st NMOS transistor M31, and the 33rd NMOS transistor M33 are connected to ground GND. Segmented Stage 1: The drain of the 26th PMOS transistor M26 and the drain of the 27th NMOS transistor M27 are connected together to form the segmented stage 1 output terminal. The gates of both are connected to the second connection node as the segmented drive stage 1 input terminal. Segmented two-stage: The drain of the twenty-eighth PMOS transistor M28 and the drain of the twenty-ninth NMOS transistor M29 are connected together to form the segmented two-stage output terminal, and their gates are connected together to the segmented first-stage output terminal; Three-stage segmentation: The drain of the 30th PMOS transistor M30 and the drain of the 31st NMOS transistor M31 are connected together to form a three-stage segmented output terminal, and their gates are connected together to form a two-stage segmented output terminal. Segmented four stages: The drain of the thirty-second PMOS transistor M32 and the drain of the thirty-third NMOS transistor M33 are connected together to form a segmented four-stage output terminal; The source of the thirty-fourth PMOS transistor M34 is connected to the four-stage drive output terminal, the drain is connected to the four-stage segmented output terminal, and the gate is connected to the drain of the thirty-seventh NMOS transistor M37. The upper ends of the fourteenth resistor R14, the seventeenth resistor R17, and the eighteenth resistor R18 are connected to the output terminals of the four-stage drive, and are connected to the gate of the twenty-fifth NMOS transistor M25 via the nineteenth resistor R19; the lower end of the fourteenth resistor R14 is connected to the third connection node, and the third connection node is connected to ground GND via the fifteenth resistor R15 and the sixteenth resistor R16 in series; the series node of the fifteenth resistor R15 and the sixteenth resistor R16 is connected to the drain of the thirty-fifth NMOS transistor M35, the source of the thirty-fifth NMOS transistor M35 is grounded to GND, and the gate is connected to the drain of the thirty-sixth NMOS transistor M36; The gate of the thirty-sixth NMOS transistor M36 is connected to the third connection node, and the drain is connected to the gate of the twenty-fifth NMOS transistor M25 via the seventeenth resistor R17; the gate of the thirty-seventh NMOS transistor M37 is connected to the drain of the thirty-sixth NMOS transistor M36, the source is grounded to GND, and the drain is connected to the nineteenth resistor R19.

6. The silicon carbide MOS integrated circuit structure according to claim 5, characterized in that, The sixth resistor R6 and the seventh resistor R7 are replaced by the first power dissipation diode D1 and the second power dissipation diode D2. The drain of the first power dissipation diode D1 and the drain of the second power dissipation diode D2 are connected to the input voltage VIN. The gate and source of the first power dissipation diode D1 are shorted and connected to the drain of the eighth NMOS transistor M8. The gate and source of the second power dissipation diode D2 are shorted and connected to the drain of the ninth NMOS transistor M9. The ninth resistor R9 and the twelfth resistor R12 are replaced by the third power dissipation transistor D3 and the fourth power dissipation transistor D4. The drain of the third power dissipation transistor D3 and the drain of the fourth power dissipation transistor D4 are connected to the input voltage VIN. The gate and source of the third power dissipation transistor D3 are shorted and connected to the drain of the twelfth NMOS transistor M12. The gate and source of the fourth power dissipation transistor D4 are shorted and connected to the drain of the thirteenth NMOS transistor M13. The seventeenth resistor R17 and the eighteenth resistor R18 are replaced by the fifth power dissipation diode D5 and the sixth power dissipation diode D6. The drain of the fifth power dissipation diode D5 and the drain of the sixth power dissipation diode D6 are connected to the input voltage VIN. The gate and source of the fifth power dissipation diode D5 are shorted and connected to the drain of the thirty-sixth NMOS transistor M36. The gate and source of the sixth power dissipation diode D6 are shorted and connected to the drain of the thirty-seventh NMOS transistor M37.

7. The silicon carbide MOS integrated circuit structure according to claim 6, characterized in that, The structure connected to the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the fourth PMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh PMOS transistor M7, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the first capacitor C1 is replaced with the following structure: This includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth NMOS transistor M4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a first PNP transistor Q1, a second PNP transistor Q2, a first operational amplifier I1, and a first inverter A1. The sources of the first PMOS transistors M1, M2, and M3 are connected to the input voltage VIN, and their gates are connected to the output of the first operational amplifier and the drain of the fourth NMOS transistor M4. The source of the fourth NMOS transistor M4 is grounded to GND. The drain of the first PMOS transistor M1 is connected to the positive input of the first operational amplifier I1 and the emitter of the first PNP transistor Q1. The first PMOS transistor M2 is connected to the inverting input of the first operational amplifier I1 via the first resistor R1 and is connected to the ground GND via the third resistor R3. The drain of the third PMOS transistor M3 is connected to the first connection node, which is connected to the ground GND via the first capacitor C1. The first connection node is connected to the ground GND via the fourth resistor R4 and the fifth resistor R5 in series. The base and collector of the first PNP transistor Q1 and the second PNP transistor Q2 are both connected to the ground GND. The emitter of the second PNP transistor Q2 is connected to the inverting input of the first operational amplifier I1 via the second resistor R2. The input of the first inverter I1 is connected to the drain of the third PMOS transistor M3, and the output of the first inverter I1 is connected to the gate of the fourth NMOS transistor M4.

8. The silicon carbide MOS integrated circuit structure according to claim 7, characterized in that, The first power dissipation transistor D1 and the second power dissipation transistor D2 are replaced with the thirty-eighth PMOS transistor M38 and the thirty-ninth PMOS transistor M39. The source of the thirty-eighth PMOS transistor M38 and the thirty-ninth PMOS transistor M39 is connected to the input voltage VIN, and the gate is connected to the gate of the third PMOS transistor M3. The drain of the thirty-eighth PMOS transistor M38 is connected to the drain of the twelfth NMOS transistor M12, and the drain of the thirty-ninth PMOS transistor is connected to the drain of the thirteenth NMOS transistor M13. The third power dissipation transistor D3 and the fourth power dissipation transistor D4 are replaced by the fortieth PMOS transistor M40 and the forty-first PMOS transistor M41. The source of the fortieth PMOS transistor M40 and the forty-first PMOS transistor M41 is connected to the input voltage VIN, and the gate is connected to the gate of the third PMOS transistor M3. The drain of the fortieth PMOS transistor M40 is connected to the drain of the eighth NMOS transistor M8, and the drain of the forty-first PMOS transistor M41 is connected to the drain of the ninth NMOS transistor M9.

9. The silicon carbide MOS integrated circuit structure according to claim 8, characterized in that, It also includes the forty-second NMOS transistor M42; the source of the forty-second NMOS transistor M42 is connected to the drain of the thirty-fourth PMOS transistor M34, the drain is connected to the source of the thirty-fourth PMOS transistor M34, and the gate is connected to the drain of the thirty-sixth NMOS transistor M36.

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