eMMC Packaging Structure and Fabrication Method

Abstract

This invention discloses an eMMC packaging structure and its fabrication method. The eMMC packaging structure includes: a substrate; at least one chip disposed on the substrate; and a multilayer stress buffer structure disposed between the bottom surface of the chip and its mounting surface. The multilayer stress buffer structure exhibits an increasing trend in its coefficient of thermal expansion and a decreasing trend in its elastic modulus along the direction from the chip to the substrate. At least one layer of the multilayer stress buffer structure contains a stress relief unit to change the transmission path of thermal stress within the multilayer stress buffer structure. At least one interlayer interface of the multilayer stress buffer structure is a blocking interface to block the crack propagation path along the interface. This forms a three-tiered synergistic stress buffer system of "thermal expansion coefficient gradient and elastic modulus gradient transition - stress relief - crack blocking." The synergistic effect of these three layers significantly improves the reliability of the interface between the chip and its mounting surface.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging technology, specifically to an eMMC packaging structure and its fabrication method. Background Technology

[0002] eMMC (Embedded MultiMedia Card) is an embedded memory device that integrates a NAND flash memory array, a controller chip, and interface logic into a single BGA (Ball Grid Array) package. It is widely used in smartphones, industrial control systems, automotive electronics, and IoT devices. Industrial-grade eMMC typically operates in a temperature range of -40°C to 85°C, while automotive-grade products require even more stringent conditions, ranging from -40°C to 105°C.

[0003] The eMMC package structure contains various heterogeneous materials, including a silicon chip, a BT resin substrate, and an epoxy molding compound, with significantly different coefficients of thermal expansion (COPs): the COP of the silicon chip is approximately 2.5-2.8 ppm / ℃, the COP of the BT resin substrate is approximately 14-17 ppm / ℃, while the COP of traditional epoxy molding compounds is typically higher than 20 ppm / ℃. When the package structure undergoes wide temperature cycling, this COP mismatch will generate periodic thermomechanical stress at the interface between the chip and the substrate. When the stress exceeds the interfacial bonding strength, microcracks first form at the interface edge and propagate along the interface towards the center, eventually leading to delamination or peeling between the chip and the substrate, causing device failure. Summary of the Invention

[0004] The purpose of this invention is to provide an eMMC packaging structure and its preparation method to solve the above-mentioned problems existing in the prior art.

[0005] The present invention solves the above-mentioned technical problems through the following technical solution: An eMMC package structure, comprising: substrate; At least one chip is disposed on the substrate; A multi-layer stress buffer structure is disposed between the bottom surface of the chip and its mounting surface; The coefficient of thermal expansion of the multilayer stress buffer structure along the direction from the chip to the substrate shows an increasing trend, while the elastic modulus shows a decreasing trend. At least one layer of the multi-layer stress buffer structure is provided with a stress relief unit to change the transmission path of thermal stress in the multi-layer stress buffer structure so as to transfer the stress concentration area to a non-critical area. The stress relief unit includes a plurality of micropores, the distribution density of the plurality of micropores gradually decreases in the direction away from the corner, and / or the stress relief unit is oriented and arranged in a direction away from the corner of the bottom surface of the chip. At least one interlayer interface of the multilayer stress buffer structure is a blocking interface, used to block the crack propagation path along the interface.

[0006] Preferably, the stress relief units are arranged oriented away from the corner of the bottom surface of the chip.

[0007] Preferably, the blocking interface is a sawtooth interface or a continuous corrugated interface.

[0008] Preferably, the peak-valley height difference at the blocking interface is 1μm-5μm.

[0009] Preferably, the multi-layer stress buffer structure includes: The first buffer layer is adjacent to the chip; The second buffer layer is adjacent to the first buffer layer; The third buffer layer is adjacent to the second buffer layer and the substrate; Wherein, the coefficient of thermal expansion of the first buffer layer is smaller than that of the second buffer layer, and the coefficient of thermal expansion of the second buffer layer is smaller than that of the third buffer layer; The elastic modulus of the first buffer layer is greater than that of the second buffer layer, and the elastic modulus of the second buffer layer is greater than that of the third buffer layer.

[0010] Preferably, the third buffer layer comprises a temperature-responsive polymer such that the elastic modulus of the layer in the low-temperature range of -40°C to 0°C is lower than its elastic modulus in the high-temperature range of 85°C to 105°C, and its elongation at break in the low-temperature range is greater than its elongation at break in the high-temperature range.

[0011] Preferably, the stress relief unit is disposed within the second buffer layer; The blocking interface is formed between the first buffer layer and the second buffer layer and / or between the second buffer layer and the third buffer layer.

[0012] Preferably, the chip includes a plurality of chips stacked sequentially along a direction perpendicular to the substrate, forming a bottom chip, an intermediate chip, and a top chip; The bottom layer chip is mounted on the substrate through its corresponding multi-layer stress buffer structure, the middle layer chip is mounted on the bottom layer chip through its corresponding multi-layer stress buffer structure, and the top layer chip is mounted on the middle layer chip through its corresponding multi-layer stress buffer structure. In the multi-layer stress buffer structure corresponding to the underlying chip, the thickness of the third buffer layer accounts for 40% to 50% of the total thickness of the multi-layer stress buffer structure; In the multi-layer stress buffer structure corresponding to the top-layer chip, the thickness of the first buffer layer accounts for 40% to 50% of the total thickness of the multi-layer stress buffer structure; In the multi-layer stress buffer structure corresponding to the intermediate layer chip, the thicknesses of the first buffer layer, the second buffer layer, and the third buffer layer are uniformly distributed.

[0013] A method for fabricating an eMMC package structure, used to manufacture the eMMC package structure as described above, includes: Based on the chip layer location, chip area, chip thickness, and preset heat source distribution data, determine the thickness ratio and material parameters of each layer of the multi-layer stress buffer structure; Multiple buffer layers with gradients in thermal expansion coefficients and elastic moduli are sequentially formed on the bottom surface of the chip and / or the surface of the substrate through layer coating, printing, spraying, lamination or dispensing processes. During the formation of at least one buffer layer, the stress relief unit is formed using a patterning process. The blocking interface is formed between adjacent buffer layers by embossing, laser processing, roughening treatment, or mold forming processes. The chip is mounted on the substrate and cured to form a package structure.

[0014] Compared with existing technologies, this invention has the following beneficial effects: it forms a synergistic stress buffering system with three levels: "gradient transition of thermal expansion coefficient and elastic modulus - stress release - crack prevention". Specifically, the gradient multi-layer stress buffering structure with increasing thermal expansion coefficient and decreasing elastic modulus achieves a gradual transition of thermal expansion coefficient between the chip and the mounting surface, reducing the overall stress level at the interface. The stress release unit guides unavoidable residual stress to non-critical areas for release, reducing stress concentration at the corners of the chip's bottom surface. Even if microcracks occur at the blocking interface, they can be effectively blocked, preventing cracks from penetrating the entire multi-layer stress buffering structure. The synergistic effect of these three levels of protection significantly improves the reliability of the interface between the chip and its mounting surface. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the eMMC packaging structure of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the stress relief unit structure of the eMMC packaging structure in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the eMMC packaging structure of Embodiment 2 of the present invention. Detailed Implementation

[0016] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments.

[0017] Example 1 like Figure 1 and Figure 2 As shown, this embodiment provides an eMMC packaging structure, including: a substrate 100, at least one chip 200, and a multilayer stress buffer structure 300. At least one chip 200 is disposed on the substrate 100. The multilayer stress buffer structure 300 is disposed between the bottom surface of the chip 200 and its mounting surface. The coefficient of thermal expansion of the multilayer stress buffer structure 300 increases and its elastic modulus decreases along the direction from the chip 200 to the substrate 100. At least one layer of the multilayer stress buffer structure 300 has a stress relief unit 350 inside, used to change the transmission path of thermal stress within the multilayer stress buffer structure 300, so as to transfer stress concentration areas to non-critical areas. At least one interlayer interface of the multilayer stress buffer structure 300 is a blocking interface 340, used to block the crack propagation path along the interface.

[0018] Specifically, in this application, stress concentration areas refer to the locations within the multilayer stress buffer structure 300 corresponding to the corners of the bottom surface of the chip 200 and the areas below the edges of the bottom surface of the chip 200. These locations, due to the CTE (coefficient of thermal expansion) mismatch between the chip 200 and the mounting surface, generate thermal stress peaks during temperature cycling, making them high-risk areas for crack initiation. Non-critical areas refer to the areas within the multilayer stress buffer structure 300 below the center area of ​​the bottom surface of the chip 200 or below the peripheral area of ​​the edge. Even if these areas experience some stress, they do not directly threaten the integrity of the connection between the chip 200 and the multilayer stress buffer structure 300. The mounting surface refers to the surface on which the chip 200 is mounted in the packaging structure. For a chip 200 directly mounted on the substrate 100, its mounting surface is the upper surface of the substrate 100. For a chip 200 stacked on a lower chip 200, its mounting surface is the upper surface of that lower chip 200 or the surface of the buffer layer above that lower chip 200.

[0019] This application establishes a three-tiered synergistic stress buffering system: a gradient transition of thermal expansion coefficient and elastic modulus, stress release, and crack prevention. Specifically, the gradient multi-layer stress buffering structure 300, with increasing thermal expansion coefficient and decreasing elastic modulus, achieves a gradual transition of thermal expansion coefficient between the chip 200 and the mounting surface, reducing the overall stress level at the interface. The stress release unit 350 guides unavoidable residual stress to non-critical areas for release, reducing stress concentration at the corners of the bottom surface of the chip 200. The blocking interface 340 effectively prevents microcracks from forming, thus preventing cracks from penetrating the entire multi-layer stress buffering structure 300. The synergistic effect of these three layers of protection significantly improves the interface reliability between the chip 200 and its mounting surface.

[0020] like Figure 2As shown, in some embodiments, the stress relief unit 350 includes multiple micropores, the distribution density of which gradually decreases away from the corner. The micropores create a stiffness field with a spatial gradient by altering the local effective elastic modulus of the multilayer stress buffer structure 300. The high-density micropore region (directly below the corner) has low effective stiffness and bears less load; the low-density micropore region (away from the corner) has high effective stiffness and bears more load. This stiffness gradient naturally "squeezes" the stress peak from the corner to the surrounding area.

[0021] like Figure 2 As shown, Figure 2 The dashed box represents the orthographic projection of chip 200 into the multilayer stress buffer structure 300. In some embodiments, the stress relief units 350 are oriented with the bottom corner of chip 200 as the starting point, moving away from that corner. This arrangement can guide and disperse the thermal stress concentrated at the bottom corner of chip 200 away from the corner, allowing the stress to gradually attenuate during transmission and preventing the formation of continuous stress peaks at the bottom corner of chip 200. It should be noted that... Figure 2 This is just one example of a scheme; the actual distribution is not limited to this, and for example, the actual number of micropores can be much greater.

[0022] In some embodiments, the stress relief unit 350 includes a plurality of micropores, the diameter of which gradually decreases away from the corners. The corners of the bottom surface of the chip 200 are the areas with the highest stress peaks. Providing larger micropores at these locations can more significantly disrupt the horizontal continuity of the multi-layer stress buffer structure 300, forming a high-strength "stress-blocking wall." When the stress is initially intervened, the energy level of the residual stress has decreased as it propagates away from the corners. Using smaller micropores at this point is sufficient to continue guiding and dispersing this attenuated stress while reducing unnecessary material removal and avoiding the creation of new weak points in non-critical areas due to excessive structural hollowing.

[0023] In some embodiments, the blocking interface 340 is a sawtooth interface or a corrugated interface.

[0024] Specifically, the peak-valley height difference at the blocking interface 340 is 1μm-5μm, and the period between adjacent tooth peaks or wave peaks is 5μm-20μm. This micron-level regular undulating structure can be precisely formed through embossing, laser processing, or mold forming processes, resulting in good process consistency. The micron-level undulating structure alters the stress field distribution at the crack tip, causing a deflection of the crack propagation direction and extending the crack propagation path.

[0025] In some embodiments, the multilayer stress buffer structure 300 includes a first buffer layer 310, a second buffer layer 320, and a third buffer layer 330. The first buffer layer 310 is adjacent to the chip 200. The second buffer layer 320 is adjacent to the first buffer layer 310. The third buffer layer 330 is adjacent to the second buffer layer 320 and the substrate 100. The coefficient of thermal expansion of the first buffer layer 310 is less than that of the second buffer layer 320, and the coefficient of thermal expansion of the second buffer layer 320 is less than that of the third buffer layer 330. The elastic modulus of the first buffer layer 310 is greater than that of the second buffer layer 320, and the elastic modulus of the second buffer layer 320 is greater than that of the third buffer layer 330.

[0026] Specifically, the coefficient of thermal expansion of the first buffer layer 310 is closest to that of the chip 200, while also possessing a high elastic modulus, ensuring a strong interface bond between it and the bottom surface of the chip 200. The coefficient of thermal expansion of the third buffer layer 330 is closest to that of the substrate 100, while also possessing a low elastic modulus and high toughness, enabling it to fully absorb thermal stress from the substrate 100 side through its own elastic deformation. The coefficient of thermal expansion and elastic modulus of the second buffer layer 320 are both between those of the first buffer layer 310 and the third buffer layer 330, undertaking the core function of gradient transition in coefficient of thermal expansion and elastic modulus, avoiding abrupt interface formation between the first buffer layer 310 and the third buffer layer 330.

[0027] In some embodiments, the third buffer layer 330 comprises a temperature-responsive polymer such that its elastic modulus in a low-temperature range of -40°C to 0°C is lower than its elastic modulus in a high-temperature range of 85°C to 105°C, and its elongation at break in the low-temperature range is greater than its elongation at break in the high-temperature range. The temperature-responsive polymer is at least one of an organosilicon hybrid epoxy resin, a core-shell rubber toughening resin, a reversible crosslinking polymer, and an epoxy-based oligomeric silsesquioxane.

[0028] The third buffer layer 330, adjacent to the substrate 100, requires low elastic modulus and high toughness to absorb the enormous thermal deformation stress on the substrate 100 side. The third buffer layer 330 achieves an adaptive performance conversion of "low temperature flexibility and high temperature rigidity": In the low temperature range, the temperature-responsive polymer allows the layer to maintain a low elastic modulus and a high elongation at break, effectively absorbing the thermomechanical stress caused by the mismatch in the thermal expansion coefficients between the chip 200 and the substrate 100 through elastic deformation, avoiding the low-temperature brittleness of traditional materials; In the high temperature range, the elastic modulus of the layer increases significantly and the elongation at break decreases relatively, automatically obtaining higher rigidity and structural support capacity, suppressing the warping of the chip 200 and preventing the layer from over-softening and failing. Thus, without relying on external control, the third buffer layer 330 can continuously play an effective stress buffering function in the entire temperature range from -40℃ to 105℃, fundamentally overcoming the problem that a single fixed-performance material cannot simultaneously meet the core contradiction of low-temperature stress absorption and high-temperature structural support in wide-temperature eMMC packaging.

[0029] In some embodiments, the stress relief unit 350 is disposed within the second buffer layer 320. The blocking interface 340 is formed between the first buffer layer 310 and the second buffer layer 320, and / or between the second buffer layer 320 and the third buffer layer 330. Disposing the stress relief unit 350 within the second buffer layer 320 utilizes the stress transition function of the second buffer layer 320, allowing thermal stress to be guided and dispersed during the gradient transition process. Disposing the blocking interface 340 between layers utilizes the characteristic that the interlayer interface itself is a stress singularity point, actively blocking potential crack initiation or propagation at this location.

[0030] In some embodiments, the serrated or corrugated tips or crests of the blocking interface 340 correspond in vertical projection to the positions of multiple micropores in the stress relief units 350 within the adjacent buffer layer. This ensures that cracks that may propagate from the micropores directly face the crests or tips of the blocking interface 340 when they reach the interlayer interface, thereby being effectively deflected or terminated.

[0031] In some embodiments, the outer surface of the multi-layer stress buffer structure 300 includes a closed-loop structure, which includes a sawtooth interface or a corrugated interface. The closed-loop structure improves the protection against external stresses.

[0032] Example 2 This embodiment is basically the same as the scheme in Embodiment 1, except that: the chip 200 includes multiple chips 200 stacked sequentially along a direction perpendicular to the substrate 100, forming a bottom chip 210, an intermediate chip 220, and a top chip 230. The bottom chip 210 is mounted on the substrate 100 through its corresponding multilayer stress buffer structure 300, and the intermediate chip 220 and the top chip 230 are each mounted on the adjacent lower chip 200 through their corresponding multilayer stress buffer structures 300. In the multilayer stress buffer structure 300 corresponding to the bottom chip 210, the thickness of the third buffer layer 330 accounts for 40% to 50% of the total thickness of the multilayer stress buffer structure 300. In the multilayer stress buffer structure 300 corresponding to the top chip 230, the thickness of the first buffer layer 310 accounts for 40% to 50% of the total thickness of the multilayer stress buffer structure 300. In the multilayer stress buffer structure 300 corresponding to the intermediate chip 220, the thicknesses of the first buffer layer 310, the second buffer layer 320, and the third buffer layer 330 are uniformly distributed.

[0033] The bottom chip 210 is directly mounted on the substrate 100 and is most significantly affected by the thermal stress caused by the mismatch in the thermal expansion coefficients of the substrate 100. Increasing the thickness of the third buffer layer 330 can fully utilize the low elastic modulus and high toughness of the third buffer layer 330 to maximize the absorption of thermal stress from the substrate 100 side. The top chip 230 is located at the top of the stack. Although it is far from the substrate 100, the cumulative effect of thermal deformation of each chip 200 amplifies its warpage layer by layer. The interface between the bottom surface of the chip 200 and the buffer layer bears a large peel stress. Increasing the thickness ratio of the first buffer layer 310 can fully utilize the high elastic modulus and high interfacial bonding strength of the first buffer layer 310, enhancing the anti-peeling ability between the bottom surface of the chip 200 and the multi-layer stress buffer structure 300. The intermediate layer chip 220 is located in the middle of the stack, with adjacent chips 200 connected to its upper and lower sides respectively. Its thermal stress conditions are between the bottom and top layers. By adopting a configuration with uniform distribution of the thickness of each buffer layer, the multi-layer stress buffer structure 300 has appropriate stress absorption and interfacial bonding capabilities on both sides in the vertical direction, playing a role in balancing the transition.

[0034] Example 3 This embodiment also provides a method for fabricating an eMMC package structure, used to manufacture the above-mentioned eMMC package structure, including: S10. Based on the chip layer position, chip area, chip thickness and preset heat source distribution data, determine the thickness ratio and material parameters of each layer of the multi-layer stress buffer structure; S20. Multiple buffer layers with gradients in thermal expansion coefficient and elastic modulus are sequentially formed on the bottom surface of the chip and / or the surface of the substrate through layer coating, printing, spraying, lamination or dispensing processes. S30. During the formation of at least one buffer layer, stress relief units 350 are formed by a patterning process. S40. A blocking interface is formed between adjacent buffer layers by embossing, laser processing, roughening treatment or mold forming process. S50. The chip is mounted on the substrate and cured to form a package structure.

[0035] The preparation method is highly compatible with existing packaging processes, does not require the introduction of expensive specialized equipment, and is realistic for large-scale application.

[0036] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. An eMMC package structure, characterized in that, include: substrate; At least one chip is disposed on the substrate; A multi-layer stress buffer structure is disposed between the bottom surface of the chip and its mounting surface; The coefficient of thermal expansion of the multilayer stress buffer structure along the direction from the chip to the substrate shows an increasing trend, while the elastic modulus shows a decreasing trend. At least one layer of the multi-layer stress buffer structure is provided with a stress relief unit to change the transmission path of thermal stress in the multi-layer stress buffer structure so as to transfer the stress concentration area to a non-critical area. The stress relief unit includes a plurality of micropores, the distribution density of the plurality of micropores gradually decreases in the direction away from the corner, and / or the stress relief unit is oriented and arranged in a direction away from the corner of the bottom surface of the chip. At least one interlayer interface of the multilayer stress buffer structure is a blocking interface, used to block the crack propagation path along the interface.

2. The eMMC packaging structure according to claim 1, characterized in that, The blocking interface is a sawtooth-shaped interface or a continuous corrugated interface.

3. The eMMC packaging structure according to claim 2, characterized in that, The height difference between the peaks and valleys at the blocking interface is 1μm-5μm.

4. The eMMC packaging structure according to claim 1, characterized in that, The multi-layer stress buffer structure includes: The first buffer layer is adjacent to the chip; The second buffer layer is adjacent to the first buffer layer; The third buffer layer is adjacent to the second buffer layer and the substrate; Wherein, the coefficient of thermal expansion of the first buffer layer is smaller than that of the second buffer layer, and the coefficient of thermal expansion of the second buffer layer is smaller than that of the third buffer layer; The elastic modulus of the first buffer layer is greater than that of the second buffer layer, and the elastic modulus of the second buffer layer is greater than that of the third buffer layer.

5. The eMMC packaging structure according to claim 4, characterized in that, The third buffer layer comprises a temperature-responsive polymer such that the elastic modulus of the layer in the low-temperature range of -40°C to 0°C is lower than its elastic modulus in the high-temperature range of 85°C to 105°C, and its elongation at break in the low-temperature range is greater than its elongation at break in the high-temperature range.

6. The eMMC packaging structure according to claim 4, characterized in that, The stress relief unit is disposed within the second buffer layer; The blocking interface is formed between the first buffer layer and the second buffer layer and / or between the second buffer layer and the third buffer layer.

7. The eMMC packaging structure according to claim 4, characterized in that, The chip includes multiple chips stacked sequentially along a direction perpendicular to the substrate, forming a bottom chip, an intermediate chip, and a top chip. The bottom layer chip is mounted on the substrate through its corresponding multi-layer stress buffer structure, the middle layer chip is mounted on the bottom layer chip through its corresponding multi-layer stress buffer structure, and the top layer chip is mounted on the middle layer chip through its corresponding multi-layer stress buffer structure. In the multi-layer stress buffer structure corresponding to the underlying chip, the thickness of the third buffer layer accounts for 40% to 50% of the total thickness of the multi-layer stress buffer structure; In the multi-layer stress buffer structure corresponding to the top-layer chip, the thickness of the first buffer layer accounts for 40% to 50% of the total thickness of the multi-layer stress buffer structure; In the multi-layer stress buffer structure corresponding to the intermediate layer chip, the thicknesses of the first buffer layer, the second buffer layer, and the third buffer layer are uniformly distributed.

8. A method for fabricating an eMMC packaging structure, characterized in that, For manufacturing the eMMC package structure according to any one of claims 1 to 7, comprising: Based on the chip layer location, chip area, chip thickness, and preset heat source distribution data, determine the thickness ratio and material parameters of each layer of the multi-layer stress buffer structure; Multiple buffer layers with gradients in thermal expansion coefficients and elastic moduli are sequentially formed on the bottom surface of the chip and / or the surface of the substrate through layer coating, printing, spraying, lamination or dispensing processes. During the formation of at least one buffer layer, the stress relief unit is formed using a patterning process. The blocking interface is formed between adjacent buffer layers by embossing, laser processing, roughening treatment, or mold forming processes. The chip is mounted on the substrate and cured to form a package structure.

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