Direct-current charging pile, control mainboard thereof, power failure protection method and storage medium

Abstract

The application discloses a direct-current charging pile, a control mainboard thereof, a power-off protection method, and a storage medium. The control mainboard comprises a power-off detection circuit, a main control circuit, a hierarchical storage module, and a power-off power supply circuit. The power-off detection circuit is used for detecting a power supply state and outputting a power supply state detection signal. The main control circuit is used for outputting a stop charging control signal after confirming that an input power supply is powered off, acquiring an electric meter reading and an order state of a current charging order, and generating order settlement data. The hierarchical storage module is used for storing order hot data and order archival data. The power-off power supply circuit comprises a super capacitor group, which is used for providing temporary power supply for the main control circuit and the hierarchical storage module when the power supply is powered off, so as to complete order settlement and data storage before the temporary power supply fails.

Description

Technical Field

[0001] This application relates to the field of DC charging pile technology, and in particular to a DC charging pile and its control motherboard, power failure protection method, and storage medium. Background Technology

[0002] DC charging stations need to continuously record order information, meter readings, order status, and equipment operation data during the charging process. If the control board cannot promptly recognize the power failure and execute actions such as stopping charging, settling accounts, and saving data when the input power is abnormally interrupted, it can easily lead to problems such as abnormal maintenance of the charging circuit, missing order settlement data, and unrecoverable order status.

[0003] Existing DC charging pile control motherboards typically rely solely on ordinary power detection or backup batteries for short-term power supply. Ordinary power detection suffers from delayed power failure recognition, making it difficult to provide sufficient processing time for the main control circuit before the power supply completely drops. Backup battery solutions, on the other hand, have issues such as limited lifespan, the need for regular maintenance, and poor environmental adaptability, resulting in insufficient reliability of order data storage and order settlement in power failure scenarios. Summary of the Invention

[0004] The main purpose of this application is to provide a DC charging pile and its control motherboard, power failure protection method, and storage medium, aiming to solve the technical problem that when the input power of the DC charging pile fails, the control motherboard is unable to complete the charging stop, order settlement, and key data saving in a timely manner, resulting in order data loss or abnormal order status.

[0005] To achieve the above objectives, this application proposes a control motherboard for a DC charging pile, wherein the DC charging pile includes a charging circuit for connecting to a power receiving terminal, comprising: The power failure detection circuit is used to detect the power supply status and output a corresponding power supply status detection signal. The main control circuit is connected to the power failure detection circuit. It is used to determine whether the input power has failed based on the power supply status detection signal, and after confirming the power failure, it outputs a stop charging control signal to the charging circuit of the DC charging pile to cut off the electrical connection between the charging circuit and the power receiving terminal. It also obtains the meter reading and order status of the current charging order to generate order settlement data based on the meter reading and order status. The tiered storage module includes a first memory and a second memory. The first memory is used to store order hot data that needs to be saved first when power is lost, and the second memory is used to store order archive data and equipment operation logs. The power-off power supply circuit includes a supercapacitor bank, which is used to provide temporary power to at least the main control circuit and the hierarchical storage module during a power outage, so that the main control circuit and the hierarchical storage module can complete order settlement and data storage before the temporary power supply fails.

[0006] In one embodiment, the first memory is a Flash memory; The second storage device is a TF card.

[0007] In one embodiment, the equivalent capacitance, initial charging voltage, and discharge cutoff voltage of the supercapacitor bank are set according to the power consumption and processing time of the main control circuit and the hierarchical storage module during the power-down process, so that the supercapacitor bank can complete order settlement and data storage before the output voltage drops to the preset cutoff voltage.

[0008] In one embodiment, the power-off power supply circuit further includes an isolation circuit, which is used to supply power to the power output terminal and charge the supercapacitor bank when the power input terminal is normally powered, and to prevent the supercapacitor bank from discharging in reverse to the power input terminal when the power input terminal is powered off, and to allow the supercapacitor bank to return power to the power output terminal. The isolation circuit includes: A switching transistor, wherein the controlled terminal of the switching transistor is connected to a first bias resistor; the first terminal of the switching transistor is connected to a current-limiting resistor network; and the second terminal of the switching transistor is connected to the supercapacitor bank. The first isolation diode has its anode connected to the power supply input terminal and its cathode connected to the power supply output terminal. The second isolation diode has its anode connected to the supercapacitor bank and its cathode connected to the power supply output terminal.

[0009] In one embodiment, the power-down detection circuit includes a sampling voltage divider branch, a reference voltage divider branch, and a comparator; The sampling voltage divider branch includes a first voltage divider resistor, a second voltage divider resistor, and a Zener diode. The first voltage divider resistor and the second voltage divider resistor are connected in series between the input power supply terminal and the ground terminal. The Zener diode is connected in parallel with the second voltage divider resistor. The connection node between the first voltage divider resistor and the second voltage divider resistor serves as the sampling node. The reference voltage divider branch includes a third voltage divider resistor, a fourth voltage divider resistor, and a first filter capacitor. The third voltage divider resistor and the fourth voltage divider resistor are connected in series between the auxiliary power supply terminal and the ground terminal. The first filter capacitor is connected between the connection node between the third voltage divider resistor and the fourth voltage divider resistor and the ground terminal. The connection node between the third voltage divider resistor and the fourth voltage divider resistor serves as the reference node. The first input terminal of the comparator is connected to the sampling node, the second input terminal of the comparator is connected to the reference node, and the output terminal of the comparator is connected to the power-down detection pin of the main control circuit via an output resistor to output the power supply status detection signal to the main control circuit.

[0010] Furthermore, to achieve the above objectives, this application also provides a power-off protection method for a DC charging pile, applied to the control motherboard, the method comprising: Acquire the power supply status detection signal from the power failure detection circuit; If the target frequency signal is not detected in the power supply status detection signal, it is determined that the input power supply has failed. Output a charging stop control signal to cut off the charging circuit, and obtain the meter reading and order status of the current charging order, and generate order settlement data based on the meter reading and order status; The order settlement data is written to the hierarchical storage module, and then enters a low-power state after the order settlement data is written. Wake up from the low-power state according to a preset wake-up cycle, and perform a reset operation when the target frequency signal is detected.

[0011] In one embodiment, determining that the input power supply has failed when no target frequency signal is detected in the power supply status detection signal includes: Within a preset detection window, count the number of level transitions and / or the time interval between adjacent level transitions; Based on the number of level transitions and / or the time interval, determine whether the power-down detection signal exists on the power-down detection pin; If no target frequency signal is detected within multiple consecutive preset detection windows, or if the frequency of the power supply status detection signal is outside the preset frequency range, it is determined that the input power supply has lost power.

[0012] In one embodiment, writing the order settlement data into the hierarchical storage module includes: The hot data of orders is preferentially written into the first memory of the hierarchical storage module; Once the order hot data writing is complete, the order archive data and / or equipment operation logs are written to the second memory in the hierarchical storage module; The order hot data includes at least one of the following: order identifier, initial meter reading, current meter reading, order status, power outage time, and verification information.

[0013] In one embodiment, the storage medium is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method.

[0014] In addition, to achieve the above objectives, this application also provides a DC charging pile, including the aforementioned control motherboard; A charging circuit is connected to a power receiving terminal, and the controlled end of the charging circuit is connected to the control motherboard; An electricity meter is installed in the charging circuit.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: This application uses a power failure detection circuit to detect the power supply status of the input power supply and transmits the power supply status detection signal to the main control circuit, so that the main control circuit can identify the power failure status of the input power supply in a timely manner and enter the power failure process before the control motherboard is completely powered off.

[0016] Upon confirmation of a power outage, this application enables the main control circuit to output a stop-charging control signal to cut off the charging circuit, allowing the DC charging pile to stop charging promptly when the input power is abnormally interrupted, thus reducing the risk of the charging circuit being in an abnormal conduction state.

[0017] This application obtains the meter reading and order status of the current charging order through the main control circuit, and generates order settlement data accordingly, so that the DC charging pile can still complete the settlement processing of the current order in the event of a power outage, reducing problems such as abnormal order status and inability to calculate order fees.

[0018] This application uses a tiered storage module to store hot order data and archived order data separately, so that critical order data that needs to be saved first can be written in advance when power is lost, thereby improving the reliability of order status recovery and order settlement after power failure.

[0019] This application utilizes a supercapacitor bank to provide temporary power to the main control circuit and hierarchical storage module during power outages, enabling the main control circuit to still have time to complete charging stop, settlement, and data saving even after the input power supply fails. Compared to traditional backup battery solutions, supercapacitor banks offer advantages such as faster charging and discharging speeds, longer cycle life, and lower maintenance requirements, which helps reduce the later maintenance costs of DC charging piles. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the module structure of the control motherboard provided in an embodiment of this application; Figure 2A schematic diagram of the circuit structure of the power-off power supply circuit provided in the embodiments of this application; Figure 3 A schematic diagram of the circuit structure of the power-down detection circuit provided in the embodiments of this application; Figure 4 This is a schematic diagram of the control flow of the power failure protection method according to an embodiment of this application; Figure 5 This is a schematic diagram of the module structure of a DC charging pile provided in an embodiment of this application.

[0023] Explanation of icon numbers: 1. Control motherboard; 2. Electricity meter; 3. Charging circuit; 10. Power failure detection circuit; 20. Main control circuit; 30. Hierarchical storage module; 40. Power failure power supply circuit; 101. Sampling node; 102. Reference node; 401. Isolation circuit; 402. Supercapacitor bank; Q44, switching transistor; R696, first bias resistor; D103, first isolation diode; D106, second isolation diode; U8, comparator; R18, output resistor; PD3_LVDR, power-down detection pin.

[0024] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0026] During normal charging, the control board of a current DC charging station needs to continuously participate in charging control, metering data acquisition, order status maintenance, and operation log recording. Since order data for DC charging stations is not generated all at once but is continuously updated across multiple stages, including charging start, charging progress, and charging end, the control board needs to quickly detect the power supply anomaly and complete operations such as stopping charging, meter reading, order settlement, and saving critical data if the input power is suddenly interrupted. If the control board cannot complete these processes before the voltage drops to an unusable level, problems may arise such as the charging circuit not being disconnected in time, the current order status remaining stuck in charging, the final meter reading not being saved, the inability to calculate order costs, or the inability to accurately restore the order status after power failure.

[0027] In existing solutions, some DC charging pile control motherboards rely solely on standard voltage detection to determine if the input power supply is abnormal. This method typically only triggers a power-down process after a significant voltage drop. By this time, the operating voltage of the main control chip, memory, and communication interfaces may be nearing their failure range, leaving very little time for the main control circuit to perform emergency processing. This is especially problematic in scenarios requiring reading meter data, updating order status, generating settlement data, and writing it to non-volatile memory. If the power-down detection is insufficient, the main control circuit may reset or stop working before completing the data writing process, resulting in incomplete order data. For DC charging piles, this data loss not only affects equipment operation records but can also lead to inconsistencies between user-side, operation platform-side, and pile-side data, increasing the difficulty of subsequent order verification and anomaly handling.

[0028] In addition, existing solutions also employ backup batteries to maintain power for short periods. While backup batteries can provide some reserve power after an input power outage, they suffer from issues such as lifespan degradation, limited cycle life, self-discharge during long-term inactivity, capacity reduction at low temperatures, and accelerated aging at high temperatures. DC charging stations are typically deployed in outdoor or semi-outdoor environments where ambient temperatures fluctuate significantly, making the actual usable capacity and reliability of backup batteries susceptible to environmental influences. As usage time increases, if backup batteries are not maintained or replaced in a timely manner, they may not provide sufficient backup power during a power outage, still preventing the main control circuit from completing order settlement and data saving. Therefore, while traditional backup battery solutions can alleviate power outage problems to some extent, they introduce issues of regular maintenance and replacement costs, as well as unreliable reliability, making them unsuitable for long-term maintenance-free DC charging station control motherboards.

[0029] Furthermore, existing control motherboards have shortcomings in their data storage methods during power outages. If all order data is simply written to a general-purpose memory, the main control circuit needs to simultaneously process and write a large amount of data within a short power outage window, resulting in long write times and a high risk of failure. In actual power outage protection, the most important data to save are critical data that enables order recovery and settlement, such as the current order identifier, initial meter reading, current meter reading, order status, power outage time, and verification information. If the existing solution does not distinguish between hot order data and archived order data, but processes all data uniformly during a power outage, it is easy to fail to ensure that critical data is prioritized for storage within the limited power supply time, thus affecting the accuracy of order reconstruction and settlement after power outage recovery.

[0030] Based on the aforementioned problems, the improvement approach of this application is not to simply add an energy storage device, nor to simply add a voltage detection circuit at the input end. Instead, it revolves around the emergency handling sequence of "first identify, then stop charging, then settle accounts, then save" when a DC charging pile loses power, and designs a collaborative approach to the power failure detection, temporary power supply, main control processing, and hierarchical storage of the control motherboard. Specifically, this application uses a comparator in the power failure detection circuit to compare the input power sampling signal with a reference signal, and outputs a power supply status detection signal based on the comparison result. This allows the main control circuit to determine whether the input power still meets normal power supply conditions based on the power supply status detection signal. When the power supply status detection signal does not meet normal power supply conditions, the main control circuit can determine that the input power has failed, thus initiating the power failure emergency handling process in advance.

[0031] Upon confirmation of a power outage, the main control circuit of this application first outputs a charging stop control signal to disconnect the charging circuit. This ensures that the DC charging process can be terminated in an orderly manner while the main control circuit remains operational, preventing the charging circuit from remaining in an uncertain state when the input power is abnormally interrupted. Subsequently, the main control circuit acquires the current order's meter reading and order status, and generates order settlement data based on these data. By integrating charging stop control, meter reading, and order settlement into a unified power outage processing flow, the order status during a power outage can be transformed from an "abnormal interruption" state to a "power outage settlement" state that can be recorded and recovered, thereby reducing the risk of order data loss and abnormal order status.

[0032] To ensure that the main control circuit and storage module still have time to complete the aforementioned processes after a power outage, this application further incorporates a power-down power supply circuit, consisting of multiple supercapacitors forming a supercapacitor bank. This supercapacitor bank provides temporary power to the main control circuit and hierarchical storage module during a power outage. Compared to traditional backup batteries, supercapacitors offer faster charging and discharging speeds, longer cycle life, and lower maintenance requirements, making them more suitable as a short-term backup power source for the control motherboard during power failures. This supercapacitor bank is not used to maintain continuous charging of the vehicle by the DC charging station, but rather to ensure that low-power critical circuits such as the main control circuit and storage module continue operating for a preset time, enabling them to complete necessary operations such as stopping charging, settlement, and data writing. This reduces the maintenance and replacement issues associated with traditional battery solutions while improving the reliability of power-down protection.

[0033] Regarding data storage, this application uses a tiered storage module to differentiate between order hot data and order archive data. This ensures that critical data that must be saved during a power outage is written first, while less real-time archive data and operational logs can be processed after the critical data is saved. Through this tiered storage method, the main control circuit can prioritize the complete preservation of data required for order recovery and settlement during the limited temporary power supply provided by the supercapacitor. Thus, even if the power outage lasts for a long time, or if subsequent power is completely exhausted, the control motherboard can restore the order status based on the already saved order hot data after power is restored, and continue to complete order archiving or platform synchronization.

[0034] Therefore, the overall improvement approach of this application is as follows: utilizing comparator-based power failure detection to improve the timeliness of power failure identification; utilizing supercapacitor banks to provide short-term temporary power supply after a power failure; utilizing the main control circuit to complete charging stoppage and order settlement within the temporary power supply window; and utilizing a hierarchical storage module to prioritize the storage of order hot data. These components work together to enable the control motherboard to complete critical business processes even when the input power is abnormally interrupted, thereby improving the reliability of order settlement and data storage in DC charging pile power failure scenarios and reducing the maintenance costs and reliability issues associated with traditional backup battery solutions.

[0035] This embodiment provides a control motherboard for a DC charging pile, see reference. Figure 1 The control motherboard can be installed in the control box of the DC charging pile and connected to the power metering unit, charging circuit control unit, communication unit and hierarchical storage module 30 of the DC charging pile. It is used to perform order processing and charging control when the DC charging pile is running normally, and to complete charging stop, order settlement and data saving when the input power fails.

[0036] It should be noted that the control motherboard can be understood as a circuit board in a DC charging pile used for control, detection, communication, metering data processing, and order data processing. It can be a single printed circuit board or a control component formed by combining multiple circuit boards such as a main control board, interface board, storage board, or power board. This embodiment uses a single control motherboard as an example, but it is not limited to the control motherboard being a single circuit board.

[0037] Reference Figure 1This application provides a control motherboard 1 for a DC charging pile. The control motherboard 1 includes a power failure detection circuit 10, a main control circuit 20, a hierarchical storage module 30, and a power failure power supply circuit 40. The power failure detection circuit 10 is connected to the main control circuit 20 and is used to detect the power supply status of the DC charging pile input power supply, and output a power supply status detection signal to the main control circuit 20 according to the detection result. The main control circuit 20 is connected to the power failure detection circuit 10, the hierarchical storage module 30, and the charging circuit control unit of the DC charging pile. It is used to determine whether the input power supply has failed based on the power supply status detection signal, and after confirming that the input power supply has failed, output a stop charging control signal to cut off the charging circuit 3. At the same time, it acquires the meter reading and order status of the current charging order, and generates order settlement data based on the meter reading and order status. The hierarchical storage module 30 is connected to the main control circuit 20 and is used to store order hot data and order archive data. The power-down power supply circuit 40 includes a supercapacitor group 402. The power-down power supply circuit 40 is used to provide temporary power to at least the main control circuit 20 and the hierarchical storage module 30 when the input power is lost, so that the main control circuit 20 can complete order settlement and data storage before the temporary power supply fails.

[0038] It should be noted that the power-down detection circuit 10 is a detection circuit used to determine whether the input power supply is still in a usable power supply state. It can determine the power supply status by detecting the voltage, level change, frequency signal, periodic signal, or sampled signal after voltage division of the input power supply. The power-down detection circuit 10 is not limited to detecting only the AC mains terminal; it can also detect the DC input terminal after rectification and conversion of the AC power supply, and it can also detect the power supply input terminal of the control motherboard 1.

[0039] In one feasible implementation, the power failure detection circuit 10 includes a voltage divider network, a reference signal generation branch, and a comparator U8. The voltage divider network is connected to the input power supply terminal and is used to convert the voltage of the input power supply terminal into a sampling signal suitable for the input of the comparator U8. The reference signal generation branch is used to generate a reference signal. The comparator U8 receives the input power supply sampling signal and the reference signal respectively, and outputs a power supply status detection signal according to the magnitude relationship between the input power supply sampling signal and the reference signal. When the input power supply sampling signal meets the normal power supply conditions, the comparator U8 outputs a power supply status detection signal in the first state; when the input power supply sampling signal does not meet the normal power supply conditions, the comparator U8 outputs a power supply status detection signal in the second state. The main control circuit 20 determines whether the input power supply has failed based on the state change of the power supply status detection signal.

[0040] It should be noted that the power supply status detection signal refers to an electrical signal that reflects whether the input power supply is in a normal power supply state. This power supply status detection signal can be a high or low level signal, or a periodic signal or a target frequency signal. For example, when the input power supply is normal, the power supply status detection signal can be a square wave signal within a preset frequency range; when the input power supply is de-energized, the square wave signal disappears or its frequency becomes abnormal. As another example, when the input power supply is normal, the power supply status detection signal can be at a high level; when the input power supply is de-energized, the power supply status detection signal can become at a low level. This embodiment does not limit the specific level form of the power supply status detection signal, as long as the main control circuit 20 can determine whether the input power supply is de-energized based on this signal.

[0041] In this embodiment, the main control circuit 20 may include a microcontroller, peripheral interface circuits, and a charging circuit control interface. Under normal power supply conditions, the main control circuit 20 receives meter readings, order status, charging gun status, vehicle communication status, and equipment operating status, and performs charging control and order management based on this data. When the main control circuit 20 confirms a power outage based on the power supply status detection signal, it immediately enters a power outage processing procedure. The power outage processing procedure includes: outputting a charging stop control signal to disconnect the contactor, relay, power module, or other charging circuit switch of the DC charging pile; stopping the reception of new charging orders; acquiring the meter reading and order status of the current charging order; generating order settlement data based on the meter reading and order status; and writing key data from the order settlement data into the hierarchical storage module 30.

[0042] It should be noted that the charging stop control signal refers to the control signal output by the main control circuit 20 after confirming the input power failure, used to stop the DC charging pile from charging. The charging stop control signal can directly control the relay, contactor, or electronic switch to open, or it can be sent to the charging circuit control unit, which will then control the charging circuit 3 to open. The charging stop control signal can be in the form of high or low level, pulse signal, communication command, or control message.

[0043] It should be noted that charging circuit 3 refers to the power transmission path in the DC charging pile used to output charging energy to the vehicle. It may include a power module, DC bus, relays, contactors, fuses, charging gun output terminals, and related sampling and protection circuits. Disconnecting charging circuit 3 does not require breaking all electrical connections, but rather at least stopping the DC charging pile from outputting charging energy to the vehicle.

[0044] In one feasible implementation, after outputting a charging stop control signal, the main control circuit 20 reads the starting meter reading, current meter reading, order start time, power outage time, order number, and order status corresponding to the current charging order. The main control circuit 20 determines the charging amount for the current order based on the difference between the current meter reading and the starting meter reading, and generates order settlement data according to the charging amount and billing rules. The main control circuit 20 can also update the order status to power outage settlement status, abnormal termination status, or pending recovery settlement status, so that after the input power is restored, order archiving or platform synchronization can continue based on the order status.

[0045] It should be noted that the current charging order refers to a charging order that is still in progress, pending settlement, or pending saving when the input power fails. The current charging order can be an order initiated by the user through scanning a code, swiping a card, account authentication, or platform issuance, or it can be a test order or maintenance order generated locally by the DC charging pile.

[0046] It should be noted that the meter reading refers to the data used to characterize the charging capacity, collected by the energy metering unit in the DC charging pile. The meter reading can be cumulative energy reading, time-of-use energy reading, energy data obtained from voltage and current integration, or metering data returned from an external meter communication interface. The main control circuit 20 can acquire the meter reading via RS485, CAN, SPI, UART, or other communication methods.

[0047] It should be noted that order status refers to the status information used to indicate the current processing stage of a charging order, such as not started, charging in progress, paused, normally completed, abnormally completed, power failure settlement, pending synchronization, or archived. Order status can be used to determine whether order settlement, platform reporting, or data repair needs to continue after the input power is restored.

[0048] It should be noted that order settlement data refers to the data set used to determine the final settlement result of the current charging order. This data may include one or more of the following: order number, starting meter reading, ending meter reading, charging amount, charging duration, cost information, order status, power outage time, and verification information. Order settlement data is not limited to directly including the cost amount; it may also include basic data required for subsequent cost calculations.

[0049] In this embodiment, the hierarchical storage module 30 is used to store order hot data and order archive data respectively. Specifically, the hierarchical storage module 30 may include a first memory and a second memory. The first memory is used to store order hot data that needs to be saved first when power is lost, and the second memory is used to store order archive data, equipment operation logs, historical order records, or platform synchronization records. During the power loss process, the main control circuit 20 first writes the order hot data to the first memory, and then writes the order archive data to the second memory after the order hot data is written.

[0050] It should be noted that the hierarchical storage module 30 refers to a storage structure that stores different types of data in layers based on their importance, real-time requirements, or write priority. The hierarchical storage module 30 is not limited to two physical storage chips; it can also be different storage areas divided within the same storage chip, or it can be formed by a combination of on-chip memory and off-chip memory.

[0051] It should be noted that order hot data refers to critical data that needs to be prioritized for saving during power outages and can be used to restore order status or complete order settlement. Order hot data may include one or more of the following: order number, initial meter reading, current meter reading, order status, order start time, power outage time, and verification information. Order hot data is typically characterized by small data volume, high real-time requirements, and high priority during power outages.

[0052] It should be noted that order archive data refers to data used to fully record the order process or equipment operation process. Order archive data can include the entire order process record, charging curve, time-of-use billing data, equipment operation logs, fault logs, platform communication records, etc. Compared to hot order data, order archive data can have a larger data volume, and its real-time writing priority can be lower.

[0053] In one feasible implementation, the first memory is a ferroelectric memory, and the second memory is a flash memory. After confirming a power outage, the main control circuit 20 prioritizes writing the order number, current meter reading, order status, and verification information into the ferroelectric memory. After the ferroelectric memory has finished writing, the main control circuit 20 then writes the order archive data into the flash memory. Thus, even when the temporary power supply provided by the supercapacitor bank 402 is short-lived, it is possible to prioritize ensuring that the critical data required for order recovery and order settlement is preserved.

[0054] In this embodiment, the power-down power supply circuit 40 includes a supercapacitor bank 402. The supercapacitor bank 402 can be charged by the power supply circuit of the control motherboard 1 when the input power is normal, and provides temporary power to the main control circuit 20 and the hierarchical storage module 30 when the input power fails. After detecting a power failure, the main control circuit 20 relies on the temporary power provided by the power-down power supply circuit 40 to perform a power-down process. The hierarchical storage module 30 also relies on the temporary power provided by the power-down power supply circuit 40 to complete the writing of order hot data and order archive data.

[0055] It should be noted that the power-down power supply circuit 40 refers to a circuit that can provide short-term backup power to critical circuits in the control motherboard 1 after the input power supply fails. The power-down power supply circuit 40 may include one or more of the following: supercapacitor group 402, charging control branch, isolation branch, current limiting branch, filter capacitor, or voltage conversion branch. The purpose of the power-down power supply circuit 40 is not to keep the DC charging pile charging the vehicle, but to enable low-power critical circuits such as the main control circuit 20 and the hierarchical storage module 30 to complete charging stop, settlement, and data saving.

[0056] It should be noted that the supercapacitor bank 402 refers to an energy storage component composed of one or more supercapacitor cells. Multiple supercapacitor cells can be connected in series, parallel, or a combination of series and parallel connections. Series connection increases the rated withstand voltage of the supercapacitor bank 402 to match the power supply voltage of the control motherboard 1; parallel connection increases the equivalent capacitance of the supercapacitor bank 402 to extend the temporary power supply time. The supercapacitor bank 402 can also be configured with voltage-equalizing resistors or balancing circuits to reduce the risk of voltage imbalance between the series-connected supercapacitor cells.

[0057] It should be noted that temporary power supply refers to the backup power provided by the power-off power supply circuit 40 to the main control circuit 20 and the hierarchical storage module 30 for a limited time after the input power supply fails. The duration of the temporary power supply can be determined by the capacitance of the supercapacitor bank 402, its starting voltage, its cutting voltage, and the load power consumption. A temporary power supply failure can be understood as the voltage of the supercapacitor bank 402 dropping to a level that cannot maintain the normal operation of the main control circuit 20 or the hierarchical storage module 30.

[0058] In one feasible implementation, during the temporary power supply period provided by the power-down power supply circuit 40, the main control circuit 20 first outputs a charging stop control signal, then acquires the meter reading and order status of the current charging order, subsequently generates order settlement data, and prioritizes writing the order hot data to the hierarchical storage module 30. After completing the above data writing, the main control circuit 20 can shut down the display, communication, or other non-essential peripherals and enter a low-power state to reduce energy consumption during the temporary power supply period. If the input power is restored, the main control circuit 20 can read the order hot data stored in the hierarchical storage module 30, restore the order status based on the order hot data, and continue to perform order archiving or platform synchronization.

[0059] Through the above embodiments, the power failure detection circuit 10 can detect the power supply status of the input power source and output a power supply status detection signal to the main control circuit 20; the main control circuit 20 can promptly determine that the input power source has failed based on the power supply status detection signal, and cut off the charging circuit 3 when the power fails, generating order settlement data; the hierarchical storage module 30 can perform hierarchical storage of order hot data and order archive data; the power failure power supply circuit 40 can provide temporary power to the main control circuit 20 and the hierarchical storage module 30 through the supercapacitor group 402. Therefore, the DC charging pile can complete the charging stop, order settlement, and data storage even after an abnormal interruption of the input power source, before the temporary power supply fails, thereby reducing the risk of order data loss and abnormal order status.

[0060] Optionally, in one embodiment, the supercapacitor bank 402 includes multiple supercapacitors connected in series and multiple voltage-equalizing resistors. The multiple supercapacitors are sequentially connected in series between the positive terminal and ground of the supercapacitor bank 402. The positive terminal of the supercapacitor bank 402 is connected to the isolation branch and / or charging control branch of the power-off circuit 40, and the negative terminal of the supercapacitor bank 402 is grounded. Each voltage-equalizing resistor is connected in parallel across the corresponding supercapacitor, enabling the multiple supercapacitors to share a relatively balanced terminal voltage during charging.

[0061] It should be noted that a voltage-equalizing resistor is a resistor connected in parallel across a supercapacitor to balance the voltage across each individual supercapacitor. Because different supercapacitors may have differences in leakage current, capacitance, or internal resistance, directly connecting multiple supercapacitors in series can easily cause some supercapacitors to experience higher voltages than others. By connecting a voltage-equalizing resistor in parallel across each supercapacitor, a discharge path is provided for each supercapacitor, making their voltages more balanced and reducing the risk of overvoltage in any single supercapacitor.

[0062] In one feasible implementation, the supercapacitor bank 402 includes four supercapacitors with a rated voltage of 2.7V and a capacitance of 1F. The four supercapacitors are connected in series to form the supercapacitor bank 402 with a rated withstand voltage of approximately 10.8V. In this connection configuration, the equivalent capacitance of the supercapacitor bank 402 is approximately 0.25F. A voltage-equalizing resistor, with a resistance value of 10kΩ, is connected in parallel across each supercapacitor. This improves the withstand voltage of the supercapacitor bank 402 while reducing the risk of uneven voltage distribution among the individual supercapacitors through the voltage-equalizing resistors.

[0063] In another feasible implementation, the supercapacitor bank 402 includes three supercapacitors with a rated voltage of 3.6V and a capacitance of 1F. The three supercapacitors are connected in series to form a supercapacitor bank 402 with a rated withstand voltage of approximately 10.8V. In this connection configuration, the equivalent capacitance of the supercapacitor bank 402 is approximately 0.333F. A voltage-equalizing resistor is connected in parallel across each supercapacitor to maintain a relatively balanced terminal voltage when charged to a preset charging voltage. This implementation can achieve a withstand voltage capability similar to that of four 2.7V supercapacitors connected in series while reducing the number of supercapacitors.

[0064] In another feasible implementation, the supercapacitor bank 402 includes two supercapacitors with a rated voltage of 5.5V and a capacitance of 1F. The two supercapacitors are connected in series to form a supercapacitor bank 402 with a rated withstand voltage of approximately 11V. In this connection method, the equivalent capacitance of the supercapacitor bank 402 is approximately 0.5F. This scheme can form a backup energy storage branch suitable for low-voltage control power supply nodes with a relatively small number of supercapacitors, which helps to reduce the number of components and space occupied on the control motherboard 1.

[0065] In another feasible implementation, the supercapacitor bank 402 can also adopt a series-parallel combination structure. Specifically, multiple supercapacitors can be connected in series to form a supercapacitor string, and then at least two supercapacitor strings can be connected in parallel. For example, four 2.7V, 1F supercapacitors can be connected in series to form a supercapacitor string with a rated withstand voltage of approximately 10.8V and an equivalent capacitance of approximately 0.25F. Then, two identical supercapacitor strings can be connected in parallel, so that the supercapacitor bank 402 maintains a rated withstand voltage of approximately 10.8V while increasing the equivalent capacitance to approximately 0.5F. Thus, while meeting the withstand voltage requirements of the power supply node of the control motherboard 1, the energy storage capacity and temporary power supply duration of the supercapacitor bank 402 can be improved.

[0066] In practical applications, the number of supercapacitors, their rated voltage, capacitance value, and the resistance value of the voltage equalizing resistors can be selected based on the power input voltage of the control motherboard 1, the power consumption of the main control circuit 20 and the hierarchical storage module 30, and the time required for order settlement and data storage. For example, when the power consumption of the main control circuit 20 and the hierarchical storage module 30 during power-down processing is low, a single supercapacitor can be used in series; when a longer temporary power supply time is required, multiple supercapacitors can be connected in series and parallel to increase the equivalent capacitance. The resistance value of the voltage equalizing resistors can be set according to the leakage current of the supercapacitors, the allowable voltage equalizing power consumption, and the charging and holding requirements, and is not limited to 10kΩ.

[0067] Through the above configuration, the series connection of multiple supercapacitors improves the voltage withstand capability of the supercapacitor bank 402, enabling it to adapt to the power supply voltage of the control motherboard 1. The voltage equalizing resistor balances the terminal voltage of each supercapacitor, reducing the risk of overvoltage failure of individual supercapacitors connected in series. Furthermore, when a longer power-down processing time is required, the equivalent capacitance of the supercapacitor bank 402 can be increased through a series-parallel combination. Therefore, the power-down power supply circuit 40 can more stably provide temporary power to the main control circuit 20 and the hierarchical storage module 30 when the input power supply fails, allowing the DC charging pile to complete order settlement and data storage before the temporary power supply fails.

[0068] Optionally, in one embodiment, the first memory is an FRAM memory, and the second memory is a Flash memory. The main control circuit can be connected to the FRAM memory and the Flash memory via I2C, SPI, parallel bus, or other storage interfaces. After the input power is lost, the main control circuit first writes at least one of the following as hot data: order identifier, initial meter reading, current meter reading, order status, power outage time, and verification information, into the FRAM memory; after the FRAM memory is written, the complete order record, charging process record, device operation log, or fault record is then written into the Flash memory.

[0069] It should be noted that FRAM refers to ferroelectric random access memory, which is non-volatile and has a fast write speed. It retains written data without requiring continuous power after a power outage. Therefore, using FRAM to store priority order data that needs to be saved during power failures can reduce the risk of losing critical order data due to insufficient write time during a power outage.

[0070] It should be noted that Flash memory refers to flash storage, which typically has a large storage capacity and is suitable for storing large amounts of data such as order archives, equipment operation logs, historical order records, and fault records. Compared to FRAM memory, Flash memory is more suitable as a storage medium for archived data.

[0071] In one feasible implementation, after writing order hot data to the FRAM memory, the main control circuit can read the written order hot data and determine whether the order hot data was successfully written based on verification information. If the verification passes, the main control circuit determines that the order hot data writing is complete and continues to write the order archive data and equipment operation log to the Flash memory; if the verification fails, the main control circuit can rewrite the order hot data if the temporary power supply still meets the operating conditions, or write an error flag so that data repair can be performed after the input power is restored.

[0072] In another embodiment, the FRAM memory contains multiple hot data recording areas. Each time a power outage occurs, the main control circuit writes the current order hot data into a new hot data recording area and updates the validity flag after writing. Upon restoration of power, the main control circuit can determine the latest and valid order hot data from the multiple hot data recording areas based on the validity flag and verification information, and restore the order status or complete the order archive data based on this order hot data.

[0073] In another embodiment, the Flash memory includes an order archive area and a log area. The order archive area stores archived order data, while the log area stores device operation logs. After the hot order data is written to the FRAM memory, the main control circuit can, based on the remaining power supply capacity of the power-down circuit, choose to write the complete archived order data to the order archive area, or only write the power-down event, charging stop result, and writing result to the log area. If the complete order archiving cannot be completed during a power outage, the main control circuit can, after the input power is restored, supplement the archived order data in the Flash memory based on the hot order data stored in the FRAM memory.

[0074] With the above settings, the FRAM memory can quickly save order hot data during power failure, while the Flash memory can save archived order data and equipment operation logs. Together, they can prioritize the preservation of critical order data during the limited temporary power supply provided by the supercapacitor bank, while also ensuring the integrity of order records and equipment operation logs.

[0075] In another embodiment, the first memory is a Flash memory, and the second memory is a TF card. The main control circuit is connected to both the Flash memory and the TF card. After confirming a power outage, the main control circuit first writes the hot data of the current charging order to the Flash memory; after the hot data is written, it then writes the order archive data and the device operation log to the TF card.

[0076] In this embodiment, the Flash memory can be an onboard memory located on the control motherboard. It has a fixed data transmission path with the main control circuit, making it suitable for quickly writing small amounts of hot order data that is crucial for order recovery and settlement during power failure. For example, the main control circuit can write the order identifier, initial meter reading, current meter reading, order status, power failure time, and verification information into the Flash memory so that after the input power is restored, the order status can be restored and the order settlement can be completed based on the data stored in the Flash memory.

[0077] It should be noted that a TF card refers to a removable memory card, which typically has a large storage capacity and is suitable for storing large amounts of order archive data and device operation logs. In this embodiment, the TF card can be used to store complete order records, historical charging records, power outage logs, device operation logs, and fault records, among other data.

[0078] In one feasible implementation, when power is lost, the main control circuit first writes the order hot data to the Flash memory and generates a write completion flag or verification information after the write is completed. If the temporary power supply provided by the power-down circuit is still sufficient to meet the write conditions, the main control circuit continues to write the order archive data and device operation log to the TF card. If the temporary power supply time is insufficient to complete the TF card writing, the main control circuit can supplement the order archive data in the TF card based on the order hot data stored in the Flash memory after the input power is restored.

[0079] With the above settings, the Flash memory can prioritize saving critical data needed to restore orders and complete settlements in the event of a power outage, while the TF card can store a larger amount of archived and log data. Therefore, in situations where power outage time is limited, priority can be given to ensuring the preservation of critical order data, while also maintaining the integrity of order records and equipment operation logs.

[0080] Optionally, in one embodiment, the equivalent capacitance, initial charging voltage, and discharge cutoff voltage of the supercapacitor bank are set according to the power consumption and processing time of the main control circuit and the hierarchical storage module during the power-down process. During the power-down process, the main control circuit and the hierarchical storage module need to complete functions such as charging stop control, meter reading, order status acquisition, order settlement data generation, order hot data writing, and necessary archiving or log writing. Therefore, the supercapacitor bank needs to provide sufficient energy to support the above-mentioned processes before its output voltage drops to the preset cutoff voltage.

[0081] It should be noted that equivalent capacitance refers to the overall capacitance formed by a supercapacitor bank when connected in series, parallel, or a combination of series and parallel connections. When multiple identical supercapacitors are connected in series, the rated voltage of the supercapacitor bank increases, but the equivalent capacitance decreases; when multiple supercapacitors are connected in parallel, the equivalent capacitance of the supercapacitor bank increases, but the rated voltage usually remains unchanged. Therefore, the equivalent capacitance can be selected based on the power supply voltage of the control motherboard, the temporary power supply time, and the load power consumption.

[0082] It should be noted that the initial charging voltage refers to the voltage to which the supercapacitor bank is charged when the input power supply is normal. A higher initial charging voltage typically means that the supercapacitor bank can release more energy after power failure, provided the device's withstand voltage requirements are met. The initial charging voltage can be set by the charging control branch, current limiting branch, voltage regulation branch, or power management circuit.

[0083] It should be noted that the discharge cutoff voltage refers to the lowest voltage to which the supercapacitor bank is allowed to discharge during power outages. The discharge cutoff voltage can be determined based on the minimum operating voltage of the main control circuit, the hierarchical storage module, and the subsequent voltage conversion circuit. When the output voltage of the supercapacitor bank drops to near the discharge cutoff voltage, the main control circuit can stop unnecessary write operations or enter a low-power state to avoid abnormal data writing due to further voltage drops.

[0084] It should be noted that operating power consumption refers to the power consumed by the main control circuit and hierarchical storage module during power-down processing. This operating power consumption can include the power consumption of the main control chip, FRAM memory write power consumption, Flash memory write power consumption, read communication power consumption, and the power consumption of necessary interface circuits. Processing time refers to the time required for the main control circuit to complete order settlement and data storage, which can include charging stop control time, read time, data calculation time, and storage write time.

[0085] In one feasible implementation, the available energy of the supercapacitor bank can be determined based on the equivalent capacitance, initial charging voltage, and discharge cutoff voltage. The energy required for the main control circuit and hierarchical storage module to complete the power-down process can be determined based on the power consumption and processing time during the power-down process. By ensuring that the available energy of the supercapacitor bank is greater than or equal to the energy required for the main control circuit and hierarchical storage module to complete order settlement and data storage, the supercapacitor bank can support the main control circuit and hierarchical storage module to complete the power-down process before the output voltage drops to the preset cutoff voltage.

[0086] In one specific implementation, if the time required for the main control circuit and hierarchical storage module to complete order settlement and write hot order data is short, a supercapacitor bank with a smaller equivalent capacitance can be selected to reduce the footprint and component cost of the control motherboard. If it is necessary to continue writing a large amount of order archive data or device operation logs after a power outage, the equivalent capacitance of the supercapacitor bank can be increased, or multiple supercapacitors can be connected in series and parallel to increase available energy and thus extend the temporary power supply time.

[0087] In another specific implementation, the main control circuit can adjust the power-down handling strategy based on the voltage state of the supercapacitor bank. When the output voltage of the supercapacitor bank is detected to be higher than a first voltage threshold, the main control circuit continues to write order archive data and device operation logs after writing order hot data; when the output voltage of the supercapacitor bank is detected to be lower than the first voltage threshold but higher than a preset cutoff voltage, the main control circuit prioritizes the writing of order hot data and reduces or suspends the writing of unnecessary archive data; when the output voltage of the supercapacitor bank is detected to be close to the preset cutoff voltage, the main control circuit enters a low-power state or stops new storage write operations. Thus, power-down handling tasks can be dynamically allocated based on the remaining power supply capacity of the supercapacitor bank.

[0088] In another embodiment, the capacity selection of the supercapacitor bank can be configured in conjunction with the write strategy of the hierarchical storage module. For example, the FRAM memory is used for fast writing of order hot data, so the supercapacitor bank must ensure that the order hot data writing in the FRAM memory is completed before the output voltage drops to a preset cutoff voltage; the Flash memory is used for writing order archive data and device operation logs, so when the available energy of the supercapacitor bank is large, the main control circuit can further complete the data writing to the Flash memory. When the available energy of the supercapacitor bank is insufficient to support complete archiving, the main control circuit can supplement the archive data in the Flash memory based on the order hot data stored in the FRAM memory after power is restored.

[0089] With the above settings, the equivalent capacitance, initial charging voltage, and discharge cutoff voltage of the supercapacitor bank are no longer arbitrarily set, but are matched with the power consumption and processing time of the main control circuit and hierarchical storage module during power failure. This improves the adaptability of the supercapacitor bank's temporary power supply capacity to order settlement and data storage needs, reducing the risk of incomplete power failure processing due to insufficient supercapacitor bank capacity or unreasonable discharge cutoff voltage settings.

[0090] Optional, refer to Figure 2In one embodiment, the power-down power supply circuit 40 further includes an isolation circuit 401. The isolation circuit 401 is connected to the power supply input terminal, the power supply output terminal, and the supercapacitor bank 402, respectively. When the power supply input terminal is normally powered, it transfers the electrical energy from the power supply input terminal to the power supply output terminal and charges the supercapacitor bank 402 through a controlled charging path. When the power supply input terminal loses power, the isolation circuit 401 prevents the supercapacitor bank 402 from discharging back to the power supply input terminal and allows the supercapacitor bank 402 to supply power back to the power supply output terminal, so as to maintain the main control circuit 20 and the hierarchical storage module 30 to continue to work within a preset time.

[0091] It should be noted that the power input terminal refers to the node that controls the motherboard 1 to receive external power or the output voltage of the previous stage power conversion circuit. For example, the power input terminal can be the 12V input node of the motherboard 1. The power output terminal refers to the node used to supply power to the subsequent circuits of the motherboard 1. For example, the power output terminal can be connected to the main control circuit 20, the hierarchical storage module 30, or the subsequent DC-DC conversion circuit. The power output terminal is not limited to directly supplying power to the main control chip; it can also first undergo voltage conversion before supplying power to the main control circuit 20 and the hierarchical storage module 30.

[0092] In this embodiment, the isolation circuit 401 includes a switching transistor Q44, a current-limiting resistor network, a first bias resistor R696, a first isolation diode D103, and a second isolation diode D106. The anode of the first isolation diode D103 is connected to the power supply input terminal, and the cathode is connected to the power supply output terminal. Thus, when the power supply input terminal is normally powered, the electrical energy at the power supply input terminal can be transferred to the power supply output terminal through the first isolation diode D103 to power the subsequent circuits of the control motherboard 1; when the power supply input terminal is powered off, the first isolation diode D103 is reverse-biased and cut off, which can prevent the electrical energy of the power supply output terminal or the supercapacitor group 402 from flowing back into the power supply input terminal.

[0093] It should be noted that an isolation diode is a diode used to form a unidirectional conduction path. An isolation diode can be a common rectifier diode, a Schottky diode, or other devices with unidirectional conduction characteristics. In this embodiment, the first isolation diode D103 is used to form a unidirectional power supply path from the power supply input terminal to the power supply output terminal, and the second isolation diode D106 is used to form a unidirectional return path from the supercapacitor bank 402 to the power supply output terminal.

[0094] The anode of the second isolation diode D106 is connected to the supercapacitor bank 402, and the cathode is connected to the power supply output terminal. Therefore, when the power input terminal loses power and the power supply output terminal voltage drops, the supercapacitor bank 402 can supply power back to the power supply output terminal via the second isolation diode D106, maintaining a usable voltage at the power supply output terminal for a short period. Since the first isolation diode D103 prevents current from flowing to the power supply input terminal when power is lost, the electrical energy released by the supercapacitor bank 402 is primarily used to maintain the critical circuitry connected to the power supply output terminal, and is not discharged in reverse to the power supply input terminal or external power lines.

[0095] It should be noted that energy recovery refers to the process by which the supercapacitor bank 402 releases stored electrical energy to the power output after a power outage at the power input terminal. This energy recovery process is used to maintain low-power critical circuits such as the main control circuit 20 and the hierarchical storage module 30 to complete charging shutdown, order settlement, and data storage, and is not used to maintain the DC charging pile to continue charging the vehicle at high power.

[0096] When the power input terminal is normally powered, it also charges the supercapacitor bank 402 through a current-limiting resistor network and a switching transistor Q44. Specifically, one end of the current-limiting resistor network is connected to the power input terminal, the other end is connected to the first terminal of the switching transistor Q44, the second terminal of the switching transistor Q44 is connected to the supercapacitor bank 402, and the controlled terminal of the switching transistor Q44 is connected to the first bias resistor R696. When there is a valid power supply voltage at the power input terminal, the first bias resistor R696 provides a bias voltage to the controlled terminal of the switching transistor Q44, causing the switching transistor Q44 to be in a conducting or controlled conducting state. The electrical energy at the power input terminal is transferred to the supercapacitor bank 402 through the current-limiting resistor network and the switching transistor Q44, thereby charging the supercapacitor bank 402.

[0097] It should be noted that the switch Q44 refers to a semiconductor switching device capable of changing the conduction state between its first and second terminals according to a controlled electrical signal. The switch Q44 can be a transistor, MOSFET, IGBT, or other controllable switching device. The controlled terminal of the switch Q44 can correspond to the base of a transistor, the gate of a MOSFET, or other control terminals; the first and second terminals of the switch Q44 can correspond to the collector and emitter, or the drain and source, depending on the specific device type. This embodiment does not limit the specific type of the switch Q44.

[0098] In one feasible implementation, the current-limiting resistor network includes multiple current-limiting resistors connected in parallel. One end of each current-limiting resistor is connected to the power supply input terminal, and the other ends are connected to the first terminal of the switching transistor Q44. The second terminal of the switching transistor Q44 is connected to the positive terminal of the supercapacitor bank 402, and the controlled terminal of the switching transistor Q44 receives a bias voltage through the first bias resistor R696. Therefore, when the voltage of the supercapacitor bank 402 is low, the power supply input terminal can charge the supercapacitor bank 402 through the multiple current-limiting resistors and the switching transistor Q44, and the current-limiting resistor network limits the inrush current during the initial charging stage, preventing excessive current surges from the supercapacitor bank 402 at the power supply input terminal during charging.

[0099] In another feasible implementation, the first bias resistor R696 can also form a bias voltage limiting structure with the voltage regulator. The voltage regulator can be connected between the controlled terminal of the switching transistor Q44 and the preset reference terminal to limit the voltage range of the controlled terminal of the switching transistor Q44, so that the switching transistor Q44 is in a preset on state during the charging process of the supercapacitor bank 402. This reduces the risk of overcharging of the supercapacitor bank 402 and maintains the charging voltage of the supercapacitor bank 402 within a voltage range suitable for power-off recovery.

[0100] Under normal power supply conditions, the power input terminal supplies power to the power output terminal via the first isolation diode D103, while simultaneously charging the supercapacitor bank 402 via the current-limiting resistor network and the switching transistor Q44. At this time, the second isolation diode D106 can be in a cutoff or non-primarily conducting state according to the voltage relationship between the supercapacitor bank 402 and the power output terminal, so that the power output terminal is mainly powered by the power input terminal, while the supercapacitor bank 402 is mainly in a charging or holding state.

[0101] In the power-off state, the voltage at the power supply input terminal drops or disappears, and the first isolation diode D103 is cut off, preventing the power supply output terminal and the supercapacitor bank 402 from discharging in reverse to the power supply input terminal. Simultaneously, when the voltage at the power supply output terminal is lower than the voltage of the supercapacitor bank 402 and the conduction condition of the second isolation diode D106 is met, the supercapacitor bank 402 returns power to the power supply output terminal via the second isolation diode D106. After receiving temporary power, the power supply output terminal can continue to supply power to the main control circuit 20 and the hierarchical storage module 30, enabling the main control circuit 20 to still complete charging stop control, order settlement data generation, and data writing even after an abnormal interruption of the input power supply.

[0102] When the power supply is restored, the power input terminal receives a valid supply voltage again, the first isolation diode D103 turns on again, and the power input terminal supplies power to the power output terminal again. Afterwards, the power input terminal can recharge the supercapacitor bank 402 through the current-limiting resistor network and the switching transistor Q44, restoring the supercapacitor bank 402 to its preset energy storage state, preparing for the next power outage protection.

[0103] Through the above configuration, the first isolation diode D103 provides an input power supply path during normal power supply and prevents reverse discharge during power failure; the second isolation diode D106 provides a return path from the supercapacitor bank 402 to the power supply output terminal during power failure; the current-limiting resistor network and the switching transistor Q44 enable controlled charging of the supercapacitor bank 402 during normal power supply, reducing charging surges. Therefore, the isolation circuit 401 enables a power supply structure that coordinates normal power supply, controlled charging, and power failure return path between the power supply input terminal, power supply output terminal, and supercapacitor bank 402, thereby improving the stability and availability of the power failure power supply circuit 40.

[0104] Optionally, in one embodiment, refer to Figure 3 The power-down detection circuit 10 includes a sampling voltage divider branch, a reference voltage divider branch, and a comparator U8. The sampling voltage divider branch is connected between the input power supply terminal and the ground terminal to generate a sampling signal based on the voltage at the input power supply terminal. The reference voltage divider branch is connected between the auxiliary power supply terminal and the ground terminal to generate a reference signal. The comparator U8 receives the sampling signal and the reference signal respectively, and outputs a power supply status detection signal to the power-down detection pin PD3_LVDR of the main control circuit 20 based on the comparison result between the sampling signal and the reference signal.

[0105] It should be noted that the input power terminal refers to the node that controls the main board 1 to receive external power or the output voltage of the previous stage power circuit. In this embodiment, the input power terminal can be the DC input node of the main board 1, such as a power supply node used to reflect whether the DC charging pile is still in an effective power supply state.

[0106] It should be noted that the auxiliary power supply terminal refers to the power node in the control motherboard 1 used to provide a stable voltage to the low-voltage detection circuit. The auxiliary power supply terminal can be formed by stepping down and regulating the input power supply terminal, or it can be provided by the low-voltage power supply circuit on the control motherboard 1. The auxiliary power supply terminal is used to provide a relatively stable voltage source for the reference voltage divider branch.

[0107] In this embodiment, the sampling voltage divider branch includes a first voltage divider resistor, a second voltage divider resistor, and a Zener diode. The first and second voltage divider resistors are connected in series between the input power supply terminal and the ground terminal, and the connection node between the first and second voltage divider resistors serves as sampling node 101. After the voltage at the input power supply terminal is divided by the first and second voltage divider resistors, a sampling signal corresponding to the change in the input power supply terminal voltage is formed at sampling node 101. Therefore, comparator U8 does not need to directly detect the higher voltage at the input power supply terminal, but instead detects the sampled signal after voltage division.

[0108] It should be noted that sampling node 101 refers to the connection point between the first voltage divider resistor and the second voltage divider resistor used for outputting the sampling signal. The voltage at sampling node 101 changes with the voltage at the input power supply terminal, and therefore can be used as a basis for determining whether the input power supply has failed.

[0109] In this embodiment, the Zener diode is connected in parallel with the second voltage divider resistor. That is, one end of the Zener diode is connected to the sampling node 101, and the other end is connected to the ground terminal. With this connection method, when a transient overvoltage occurs at the input power supply terminal or the voltage of the sampling node 101 rises abnormally, the Zener diode can provide amplitude limiting protection for the sampling node 101, reducing the risk of overvoltage impact on the input terminal of comparator U8.

[0110] It should be noted that a Zener diode is a diode device that can provide voltage limiting near a preset voltage. In this embodiment, the Zener diode mainly protects the sampling node 101 and the input terminal of comparator U8. It can also be replaced by a transient suppression diode, a clamping diode, or other protective devices with voltage clamping function.

[0111] In this embodiment, the reference voltage divider branch includes a third voltage divider resistor, a fourth voltage divider resistor, and a first filter capacitor. The third and fourth voltage divider resistors are connected in series between the auxiliary power supply terminal and the ground terminal, and the connection node between the third and fourth voltage divider resistors serves as the reference node 102. The voltage at the auxiliary power supply terminal is divided by the third and fourth voltage divider resistors to form a reference signal at the reference node 102. The first filter capacitor is connected between the reference node 102 and the ground terminal to filter out voltage fluctuations at the reference node 102, keeping the reference signal relatively stable.

[0112] It should be noted that reference node 102 refers to the connection point between the third and fourth voltage divider resistors used to output the reference signal. The voltage at reference node 102 can be determined based on the auxiliary power supply voltage and the resistance ratio of the third and fourth voltage divider resistors. For example, when the auxiliary power supply is a low-voltage stable power supply and the third and fourth voltage divider resistors have the same resistance value, reference node 102 can output a reference signal that is approximately half the voltage at the auxiliary power supply terminal.

[0113] It should be noted that the reference signal refers to the reference voltage signal used for comparison with the sampled signal. The magnitude of the reference signal can be set according to the normal voltage at the input power supply terminal, the power failure judgment threshold, and the voltage division ratio of the sampling voltage divider branch. By adjusting the correspondence between the reference signal and the sampled signal, the power failure judgment condition of the power failure detection circuit 10 can be set.

[0114] In this embodiment, the first input terminal of comparator U8 is connected to sampling node 101, and the second input terminal of comparator U8 is connected to reference node 102. Specifically, sampling node 101 can be connected to the first input terminal of comparator U8 via a first input resistor, and reference node 102 can be connected to the second input terminal of comparator U8 via a second input resistor. By setting the first and second input resistors, the current entering the input terminal of comparator U8 can be limited, and the influence of external interference on the input terminal of comparator U8 can be reduced.

[0115] The output of comparator U8 is connected to the power-down detection pin PD3_LVDR of the main control circuit 20 via output resistor R18. Comparator U8 outputs a power supply status detection signal corresponding to the state based on the comparison result between the sampled signal received at the first input and the reference signal received at the second input. When the sampled signal meets the comparison condition corresponding to normal power supply, the power supply status detection signal is in the normal power supply state; when the sampled signal does not meet the comparison condition corresponding to normal power supply, the power supply status detection signal switches to the power-down state. The main control circuit 20 can determine whether the input power supply has failed by detecting the power supply status detection signal received at the power-down detection pin PD3_LVDR.

[0116] It should be noted that comparator U8 refers to a circuit used to compare the magnitudes of two input signals and output a corresponding state signal. Comparator U8 can be a standalone comparator U8, or it can be implemented by an operational amplifier, a voltage comparator unit, or a comparator module integrated within the main control circuit 20. The output of comparator U8 can be a high or low level signal, or it can output a periodic signal corresponding to the input power supply state when the input power supply sampling signal has periodic changes.

[0117] It should be noted that the power-down detection pin PD3_LVDR is the input port of the main control circuit 20 used to receive the power supply status detection signal. The main control circuit 20 can determine whether the power supply status detection signal meets the normal power supply conditions by reading the level state, number of level changes, pulse interval, or frequency state of the power-down detection pin PD3_LVDR.

[0118] In one feasible implementation, an output resistor R18 is provided between the output terminal of comparator U8 and the power-down detection pin PD3_LVDR, and an output filter capacitor can also be provided between the power-down detection pin PD3_LVDR and the ground terminal. The output resistor R18 and the output filter capacitor can limit the current and filter the power supply status detection signal, reducing the impact of transient jumps or noise at the output terminal of comparator U8 on the judgment result of the main control circuit 20. A decoupling capacitor can also be connected between the power supply terminal and the ground terminal of comparator U8 to improve the power supply stability of comparator U8.

[0119] Under normal power supply conditions, the voltage at the input power supply terminal, after passing through the sampling voltage divider branch, forms a sampling signal corresponding to normal power supply at sampling node 101. Comparator U8, based on the comparison result between the sampling signal and the reference signal, outputs a power supply status detection signal corresponding to normal power supply to the main control circuit 20. After the main control circuit 20 detects that the power supply status detection signal meets the normal power supply conditions, it controls the DC charging pile to maintain normal operation.

[0120] In a power-off state, the voltage at the input power supply terminal drops or disappears, and the sampling signal at sampling node 101 drops accordingly. When the sampling signal no longer meets the comparison conditions corresponding to normal power supply, the power supply status detection signal output by comparator U8 changes. After the main control circuit 20 detects that the power supply status detection signal does not meet the normal power supply conditions, it confirms that the input power supply has failed and triggers the power-off processing procedure. The power-off processing procedure may include outputting a charging stop control signal to cut off the charging circuit 3, obtaining the meter reading and order status of the current charging order, generating order settlement data, and writing the order hot data into the hierarchical storage module 30.

[0121] With the above configuration, the sampling voltage divider branch can convert the voltage at the input power supply terminal into a sampling signal suitable for comparator U8 detection, the Zener diode can provide amplitude limiting protection for sampling node 101, the reference voltage divider branch can provide a stable reference signal, and comparator U8 can output a power supply status detection signal in a timely manner based on the comparison result between the sampling signal and the reference signal. Therefore, the main control circuit 20 can promptly identify the power failure state when the input power supply experiences an abnormal drop, and complete charging stop, order settlement, and data storage during the temporary power supply period provided by the power failure power supply circuit 40.

[0122] Optionally, in one embodiment, the hierarchical storage module 30 includes a first memory and a second memory, both of which are connected to the main control circuit 20. After confirming a power outage, the main control circuit 20 prioritizes writing the order hot data corresponding to the current charging order into the first memory. After writing the order hot data, it writes the order archive data and device operation logs into the second memory. Thus, even when the temporary power supply provided by the power outage circuit 40 is limited in duration, the main control circuit 20 can prioritize ensuring that critical data required for order recovery and settlement is preserved.

[0123] It should be noted that the terms "first" and "second" in "first memory" and "second memory" are only used to distinguish different storage objects or different storage areas, and do not limit their physical location or storage medium. The first memory and the second memory can be two independent memory chips, two different storage areas within the same memory chip, or a storage structure formed by combining the on-chip storage area of ​​the main control chip with external memory.

[0124] In one feasible implementation, the first memory is a non-volatile fast memory used to quickly write order hot data in the event of a power outage. The order hot data may include one or more of the following: order identifier of the current charging order, starting meter reading, current meter reading, order start time, power outage time, order status, charging amount, and verification information. When power is lost, the main control circuit 20 first reads the current meter reading, generates the charging amount based on the current meter reading and the starting meter reading, and then writes the order identifier, current meter reading, charging amount, and order status into the first memory.

[0125] In one specific embodiment, the first memory is a ferroelectric memory. Ferroelectric memory features fast write speed and data retention after power failure, making it suitable for storing order hot data that must be prioritized for disk storage during power outages. After confirming a power failure, the main control circuit 20 can assemble the current order's order identifier, initial meter reading, current meter reading, order status, and verification information into a hot data record, and write this hot data record into the ferroelectric memory. After writing is complete, the main control circuit 20 can read the hot data record and perform verification to confirm that the order hot data has been effectively saved.

[0126] It should be noted that "priority saving" means that during power failure processing, the main control circuit 20 determines the writing order based on data importance and recovery needs, ensuring that data that can be used to restore order status and complete order settlement is written to the memory before other data. Priority saving does not require that other data be completely ignored; rather, it means that when temporary power supply time is insufficient, critical data is prioritized for successful writing.

[0127] In one specific embodiment, the second memory is flash memory. After the order hot data is written to the first memory and verified, the main control circuit 20 can write the order archive data and equipment operation logs to the flash memory. Because flash memory has a large capacity, it is suitable for storing complete order records and equipment operation logs over a relatively long period. If the temporary power supply provided by the power-off circuit 40 is insufficient to complete the writing of all archive data, the main control circuit 20 can prioritize ensuring the completion of writing the order hot data in the first memory, and after the input power is restored, continue to generate or supplement the order archive data based on the order hot data stored in the first memory.

[0128] In one embodiment, the main control circuit 20 writes to the hierarchical storage module 30 according to the following process during a power outage: First, the main control circuit 20 outputs a charging stop control signal to cut off the charging circuit 3; then, the main control circuit 20 reads the meter reading and order status of the current charging order and generates order settlement data; next, the main control circuit 20 extracts order hot data from the order settlement data and writes the order hot data into the first memory; after the first memory is written, the main control circuit 20 updates the order status to the power outage settlement status; then, the main control circuit 20 writes the order archive data and device operation log into the second memory. This writing sequence avoids directly writing a large amount of archive data in the initial stage of a power outage, thus avoiding the use of temporary power supply time and improving the success rate of saving critical order data.

[0129] In another embodiment, the main control circuit 20 can also add verification information to the order hot data. The verification information can be generated based on the order identifier, meter reading, order status, and power outage time. After the input power is restored, the main control circuit 20 reads the order hot data from the first memory and determines whether the order hot data is complete based on the verification information. If the verification passes, the main control circuit 20 restores the order status based on the order hot data and writes the corresponding order to the second memory; if the verification fails, the main control circuit 20 can generate an exception record and write the exception record to the second memory for subsequent verification by maintenance personnel or the platform.

[0130] In another embodiment, multiple circular storage areas can be configured in the first memory. Each time power fails, the main control circuit 20 writes the latest order hot data to the current circular storage area and updates the write flag after writing is complete. After the input power is restored, the main control circuit 20 can read the latest order hot data with a valid write flag and passed verification. The circular storage areas reduce the impact of repeated writing to the same storage area during repeated power failures and improve the efficiency of locating the latest order hot data upon power recovery.

[0131] In another embodiment, the second memory can be divided into an order archive area and a log area. The order archive area is used to store complete order records, and the log area is used to store device operation logs. During the power failure processing phase, the main control circuit 20 can only write the necessary order archive summary and power failure log; after the input power is restored, it then completes the complete order archive data based on the hot order data in the first memory. Thus, both write speed during power failure and data integrity after power restoration can be considered.

[0132] Through the above configuration, the first memory can prioritize saving order hot data during power outages, enabling the DC charging pile to restore the order status and complete order settlement based on the order hot data after the input power is restored. The second memory can save archived order data and equipment operation logs, making order records and equipment status records more complete. The first and second memories work together to form a hierarchical storage structure, which can prioritize the preservation of critical order data during the limited temporary power supply provided by the supercapacitor group 402, thereby reducing the risk of order data loss and abnormal order status.

[0133] This application also provides a power failure protection method for DC charging piles, referring to... Figure 4 .

[0134] In this embodiment, the power failure protection method includes steps S100~S500: Step S100: Obtain the power supply status detection signal from the power failure detection circuit 10; Step S200: If the target frequency signal is not detected in the power supply status detection signal, it is determined that the input power supply has failed. Step S300: Output a charging stop control signal to cut off the charging circuit 3, and obtain the meter reading and order status of the current charging order, and generate order settlement data based on the meter reading and the order status; Step S400: Write the order settlement data into the hierarchical storage module 30, and enter a low-power state after the order settlement data is written; Step S500: Wake up from the low power state according to the preset wake-up cycle, and perform a reset operation when the target frequency signal is detected.

[0135] Specifically, this method can be applied to the aforementioned control motherboard 1 and executed by the main control circuit 20 within the control motherboard 1. During the operation of the DC charging pile, the main control circuit 20 acquires a power supply status detection signal from the power failure detection circuit 10 and determines whether the input power supply is in a normal power supply state based on the power supply status detection signal. When the main control circuit 20 does not detect the target frequency signal in the power supply status detection signal, it determines that the input power supply has failed and enters the power failure protection process.

[0136] It should be noted that the target frequency signal refers to the periodic signal output from the power-down detection circuit 10 to the main control circuit 20 when the input power supply is normal, reflecting that the input power supply is in a normal state. For example, the target frequency signal can be a square wave signal corresponding to the mains frequency, or it can be other periodic pulse signals obtained according to the state transition of the input power supply. The target frequency signal is not limited to a fixed 50Hz signal, and can also be set to a periodic signal within other preset frequency ranges according to the power supply frequency of the area where the DC charging pile is located or the specific design of the power-down detection circuit 10.

[0137] In this embodiment, the main control circuit 20 can receive a power supply status detection signal through the power failure detection pin PD3_LVDR. The main control circuit 20 checks whether a target frequency signal exists in the power supply status detection signal within a preset detection window. If the main control circuit 20 detects the target frequency signal within the preset detection window, it determines that the input power supply is in a normal power supply state, and the DC charging pile remains in normal operation. If the main control circuit 20 does not detect the target frequency signal within the preset detection window, or does not detect the target frequency signal within multiple consecutive preset detection windows, it determines that the input power supply has failed.

[0138] It should be noted that the preset detection window refers to the detection time period used by the main control circuit 20 to determine whether the power supply status detection signal contains the target frequency signal. The preset detection window can be set according to the period of the target frequency signal. For example, when the target frequency signal is a periodic signal corresponding to the 50Hz mains frequency, the preset detection window can be set to a time period that can cover one or more signal periods to avoid misjudgment due to transient interference.

[0139] Upon detecting a power outage, the main control circuit 20 outputs a charging stop control signal to disconnect the charging circuit 3. Specifically, the main control circuit 20 can output a charging stop control signal to the charging circuit control unit of the DC charging pile, causing the contactors, relays, power switches, or other switching devices in the charging circuit 3 to disconnect, thereby stopping the DC charging pile from outputting charging power to the vehicle. This avoids the charging circuit 3 being in an uncertain state when the input power is abnormally interrupted.

[0140] After outputting the charging stop control signal, the main control circuit 20 acquires the meter reading and order status of the current charging order. Specifically, the main control circuit 20 can read the current meter reading through the meter communication interface and retrieve the order status of the current charging order from the order management data. The main control circuit 20 generates order settlement data based on the current meter reading and order status. For example, the main control circuit 20 can determine the charging amount of the current charging order based on the difference between the initial meter reading and the current meter reading, and generate order settlement data by combining the order status, order start time, power outage time, and billing rules.

[0141] It should be noted that the "obtaining the meter reading and order status of the current charging order" in the power outage protection process is not limited to obtaining the above data for the first time after a power outage. The main control circuit 20 can also periodically cache the meter reading and order status during normal charging, recall the most recently cached data after confirming a power outage, and read the latest meter reading again if temporary power supply allows, thereby improving the accuracy of order settlement data.

[0142] After generating order settlement data, the main control circuit 20 writes the order settlement data into the hierarchical storage module 30. Specifically, the main control circuit 20 can first extract the hot data of the order from the order settlement data and write the hot data into the first memory in the hierarchical storage module 30; after the hot data is written, the order archive data and equipment operation logs are then written into the second memory. Thus, when the temporary power supply provided by the power failure circuit 40 is limited in time, priority can be given to ensuring that the key data used for order recovery and order settlement is saved.

[0143] In one feasible implementation, the order hot data includes an order identifier, initial meter reading, current meter reading, order status, power outage time, and verification information. After the main control circuit 20 writes the above order hot data into the first memory, it can read the written data and perform verification. If the verification passes, it is determined that the order settlement data has been written successfully; if the verification fails, the main control circuit 20 can rewrite the order hot data if the temporary power supply still meets the operating conditions, or record a write error flag.

[0144] After the order settlement data is written, the main control circuit 20 enters a low-power state. Before entering the low-power state, the main control circuit 20 can shut down unnecessary power-consuming peripherals, such as the display interface, some communication interfaces, indicator light driver circuits, or other peripherals that do not affect power recovery detection, while retaining the power-down detection pin PD3_LVDR and the timed wake-up function. This reduces the power consumption of the main control circuit 20 during power outages and extends the duration of temporary power supply provided by the supercapacitor bank 402.

[0145] It should be noted that low-power state refers to the operating state of the main control circuit 20 after power-down processing, which reduces its operating power consumption. Low-power state may include reducing the operating frequency of the main control circuit 20, shutting down some peripherals, disabling unnecessary communication interfaces, entering sleep mode or standby mode, etc. Low-power state does not require the main control circuit 20 to completely stop working, but at least retains the functions required for power restoration detection.

[0146] Subsequently, the main control circuit 20 wakes up from the low-power state according to a preset wake-up cycle and re-detects the presence of the target frequency signal in the power supply status detection signal. If the main control circuit 20 still does not detect the target frequency signal after waking up, it determines that the input power supply has not been restored, and the main control circuit 20 re-enters the low-power state. If the main control circuit 20 detects the target frequency signal after waking up, it determines that the input power supply has been restored and performs a reset operation.

[0147] It should be noted that the preset wake-up period refers to the time interval during which the main control circuit 20 periodically recovers from a low-power state. The preset wake-up period can be set according to the temporary power supply capability of the supercapacitor group 402, the power consumption of the main control circuit 20, and the power recovery detection requirements. When the preset wake-up period is shorter, the main control circuit 20 can detect power recovery more quickly; when the preset wake-up period is longer, the average power consumption during power outages can be further reduced.

[0148] It should be noted that the reset operation refers to the initialization or restart operation performed by the main control circuit 20 after detecting the restoration of the input power, in order to bring the control program and peripheral devices back into a controllable operating state. The reset operation can include software reset, peripheral device reinitialization, order status restoration, stored data reading, and running status clearing, and is not limited to hardware reset.

[0149] In one feasible implementation, after the main control circuit 20 performs a reset operation, it reads the order hot data stored in the hierarchical storage module 30, restores the order status of the current charging order based on the order hot data, and supplements the order settlement data by writing it into the second memory or uploading it to the operation platform. If the order hot data indicates that there were unsettled charging orders before the power supply failed, the main control circuit 20 completes the order archiving based on the order hot data; if the order hot data does not exist or the verification fails, the main control circuit 20 can generate an exception log and write the exception log into the second memory in the hierarchical storage module 30.

[0150] Using the above method, the main control circuit 20 can promptly identify input power failure based on the power supply status detection signal output by the power failure detection circuit 10. During the temporary power supply provided by the power failure power supply circuit 40, it sequentially completes the processes of cutting off the charging circuit 3, acquiring meter readings and order status, generating order settlement data, and writing to the hierarchical storage module 30. After the data writing is completed, the main control circuit 20 enters a low-power state and periodically wakes up to detect whether the input power has been restored. Thus, while reducing power consumption during power failures, it ensures that the DC charging pile can still complete order settlement and save key data after an abnormal interruption of the input power.

[0151] Optionally, in one embodiment, after acquiring the power supply status detection signal from the power-down detection circuit 10, the main control circuit 20 can determine whether a target frequency signal exists in the power supply status detection signal by detecting the level change of the power-down detection pin PD3_LVDR. Specifically, the main control circuit 20 samples the power-down detection pin PD3_LVDR within a preset detection window and counts the number of level transitions within the preset detection window, and / or counts the time interval between two adjacent level transitions. Based on the number of level transitions and / or the time interval between adjacent level transitions, the main control circuit 20 determines whether the power supply status detection signal on the power-down detection pin PD3_LVDR conforms to the change pattern corresponding to the target frequency signal.

[0152] It should be noted that the number of level transitions refers to the number of times the power-down detection pin PD3_LVDR changes from high to low, from low to high, or both within a preset detection window. The main control circuit 20 can count only the number of rising edges, only the number of falling edges, or both simultaneously. By counting the number of level transitions, it can be determined whether the power supply status detection signal still exhibits periodic variation characteristics.

[0153] It should be noted that the time interval between adjacent level transitions refers to the time difference between two consecutive level changes on the power-down detection pin PD3_LVDR. This time interval can be used to calculate the period or frequency of the power supply status detection signal. For example, when the power supply status detection signal is a square wave signal corresponding to the input power frequency, the time interval between adjacent level transitions of the same type can correspond to one signal period, and the time interval between adjacent level transitions of different types can correspond to half a signal period.

[0154] In one feasible implementation, the main control circuit 20 counts the number of rising and falling edges of the power-down detection pin PD3_LVDR within a preset detection window. If the number of rising and / or falling edges detected within the preset detection window meets a preset count condition, the main control circuit 20 continues to determine whether the frequency of the power supply status detection signal is within a preset frequency range based on the time interval between adjacent level transitions. If the number of level transitions meets the preset count condition and the frequency of the power supply status detection signal is within the preset frequency range, the main control circuit 20 determines that a target frequency signal exists in the power supply status detection signal, and the input power supply is in a normal power supply state.

[0155] It should be noted that the preset frequency range refers to the frequency range used to determine whether the power supply status detection signal belongs to the target frequency signal. Since actual circuits may have detection errors, signal jitter, or slight fluctuations in the power supply frequency, the preset frequency range can be set to an allowable range that includes the target frequency. For example, when the target frequency signal is a periodic signal corresponding to a 50Hz input power supply, the preset frequency range can be set to 45Hz to 55Hz, or it can be set to a wider or narrower range depending on the actual circuit precision.

[0156] In another feasible implementation, the main control circuit 20 can calculate the frequency of the power supply status detection signal based on the time interval between adjacent level transitions of the same type. For example, the main control circuit 20 records the time interval between two consecutive rising edges, obtains the period of the power supply status detection signal based on this time interval, and then calculates the frequency of the power supply status detection signal based on the period. If the calculated frequency is within a preset frequency range, it is determined that a target frequency signal exists in the power supply status detection signal; if the calculated frequency is outside the preset frequency range, it is determined that the power supply status detection signal is abnormal.

[0157] In another feasible implementation, the main control circuit 20 can determine a power failure based on the detection results of multiple consecutive preset detection windows. If the main control circuit 20 does not detect the target frequency signal within one preset detection window, it can temporarily delay determining that the input power supply is down and instead continue to the next preset detection window for detection. If the main control circuit 20 fails to detect the target frequency signal within multiple consecutive preset detection windows, it determines that the input power supply has failed. This reduces the risk of misjudging a power failure due to transient interference, single sampling anomalies, or signal glitches.

[0158] It should be noted that multiple consecutive preset detection windows refer to multiple detection time periods that are sequentially adjacent in time or arranged at preset intervals. Using multiple consecutive preset detection windows for judgment allows the power failure detection result to be independent of a single detection result, thereby improving the reliability of power failure detection. The number of consecutive preset detection windows can be set according to the power failure response speed and anti-interference requirements, for example, to two, three, or more detection windows.

[0159] In one specific implementation, if the main control circuit 20 does not detect a valid level transition within a preset detection window, it determines that there is no target frequency signal within that preset detection window; or, if the main control circuit 20 detects a level transition, but the frequency calculated based on the time interval between adjacent level transitions is not within a preset frequency range, it also determines that there is no valid target frequency signal within that preset detection window. When the above situations occur in multiple consecutive preset detection windows, the main control circuit 20 determines that the input power supply has failed and triggers the subsequent power failure protection process.

[0160] In another specific embodiment, if the power supply status detection signal remains at a high or low level within a preset detection window, the main control circuit 20 can determine that no target frequency signal is detected on the power-down detection pin PD3_LVDR. If the power supply status detection signal exhibits level transitions, but the transition interval is too long, too short, or unstable, causing the calculated frequency to deviate from the preset frequency range, the main control circuit 20 can determine that the power supply status detection signal does not meet normal power supply conditions. Therefore, the main control circuit 20 can not only identify a power-down state where the target frequency signal completely disappears, but also identify a power supply anomaly state corresponding to an abnormal power supply frequency in the power supply status detection signal.

[0161] Optionally, in one embodiment, after the main control circuit 20 generates order settlement data based on the meter reading and order status of the current charging order, the main control circuit 20 does not directly write all the order settlement data into the same storage area at once. Instead, according to the importance of the data and the power failure recovery requirements, the order settlement data is divided into hot order data and archived order data, and stored in the order of writing hot order data first, followed by archived order data and device operation logs.

[0162] Specifically, after confirming a power outage, the supercapacitor bank 402 in the power outage power supply circuit 40 provides temporary power to the main control circuit 20 and the hierarchical storage module 30. During this temporary power supply period, the main control circuit 20 first extracts order hot data from the order settlement data and preferentially writes the order hot data into the first memory in the hierarchical storage module 30. The order hot data may include at least one of the following: order identifier, initial meter reading, current meter reading, order status, power outage time, and verification information.

[0163] It should be noted that the order identifier is data used to uniquely or relatively uniquely distinguish the current charging order. The order identifier can be an order number, transaction serial number, local order number, order number issued by the platform, or a temporary order number generated by the main control circuit 20. By saving the order identifier, the data saved before the power outage can be matched with the corresponding charging order after the input power is restored.

[0164] It should be noted that verification information refers to data used to determine whether order hot data is complete and whether a write or read error has occurred. Verification information may include one or more of the following: checksum, cyclic redundancy check code, hash value, write flag, data length, and version number. When writing order hot data, the main control circuit 20 can generate verification information based on the order identifier, starting meter reading, current meter reading, order status, and power outage time, and write the verification information along with the order hot data into the first memory.

[0165] In one feasible implementation, before writing the order hot data, the main control circuit 20 first reads the initial meter reading and the current meter reading of the current charging order, and determines the charging capacity of the current charging order based on the difference between the initial meter reading and the current meter reading. Subsequently, the main control circuit 20 writes the order identifier, initial meter reading, current meter reading, charging capacity, order status, power outage time, and verification information as a set of order hot data into the first memory. Therefore, even if the order archive data has not been completely written to the second memory, the control motherboard 1 can restore the order status and complete the order settlement based on the order hot data in the first memory after the input power is restored.

[0166] It should be noted that "write complete" means that the main control circuit 20 can confirm that the target data has been saved to the corresponding memory. Write completion can be confirmed through reading the checksum, the write response signal, the write completion flag, or the memory status register. Write completion is not limited to writing all order settlement data; it can be confirmed first for hot order data.

[0167] Once the order hot data writing is complete, the main control circuit 20 writes the order archive data and / or device operation logs to the second memory in the hierarchical storage module 30. The order archive data may include complete order records, billing results, charging duration, charging capacity, order termination reason, platform synchronization status, and other information. The device operation logs may include power outage time, power outage recovery time, charging stop control signal output records, charging circuit 3 disconnection records, supercapacitor power supply status, storage write results, and abnormal flags, etc.

[0168] In one feasible implementation, if the temporary power supply time provided by the supercapacitor bank 402 is sufficient, the main control circuit 20, after completing the writing of the order hot data, continues to write the complete order archive data and equipment operation log to the second memory. If the temporary power supply time is insufficient, the main control circuit 20 can write only the order archive summary and power outage log to the second memory, and after the input power is restored, supplement the order archive data based on the order hot data in the first memory. Thus, in the case of limited power outage time, priority can be given to ensuring the successful saving of critical order data, while also taking into account the complete archiving requirements after power restoration.

[0169] Through the above implementation, after a power outage, the main control circuit 20 can first write the order hot data into the first memory to prioritize the preservation of key data required for order recovery and settlement. After the order hot data is written, the order archive data and / or equipment operation logs are then written into the second memory to improve the integrity of order records and equipment operation records. Therefore, the risk of losing key order data can be reduced within the limited temporary power supply time provided by the supercapacitor bank 402, and the reliability of order settlement after power failure of the DC charging pile can be improved.

[0170] This application also provides a DC charging pile, as shown in the reference. Figure 5 The DC charging station includes a control motherboard 1, a charging circuit 3, and a meter 2. The control motherboard 1 can be the same as the one described in the previous embodiment. The controlled terminal of the charging circuit 3 is connected to the control motherboard 1, and the meter 2 is located within the charging circuit 3. The control motherboard 1 controls the charging circuit 3 to be turned on or off during normal operation of the DC charging station, and outputs a stop-charging control signal when the input power fails, thereby cutting off the charging circuit 3 through its controlled terminal.

[0171] It should be noted that a DC charging pile refers to a charging device used to output DC charging energy to electric vehicles. It may include a power conversion module, a charging gun, a control motherboard 1, a metering unit, a communication unit, a charging circuit 3, and a protection circuit, etc. In this embodiment, the DC charging pile is not limited to a specific power level; it can be a DC fast charging pile in a public charging station, or a DC charging device in a park, parking lot, or other dedicated scenario.

[0172] In this embodiment, charging circuit 3 is used to transmit charging energy from the DC charging pile to the vehicle. Charging circuit 3 may include a power output terminal, a DC bus, a charging contactor, a relay, an electronic switch, a fuse, a charging gun output terminal, and related sampling circuitry. The controlled terminal of charging circuit 3 is connected to the control motherboard 1, enabling the control motherboard 1 to control the conduction state of charging circuit 3 through the controlled terminal. When the control motherboard 1 outputs a charging enable signal, charging circuit 3 can be in a conducting state; when the control motherboard 1 outputs a charging stop control signal, charging circuit 3 can be disconnected to stop outputting charging energy to the vehicle.

[0173] It should be noted that the controlled end refers to the control interface or control node in the charging circuit 3 used to receive external control signals. The controlled end can be the control end of a contactor coil, the drive end of a relay, the drive end of a power switch, or the communication control end of the charging circuit control unit. The connection between the control motherboard 1 and the controlled end is not limited to a direct electrical connection; it can also be indirectly connected through a drive circuit, isolation circuit 401, or communication interface.

[0174] In one embodiment, meter 2 is disposed in charging circuit 3 to measure the charging amount corresponding to the current charging order. Meter 2 can be disposed on the output side of charging circuit 3 or in the power transmission path between power module and charging gun. Control motherboard 1 is communicatively connected to meter 2 to acquire meter readings during charging and to read the current meter reading when the input power fails, so as to generate order settlement data based on the current meter reading and order status.

[0175] It should be noted that meter 2 refers to the metering device used to measure electrical energy data in charging circuit 3. Meter 2 can be a standalone electricity meter or a metering module integrated into the DC charging pile. Meter 2 can output data such as cumulative electrical energy, voltage, current, power, and time-of-use electricity. The control motherboard 1 can read the data from meter 2 through a wired communication interface or internal bus.

[0176] During normal charging, the control board 1 controls the charging circuit 3 to be activated based on the user's order initiation, vehicle communication status, and equipment operating status. The DC charging pile outputs DC charging energy to the vehicle through the charging circuit 3. The meter 2 measures the electrical energy transmitted during the charging process. The control board 1 periodically reads the meter reading and updates the order status and charging data of the current charging order based on the meter reading.

[0177] When the input power fails, the power failure detection circuit 10 in the control motherboard 1 outputs a power supply status detection signal, and the main control circuit 20 confirms the power failure based on the power supply status detection signal. At this time, the supercapacitor group 402 in the power failure power supply circuit 40 provides temporary power to at least the main control circuit 20 and the hierarchical storage module 30. During the temporary power supply period, the main control circuit 20 outputs a stop-charging control signal to the controlled end of the charging circuit 3, causing the charging circuit 3 to disconnect, thereby stopping the DC charging pile from outputting charging energy to the vehicle.

[0178] After charging circuit 3 is disconnected, the main control circuit 20 reads the current meter reading of meter 2 and obtains the order status of the current charging order. The main control circuit 20 generates order settlement data based on the current meter reading, the initial meter reading, and the order status, and writes the order settlement data into the hierarchical storage module 30. Specifically, the main control circuit 20 can first write the order identifier, initial meter reading, current meter reading, order status, power outage time, and verification information into the first memory, and then write the order archive data and equipment operation log into the second memory.

[0179] In one embodiment, the DC charging pile may further include a platform communication unit. After the input power is restored, the control motherboard 1 reads the order hot data stored in the hierarchical storage module 30 and restores the order status before the power outage based on the order hot data. If the order hot data verification passes, the control motherboard 1 can complete the order archiving based on the order hot data and upload the power outage settlement result to the operation platform through the platform communication unit. If the order hot data verification fails, the control motherboard 1 can generate an exception log and store the exception log in the hierarchical storage module 30 for subsequent maintenance or order verification.

[0180] In another embodiment, the control motherboard 1 can also detect the disconnection status of the charging circuit 3 after outputting the charging stop control signal. For example, the control motherboard 1 can detect the status of the contactor auxiliary contacts, the output voltage status, or the current status to confirm whether the charging circuit 3 has been disconnected. If the control motherboard 1 detects that the charging circuit 3 has not been disconnected as expected, it can write this abnormal status as a device operation log into the hierarchical storage module 30 and provide a fault prompt after power is restored.

[0181] With the above settings, the DC charging pile can promptly disconnect the charging circuit via the control motherboard when the input power fails, and generate order settlement data using the current meter reading. Since the control motherboard completes charging stop, meter reading, settlement, and data saving during the temporary power supply provided by the power outage circuit, the risk of charging order data loss, abnormal order status, or settlement failure due to power outages can be reduced, thus improving the operational reliability of the DC charging pile in abnormal power outage scenarios.

[0182] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the power-down protection method in the above embodiments.

[0183] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0184] The aforementioned computer-readable storage medium may be included in the DC charging pile or control motherboard; or it may exist independently and not assembled into the DC charging pile or control motherboard.

[0185] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0186] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0187] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0188] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A control motherboard for a DC charging pile, the DC charging pile including a charging circuit, the charging circuit being used to connect to a power receiving terminal, characterized in that, include: The power failure detection circuit is used to detect the power supply status and output a corresponding power supply status detection signal. The main control circuit is connected to the power failure detection circuit. It is used to determine whether the input power has failed based on the power supply status detection signal, and after confirming the power failure, it outputs a stop charging control signal to the charging circuit of the DC charging pile to cut off the electrical connection between the charging circuit and the power receiving terminal. It also obtains the meter reading and order status of the current charging order to generate order settlement data based on the meter reading and order status. The tiered storage module includes a first memory and a second memory. The first memory is used to store order hot data that needs to be saved first when power is lost, and the second memory is used to store order archive data and equipment operation logs. The power-off power supply circuit includes a supercapacitor bank, which is used to provide temporary power to at least the main control circuit and the hierarchical storage module during a power outage, so that the main control circuit and the hierarchical storage module can complete order settlement and data storage before the temporary power supply fails. The equivalent capacitance, initial charging voltage, and discharge cutoff voltage of the supercapacitor bank are set according to the power consumption and processing time of the main control circuit and the hierarchical storage module during the power failure process, so that the main control circuit and the hierarchical storage module can complete order settlement and data storage before the output voltage of the supercapacitor bank drops to the preset cutoff voltage.

2. The control motherboard as described in claim 1, characterized in that, The first memory is a Flash memory; The second storage device is a TF card.

3. The control motherboard as described in claim 1, characterized in that, The power-off power supply circuit also includes an isolation circuit, which is used to supply power to the power output terminal and charge the supercapacitor bank when the power input terminal is normally powered, and to prevent the supercapacitor bank from discharging in reverse to the power input terminal when the power input terminal is powered off, and to allow the supercapacitor bank to return power to the power output terminal. The isolation circuit includes: A switching transistor, wherein the controlled terminal of the switching transistor is connected to a first bias resistor; the first terminal of the switching transistor is connected to a current-limiting resistor network; and the second terminal of the switching transistor is connected to the supercapacitor bank. The first isolation diode has its anode connected to the power supply input terminal and its cathode connected to the power supply output terminal. The second isolation diode has its anode connected to the supercapacitor bank and its cathode connected to the power supply output terminal.

4. The control motherboard as described in claim 1, characterized in that, The power failure detection circuit includes a sampling voltage divider branch, a reference voltage divider branch, and a comparator; The sampling voltage divider branch includes a first voltage divider resistor, a second voltage divider resistor, and a Zener diode. The first voltage divider resistor and the second voltage divider resistor are connected in series between the input power supply terminal and the ground terminal. The Zener diode is connected in parallel with the second voltage divider resistor. The connection node between the first voltage divider resistor and the second voltage divider resistor serves as the sampling node. The reference voltage divider branch includes a third voltage divider resistor, a fourth voltage divider resistor, and a first filter capacitor. The third voltage divider resistor and the fourth voltage divider resistor are connected in series between the auxiliary power supply terminal and the ground terminal. The first filter capacitor is connected between the connection node between the third voltage divider resistor and the fourth voltage divider resistor and the ground terminal. The connection node between the third voltage divider resistor and the fourth voltage divider resistor serves as the reference node. The first input terminal of the comparator is connected to the sampling node, the second input terminal of the comparator is connected to the reference node, and the output terminal of the comparator is connected to the power-down detection pin of the main control circuit via an output resistor to output the power supply status detection signal to the main control circuit.

5. A power failure protection method for DC charging piles, characterized in that, Applied to a control motherboard as described in any one of claims 1 to 4, the method comprises: Acquire the power supply status detection signal from the power failure detection circuit; When the power supply status detection signal indicates that the input power supply does not meet the normal power supply conditions, it is determined that the input power supply has failed. Output a charging stop control signal to cut off the charging circuit, and obtain the meter reading and order status of the current charging order, and generate order settlement data based on the meter reading and order status; The order settlement data is written to the hierarchical storage module, and then enters a low-power state after the order settlement data is written. Wake up from the low-power state according to a preset wake-up cycle, and perform a reset operation when the target frequency signal is detected.

6. The method as described in claim 5, characterized in that, The determination that the input power supply has failed when no target frequency signal is detected in the power supply status detection signal includes: Within a preset detection window, count the number of level transitions and / or the time interval between adjacent level transitions; Based on the number of level transitions and / or the time interval, determine whether the target frequency signal exists in the power supply status detection signal; If no target frequency signal is detected within multiple consecutive preset detection windows, or if the frequency of the power supply status detection signal is outside the preset frequency range, it is determined that the input power supply has lost power.

7. The method as described in claim 5, characterized in that, The step of writing the order settlement data into the hierarchical storage module includes: The hot data of orders is preferentially written into the first memory of the hierarchical storage module; Once the order hot data writing is complete, the order archive data and / or equipment operation logs are written to the second memory in the hierarchical storage module; The order hot data includes at least one of the following: order identifier, initial meter reading, current meter reading, order status, power outage time, and verification information.

8. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 5 to 7.

9. A DC charging pile, characterized in that, Includes the control motherboard as described in any one of claims 1 to 4; A charging circuit is used for electrical connection with the powered terminal, and the controlled end of the charging circuit is connected to the control motherboard; An electricity meter is installed in the charging circuit.

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