Millimeter wave large dynamic log detector and peak detection circuit thereof

Abstract

The application discloses a kind of millimeter wave big dynamic log detection and peak detection circuit thereof, peak detection circuit includes common mode and difference mode detection circuit, common mode elimination circuit and filter output circuit;Common mode and difference mode detection circuit is used to output common mode detection current and first difference mode detection current;Common mode elimination circuit is used to eliminate the influence caused by common mode detection current to first difference mode detection current, output second difference mode detection current filter output circuit is used to filter high frequency component in second difference mode detection current, output third difference mode detection current.The application eliminates the influence caused by common mode detection current to first difference mode detection current, guarantees that the detection dynamic of big dynamic millimeter wave log detection meets the requirements, can satisfy the use requirement of millimeter wave big dynamic log peak detection.

Description

Technical Field

[0001] This invention belongs to the field of microwave integrated circuits, and in particular relates to a millimeter-wave large dynamic logarithmic detector and its peak detection circuit. Background Technology

[0002] Existing millimeter-wave logarithmic detectors employ multi-stage cascaded limiting amplifiers. The output of each limiting amplifier is connected to a peak detection circuit. The sum of the detected currents is then converted to voltage by an output stage transimpedance amplifier, thus achieving a logarithmic response to the input signal amplitude. Current peak detection circuits utilize a transistor to detect the common-mode voltage, and two parallel transistors form an absolute value circuit to achieve full-wave detection. These are then converted to common-mode and differential-mode detection voltages via load resistors. While this circuit structure can achieve peak detection within a 12dB dynamic range in a single stage, the influence of the common-mode detection current significantly reduces the overall detection dynamic range in multi-stage cascaded configurations at millimeter-wave frequencies. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a millimeter-wave large dynamic logarithmic detector and its peak detection circuit.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A peak detection circuit for a millimeter-wave large dynamic range logarithmic detector, comprising: The common-mode and differential-mode detection circuit is used to perform peak detection on the input common-mode voltage VCOMM and output the common-mode detection current, and to detect the input differential-mode positive voltage VI+ and differential-mode negative voltage VI- and output the first differential-mode detection current. A common-mode cancellation circuit is used to eliminate the influence of the common-mode detector current on the first differential-mode detector current, and output a second differential-mode detector current; and The filter output circuit is used to filter out the high-frequency components in the second differential mode detector current and output the third differential mode detector current.

[0005] Furthermore, the common-mode and differential-mode detection circuits include The common-mode detector sub-circuit is used to perform peak detection on the input common-mode voltage VCOMM and output the common-mode detection current. The differential mode detector circuit is used to detect the input differential mode voltages VI+ and VI- and output the first differential mode detection current. The first bias sub-circuit is used to provide bias current for the common-mode detector sub-circuit and the differential-mode detector sub-circuit, and to set the bias voltage for the common-mode detector sub-circuit and the differential-mode detector sub-circuit.

[0006] Furthermore, the common-mode detector sub-circuit includes a transistor Q1 and a resistor R1; the base of the transistor Q1 serves as the input terminal of the common-mode detector sub-circuit and is connected to the common-mode voltage VCOMM; the collector of the transistor Q1 is electrically connected to the second terminal of the resistor R1 through a common-mode cancellation circuit, and the first terminal of the resistor R1 is connected to the supply voltage VCC; the emitter of the transistor Q1 serves as the bias terminal of the common-mode detector sub-circuit and is electrically connected to the output terminal of the first bias sub-circuit.

[0007] Furthermore, the differential mode detector circuit includes transistors Q2 and Q3 and resistor R2. The base of transistor Q2 serves as the negative input terminal of the differential mode detector circuit, used to connect to the differential mode negative voltage VI-. The base of transistor Q3 serves as the positive input terminal of the differential mode detector circuit, used to connect to the differential mode positive voltage VI+. The collectors of transistors Q2 and Q3 are electrically connected and then serve as the output terminal of the differential mode detector circuit, which is electrically connected to the filter output circuit. The collectors of transistors Q2 and Q3 are also electrically connected to the second terminal of resistor R2 through a common mode cancellation circuit. The first terminal of resistor R2 is connected to the supply voltage VCC. The emitters of transistors Q2 and Q3 are electrically connected and then serve as the bias terminal of the differential mode detector circuit, which is electrically connected to the output terminal of the first bias sub-circuit.

[0008] Furthermore, the first bias sub-circuit includes a transistor Q4 and a resistor R3. The base of the transistor Q4 serves as the input terminal of the first bias sub-circuit and is used to connect to the first bias voltage Vbais1. The collector of the transistor Q4 serves as the output terminal of the first bias sub-circuit and is electrically connected to the bias terminals of the common-mode detector sub-circuit and the differential-mode detector sub-circuit, respectively. The emitter of the transistor Q4 is grounded through the resistor R3.

[0009] Furthermore, the common-mode cancellation circuit adopts a mirror current source circuit. The collector of transistor Q1 is electrically connected to the second terminal of resistor R1 through the reference branch of the mirror current source circuit. The collectors of transistors Q2 and Q3 are electrically connected to the second terminal of resistor R2 through the mirror branch of the mirror current source circuit.

[0010] Furthermore, the common-mode cancellation circuit includes PMOS transistors M1 and M2. PMOS transistor M1 forms the reference branch of the current mirror circuit, and PMOS transistor M2 forms the mirror branch of the current mirror circuit. The drain of PMOS transistor M1 is electrically connected to its gate, the gate of PMOS transistor M2, and the collector of transistor Q1, respectively. The source of PMOS transistor M1 is electrically connected to the second terminal of resistor R1. The source of PMOS transistor M2 is electrically connected to the second terminal of resistor R2. The drain of PMOS transistor M2 is electrically connected to the collectors of transistors Q2 and Q3.

[0011] Furthermore, the filter output circuit includes a transistor Q6 and a second bias sub-circuit. The base of the transistor Q6 is electrically connected to its collector and then electrically connected as the output terminal of the sum and difference mode detector sub-circuit. The emitter of the transistor Q6 is electrically connected to the second bias sub-circuit, which is used to bring the transistor Q6 to a critical saturation state.

[0012] Furthermore, the second bias sub-circuit includes a transistor Q5 and a resistor R4. The base of the transistor Q5 serves as the input terminal of the second bias sub-circuit and is used to connect to the second bias voltage Vbais2. The collector of the transistor Q5 serves as the output terminal of the second bias sub-circuit and is electrically connected to the emitter of the transistor Q6. The emitter of the transistor Q5 is grounded through the resistor R4.

[0013] A millimeter-wave large dynamic range logarithmic detector includes a transimpedance amplifier and multiple cascaded limiting amplifiers. A peak detector is connected to the output of each limiting amplifier. The peak detectors employ the peak detection circuit of the millimeter-wave large dynamic range logarithmic detector as described in any of the above claims. The outputs of each peak detector are electrically connected to each other and then electrically connected to the input of the transimpedance amplifier, which is used to convert current signals into output voltages.

[0014] In this invention, the common-mode detection current is mirrored to the differential-mode detection current port through a mirror current source circuit for cancellation, eliminating the common-mode influence of the differential-mode output port and ensuring that the detection dynamics of the large dynamic range millimeter-wave logarithmic detector meet the requirements. The differential-mode detection current is driven by a transistor, thereby using the transistor's junction capacitance instead of the chip capacitance to filter out the high-frequency components in the second differential-mode detection current, which can significantly reduce the chip area. This invention is highly versatile, applicable to SiGeBCD technology, and can meet the usage requirements of millimeter-wave large dynamic range logarithmic peak detectors. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a diagram showing the overall topology of a millimeter-wave large dynamic logarithmic detector.

[0016] Figure 2 This is a circuit diagram of a traditional peak detector.

[0017] Figure 3 This is a structural block diagram of an embodiment of the peak detection circuit of the millimeter-wave large dynamic logarithmic detector of the present invention.

[0018] Figure 4This is a circuit diagram of an embodiment of the peak detection circuit of the millimeter-wave large dynamic logarithmic detector of the present invention.

[0019] Figure 5 The simulation curves show the output third differential mode detector current at different power levels. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0021] Please see Figure 1 This is a block diagram of a large dynamic range logarithmic detector employing a five-stage cascaded limiting amplifier structure. The input signal Vin is processed sequentially by five cascaded limiting amplifiers (A1 to A5). A peak detector (DET1 to DET6) is connected at the signal input and after the output of each amplifier stage, forming six independent detection branches. Each detector converts the AC signal output from the amplifier into DC or quasi-DC current. These currents are summed at subsequent nodes to form the total detection current. Finally, the total detection current is input to the output stage transimpedance amplifier (IV) to complete the current-to-voltage conversion, and the output voltage Vout is logarithmically related to the amplitude of the input signal.

[0022] Please see Figure 2 To detect and sum the peak-to-peak values ​​of the output voltage of each amplifier stage, a full-wave detection structure is used in the peak detection circuit. The emitter of transistor Q1 is connected to the emitters of transistors Q2 and Q3 to perform peak detection on the input common-mode voltage VCOMM. The emitters and collectors of transistors Q2 and Q3 are connected respectively. Since the bases of transistors Q2 and Q3 are connected to the inverted differential-mode positive voltage VI+ and differential-mode negative voltage VI- respectively, transistors Q2 and Q3 form an absolute value circuit. That is, transistors Q2 and Q3 only conduct when their base voltage is positive, thus ensuring that the collectors of transistors Q2 and Q3 always output a positive voltage, which is equivalent to inverting the negative half-cycle signal. Resistor R1 serves as the load for transistor Q1, converting the common-mode detection current into a common-mode detection voltage. Resistor R2 serves as the load for transistors Q2 and Q3, converting the differential-mode detection current into a differential-mode detection voltage.

[0023] The output response relationship of the circuit is as follows: (1) in, The initial differential-mode detection current is specifically the sum of the differential-mode detection current and the common-mode detection current output from transistors Q2 and Q3. Figure 2 In I2; The amplitude of the input differential voltage; For input and output transconductance; The angular frequency of the input signal; t For time; This refers to the common-mode detection current, specifically the common-mode detection current output by transistors Q2 and Q3, which is approximately equal to the common-mode detection current output by transistor Q1. Figure 2 In I 1.

[0024] Expanding equation (1) using Fourier series, we get: (2) The initial differential mode detector current is filtered out by a subsequent filter. After processing the high-frequency components, the final output detector current is obtained. for: (3) In conjunction with a differential limiting amplifier, using Figure 2 While it can achieve single-stage peak detection with 12dB dynamic range, in millimeter-wave detection, the detection dynamics are susceptible to common-mode detection current. The effects of this, especially after multi-stage cascading, can more easily cause a decrease in the dynamic range of the detector.

[0025] Please see Figure 3 , Figure 3 This is a structural block diagram of an embodiment of the peak detection circuit of the millimeter-wave large dynamic range logarithmic detector of the present invention. The peak detection circuit of this embodiment includes common-mode and differential-mode detection circuits, a common-mode cancellation circuit, and a filter output circuit. The common-mode and differential-mode detection circuits are used to perform peak detection on the input common-mode voltage VCOMM, outputting a common-mode detection current, and to detect the input differential-mode positive voltage VI+ and differential-mode negative voltage VI-, outputting a first differential-mode detection current. The common-mode voltage VCOMM is generated in the pre-stage circuit of the millimeter-wave large dynamic range logarithmic detector through the differential-mode positive voltage VI+ and differential-mode negative voltage VI-. The common-mode cancellation circuit is used to cancel the common-mode detection current. For the first differential mode detector current (equivalent to Figure 2 The initial differential mode detector current generated by the intermediate circuit The effect caused by this will result in the output of a second differential mode detector current. The filter output circuit is used to filter out the second differential mode detector current. The high-frequency components in the output third differential mode detector current. .

[0026] The common-mode and differential-mode detection circuit includes a common-mode detection sub-circuit, a differential-mode detection sub-circuit, and a first bias sub-circuit. The common-mode detection sub-circuit is used to perform peak detection on the input common-mode voltage VCOMM and output a common-mode detection current. Please refer to [link to relevant documentation]. Figure 4 The common-mode detector sub-circuit may include a transistor Q1 and a resistor R1. The base of the transistor Q1 serves as the input terminal of the common-mode detector sub-circuit and is connected to the common-mode voltage VCOMM. The collector of the transistor Q1 is electrically connected to the second terminal of the resistor R1 through a common-mode cancellation circuit, and the first terminal of the resistor R1 is connected to the supply voltage VCC. The emitter of the transistor Q1 serves as the bias terminal of the common-mode detector sub-circuit and is electrically connected to the output terminal of the first bias sub-circuit.

[0027] The differential mode detector sub-circuit is used to detect the input differential mode voltages VI+ and VI-, and outputs a first differential mode detection current. The differential mode detector sub-circuit may include transistors Q2 and Q3 and resistor R2. The base of transistor Q2 serves as the negative input terminal of the differential mode detector sub-circuit to receive the negative differential mode voltage VI-, and the base of transistor Q3 serves as the positive input terminal of the differential mode detector sub-circuit to receive the positive differential mode voltage VI+. The collectors of transistors Q2 and Q3 are electrically connected and then serve as the output terminal of the differential mode detector sub-circuit, which is electrically connected to the filter output circuit. The collectors of transistors Q2 and Q3 are also electrically connected to the second terminal of resistor R2 through a common mode cancellation circuit. The first terminal of resistor R2 is connected to the supply voltage VCC. The emitters of transistors Q2 and Q3 are electrically connected and then serve as the bias terminal of the differential mode detector sub-circuit, which is electrically connected to the output terminal of the first bias sub-circuit.

[0028] The first bias sub-circuit is used to provide bias current to the common-mode detector sub-circuit and the differential-mode detector sub-circuit, and to set the bias voltage of the common-mode detector sub-circuit and the differential-mode detector sub-circuit. The first bias sub-circuit may include a transistor Q4 and a resistor R3, with the base of the transistor Q4 serving as the input terminal of the first bias sub-circuit for connecting to a first bias voltage Vbais1. By adjusting the first bias voltage Vbais1, the required bias current can be provided to the common-mode detector sub-circuit and the differential-mode detector sub-circuit, and the bias voltage of the common-mode detector sub-circuit and the differential-mode detector sub-circuit can be set.

[0029] The collector of transistor Q4 serves as the output terminal of the first bias sub-circuit and is electrically connected to the bias terminals of the common-mode detector sub-circuit and the differential-mode detector sub-circuit, respectively. Specifically, it is electrically connected to the emitters of transistors Q1, Q2, and Q3. The emitter of transistor Q4 is grounded through resistor R3.

[0030] The common-mode cancellation circuit can employ a mirror current source circuit. The collector of transistor Q1 is electrically connected to the second terminal of resistor R1 through the reference branch of the mirror current source circuit. The collectors of transistors Q2 and Q3 are electrically connected to the second terminal of resistor R2 through the mirror branch of the mirror current source circuit. In this embodiment, the common-mode cancellation circuit includes PMOS transistors M1 and M2. PMOS transistor M1 forms the reference branch of the mirror current source circuit, and PMOS transistor M2 forms the mirror branch of the mirror current source circuit. The drain of PMOS transistor M1 is electrically connected to its gate, the gate of PMOS transistor M2, and the collector of transistor Q1, respectively. The source of PMOS transistor M1 is electrically connected to the second terminal of resistor R1. The source of PMOS transistor M2 is electrically connected to the second terminal of resistor R2; the drain of PMOS transistor M2 is electrically connected to the collectors of transistors Q2 and Q3.

[0031] The filter output circuit includes a transistor Q6 and a second bias sub-circuit. The base of transistor Q6 is electrically connected to its collector and then serves as the output terminal of the sum and difference mode detector sub-circuit (i.e., the collectors of transistors Q2 and Q3). The emitter of transistor Q6 is electrically connected to the second bias sub-circuit, which is used to bring transistor Q6 to a critical saturation state. In this embodiment, the second bias sub-circuit includes a transistor Q5 and a resistor R4. The base of transistor Q5 serves as the input terminal of the second bias sub-circuit and is connected to a second bias voltage Vbais2. By adjusting the second bias voltage Vbais2, the collector current of transistor Q5 can be adjusted, thereby adjusting the bias voltage of transistor Q6 to bring it to a critical saturation state, which is equivalent to a diode junction capacitance filter. The collector of transistor Q5 serves as the output terminal of the second bias sub-circuit and is electrically connected to the emitter of transistor Q6. The emitter of transistor Q5 is grounded through resistor R4.

[0032] In order to subtract the common-mode detection current at the differential-mode detection port, this embodiment... Figure 2 Based on the circuit, PMOS transistors M1 and M2 were added to form a current mirror, thereby controlling the common-mode detection current generated by transistor Q1. The image is mirrored to the differential mode output for subtraction. Therefore, in this embodiment, the second differential mode detector current... The calculation formula becomes: (4) To make the resistances of resistors R1 and R2 equal, that is, to set R1 = R2, we can make... Figure 4 In This makes This completely cancels out the common-mode detection current, therefore, the second differential-mode detection current... The calculation formula can be simplified to: (5) Then, through Fourier series expansion, we get: (6) The second differential mode detector current After being filtered by the junction capacitance of transistor Q6, its high-frequency components are filtered out, and the output third differential mode detector current is... (correspond Figure 4 In I 7) is: (7) Please see Figure 5 This refers to the third differential mode detector current output at different power levels after adopting the circuit structure of this embodiment. The simulation curve, from Figure 5 It can be seen that the output third differential mode detector current under different power conditions The curves coincide at zero points in the interval from 0 ns to nearly 6 ns, indicating that the third differential mode detector current... It cancels out the component of the common-mode current.

[0033] Therefore, after adopting the circuit structure of this embodiment, the output detection current of the peak detection circuit (i.e., the third differential mode detection current) This circuit only detects the peak value of the input signal, thus canceling out the common-mode current component compared to traditional methods. It is more suitable for multi-stage cascading to form a millimeter-wave high-dynamic-range logarithmic detector. Since this circuit uses the PN junction capacitance of transistor Q6 as a filter, it is suitable for peak detection in millimeter-wave high-dynamic-range circuits.

[0034] In this embodiment, the common-mode detection current is mirrored to the differential-mode detection current port through a mirror current source circuit for cancellation, eliminating the common-mode influence of the differential-mode output port and ensuring that the detection dynamics of the large dynamic range millimeter-wave logarithmic detector meet the requirements. The differential-mode detection current is driven by transistor Q6, thereby using the junction capacitance of transistor Q6 instead of the chip capacitance to filter out the high-frequency components in the second differential-mode detection current, which can greatly reduce the chip area. This embodiment is highly versatile, applicable to SiGe BCD technology, and can meet the usage requirements of millimeter-wave large dynamic range logarithmic peak detectors.

[0035] Please continue reading. Figure 1The present invention also discloses a millimeter-wave large dynamic range logarithmic detector. A preferred embodiment of the millimeter-wave large dynamic range logarithmic detector of the present invention includes a transimpedance amplifier (IV) and multiple cascaded limiting amplifiers, preferably a five-stage cascaded structure, including limiting amplifiers A1 to A5. A peak detector is connected to the output of each limiting amplifier stage, wherein the outputs of limiting amplifiers A1 to A5 are respectively connected to peak detectors DET2 to DET6. Of course, peak detector DET1 can also be connected to the input.

[0036] Peak detectors DET1 to DET6 all employ the peak detection circuit of a millimeter-wave large dynamic logarithmic detector as described in any of the above embodiments; the output terminals of peak detectors DET1 to DET6 are electrically connected to each other and then electrically connected to the input terminal of a transimpedance amplifier (IV), which is used to convert the current signal into an output voltage.

[0037] In this embodiment, the peak detector mirrors the common-mode detection current to the differential-mode detection current port via a current mirror, achieving precise cancellation of the common-mode effect. This significantly improves the purity and linearity of the output signal, effectively expands the detection dynamic range, and ensures that the millimeter-wave logarithmic detector maintains excellent dynamic response performance over a wide input power range. The junction capacitance of the transistor replaces the traditional on-chip capacitor to filter the high-frequency components of the differential-mode detection current, saving chip area, reducing process complexity and manufacturing costs. Simultaneously, it fully leverages the positive role of transistor parasitic capacitance in high-frequency signal processing, improving system integration and frequency adaptability. The millimeter-wave large dynamic range logarithmic detector of this embodiment can achieve stable and reliable logarithmic detection in the millimeter-wave band, possessing good process portability and industrial application prospects. It is suitable for high-performance, highly integrated millimeter-wave large dynamic range logarithmic peak detection systems.

[0038] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A peak detection circuit for a millimeter-wave large dynamic range logarithmic detector, characterized in that: include The common-mode and differential-mode detection circuit is used to perform peak detection on the input common-mode voltage VCOMM and output the common-mode detection current, and to detect the input differential-mode positive voltage VI+ and differential-mode negative voltage VI- and output the first differential-mode detection current. The common-mode cancellation circuit is used to eliminate the influence of the common-mode detector current on the first differential-mode detector current and output the second differential-mode detector current. as well as The filter output circuit is used to filter out the high-frequency components in the second differential mode detector current and output the third differential mode detector current.

2. The peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in claim 1, characterized in that: The common-mode and differential-mode detection circuits include The common-mode detector sub-circuit is used to perform peak detection on the input common-mode voltage VCOMM and output the common-mode detection current. The differential mode detector circuit is used to detect the input differential mode voltages VI+ and VI- and output the first differential mode detection current. The first bias sub-circuit is used to provide bias current for the common-mode detector sub-circuit and the differential-mode detector sub-circuit, and to set the bias voltage for the common-mode detector sub-circuit and the differential-mode detector sub-circuit.

3. The peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in claim 2, characterized in that: The common-mode detector sub-circuit includes a transistor Q1 and a resistor R1; the base of the transistor Q1 serves as the input terminal of the common-mode detector sub-circuit and is connected to the common-mode voltage VCOMM; the collector of the transistor Q1 is electrically connected to the second terminal of the resistor R1 through a common-mode cancellation circuit, and the first terminal of the resistor R1 is connected to the supply voltage VCC; the emitter of the transistor Q1 serves as the bias terminal of the common-mode detector sub-circuit and is electrically connected to the output terminal of the first bias sub-circuit.

4. The peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in claim 3, characterized in that: The differential mode detector circuit includes transistors Q2 and Q3 and resistor R2. The base of transistor Q2 serves as the negative input terminal of the differential mode detector circuit, used to connect to the differential mode negative voltage VI-. The base of transistor Q3 serves as the positive input terminal of the differential mode detector circuit, used to connect to the differential mode positive voltage VI+. The collectors of transistors Q2 and Q3 are electrically connected and then serve as the output terminal of the differential mode detector circuit, which is electrically connected to the filter output circuit. The collectors of transistors Q2 and Q3 are also electrically connected to the second terminal of resistor R2 through a common mode cancellation circuit. The first terminal of resistor R2 is connected to the supply voltage VCC. The emitters of transistors Q2 and Q3 are electrically connected and then serve as the bias terminal of the differential mode detector circuit, which is electrically connected to the output terminal of the first bias sub-circuit.

5. The peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in claim 2, characterized in that: The first bias sub-circuit includes a transistor Q4 and a resistor R3. The base of the transistor Q4 serves as the input terminal of the first bias sub-circuit and is used to connect to the first bias voltage Vbais1. The collector of the transistor Q4 serves as the output terminal of the first bias sub-circuit and is electrically connected to the bias terminals of the common-mode detector sub-circuit and the differential-mode detector sub-circuit, respectively. The emitter of the transistor Q4 is grounded through the resistor R3.

6. The peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in claim 4, characterized in that: The common-mode cancellation circuit adopts a mirror current source circuit. The collector of transistor Q1 is electrically connected to the second terminal of resistor R1 through the reference branch of the mirror current source circuit. The collectors of transistors Q2 and Q3 are electrically connected to the second terminal of resistor R2 through the mirror branch of the mirror current source circuit.

7. The peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in claim 6, characterized in that: The common-mode cancellation circuit includes PMOS transistors M1 and M2. PMOS transistor M1 forms the reference branch of the current mirror circuit, and PMOS transistor M2 forms the mirror branch of the current mirror circuit. The drain of PMOS transistor M1 is electrically connected to its gate, the gate of PMOS transistor M2, and the collector of transistor Q1, respectively. The source of PMOS transistor M1 is electrically connected to the second terminal of resistor R1. The source of PMOS transistor M2 is electrically connected to the second terminal of resistor R2. The drain of PMOS transistor M2 is electrically connected to the collectors of transistors Q2 and Q3.

8. The peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in any one of claims 2 to 7, characterized in that: The filter output circuit includes a transistor Q6 and a second bias sub-circuit. The base of the transistor Q6 is electrically connected to its collector and then electrically connected to the output terminal of the sum and difference mode detector sub-circuit. The emitter of the transistor Q6 is electrically connected to the second bias sub-circuit, which is used to keep the transistor Q6 in a critical saturation state.

9. The peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in claim 8, characterized in that: The second bias sub-circuit includes a transistor Q5 and a resistor R4. The base of the transistor Q5 serves as the input terminal of the second bias sub-circuit and is used to connect to the second bias voltage Vbais2. The collector of the transistor Q5 serves as the output terminal of the second bias sub-circuit and is electrically connected to the emitter of the transistor Q6. The emitter of the transistor Q5 is grounded through the resistor R4.

10. A millimeter-wave large dynamic range logarithmic detector, characterized in that: The device includes a transimpedance amplifier and multiple cascaded limiting amplifiers. A peak detector is connected to the output of each limiting amplifier. The peak detector adopts the peak detection circuit of the millimeter-wave large dynamic logarithmic detector as described in any one of claims 1 to 9. The outputs of each peak detector are electrically connected to each other and then electrically connected to the input of the transimpedance amplifier. The transimpedance amplifier is used to convert the current signal into an output voltage.

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