A test system and test method for a jtag link
By comprehensively testing the basic resources of the JTAG link, the problem of insufficient test coverage in existing technologies is solved, achieving high-coverage testing and fault location, and ensuring the reliability of circuit board test results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-14
Smart Images
Figure CN122386084A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital circuit testing technology, and more specifically, to a testing system and method for a JTAG link. Background Technology
[0002] To address the testing challenges of very large-scale integrated circuits (VLSI), the Joint Test Action Group (JTAG) proposed boundary scan technology. By leveraging the JTAG link, test vectors are injected into the boundary scan cell (BC cell) and other related registers located between the device's I / O pins and internal circuitry, enabling indirect control of the I / O pins and thus allowing for testing of the circuit board's assembly performance.
[0003] To ensure stable and reliable test results, the primary condition is that the JTAG link and related resources on the circuit board are functioning correctly and are consistent with the design documents in the component datasheet and circuit diagram. The correctness of the JTAG link and related test resources can also prevent damage to the circuit board caused by abnormal voltage levels due to resource anomalies. Therefore, it is essential to ensure that the JTAG link resources are functioning correctly and reliably before conducting other boundary scan tests, and to verify through testing that they are consistent with expectations.
[0004] Chinese patent application CN101470170A discloses a JTAG link testing method and apparatus. This system uses a testing method that captures only the status code of one device for each boundary scan device and verifies the feature code of the test vector. The length of the test vector is the number of boundary scan devices plus the length of the test vector feature code; for a typical circuit board, the test vector length is generally within 10 bytes. Chinese patent application CN102645609A discloses a JTAG link testing apparatus and method that verifies only the device's ID Code for each boundary scan device; the test vector length is also generally within 100 bytes.
[0005] The two publicly disclosed patents and existing technologies mentioned above only perform basic testing and verification of simple JTAG link information, such as the boundary scan device ID code, individual device status codes, and the interconnection of the device's JTAG interface. They do not conduct comprehensive testing of information such as the length and default values of all instruction registers, and the length and some predictable voltage levels of data registers. For scenarios requiring comprehensive boundary scan testing, existing methods suffer from insufficient coverage in testing JTAG link resources. Summary of the Invention
[0006] To address the aforementioned problems, this invention provides a testing system and method for JTAG links. Before conducting standard boundary scan tests, the basic resources of the JTAG link are tested to ensure that they are normal, stable, reliable, and consistent with expectations, thereby guaranteeing the reliability of subsequent test results.
[0007] In a first aspect, the present invention provides a testing system for a JTAG link, including a host, a motherboard, a data interface adapter, and a power supply. The power connector interface on the motherboard is connected to the power supply via a power supply cable, and the product under test (DUT) interface on the template is connected to the DUT. The boundary scan chip inside the DUT has a JTAG link and is brought out through a JTAG interface. The USB interface of the host is connected to the JTAG interface of the DUT via a data interface converter. The host runs host computer software, which is used to send test sequences to the JTAG link to complete the testing of all boundary scan chip JTAG links in the JTAG link.
[0008] Secondly, the present invention provides a testing method for a JTAG link, implemented based on the JTAG link testing system described in the first aspect; the testing method includes: Step S1: The host computer software first sends a BYPASS command to all boundary scan chips on the JTAG link, synchronously reads back the data in the command register of the boundary scan chip, then sends data to the data register, synchronously reads back the data in the BYPASS data register of the boundary scan chip, and compares the read-back data with the first expected value. Based on the comparison result, the basic continuity of the JTAG link is tested. Step S2: The host computer software sends a polling instruction to all boundary scan chips to the general data register, reads back the data of the general data register after the instruction is executed, compares the read data with the second expected value, and tests whether all general data registers are normal based on the comparison result; Step S3: The host computer software sends a combination of instructions to all boundary scan chips on the JTAG link. The combination of instructions is a combination of SAMPLE and BYPASS instructions. After the instructions are executed, data is sent to all boundary scan chips on the JTAG link, the response data of the JTAG link is read back, and the read-back response data is compared with the third expected value. The JTAG link test is verified based on the comparison result.
[0009] Furthermore, step S2 specifically includes: Step S21: Send an instruction to all boundary scan chips on the JTAG link. The instruction content is that one boundary scan chip selects a certain general data register, and the other boundary scan chips select the BYPASS register. Step S22: Send data to the JTAG link and read back the data in the ordinary data register. Compare the read-back data with the second expected value to determine whether the ordinary data register of this boundary scan chip is normal. Step S22 can be repeated multiple times. Step S23: Replace the boundary scan chip corresponding to the ordinary data register in step S21. From the first to the last, poll all boundary scan chips on the JTAG link in turn, and repeat steps S21 to S22. Step S24: Change the type of the general data register in step S21, and poll all general data registers that have test value in turn, repeating steps S21 to S23.
[0010] Furthermore, step S3 specifically includes: Step S31: Send instruction combinations to all boundary scan chips on the JTAG link. In the instruction combination, the SAMPLE instruction connects the boundary scan unit inside the boundary scan chip to the JTAG link, while the corresponding BYPASS instruction only connects one bit of the register of the boundary scan chip to the JTAG link, which is equivalent to bypassing the boundary scan chip in the JTAG link. Step S32: Send data to the JTAG link and inject a feature vector Vector1 before sending the data; read back the JTAG link response data, which includes the injected feature vector Vector1, the register value of the boundary scan unit inside the boundary scan chip in response to the SAMPLE instruction, and a constant value of 1 bit of the boundary scan chip in response to the BYPASS instruction; compare the read-back data with the third expected value, and if they are completely consistent, the test passes.
[0011] Furthermore, step S3 also includes: Step S33: Replace with a feature vector Vector2 and repeat step S32; feature vector Vector1 and feature vector Vector2 have the same length.
[0012] Furthermore, step S3 also includes: Step S34: Change the combination of SAMPLE and BYPASS instructions for each boundary scan chip in the instruction combination in step S31, and repeat steps S31 to S33.
[0013] Furthermore, the combination of the SAMPLE and BYPASS instructions in the instruction set adopts either a traversal method or a sampling method. The traversal method shown is based on the SAMPLE and BYPASS instructions of all boundary scan chips. The sampling method involves each boundary scan chip executing the SAMPLE instruction once in turn, while the remaining boundary scan chips execute the BYPASS instruction, and finally all boundary scan chips execute the SAMPLE instruction.
[0014] Furthermore, if in step S31 the instruction combination is that all boundary scan chips execute the SAMPLE instruction, then step S32 needs to be repeated multiple times.
[0015] Furthermore, the method for the host computer software to read back data is as follows: while sending instructions or data to the JTAG link, it will simultaneously remove data of the same length as the sent data bit by bit. This data is the read-back data. If the host computer sends an instruction to the JTAG link, it will read back the data in the instruction register; otherwise, it will read back the data in the data register.
[0016] In summary, before conducting standard boundary scan testing, this invention first tests the basic resources of the JTAG link, including the length and predictable values of all relevant instruction and data registers, the length of the boundary scan unit, and the external state of the boundary scan unit. This ensures that the resources are normal, stable, and reliable, and consistent with expectations (the circuit board netlist file and device description file of the boundary scan chip). This guarantees the reliability of subsequent test results and supports the normal conduct of testing and debugging based on the JTAG link. The specific beneficial effects are as follows: 1. This invention can comprehensively test structural information and components related to the JTAG link of a circuit board, including the length and default values of the instruction register, the length and default values of the general data register, the length of the boundary scan unit of a single boundary scan chip and the default values of some key data, and the length of the boundary scan unit of the entire link. Compared with existing technologies that only test the ID code and individual device status codes, this invention has higher test coverage and more test combination modes. In case of a fault, with the help of complete test information, chip-level and pin-level fault location guidance can be performed.
[0017] 2. This invention uses the SAMPLE instruction to shift out the data bit by bit from the boundary scan unit in the boundary scan chip. Leveraging the boundary scan unit's ability to read default values from external I / O, some key signals directly connected to external I / O in the circuit design are transmitted to a host computer for comparison. This achieves verification testing of the JTAG link-related circuit topology and the level values of key signal points on the circuit board, further improving the probability of detecting potential circuit board faults.
[0018] 3. If all boundary scan chips receive the SAMPLE instruction, all boundary scan units on the JTAG link will be connected in series. Since boundary scan units are usually long, complex boundary scan chips usually number more than 1,000. The total length of test data when multiple boundary scan chips on a single circuit board are combined will exceed 4,000. This test is repeated many times, for example, 100 times, to fully verify the signal integrity of the JTAG link. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of a JTAG link testing system provided in an embodiment of the present invention.
[0020] Figure 2 This is a schematic diagram of the JTAG link-related circuit of the product under test as an example in an embodiment of the present invention.
[0021] Figure 3 A flowchart illustrating a testing method for a JTAG link provided in an embodiment of the present invention. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0024] like Figure 1 As shown, this embodiment of the invention provides a testing system for a JTAG link, including a host, a motherboard, a data interface adapter, and a power supply. The power connector interface on the motherboard is connected to the power supply via a power supply cable, and the product under test (DUT) interface on the template is connected to the DUT. The boundary scan chip inside the DUT has a JTAG link and is brought out through a JTAG interface. The USB interface of the host is connected to the JTAG interface of the DUT via a data interface converter. The host runs host computer software, which is used to send test sequences to the JTAG link to complete the testing of all boundary scan chip JTAG links in the JTAG link.
[0025] Furthermore, one interface of the data interface converter is a JTAG interface to match the JTAG interface of the product under test, and the other interface is configured according to the data interface provided by the host, such as common USB, Type-C, etc. In this embodiment of the invention, the host provides a USB interface, therefore the data interface adapter uses a USB interface. JTAG converter.
[0026] Furthermore, the boundary scan chip inside the product under test (DUT) is typically a common processor, high-speed storage, or switching chip, such as an FPGA, DSP, PowerPC, microcontroller, DDR4, SRIO switch, or network switch chip. These boundary scan chips conform to the IEEE 1149.x standard, possess basic JTAG links, and are described by the equipment vendor using BSDL (Boundary-Scan Description Language) files, which inform the user of the JTAG link resource information. The DUT may contain one or more boundary scan chips.
[0027] like Figure 2 The example product under test (DUT) shown is a complex digital circuit board. Internally, the DUT contains three boundary scan chips: Boundary scan chip 1 is a Xilinx K7 series FPGA processor, while boundary scan chips 2 and 3 are both Xilinx V7 series FPGA processors. These three boundary scan chips are connected via a JTAG bus. Furthermore, the boundary scan chips within the DUT are daisy-chained together and brought out through a connector's external JTAG interface, allowing test sequences to be injected from the connector's JTAG interface and applied to all boundary scan chips. Figure 2 In the example, the JTAG interface directly provides TMS and TCK signals to three boundary scan chips. The JTAG interface provides TDI signal to boundary scan chip 1. The TDI signal of boundary scan chip 1 is connected to the TDI signal of boundary scan chip 2 through printed circuit board traces. The TDI signal of boundary scan chip 2 is connected to the TDI signal of boundary scan chip 3 through printed circuit board traces. The JTAG interface receives the TDI signal of boundary scan chip 3.
[0028] Furthermore, the host computer runs internal host computer software. This software generates test sequences based on a preset test algorithm. Through a data interface converter, the host computer accesses the JTAG interface of the boundary scan chip and sends the test sequences into the JTAG link to perform the test. For example, the host computer software is written in C# programming language. The host computer software sends the generated test sequences through a USB interface and a USB port. The JTAG converter and JTAG interface are used to send JTAG data to the product under test (DUT). Different test sequences are combined to stimulate the testing of the JTAG link structure and key probe points directly connected to the boundary scan chip. The host computer connects via USB interface and USB... The JTAG converter and JTAG interface synchronously receive response sequences. The host computer software runs test algorithms, processes the sent and reported sequence data, determines whether there is a fault in the JTAG link, and if a fault exists, analyzes the fault data to provide pin-level fault location guidance.
[0029] Based on the JTAG link testing system provided above, the following implements a JTAG link testing method, such as... Figure 3 As shown, the test method includes the following steps: Step S1: The host computer software first sends a BYPASS command to all boundary scan chips on the JTAG link, synchronously reads back the data in the instruction register of the boundary scan chip, then sends data to the data register, synchronously reads back the data in the BYPASS data register of the boundary scan chip, and compares the read-back data with the first expected value. Based on the comparison result, the basic connectivity of the JTAG link is tested. The first expected value is determined by the instruction register and BYPASS data register of the boundary scan chip used. For example, for... Figure 2 In this three-chip FPGA boundary scan system, the host computer first sends the instruction sequence 0x3FFFF to the JTAG interface of the three boundary scan chips, and then synchronously reads back the data in the instruction register. In this example, the read-back data in the instruction register should be 0x11451. If the read-back matches, then the host computer sends a data sequence, specifically 3 bits of 0b000, to the JTAG interface of the boundary scan chips, and then synchronously reads back the data in the BYPASS data register. The read-back data in the BYPASS data register should be 0b111. If the read-back matches, then the basic continuity test of the JTAG link is passed.
[0030] Furthermore, the method for the host computer software to read back data is as follows: while sending instructions or data to the JTAG link, it simultaneously reorders data bit by bit, with the same length as the sent data; this data is the read-back data. If the host computer sends an instruction to the JTAG link, it reads back the data from the instruction register; otherwise, it reads back the data from the data register. Wherein: For each boundary scan chip instruction register readback value, the lowest two bits must be 0 or 1, and the values of the higher bits must also be consistent with the values specified in the boundary scan chip BSDL file.
[0031] The readback value of the general data register of each boundary scan chip must be consistent with that specified in the boundary scan chip BSDL file, and the readback value of the BYPASS data register must be 1.
[0032] Step S2: The host computer software sends a polling instruction to all boundary scan chips to access the general data registers, reads back the data from the general data registers after the instruction is executed, compares the read-back data with the second expected value, and tests whether all general data registers are functioning correctly based on the comparison result. Specifically, this includes: Step S21: Send instructions to all boundary scan chips on the JTAG link. The instructions specify that one boundary scan chip should select a specific general data register, while the other boundary scan chips should select the BYPASS register.
[0033] Step S22: Send data to the JTAG link and read back the data from the general data register. Compare the read-back data with the second expected value to determine whether the general data register of this boundary scan chip is normal. This step S22 can be repeated multiple times, with a default of 50 times.
[0034] Step S23: Replace the boundary scan chip corresponding to the ordinary data register in step S21. From the first to the last, poll all boundary scan chips on the JTAG link in turn, and repeat steps S21 to S22.
[0035] Step S24: Change the type of the general data register in step S21, and poll all general data registers that are valuable for testing in turn. Repeat steps S21 to S23.
[0036] The second expected value is determined by the general data registers in the boundary scan chip used. For example, general data registers do not include the boundary scan units and BYPASS registers in the boundary scan chip, but typically include IDCODE registers, USERCODE registers, optional IDCODE registers, and optional BIST (built-in self-test) registers, with a length generally of tens of bits. Boundary scan registers refer to the boundary scan units distributed between the I / O pins and the chip core; the register length is positively correlated with the number of I / O pins, typically thousands of bits. For Figure 2The three FPGA processor boundary scan chips in the example have general data registers including an IDCODE register and a USERCODE register. The instruction code in the IDCODE register is 6 bits (0b001001), and the instruction code in the USERCODE register is 6 bits (0b001000). The IDCODE for the K7 series FPGA processor is 0x03651093, and the IDCODE for the V7 series FPGA processor is 0x03691093. The USERCODE for both the K7 and V7 series FPGA processors can be customized and is defined as 0x12345678.
[0037] In the example, the IDCODE register of the boundary scan chip of the first K7 series FPGA processor on the JTAG link is first verified. Specifically, the host computer software sends an 18-bit instruction sequence 18b001001111111111111 to the JTAG interfaces of the three boundary scan chips. This instruction sequence places the IDCODE register of the K7 between the TDI and TDO interfaces, and the BYPASS registers of the boundary scan chips of the two V7 series FPGA processors between their TDI and TDO interfaces. The host computer software then sends a 34-bit data sequence to the JTAG interfaces of the three boundary scan chips. The readback information from the data register should be 0x0D94424F. This data is the result of concatenating 0x03651093, 1b1, and 1b1 bit by bit. If the readback matches, the test passes. The operation of sending the 34-bit data sequence, reading back the 34-bit data information, and comparing it with 0x0D94424F needs to be repeated 50 times.
[0038] In this example, the IDCODE register of the boundary scan chip of the second V7 series FPGA processor, the IDCODE register of the boundary scan chip of the third V7 series FPGA processor, and the USERCODE register of the boundary scan chip of the first K7 series FPGA processor are also tested and verified sequentially. The testing method is the same as that for the IDCODE register of the boundary scan chip of the first K7 series FPGA processor. After all the above tests are completed, this step is considered successful, and the next step can be performed.
[0039] Step S3: The host computer software sends a combination of commands to all boundary scan chips on the JTAG link. This command combination consists of a SAMPLE command and a BYPASS command. After the commands are executed, data is sent to all boundary scan chips on the JTAG link. The response data of the JTAG link is read back and compared with the third expected value. The comparison result verifies whether the JTAG link test has passed. Specifically, this includes: Step S31: Send instruction combinations to all boundary scan chips on the JTAG link. In the instruction combination, the SAMPLE instruction connects the boundary scan unit inside the boundary scan chip to the JTAG link, while the corresponding BYPASS instruction only connects one bit of the boundary scan chip's register to the JTAG link, which is equivalent to bypassing the boundary scan chip in the JTAG link.
[0040] Step S32: Send data to the JTAG link, injecting a feature vector Vector1 into the first 128 bits of the sent data, based on the originally expected response data length. Then read back the data, which includes the injected feature vector Vector1, the register value of the boundary scan unit inside the boundary scan chip in response to the SAMPLE instruction, and a constant 1-bit value from the boundary scan chip in response to the BYPASS instruction. Compare the read-back response data with the third expected value; if they match completely, the test passes.
[0041] Step S33: Replace with a feature vector Vector2 and repeat step S32. Typically, feature vectors Vector1 and Vector2 can be chosen to have the same length, that is, both are injected into the first 128 bits of the transmitted data.
[0042] Step S34: Change the combination of SAMPLE and BYPASS instructions for each boundary scan chip in the instruction combination in step S31, and repeat steps S31 to S33.
[0043] Furthermore, in step S31, the combination of SAMPLE and BYPASS instructions for each boundary scan chip can be achieved through a traversal method, a sampling method, or other possible methods. The traversal method shown is based on traversing the SAMPLE and BYPASS instructions of all boundary scan chips, and is the most comprehensive and rigorous implementation of step S3. The sampling method involves each boundary scan chip executing the SAMPLE instruction once in turn, while the remaining boundary scan chips execute the BYPASS instruction, and finally, all boundary scan chips execute the SAMPLE instruction. This is the most basic implementation of step S3.
[0044] Furthermore, if in step S31 the instruction combination is that all boundary scan chips execute the SAMPLE instruction, then step S32 needs to be repeated multiple times, for example, 100 times, to verify the signal integrity of the JTAG link at a specific rate.
[0045] Furthermore, in steps S32 and S33, the feature vectors Vector1 and Vector2, representing the first 128 bits during data transmission to the JTAG link, serve to insert a preset end marker into the unpredictable serial scan data stream. This confirms the total length of valid data in the boundary scan link. Combined with the known length of the BYPASS register, the exact number of boundary scan units in the JTAG link can be measured using the feature vectors, and compared to the length described in the BSDL chip. Simultaneously, the feature vectors also verify the signal integrity of the JTAG link. Testing twice with two feature vectors avoids the data stream containing vectors with identical feature vectors, which could affect the accuracy of the test.
[0046] Furthermore, in steps S32 and S33, the feature vectors in the readback response data and the data output by the boundary scan chip in response to the BYPASS command are completely known. The boundary scan chip outputting the SAMPLE command outputs the values of all boundary scan chips. Considering the circuit design of the circuit board, some data is known. In the data comparison stage, the unknown parts need to be masked, and only the known data parts are verified.
[0047] The third expected value is determined jointly by the boundary scan unit in the boundary scan chip when responding to the SAMPLE and BYPASS instructions and the injected feature vector. For Figure 2 The boundary scan chips of the three FPGA processors in the example all have a 6-bit SAMPLE instruction code of 6b000001 and a 6-bit BYPASS instruction code of 6b111111. After responding to the SAMPLE instruction, the boundary scan chip of the K7 series processor is connected to the boundary scan unit between TDI and TDO with a length of 1631. The boundary scan chip of the V7 series processor is placed between TDI and TDO with a length of 3389. After responding to the BYPASS instruction, all three boundary scan chips are placed between TDI and TDO with a 1-bit 1b1.
[0048] In the example, during the first test, the host computer software first sent an 18-bit instruction sequence 18b000001111111111111 to the JTAG interfaces of the three boundary scan chips. The boundary scan chip of the K7 series processor responded with the SAMPLE instruction, while the boundary scan chips of the two V7 series processors responded with the BYPASS instruction. Then, the host computer software began to inject a 1761-bit data sequence into the JTAG link, specifically a 1633-bit data sequence plus a 128-bit feature vector Vector1. The host computer simultaneously read back 1761 bits of response data from the TDO interface.
[0049] In the first test, after receiving 1761 bits of response data, the host computer software performed a three-dimensional verification. The first dimension involved capturing a 128-bit feature vector (Vector1) within a certain window and calculating whether the data length at the end of the feature vector was 1633. If it matched this data, the test passed. The second dimension verified the last two bits of the feature vector. In this example test, this was the 2 bits (2b11) shifted out of the BYPASS registers of the two V7 series processor boundary scan chips. If it matched this data, the test passed. The third dimension involves verifying the last 1631 bits of the data sequence, specifically the data from the boundary scan unit shifted out by the boundary scan chip of the K7 series processor. This data requires a judgment criterion based on the circuit diagram design. In the example, the BootMode pins M2, M1, and M0 of the K7 series processor's boundary scan chip are 3b100, and the critical startup pin INITB is pulled up to 1b1 in the circuit diagram. The levels of pull-up and pull-down resistors on some ordinary I / O pins are also predictable. These pins are all connected to the boundary scan unit of the K7 series processor's boundary scan chip, and their levels are uploaded to the host computer software via a 1631-bit serial data stream. The host computer software verifies whether this data matches the expectations; if they do, the test passes. This completes the first test of step S3.
[0050] In the example, the first test uses a 128-bit feature vector Vector1, which is 0x555500001234567887654321FFFFAAAA. The second test repeats the first test, but the feature vector Vector2 is changed to a 128-bit vector, which is 0xAAAAFFFF876543211234567800005555.
[0051] In the first two tests, the instruction combination for the three boundary scan chips was {SAMPLE, BYPASS, BYPASS}. This example considers that there are only 3 boundary scan chips, and the traversal method is used to test step S3. Therefore, the instructions for the three boundary scan chips also need to be combined as {BYPASS, SAMPLE, BYPASS}, {BYPASS, BYPASS, SAMPLE}, {BYPASS, SAMPLE, SAMPLE}, {SAMPLE, BYPASS, SAMPLE}, {SAMPLE, SAMPLE, SAMPLE}, {SAMPLE, SAMPLE, SAMPLE}, {SAMPLE, SAMPLE, SAMPLE}, a total of 14 more tests are needed.
[0052] When the instruction combination of the three boundary scan chips is {SAMPLE, SAMPLE, SAMPLE}, all boundary scan units of the boundary scan chips are connected to the JTAG link. At this time, the data link length is 8539 bits, namely 1633 bits of K7 link + 3389 bits of V7 link + 3389 bits of V7 link + 128 bits of feature vector. The test needs to be repeated 100 times; only if all repetitions are normal does the test pass, verifying the signal integrity of the JTAG link at the current data rate.
[0053] If any of the above steps fails, the host computer software can provide guidance for fault location based on the overall test results. For example, if a test in step S2 fails, it may indicate an IDCODE error in a boundary scan chip, most likely due to incorrect chip installation. Similarly, if the first dimension test in step S3 fails, depending on the specific anomaly, it may indicate a cold solder joint on the M2 pin of the boundary scan chip or a missing pull-up / pull-down resistor.
[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A testing system for a JTAG link, characterized in that, Includes the host, motherboard, data interface adapter, and power supply; The power connector interface on the motherboard is connected to the power supply via a power supply cable, and the product under test (DUT) interface on the template is connected to the DUT. The boundary scan chip inside the DUT has a JTAG link and is brought out through a JTAG interface. The USB interface of the host is connected to the JTAG interface of the DUT through a data interface converter. The host runs host computer software, which is used to send test sequences to the JTAG link to complete the JTAG link test of all boundary scan chips in the JTAG link.
2. A testing method for a JTAG link, implemented based on the JTAG link testing system described in claim 1, characterized in that, The testing method includes: Step S1: The host computer software first sends a BYPASS command to all boundary scan chips on the JTAG link, synchronously reads back the data in the command register of the boundary scan chip, then sends data to the data register, synchronously reads back the data in the BYPASS data register of the boundary scan chip, and compares the read-back data with the first expected value. Based on the comparison result, the basic continuity of the JTAG link is tested. Step S2: The host computer software sends a polling instruction to all boundary scan chips to the general data register, reads back the data of the general data register after the instruction is executed, compares the read data with the second expected value, and tests whether all general data registers are normal based on the comparison result; Step S3: The host computer software sends a combination of instructions to all boundary scan chips on the JTAG link. The combination of instructions is a combination of SAMPLE and BYPASS instructions. After the instructions are executed, data is sent to all boundary scan chips on the JTAG link, the response data of the JTAG link is read back, and the read-back response data is compared with the third expected value. The JTAG link test is verified based on the comparison result.
3. The testing method for a JTAG link according to claim 2, characterized in that, Step S2 specifically includes: Step S21: Send an instruction to all boundary scan chips on the JTAG link. The instruction content is that one boundary scan chip selects a certain general data register, and the other boundary scan chips select the BYPASS register. Step S22: Send data to the JTAG link and read back the data in the ordinary data register. Compare the read-back data with the second expected value to determine whether the ordinary data register of this boundary scan chip is normal. Step S23: Replace the boundary scan chip corresponding to the ordinary data register in step S21. From the first to the last, poll all boundary scan chips on the JTAG link in turn, and repeat steps S21 to S22. Step S24: Change the type of the general data register in step S21, and poll all general data registers that have test value in turn, repeating steps S21 to S23.
4. The testing method for a JTAG link according to claim 2, characterized in that, Step S22 is repeated multiple times.
5. The testing method for a JTAG link according to claim 2, characterized in that, Step S3 specifically includes: Step S31: Send instruction combinations to all boundary scan chips on the JTAG link. In the instruction combination, the SAMPLE instruction connects the boundary scan unit inside the boundary scan chip to the JTAG link, while the corresponding BYPASS instruction only connects one bit of the register of the boundary scan chip to the JTAG link, which is equivalent to bypassing the boundary scan chip in the JTAG link. Step S32: Send data to the JTAG link and inject a feature vector Vector1 before sending the data; read back the JTAG link response data, which includes the injected feature vector Vector1, the register value of the boundary scan unit inside the boundary scan chip in response to the SAMPLE instruction, and a constant value of 1 bit of the boundary scan chip in response to the BYPASS instruction; compare the read-back data with the third expected value, and if they are completely consistent, the test passes.
6. The testing method for a JTAG link according to claim 5, characterized in that, Step S3 further includes: Step S33: Replace with a feature vector Vector2 and repeat step S32; feature vector Vector1 and feature vector Vector2 have the same length.
7. The testing method for a JTAG link according to claim 6, characterized in that, Step S3 further includes: Step S34: Change the combination of SAMPLE and BYPASS instructions for each boundary scan chip in the instruction combination in step S31, and repeat steps S31 to S33.
8. The testing method for a JTAG link according to claim 7, characterized in that, The combination of the SAMPLE and BYPASS instructions in the instruction set adopts either a traversal method or a sampling method. The traversal method shown is based on the SAMPLE and BYPASS instructions of all boundary scan chips. The sampling method involves each boundary scan chip executing the SAMPLE instruction once in turn, while the remaining boundary scan chips execute the BYPASS instruction, and finally all boundary scan chips execute the SAMPLE instruction.
9. The testing method for a JTAG link according to claim 5, characterized in that, If in step S31 the instruction combination is that all boundary scan chips execute the SAMPLE instruction, then step S32 needs to be repeated multiple times.
10. The testing method for a JTAG link according to any one of claims 2-9, characterized in that, The method for the host computer software to read back data is as follows: while sending instructions or data to the JTAG link, it will simultaneously remove data of the same length as the sent data bit by bit. This data is the read-back data. If the host computer sends an instruction to the JTAG link, it will read back the data in the instruction register; otherwise, it will read back the data in the data register.