Optoelectronic co-packaged photonic transceiver device, method of manufacture, and optoelectronic co-packaged switch

Abstract

The application discloses an optoelectronic co-packaged photonic transceiver device, a preparation method and an optoelectronic co-packaged switch. The device comprises: an optoelectronic hybrid glass substrate integrated with a substrate edge waveguide, an on-chip waveguide and an optical multiplexer / demultiplexer, the optical multiplexer / demultiplexer being connected with the on-chip waveguide and the substrate edge waveguide respectively; a silicon optical PIC chip integrated with a chip edge waveguide, a plurality of optical modulators and a plurality of optical detectors, the chip edge waveguide being connected with the optical modulators and the optical detectors respectively, and the chip edge waveguide being connected with the on-chip waveguide through evanescent wave coupling to realize optical path connection; the optical multiplexer / demultiplexer is used for demultiplexing a multi-wavelength light source input through a single optical fiber into a plurality of single-wavelength lights, transmitting the plurality of single-wavelength lights to the optical modulators to be modulated into high-speed optical signals, and then outputting the high-speed optical signals; and the optical multiplexer / demultiplexer is also used for demultiplexing an input multi-wavelength optical signal into a plurality of single-wavelength lights, transmitting the plurality of single-wavelength lights to the optical detectors to be converted into current signals. The application can improve the bandwidth density of the optoelectronic co-packaged photonic transceiver device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an optoelectronic co-packaged photonic transceiver device, its fabrication method, and an optoelectronic co-packaged switch. Background Technology

[0002] With the exponential growth in demand for generative AI computing power, next-generation data center interconnect bandwidth is rapidly evolving towards 3.2T and 25.6T. Traditional pluggable optical modules, due to high signal loss over long distances, high power consumption, and insufficient bandwidth density, can no longer meet the high-speed interconnect requirements of AI clusters. Co-packaged Optics (CPO) technology, by integrating the optical engine with the computing chip, compresses the electrical signal transmission distance to the sub-millimeter level, significantly reducing link power consumption and increasing bandwidth density, and has become the industry's recognized next-generation core interconnect technology.

[0003] However, in the current mainstream silicon photonics CPO architecture, the CWDM4 demultiplexer based on silicon-based materials has extremely small design tolerance. Even small process deviations during manufacturing can lead to decreased isolation, increased channel crosstalk, low yield, and high cost. In addition, the existing CWDM4 architecture CPO light source requires multiple independent optical fibers for input, which leads to a sharp increase in the fiber density inside the data center, significantly increasing cabling complexity and maintenance costs. Furthermore, in the current solution, photonic devices and electronic circuits are still on the same plane, making it difficult to further improve photonic integration. Summary of the Invention

[0004] The purpose of this application is to provide an optoelectronic co-packaged photonic transceiver device, a manufacturing method, and an optoelectronic co-packaged switch, which improves the product yield and bandwidth density of the optoelectronic co-packaged photonic transceiver device, and reduces fiber density and maintenance costs.

[0005] To address the aforementioned technical problems, embodiments of this application provide an optoelectronic co-packaged photonic transceiver device, comprising: A hybrid optoelectronic glass substrate integrates a substrate edge waveguide, an on-chip waveguide, and an optical multiplexer / demultiplexer, wherein the optical multiplexer / demultiplexer is connected to the on-chip waveguide and the substrate edge waveguide, respectively. The silicon photonics PIC chip integrates a chip edge waveguide, multiple optical modulators, and multiple photodetectors. The chip edge waveguide is connected to the optical modulators and the photodetectors respectively, and the chip edge waveguide is connected to the on-chip waveguide through evanescent wave coupling to achieve optical path connection. The optical multiplexer / demultiplexer is used to demultiplex a multi-wavelength light source input through a single optical fiber into multiple single-wavelength light sources, which are then transmitted to the optical modulator to be modulated into high-speed optical signals and then combined and output; and simultaneously, it is used to demultiplex the input multi-wavelength optical signals into multiple single-wavelength light sources, which are then transmitted to the photodetector to be converted into current signals.

[0006] In other embodiments, the optoelectronic co-packaged photonic transceiver also includes an electrical chip, wherein the two opposing surfaces of the silicon photonic PIC chip are flip-chip-mounted with the electrical chip and the optoelectronic hybrid glass substrate respectively to form a vertical architecture in which electronic links and photonic links are synchronously stacked in three dimensions.

[0007] In other embodiments, the silicon photonics PIC chip has opposing first and second surfaces, and the optoelectronic hybrid glass substrate has opposing first and second substrate surfaces. Electrical connection structures are respectively provided on the first surface, the second surface, the first substrate surface, and the second substrate surface. Furthermore, the silicon photonics PIC chip has a through-silicon via penetrating the first and second surfaces and connecting the electrical connection structures at the first and second surfaces. The optoelectronic hybrid glass substrate also has a glass via penetrating the first substrate surface and the second substrate surface and connecting the electrical connection structures at the first and second substrate surfaces. The first surface is flip-chip mounted on the first substrate surface, and the electrical chip is flip-chip mounted on the second surface. The electrical connection structure of the first surface is bonded to the electrical connection structure of the first substrate surface, and is respectively connected to the optical modulator and the photodetector.

[0008] In other embodiments, the electrical chip integrates a driving circuit and a transimpedance amplifier circuit, and the surface of the electrical chip is provided with an electrical connection structure. The electrical connection structure on the surface of the electrical chip is bonded to the electrical connection structure on the second surface, so as to enable the driving circuit to conduct with the optical modulator and the transimpedance amplifier circuit to conduct with the photodetector.

[0009] In other embodiments, the chip edge waveguide includes a light source input waveguide, a transmit output waveguide, and a receive input waveguide. Each light source input waveguide is connected to one end of a plurality of optical modulators, and the other end of each optical modulator is connected to one of the transmit output waveguides. Each photodetector is connected to one of the receive input waveguides.

[0010] In other embodiments, the optoelectronic co-packaged photonic transceiver also includes: A multi-channel fiber array includes a single input fiber for transmitting the multi-wavelength light source, and a transmitting output fiber and a receiving input fiber for transmitting the multi-wavelength optical signals. The multi-channel fiber array is coupled and fixed to the substrate edge waveguide of the optoelectronic hybrid glass substrate.

[0011] In other embodiments, U-shaped waveguides are provided on both sides of the substrate edge waveguide. The U-shaped waveguides are used to cooperate with the multi-channel fiber array to achieve full-channel alignment between the multi-channel fiber array and the substrate edge waveguide by monitoring the coupling power of the U-shaped waveguides.

[0012] This application also proposes a method for fabricating the optoelectronic co-packaged photonic transceiver device as described above, comprising: The U-shaped waveguides on both sides of the optoelectronic hybrid glass substrate are aligned with the multi-channel fiber array. When the coupling power corresponding to the U-shaped waveguides on both sides reaches the maximum, the end face of the optoelectronic hybrid glass substrate and the end face of the multi-channel fiber array are bonded with end face bonding refractive index matching glue. The fixation is completed by UV curing, baking and temperature cycling treatment. The bump pads of the electrical chip are connected to the pads of the silicon photonics PIC chip, and the solder is melted by heating and pressurizing to achieve electrical connection and fixation between the electrical chip and the silicon photonics PIC chip. The silicon photonics PIC chip and the optoelectronic hybrid glass substrate are aligned by waveguide evanescent wave coupling, and the pads of the silicon photonics PIC chip are docked with the pads of the optoelectronic hybrid glass substrate. The solder is melted by heating and pressurizing, so as to realize the synchronous connection and fixation of the optical path and electrical circuit of the silicon photonics PIC chip and the optoelectronic hybrid glass substrate.

[0013] In other embodiments, the waveguide evanescent wave coupling alignment of the silicon photonics PIC chip and the optoelectronic hybrid glass substrate includes: A single wavelength light is input to the silicon photonics PIC chip through a multi-channel fiber array, and the output power of the single wavelength light output by the silicon photonics PIC chip through the multi-channel fiber array is monitored. When the output power is at its maximum, it is confirmed that the optical path of the silicon photonics PIC chip and the optoelectronic hybrid glass substrate are aligned. The wavelength of the single wavelength light corresponds to the wavelength of the optical modulator of the silicon photonics PIC chip.

[0014] This application also proposes an optoelectronic co-packaged switch, including the optoelectronic co-packaged photonic transceiver device as described above.

[0015] The optoelectronic co-packaged photonic transceiver in this embodiment integrates an optical multiplexer / demultiplexer onto a glass substrate. Compared to silicon-based devices, glass-based optical multiplexers / demultiplexers offer greater design tolerance and superior optical performance, significantly reducing manufacturing difficulty and cost, and improving product yield. Evanescent wave coupling is used to achieve optical path connection between the silicon photonic PIC chip and the glass substrate, realizing a vertical optical path connection between the silicon photonic PIC chip and the glass substrate. This lays the foundation for subsequent three-dimensional stacking of photonic links and further enhances the bandwidth density of the CPO photonic transceiver. External four-wavelength light sources require only a single optical fiber input. The optical multiplexer / demultiplexer demultiplexes the multi-wavelength light sources input via a single optical fiber into multiple single-wavelength beams, reducing fiber density and maintenance costs, saving on the number of light source fibers, and significantly reducing the complexity and maintenance costs of fiber optic cabling in data centers. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 This is a schematic diagram of the structure of a photonic transceiver device co-packaged with optoelectronics provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a photonic transceiver device co-packaged with optoelectronics provided in another embodiment of this application; Figure 3 This is a schematic diagram of the structure of a photonic transceiver device co-packaged with optoelectronics provided in another embodiment of this application; Figure 4 This is a schematic diagram of the structure of the silicon photonics PIC chip in the optoelectronic co-packaged photonic transceiver provided in one embodiment of this application; Figure 5 This is a schematic diagram of the silicon photonic PIC chip in a photonic co-packaged photonic transceiver provided in another embodiment of this application; Figure 6 This is a schematic diagram of the silicon photonic PIC chip in a photonic co-packaged photonic transceiver provided in another embodiment of this application; Figure 7 This is a schematic diagram of the structure of the optoelectronic hybrid glass substrate in the optoelectronic co-packaged photonic transceiver provided in one embodiment of this application; Figure 8 This is a schematic diagram of the structure of the optoelectronic hybrid glass substrate in the optoelectronic co-packaged photonic transceiver provided in another embodiment of this application; Figure 9 This is a schematic diagram of the structure of the optoelectronic hybrid glass substrate in the optoelectronic co-packaged photonic transceiver provided in another embodiment of this application; Figure 10 This is a schematic diagram of optical transmission between the chip edge waveguide of a silicon photonics PIC chip and the on-chip waveguide of an optoelectronic hybrid glass substrate in one embodiment of this application. Figure 11 This is a schematic diagram of step S1 of the fabrication method of the optoelectronic co-packaged photonic transceiver device in one embodiment of this application; Figure 12 This is a schematic diagram of step S2 of the fabrication method of the optoelectronic co-packaged photonic transceiver device in one embodiment of this application; Figure 13 This is a schematic diagram of step S3 of the fabrication method of the optoelectronic co-packaged photonic transceiver device in one embodiment of this application; Figure 14 This is a schematic diagram of the structure of an optoelectronic co-packaged switch provided in one embodiment of this application.

[0018] Explanation of reference numerals in the attached figures: 1. Electrical chip; 101. Bump pad; 2. Silicon photonics PIC chip; 201. First surface; 202. Second surface; 203. Through-silicon via; 204. Electrical connection structure; 205. Optical modulator; 206. Photodetector; 20a. Chip edge waveguide; 207. Light source input waveguide; 208. Transmitting output waveguide; 209. Receiving input waveguide; 3. Optoelectronic hybrid glass substrate; 301. First substrate surface; 302. Second surface; 203. Third surface; 204. Second surface; 205. Second surface; 206. Third surface; 207. Second surface; 208. Second surface; 209. Second surface; 200. Third surface; 200. Second surface; 201. Second surface; 20 ... 303. Substrate surface; 304. Glass via; 305. Electrical connection structure; 306. On-chip waveguide; 307. Optical multiplexer / demultiplexer; 308. U-shaped waveguide; 309. Substrate edge waveguide; 3091. Transmit output waveguide; 3092. Receive input waveguide; 3093. Light source input waveguide; 4. Multi-channel fiber optic array; 501. Switch ASIC chip; 502. Switch PCB; 6. Refractive index matching adhesive. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0020] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] Current CPO solutions are essentially "circuit stacking" rather than "optical path stacking." Photonic devices and electronic circuits remain on the same plane, and the optical signal path does not achieve multi-layer stacking in the vertical direction. The optical engine is still confined to a single-layer planar architecture, becoming a physical ceiling restricting the evolution of CPO to 3.2T or even higher bandwidths. Furthermore, current CPO technology has significant problems in fiber optic applications. Most use a single-fiber, single-wavelength 1310nm transmission scheme. Even CWDM4 (coarse wavelength division multiplexing) architecture CPO light sources require four different wavelength fiber inputs. This results in excessive fiber density, posing significant challenges to data center operations and maintenance, leading to high costs. From a data center layout perspective, high fiber density means more fiber cabling space and a more complex fiber management system. In traditional data centers, fiber cabling already occupies a large amount of physical space, and the higher fiber density brought by CPO technology further exacerbates this problem. Excessive fiber not only increases cabling difficulty but also reduces data center space utilization and creates inconvenience for subsequent equipment expansion and maintenance.

[0022] Furthermore, the silicon photonics manufacturing process faces challenges in isolation and channel crosstalk in CWDM4demux (demultiplexers). The high design difficulty and small tolerance of the solutions have become significant factors hindering the widespread adoption of the technology. From a design perspective, the properties of silicon photonics materials and the precision of the manufacturing process have a decisive impact on the performance of CWDM4demux. Parameters such as the refractive index and dispersion of silicon photonics materials change with wavelength, requiring precise control of various parameters when designing waveguides for different wavelength channels to ensure stable transmission of optical signals in their respective channels. Simultaneously, minute errors in the manufacturing process, such as deviations in waveguide width and thickness, and insufficient precision in grating etching, can lead to decreased isolation and increased crosstalk. Moreover, the small tolerance of the CWDM4 architecture means a limited range of adjustable design parameters. Errors exceeding this tolerance during manufacturing can result in substandard device performance, significantly increasing production costs and the difficulty of controlling yield.

[0023] In view of this, embodiments of this application propose an optoelectronic co-packaged photonic transceiver device, referring to... Figure 1 As shown, the optoelectronic co-packaged photonic transceiver includes: The optoelectronic hybrid glass substrate 3 integrates a substrate edge waveguide, an on-chip waveguide 306, and an optical multiplexer / demultiplexer 307, wherein the optical multiplexer / demultiplexer 307 is connected to the on-chip waveguide 306 and the substrate edge waveguide, respectively. The silicon photonics PIC chip 2 integrates a chip edge waveguide 20a, multiple optical modulators 205 and multiple photodetectors 206. The chip edge waveguide 20a is connected to the optical modulators 205 and the photodetectors 206 respectively, and the chip edge waveguide 20a is connected to the on-chip waveguide 306 through evanescent wave coupling to achieve optical path connection. The optical multiplexer / demultiplexer 307 is used to demultiplex a multi-wavelength light source input through a single optical fiber into multiple single-wavelength light sources, which are then transmitted to the optical modulator 205 to be modulated into high-speed optical signals and then combined and output; and simultaneously, it is used to demultiplex the input multi-wavelength optical signals into multiple single-wavelength light sources, which are then transmitted to the photodetector 206 to be converted into current signals.

[0024] The optoelectronic co-packaged photonic transceiver device provided in this embodiment adopts a glass-based optoelectronic hybrid integrated architecture.

[0025] The optoelectronic hybrid glass substrate 3 can use low-loss optical glass as the substrate, integrating high-speed circuit traces and optical waveguide structures on the same substrate. The substrate edge waveguide is used for coupling with an external fiber array, and the on-chip waveguide 306 is used for transmitting optical signals inside the substrate. The optical multiplexer / demultiplexer is directly integrated on the glass substrate. In one specific embodiment, the optical multiplexer / demultiplexer is a glass-based CWDM4 device, supporting multiplexing and demultiplexing operations of four standard wavelengths: 1271nm, 1291nm, 1311nm, and 1331nm. Its insertion loss is less than 1.5dB, and the isolation between adjacent channels is greater than 26dB, exhibiting greater design tolerance and superior optical performance compared to silicon-based CWDM4 devices.

[0026] The silicon photonics PIC chip 2 is manufactured using standard silicon photonics technology and integrates a complete optical transceiver module. The chip's edge waveguide 20a may include a light source input waveguide 207, a transmit output waveguide 208, and a receive input waveguide 209, used for receiving light from the optoelectronic hybrid glass substrate 3, outputting modulated transmitted light to the optoelectronic hybrid glass substrate 3, and receiving received light from the optoelectronic hybrid glass substrate 3, respectively. In a specific embodiment, the optical modulator 205 is a Mach-Zehnder modulator (MZM) with eight units, an analog bandwidth of 38 GHz, and supports 100 Gbps PAM4 modulation format; the photodetector 206 is a germanium-silicon (GeSi) detector with a bandwidth of 40 GHz, an operating rate of 100 Gbps, and supports PAM4 modulation format. The overall responsivity of the GeSi detector is 0.5 A / W, which meets the receiving sensitivity requirements of 100 Gbps PAM4 signals.

[0027] Reference Figure 10 As shown, in one specific embodiment, the chip edge waveguide 20a of the silicon photonics PIC chip 2 and the on-chip waveguide 306 of the optoelectronic hybrid glass substrate 3 are optically connected using evanescent wave coupling. The arrows in the figure indicate the light transmission direction from each chip edge waveguide 20a to the on-chip waveguide 306. The coupling length is L, which is 1.7 mm in one specific embodiment, and the measured coupling efficiency can reach 88%. Evanescent wave coupling eliminates the need for end-face polishing, provides good process compatibility, and enables synchronous alignment and fixation of the optical path and electrical connections, significantly improving packaging efficiency and reliability.

[0028] The evanescent wave coupling gap between the silicon photonics PIC chip 2 and the optoelectronic hybrid glass substrate 3 can be filled with a bottom-filled refractive index matching adhesive to fill the coupling gap, achieve refractive index matching, and further reduce coupling loss. Additionally, when the silicon photonics PIC chip 2 is flip-chip mounted onto the optoelectronic hybrid glass substrate 3, the adhesive can strengthen the surface mechanical strength and improve the device's shock and vibration resistance. In one specific embodiment, the bottom-filled refractive index matching adhesive has a refractive index of 1.43 at a wavelength of 1310 nm.

[0029] In a specific application scenario, the optical path for a photonic transceiver device co-packaged with an optoelectronic interface as the transmitter is as follows: External CWDM4 four-wavelength continuous light (output power +20dBm) is input to the optoelectronic hybrid glass substrate 3 via a single optical fiber. After being split into four single-wavelength beams by an optical multiplexer / demultiplexer, the beams are transmitted through on-chip waveguide 306 to the chip edge waveguide 20a (light source input waveguide 207) of the silicon photonics PIC chip 2. Each wavelength of light undergoes a 1-to-2 power split before being input to eight MZM optical modulators 205. These modulated beams are then modulated by high-speed electrical signals into high-speed optical signals carrying data. The two sets of modulated CWDM4 high-speed optical signals are output from the chip edge waveguide 20a (two sets of transmit output waveguides 208) of the silicon photonics PIC chip 2. After being transmitted through on-chip waveguide 306 to the optical multiplexer / demultiplexer for multiplexing, the beams are output through two transmit optical fibers (e.g., to a switch circuit). In a specific embodiment, the final output optical power is approximately +1dBm.

[0030] In a specific application scenario, for the optical path of the optoelectronic co-packaged photonic transceiver device as the receiving end: two sets of externally input CWDM4 optical signals are input to the optoelectronic hybrid glass substrate 3 through two receiving optical fibers. The optoelectronic hybrid glass substrate 3 optical multiplexer / demultiplexer 307 splits each set of CWDM4 optical signals into 4 single-wavelength light signals, which are transmitted through the on-chip waveguide 306 to the chip edge waveguide 20a (receiving input waveguide 209) of the silicon photonics PIC chip 2, and then enter the GeSi photodetector 206 to be converted into a current signal.

[0031] The optoelectronic co-packaged photonic transceiver in this embodiment integrates an optical multiplexer / demultiplexer 307 onto a glass substrate. Compared to silicon-based devices, glass-based optical multiplexers / demultiplexers offer greater design tolerance and superior optical performance, significantly reducing manufacturing difficulty and cost, and improving product yield. Evanescent wave coupling is used to achieve the optical path connection between the silicon photonic PIC chip 2 and the glass substrate, realizing a vertical optical path connection between the silicon photonic PIC chip 2 and the glass substrate. This lays the foundation for subsequent three-dimensional stacking of photonic links and further improves the bandwidth density of the CPO photonic transceiver. External four-wavelength light sources require only a single optical fiber input. The optical multiplexer / demultiplexer 307 demultiplexes the multi-wavelength light sources input via a single optical fiber into multiple single-wavelength beams, reducing fiber density and maintenance costs, saving the number of light source fibers, and significantly reducing the complexity and maintenance costs of fiber optic cabling in data centers.

[0032] Reference Figure 2 and Figure 3 As shown, in an optional embodiment of this application, the optoelectronic co-packaged photonic transceiver device further includes an electrical chip 1, wherein the two opposing surfaces of the silicon photonic PIC chip 2 are flip-mounted with the electrical chip 1 and the optoelectronic hybrid glass substrate 3 to form a vertical architecture in which electronic links and photonic links are synchronously stacked in three dimensions.

[0033] In this embodiment of the application, the co-packaged photonic transceiver device also includes an electrical chip 1. The electrical chip 1, the silicon photonic PIC chip 2, and the optoelectronic hybrid glass substrate 3 adopt a three-layer vertical stacking architecture, which realizes the synchronous three-dimensional stacking of electronic links and photonic links, and further improves the packaging integration.

[0034] The electrical chip 1 can be manufactured using CMOS technology. The surface of the electrical chip 1 is provided with copper-silver-tin bump pads 101 as electrical connection structures for electrical connection with the electrical connection structure 204 of the silicon photonics PIC chip 2 to realize electrical signal transmission. The copper pillars have a diameter of 45μm and a minimum spacing of 130μm for flip-chip bonding with the silicon photonics PIC chip 2.

[0035] Specifically, one surface of the silicon photonics PIC chip 2 (the surface with the chip edge waveguide 20a) is flip-chip bonded to the optoelectronic hybrid glass substrate 3, and the other surface is flip-chip bonded to the electrical chip 1. This architecture vertically stacks the electrical chip 1 and the silicon photonics PIC chip 2, which significantly shortens the transmission distance of electrical signals, reduces link power consumption and signal loss, and frees up space on the waveguide surface of the silicon photonics PIC chip 2 for arranging more optical devices and waveguide structures.

[0036] In this embodiment, an electronic chip 1, a silicon photonics PIC chip 2, and a photoelectric hybrid glass substrate 3 are used to form a synchronous three-dimensional stack of electronic and photonic links. Compared with the planar integration architecture of the electronic chip 1 and the silicon photonics chip in the traditional CPO scheme, the packaging density can be greatly improved and the electrical signal transmission distance can be significantly reduced. For example, in one specific embodiment, the electrical signal transmission distance is shortened from the centimeter level to the sub-millimeter level.

[0037] Reference Figures 4-9 As shown, in an optional embodiment of this application, the silicon photonics PIC chip 2 has a first surface 201 and a second surface 202 opposite to each other, and the optoelectronic hybrid glass substrate 3 has a first substrate surface 301 and a second substrate surface 302 opposite to each other. The first surface 201, the second surface 202, the first substrate surface 301, and the second substrate surface 302 are respectively provided with electrical connection structures; and the silicon photonics PIC chip 2 is provided with a silicon via 203 that penetrates the first surface 201 and the second surface 202 and conducts the electrical connection structure 204 at the first surface 201 and the second surface 202; and the optoelectronic hybrid glass substrate 3 is provided with a glass via 303 that penetrates the first substrate surface 301 and the second substrate surface 302 and conducts the electrical connection structure 305 at the first substrate surface 301 and the second substrate surface 302. The first surface 201 is flip-chip mounted on the first substrate surface 301, and the electrical chip 1 is flip-chip mounted on the second surface 202. The electrical connection structure 204 of the first surface 201 is bonded to the electrical connection structure 304 of the first substrate surface 301, and is respectively connected to the optical modulator 205 and the photodetector 206.

[0038] In this embodiment, the first surface 201 of the silicon photonics PIC chip 2 is a waveguide surface, and the second surface 202 is a bottom surface. Both the waveguide surface and the bottom surface are provided with metal pads as electrical connection structures 204, and the two are electrically connected through a through-silicon via 203 (TSV) penetrating the chip. The metal pads of the waveguide surface are simultaneously connected to the electrodes of the optical modulator 205 and the electrodes of the photodetector 206 for transmitting high-speed electrical signals.

[0039] The first substrate surface 301 of the optoelectronic hybrid glass substrate 3 is a waveguide surface, and the second substrate surface 302 is a bottom surface. Both the waveguide surface and the bottom surface are provided with metal pads as electrical connection structures. The two are electrically connected through a glass through-hole 303 (TGV) that penetrates the substrate.

[0040] Electrical chip 1 is flip-chip bonded to the bottom surface of silicon photonics PIC chip 2. The bump pads 101 of electrical chip 1 are bonded to the metal pads on the bottom surface of silicon photonics PIC chip 2. The first surface 201 of silicon photonics PIC chip 2 is flip-chip bonded to the first substrate surface 301 of optoelectronic hybrid glass substrate 3. The metal pads on the first substrate surface 301 of silicon photonics PIC chip 2 are bonded to the metal pads on the waveguide surface of the glass substrate. The metal pads on the second substrate surface 302 of optoelectronic hybrid glass substrate 3 are used for connection to an external switch circuit board, thereby forming a complete vertical electrical path from electrical chip 1 to the switch circuit board.

[0041] This embodiment achieves vertical electrical interconnection through silicon vias 203 and glass vias 303, avoiding the parasitic inductance and capacitance problems caused by traditional wire bonding, significantly improving the transmission quality of high-speed electrical signals, and simultaneously achieving synchronous alignment and fixation of optical paths and electrical connections, thereby improving packaging efficiency and reliability.

[0042] In one specific embodiment, the metal pads on the first substrate surface 301 of the optoelectronic hybrid glass substrate 3 are pre-filled with low-temperature solder, the melting temperature of which is lower than that of the solder on the bump pads 101 of the electrical chip 1 (for example, the melting temperature of the solder on the electrical chip 1 is about 290°C, and the melting temperature of the solder on the glass substrate is about 260°C). This ensures that the solder joints of the first flip-chip bonding (electrical chip 1 and silicon photonics PIC chip 2) will not melt during the second flip-chip bonding (the silicon photonics PIC chip 2 and the optoelectronic hybrid glass substrate 3), thus ensuring the process compatibility of the two flip-chip bonding processes.

[0043] In an optional embodiment of this application, the electrical chip 1 integrates a driving circuit and a transimpedance amplifier circuit, and the surface of the electrical chip 1 is provided with an electrical connection structure (bump pad 101). The electrical connection structure on the surface of the electrical chip 1 is bonded to the electrical connection structure on the second surface 202 so that the driving circuit can be connected to the optical modulator 205, and the transimpedance amplifier circuit can be connected to the photodetector 206.

[0044] Specifically, refer to Figure 2 As shown, the bump pads 101 on the surface of the electronic chip 1 are bonded to the metal pads on the bottom surface of the silicon photonics PIC chip 2 by flip-chip bonding. The driving circuit is connected to the electrodes of the optical modulator 205 through the through-silicon via 203, and the transimpedance amplifier circuit is connected to the electrodes of the photodetector 206 through the through-silicon via 203.

[0045] In one specific embodiment, the transimpedance amplifier (TIA) circuit receives the current signal output from the photodetector 206 and converts and amplifies the weak current signal output by the photodetector 206 into a large voltage signal, which is then output to the switch. The driving circuit amplifies the voltage signal output by the switch into a voltage signal with a large swing, driving the optical modulator 205 to work. It also integrates an equalization function to improve the high-frequency response characteristics of the transmission link.

[0046] In this embodiment, the driving circuit and the transimpedance amplifier circuit are integrated on the same electrical chip 1 and directly connected to the silicon photonics PIC chip 2 by flip-chip bonding, which greatly shortens the transmission path of electrical signals, reduces signal loss and crosstalk, and improves the overall performance of the link.

[0047] In an optional embodiment, both the driver circuitry and the transimpedance amplifier circuitry integrate equalization (EQ) functionality to improve the high-frequency response characteristics of the link.

[0048] In an optional embodiment of this application, the chip edge waveguide 20a includes a light source input waveguide 207, a transmit output waveguide 208, and a receive input waveguide 209. Each of the light source input waveguides 207 is connected to one end of a plurality of optical modulators 205, and the other end of each optical modulator 205 is connected to one of the transmit output waveguides 208. Each of the photodetectors is connected to one of the receive input waveguides 209.

[0049] Reference Figure 1 and Figure 7 As shown, in a specific embodiment of this application, the optical multiplexer / demultiplexer 307 supports the multiplexing and demultiplexing of four different wavelengths of light. Based on this: the chip edge waveguide 20a has four light source input waveguides 207, each corresponding to one of the four wavelengths of the multi-wavelength light source. Each light source input waveguide 207 is connected to a 1-to-2 power divider, splitting the input single-wavelength light into two paths, which are then input to two optical modulators 205 respectively. The chip edge waveguide 20a has eight transmit output waveguides 208, each connected to the output of an optical modulator 205 for outputting the modulated high-speed optical signal. The eight transmit output waveguides 208 are divided into two groups of four, each corresponding to one of the two transmit channels. The chip edge waveguide 20a has eight receive input waveguides 209, each connected to the input of a photodetector 206 for inputting the demultiplexed single-wavelength optical signal. The eight receive input waveguides 209 are divided into two groups of four, each corresponding to one of the two receive channels.

[0050] It is understood that, based on the different wavelengths of the external multi-wavelength light source, this application can adaptively adjust the number and arrangement of the optical multiplexer / demultiplexer 307, edge waveguide, optical modulator 205 and photodetector 206 to meet processing requirements.

[0051] This embodiment achieves the integration of N×FR4 transceiver channels through reasonable waveguide layout and power distribution design. The rate of a single optoelectronic co-packaged photonic transceiver device can reach 800G, which can meet the high bandwidth requirements of AI data centers.

[0052] In an optional embodiment of this application, the optoelectronic co-packaged photonic transceiver further includes: The multi-channel fiber array 4 includes a single input fiber for transmitting the multi-wavelength light source, and a transmitting output fiber and a receiving input fiber for transmitting the multi-wavelength optical signal. The multi-channel fiber array 4 is coupled and fixed to the edge waveguide of the optoelectronic hybrid glass substrate 3.

[0053] This embodiment adds a multi-channel fiber array 4 (FA) to enable the connection between the optoelectronic co-packaged photonic transceiver device and the external optical fiber.

[0054] Reference Figure 5 As shown, in a specific embodiment of this application, the chip edge waveguide 20a adapted to the specific form of the silicon photonics PIC chip 2 is provided with a light source input waveguide 3093, a transmit output waveguide 3091, and a receive input waveguide 3092 on the substrate edge waveguide of the optoelectronic hybrid glass substrate 3. The transmit output waveguide 3091 and the receive output waveguide 3092 are two paths. Correspondingly, the multi-channel fiber array 4 contains a total of 5 optical fibers, of which 1 is a light source input fiber connected to the light source input waveguide 3093 of the substrate edge waveguide 309 for transmitting multi-wavelength light sources output from an external centralized light source pool; 2 are transmit output fibers connected to the transmit output waveguide 3091 of the substrate edge waveguide 309 for outputting modulated high-speed optical signals; and 2 are receive input fibers connected to the receive input waveguide 3092 of the substrate edge waveguide 309 for inputting multi-wavelength optical signals sent by external devices.

[0055] In one specific embodiment, the multi-channel fiber array 4 can be coupled and fixed to the edge waveguide of the optoelectronic hybrid glass substrate 3 via end-face bonding refractive index matching adhesive 6. The end-face bonding refractive index matching adhesive 6 has a refractive index of 1.43 at a wavelength of 1310 nm, which matches the refractive index of the silicon waveguide and the glass waveguide, effectively reducing end-face reflection loss. The adhesive strength ensures the long-term reliability of the coupling connection within a wide temperature range of -45℃ to 85℃.

[0056] This embodiment uses a single optical fiber to input a multi-wavelength light source, which significantly reduces the number of optical fibers compared to traditional solutions, thereby reducing the complexity of fiber optic cabling and maintenance costs in data centers.

[0057] In an optional embodiment of this application, U-shaped waveguides are respectively provided on both sides of the edge waveguide of the optoelectronic hybrid glass substrate 3. The U-shaped waveguides are used to cooperate with the multi-channel fiber array 4 so as to achieve full-channel alignment between the multi-channel fiber array 4 and the edge waveguide of the optoelectronic hybrid glass substrate 3 by monitoring the coupling power of the U-shaped waveguides.

[0058] Reference Figures 1-7 As shown, a U-shaped waveguide is disposed on each side of the edge waveguide of the optoelectronic hybrid glass substrate 3. Each U-shaped waveguide corresponds to two optical fibers on both sides of the multi-channel fiber array 4. Taking the alignment of two optical fibers on one side with the U-shaped waveguide as an example, one optical fiber is used to input light, and the other optical fiber is used to receive light by an optical power meter. When the U-shaped waveguide is aligned with the optical fiber, the optical power received by the optical power meter is at its maximum. When the U-shaped waveguides on both sides are aligned with the optical fiber at the same time, it indicates that the array waveguide and array optical fiber have achieved full-channel alignment.

[0059] Since silicon waveguides have certain polarization-dependent losses, the input fiber of the U-shaped waveguide can be coupled using a low-cost, ordinary SMT external polarization controller. By adjusting the polarization state, the coupling output value can be maximized, thereby improving alignment accuracy.

[0060] This embodiment uses a U-shaped waveguide-assisted alignment method to achieve rapid and high-precision full-channel alignment between the multi-channel fiber array 4 and the optoelectronic hybrid glass substrate 3, which greatly improves packaging efficiency and coupling yield.

[0061] An embodiment of this application also provides a method for fabricating the optoelectronic co-packaged photonic transceiver device as described above, comprising the following steps: S1. Align the U-shaped waveguides on both sides of the optoelectronic hybrid glass substrate 3 with the multi-channel fiber array 4. When the coupling power corresponding to the U-shaped waveguides on both sides reaches the maximum, use end-face bonding refractive index matching glue 6 to bond the end faces of the optoelectronic hybrid glass substrate 3 and the multi-channel fiber array 4. Fix the substrate after UV curing, baking and temperature cycling treatment. S2. Connect the bump pads 101 of the electrical chip 1 to the pads of the silicon photonics PIC chip 2, and heat and pressurize to melt the solder, thereby achieving the electrical connection and fixation between the electrical chip 1 and the silicon photonics PIC chip 2. S3. Align the silicon photonics PIC chip 2 with the optoelectronic hybrid glass substrate 3 using waveguide evanescent wave coupling, and connect the pads of the silicon photonics PIC chip 2 with the pads of the optoelectronic hybrid glass substrate 3. Heat and pressurize to melt the solder, thereby achieving synchronous connection and fixation of the optical and electrical paths of the silicon photonics PIC chip 2 and the optoelectronic hybrid glass substrate 3.

[0062] Specifically, refer to Figure 11As shown, in step S1, the U-shaped waveguides on both sides of the optoelectronic hybrid glass substrate 3 are aligned with the optical fibers on both sides of the multi-channel fiber array 4. When the optical power received by the corresponding optical fibers on both sides of the U-shaped waveguides reaches its maximum, the alignment of all channels is confirmed. Then, the end faces are bonded together using end-face bonding refractive index matching adhesive 6. UV curing is performed first, followed by baking to enhance shear force. Finally, a temperature cycling treatment is performed to release adhesive stress. In a specific embodiment, the temperature range of the temperature cycling treatment is -45℃ to 85℃, for a total of 10 cycles, with a heating and cooling rate of 10℃ per minute. This temperature cycling parameter can effectively release the internal stress generated during the adhesive curing process, avoiding problems such as adhesive cracking or coupling misalignment during long-term use.

[0063] In step S2, refer to Figure 12 As shown, the bump pads 101 of the electrical chip 1 are precisely aligned with the metal pads on the bottom surface of the silicon photonics PIC chip 2 (these metal pads also serve as the electrical connection structure 204 on the surface of the silicon photonics PIC chip 2). Then, heating and pressurization are applied to melt the solder, achieving both electrical connection and mechanical fixation. This step can be performed using a high-precision flip-chip mounter. In one specific embodiment, the mounter pressure is set to 50g, the heating temperature to 290℃, and the duration to 3 seconds. This ensures that the solder melts fully, forming a good electrical connection, while preventing damage to the electrical chip 1 and the silicon photonics PIC chip 2 from high temperatures.

[0064] In step S3, refer to Figure 13 As shown, the semi-finished product obtained in step S2 is aligned with the semi-finished product obtained in step S1 using waveguide evanescent wave coupling, while simultaneously confirming pad alignment. Then, heating and pressurization are applied to melt the pre-placed low-temperature solder on the glass substrate, achieving synchronous connection and fixation of the optical and electrical paths. The placement machine pressure in this step is set to 10g, the heating temperature to 260℃, and the duration to 3s. The lower pressure prevents the silicon photonics PIC chip and the optoelectronic hybrid glass substrate 3 from cracking, and the lower temperature ensures that the solder joints from the first flip-chip bonding will not remelt.

[0065] The embodiments of this application adopt a step-by-step flip-chip soldering process, which achieves process compatibility of two flip-chip soldering processes by using solders with different melting temperatures. At the same time, it achieves synchronous alignment and fixation of optical paths and electrical connections, which greatly improves packaging efficiency and product reliability.

[0066] In an optional embodiment of this application, waveguide evanescent wave coupling alignment of the silicon photonics PIC chip and the optoelectronic hybrid glass substrate 3 includes: Single-wavelength light is input to the silicon photonics PIC chip through a multi-channel fiber array 4, and the output power of the single-wavelength light output by the silicon photonics PIC chip 2 through the multi-channel fiber array 4 is monitored. When the output power is at its maximum, it is confirmed that the optical path of the silicon photonics PIC chip 2 is aligned with that of the optoelectronic hybrid glass substrate 3. The wavelength of the single-wavelength light corresponds to the wavelength of the optical modulator 205 of the silicon photonics PIC chip 2.

[0067] Specifically, a single wavelength of light (corresponding to the wavelength of the optical modulator 205) is input into the fiber channel of the multi-channel fiber array 4 corresponding to the outermost waveguide of the light source input waveguide of the silicon photonics PIC chip. At the same time, the output power of the fiber channel of the multi-channel fiber array 4 corresponding to the outermost waveguide of the output waveguide 208 of the silicon photonics PIC chip 2 is monitored. When the output power reaches the maximum, it indicates that the chip edge waveguide 20a of the silicon photonics PIC chip and the on-chip waveguide 306 of the optoelectronic hybrid glass substrate 3 have been aligned.

[0068] In one specific embodiment, a high-precision coupler with a moving step size accuracy of 0.1 μm can be used for alignment operations, which can achieve sub-micron level alignment accuracy and ensure optical path coupling efficiency greater than 80%.

[0069] This embodiment uses an optical power monitoring method to achieve high-precision evanescent wave coupling alignment between the silicon photonics PIC chip and the optoelectronic hybrid glass substrate 3, ensuring low loss and high reliability of the optical path connection.

[0070] The embodiments of this application also propose an optoelectronic co-packaged switch, including the optoelectronic co-packaged photonic transceiver device as described above, or the optoelectronic co-packaged photonic transceiver device prepared by the preparation method of the optoelectronic co-packaged photonic transceiver device as described above.

[0071] Reference Figure 14 As shown, in one specific embodiment, the optoelectronic co-packaged switch includes a switch ASIC chip, a switch PCB, and 32 optoelectronic co-packaged photonic transceivers as described above. The switch PCB has slots, and the 32 photonic transceivers are installed in the slots surrounding the switch ASIC chip, enabling high-speed communication with the ASIC chip. Each optoelectronic co-packaged photonic transceiver has a speed of 800G, thus achieving a switching rate of 25.6T. Compared to traditional pluggable optical module switches, this system reduces link power consumption and increases bandwidth density, meeting the interconnection needs of next-generation AI data centers.

[0072] In addition, the optoelectronic co-packaged switch described in this application has similar technical effects to the aforementioned optoelectronic co-packaged photonic transceiver devices, which will not be elaborated further here.

[0073] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A photonic transceiver device co-packaged with optoelectronic components, characterized in that, include: A hybrid optoelectronic glass substrate integrates a substrate edge waveguide, an on-chip waveguide, and an optical multiplexer / demultiplexer, wherein the optical multiplexer / demultiplexer is connected to the on-chip waveguide and the substrate edge waveguide, respectively. The silicon photonics PIC chip integrates a chip edge waveguide, multiple optical modulators, and multiple photodetectors. The chip edge waveguide is connected to the optical modulators and the photodetectors respectively, and the chip edge waveguide is connected to the on-chip waveguide through evanescent wave coupling to achieve optical path connection. A multi-channel fiber array includes a single input fiber for transmitting multi-wavelength light sources, and a transmitting output fiber and a receiving input fiber for transmitting multi-wavelength optical signals. The multi-channel fiber array is coupled and fixed to the substrate edge waveguide of the optoelectronic hybrid glass substrate. The optical multiplexer / demultiplexer is used to demultiplex a multi-wavelength light source input through a single optical fiber into multiple single-wavelength light sources, which are then transmitted to the optical modulator to be modulated into high-speed optical signals and then combined and output. And simultaneously used to demultiplex the multi-wavelength optical signal input through the receiving input optical fiber into multiple single-wavelength optical signals, which are then transmitted to the photodetector and converted into current signals.

2. The optoelectronic co-packaged photonic transceiver device according to claim 1, characterized in that, It also includes an electrical chip, wherein the two opposing surfaces of the silicon photonics PIC chip are flip-mounted with the electrical chip and the optoelectronic hybrid glass substrate respectively to form a vertical architecture in which electronic links and photonic links are stacked in three dimensions simultaneously.

3. The optoelectronic co-packaged photonic transceiver device according to claim 2, characterized in that, The silicon photonics PIC chip has a first surface and a second surface opposite to each other, and the optoelectronic hybrid glass substrate has a first substrate surface and a second substrate surface opposite to each other. Electrical connection structures are respectively provided on the first surface, the second surface, the first substrate surface, and the second substrate surface. The silicon photonics PIC chip is provided with a through-silicon via that penetrates the first surface and the second surface and conducts the electrical connection structures at the first surface and the second surface. Furthermore, the optoelectronic hybrid glass substrate is provided with a glass through-hole that penetrates the first substrate surface and the second substrate surface and conducts the electrical connection structure at the first substrate surface and the second substrate surface; The first surface is flip-chip mounted on the first substrate surface, the electrical chip is flip-chip mounted on the second surface, the electrical connection structure of the first surface is bonded to the electrical connection structure of the first substrate surface, and is respectively connected to the optical modulator and the photodetector.

4. The optoelectronic co-packaged photonic transceiver device according to claim 3, characterized in that, The electrical chip integrates a driving circuit and a transimpedance amplifier circuit, and the surface of the electrical chip is provided with an electrical connection structure. The electrical connection structure on the surface of the electrical chip is bonded to the electrical connection structure on the second surface, so as to enable the driving circuit to conduct with the optical modulator and the transimpedance amplifier circuit to conduct with the photodetector.

5. The optoelectronic co-packaged photonic transceiver device according to claim 1, characterized in that, The chip edge waveguide includes a light source input waveguide, a transmit output waveguide, and a receive input waveguide. Each light source input waveguide is connected to one end of a plurality of optical modulators, and the other end of each optical modulator is connected to one of the transmit output waveguides. Each photodetector is connected to one of the receive input waveguides.

6. The optoelectronic co-packaged photonic transceiver device according to claim 1, characterized in that, The substrate edge waveguide is provided with U-shaped waveguides on both sides. The U-shaped waveguides are used to cooperate with the multi-channel fiber array to achieve full-channel alignment between the multi-channel fiber array and the substrate edge waveguide by monitoring the coupling power of the U-shaped waveguides.

7. A method for fabricating a photonic co-packaged photonic transceiver device as described in any one of claims 1-6, characterized in that, include: The U-shaped waveguides on both sides of the optoelectronic hybrid glass substrate are aligned with the multi-channel fiber array. When the coupling power corresponding to the U-shaped waveguides on both sides reaches the maximum, the end face of the optoelectronic hybrid glass substrate and the end face of the multi-channel fiber array are bonded with end face bonding refractive index matching glue. The fixation is completed by UV curing, baking and temperature cycling treatment. The bump pads of the electrical chip are connected to the pads of the silicon photonics PIC chip, and the solder is melted by heating and pressurizing to achieve electrical connection and fixation between the electrical chip and the silicon photonics PIC chip. The silicon photonics PIC chip and the optoelectronic hybrid glass substrate are aligned by waveguide evanescent wave coupling, and the pads of the silicon photonics PIC chip are docked with the pads of the optoelectronic hybrid glass substrate. The solder is melted by heating and pressurizing, so as to realize the synchronous connection and fixation of the optical path and electrical circuit of the silicon photonics PIC chip and the optoelectronic hybrid glass substrate.

8. The method for fabricating the optoelectronic co-packaged photonic transceiver device according to claim 7, characterized in that, The process of aligning the silicon photonics PIC chip with the optoelectronic hybrid glass substrate using waveguide evanescent wave coupling includes: A single wavelength light is input to the silicon photonics PIC chip through a multi-channel fiber array, and the output power of the single wavelength light output by the silicon photonics PIC chip through the multi-channel fiber array is monitored. When the output power is at its maximum, it is confirmed that the optical path of the silicon photonics PIC chip and the optoelectronic hybrid glass substrate are aligned. The wavelength of the single wavelength light corresponds to the wavelength of the optical modulator of the silicon photonics PIC chip.

9. A photoelectric co-packaged switch, characterized in that, This includes the optoelectronic co-packaged photonic transceiver device as described in any one of claims 1-6, or the optoelectronic co-packaged photonic transceiver device prepared by the preparation method of the optoelectronic co-packaged photonic transceiver device as described in any one of claims 7 and 8.

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