Display panel and display screen

Abstract

The application provides a display panel and a display screen, and relates to the display field.The display panel comprises a lead area and a display area.In the display area, the resolution of the display panel in the length direction is m, the resolution in the width direction is n, and m>3*n.In the lead area, the gate layer of the display panel is provided with a first wire, the first wire is used for transmitting one of a gate driving signal and a common voltage signal, the first wire is connected to a second wire through a first via, and the second wire is arranged on the source layer or the metal wire layer of the display panel.In the display area, the second wire is connected to one of the gate driving line in the gate layer and the common electrode layer through a second via.Through the technical scheme, the narrow frame design of the display screen can be realized, or the picture flicker and residual image of the display screen and other problems can be reduced, the display effect of the display screen is improved, and the performance of the display screen is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and a display screen. Background Technology

[0002] With further breakthroughs in display technology and the deepening expansion of the market, automotive displays will become a core component of in-vehicle information systems, providing drivers with more intelligent and convenient services. In particular, the rapid development of new energy vehicle companies has led to an increasing demand for in-vehicle screens, with a growing preference for integrated, large, elongated screens.

[0003] With the increasingly broad market for long, large screens in the automotive sector and the increasingly stringent technical requirements, improving the overall performance of displays has become an urgent technical problem to be solved. Summary of the Invention

[0004] This application provides a display panel and a display screen that can have better performance.

[0005] In a first aspect, a display panel is provided, the display panel including a lead area and a display area, wherein the resolution of the display panel in the length direction is m and the resolution in the width direction is n, where m > 3*n; in the lead area, a first trace is provided on the gate layer of the display panel, the first trace being used to transmit one of a gate drive signal and a common voltage signal, the first trace being connected to a second trace through a first via, the second trace being disposed on the source layer or a metal trace layer of the display panel; in the display area, the second trace is connected to one of a gate drive line in the gate layer and a common electrode layer through a second via.

[0006] In this technical solution, the gate drive signal is transmitted to the source layer or metal trace layer using the first trace and the first via in the fanout area. Therefore, the gate driver chip used to transmit the gate drive signal can be located on the same side of the display panel as the source driver chip used to transmit the source drive signal, which is beneficial for achieving a narrow bezel design on the other three sides of the display screen. Furthermore, by using the second trace and the second via in the display area (AA area) to transmit the common voltage signal to the common electrode layer, the uniformity of the common voltage within the AA area is improved, reducing screen flicker and afterimages, and enhancing the display effect.

[0007] In some possible implementations, in the lead area, the gate layer is further provided with a third trace, which is used to transmit the other of the gate drive signal and the common voltage signal. The third trace is connected to a fourth trace through a third via. The fourth trace is disposed in the source layer or the metal trace layer. In the display area, the fourth trace is connected to the gate drive line in the gate layer and the other of the common electrode layer through a fourth via.

[0008] In this technical solution, the transmission of gate drive signals and common voltage signals can be achieved simultaneously using the source layer or metal trace layer through the traces and vias in the Fanout area and AA area. This not only achieves the narrow bezel design of the display panel, but also further improves the uniformity of the common voltage in the AA area, thereby enhancing the display effect.

[0009] In some possible implementations, the second trace is disposed on a metal trace layer, which is located above the common electrode layer, and an insulating layer is provided between the metal trace layer and the common electrode layer; the orthogonal projection of the second trace in the source layer overlaps with the source drive line in the source layer.

[0010] In this technical solution, the second trace in the metal trace layer is designed to be consistent with the source drive line in the source layer. The gate drive signal or common voltage signal is transmitted to the second trace. The gate drive chip used to transmit the gate drive signal can be located on the same side of the display panel as the source drive chip used to transmit the source drive signal, which is beneficial for achieving a narrow bezel design of the display screen. In addition, providing the common voltage signal within the AA area helps reduce display screen flicker and afterimage problems, thereby improving the display screen's display effect.

[0011] In some possible implementations, the second trace is used to transmit a common voltage signal. In the display area, the second via is disposed in the insulating layer between the metal trace layer and the common electrode layer, and is located in the orthogonal projection area of ​​the source drive line. The second trace in the metal trace layer is disposed in the second via and is connected to the common electrode layer.

[0012] In this technical solution, the second via is located in the orthographic projection area of ​​the source driving line, and is not set in the pixel area. This will not affect the aperture ratio of the pixel and will help ensure the display effect of the pixel.

[0013] In some possible implementations, the second via is positioned adjacent to the pixel region of the blue pixel in the display panel.

[0014] In this technical solution, the blue pixel has a lower brightness than the red or green pixel. By placing the second via next to the pixel area of ​​the blue pixel, the impact of the second via on the display of the AA area can be reduced.

[0015] In some possible implementations, the second trace is used to transmit the gate drive signal. In the display area, the second via is disposed in a plurality of insulating layers between the gate layer and the metal trace layer. The second trace in the metal trace layer is disposed in the second via and connected to the gate drive line in the gate layer.

[0016] In some possible implementations, the second via is located at a corner of the pixel area of ​​a pixel in the display panel.

[0017] In this technical solution, the second via is located at the corner of the pixel area, which can reduce the impact on the display effect of the pixel.

[0018] In some possible implementations, in the lead area, the first trace is connected to the common voltage area of ​​the display panel or the gate driver chip, the first via is disposed in a plurality of insulating layers between the gate layer and the metal trace layer, and the second trace in the metal trace layer is disposed in the first via and connected to the first trace in the gate layer.

[0019] In some possible implementations, in the lead area, the gate layer is provided with N1 first traces and N2 third traces. The N1 first traces are connected to the same gate driver chip, and the N2 third traces are connected to the common voltage area of ​​the display panel. N1 and N2 are positive integers greater than 1. The N1 first traces and N2 third traces are arranged alternately. Alternatively, the N1 first traces are arranged adjacent to each other, and the N2 third traces are arranged adjacent to each other.

[0020] In this technical solution, N1 first traces and N2 third traces are arranged alternately, which allows the traces used to transmit common voltage signals and the traces used to transmit gate drive signals to be evenly distributed, thus improving the uniformity of the common voltage within the display screen. Alternatively, N1 first traces are arranged adjacent to each other, and N2 second traces are arranged adjacent to each other, which is beneficial for the arrangement and distribution of traces in the Fanout area, improving the uniformity of metal traces within the display panel, thereby enhancing the overall performance of the display panel.

[0021] In some possible implementations, the second trace is disposed in the source layer; wherein the second trace is located between two adjacent rows of pixels in the display panel, and the second trace is a suspended source driving line in the source layer, and the suspended source driving line does not receive source driving signals; or, the second trace corresponds to the bend of the pixel electrode of a row of pixels in the display panel.

[0022] In this technical solution, the excess source drive lines suspended in the source layer are used as signal traces to transmit gate drive signals or common voltage signals. This eliminates the need for additional metal traces, achieving narrow bezels and good display quality while reducing hardware costs. Alternatively, the second trace can be placed at the bend of the pixel electrode in a row of 2-domain pixels. This has minimal impact on pixel display quality, and the addition of a second trace in the source layer can be achieved using a single mask, without incurring higher hardware costs.

[0023] In some possible implementations, the second trace is used to transmit a common voltage signal. In the display area, the second via is disposed in the insulating layer between the source layer and the common electrode layer. The common electrode layer is disposed in the second via and connected to the second trace in the source layer.

[0024] In some possible implementations, the second trace is used to transmit the gate drive signal. In the display area, the second via is disposed in the insulating layer between the gate layer and the source layer, and is located in the intersection area of ​​the second trace and the gate drive line. The second trace in the source layer is disposed in the second via and is connected to the gate drive line in the gate layer.

[0025] In some possible implementations, the second via is positioned adjacent to the pixel region of the blue pixel in the display panel.

[0026] In this technical solution, the blue pixel has a lower brightness than the red or green pixel. By placing the second via next to the pixel area of ​​the blue pixel, the impact of the second via on the display of the AA area can be reduced.

[0027] In some possible implementations, in the lead region, the gate layer is provided with a plurality of first traces, and the source layer is provided with a plurality of source drive lines, with the plurality of first traces and the plurality of source drive lines arranged alternately in sequence.

[0028] The technical solution facilitates routing in the Fanout area and also allows multiple first routing lines to connect to multiple second routing lines that are spaced apart in the AA area.

[0029] In some possible implementations, in the display area, a plurality of second traces are connected to a common electrode layer. The plurality of second traces include multiple sets of second traces, each set of second traces includes at least one second trace, and the multiple sets of second traces are arranged in the display panel at fixed intervals.

[0030] Through this technical solution, multiple second traces used to transmit common voltage signals can be evenly distributed within the plane of the AA area, thereby better ensuring the uniformity of the common voltage within the AA area.

[0031] In some possible implementations, multiple gate driver chips and multiple source driver chips are connected to the same long side of the display panel, and multiple common voltage regions are provided between the multiple gate driver chips in the display panel, which are used to provide a common voltage signal.

[0032] In some possible implementations, the display panel is a touch display panel, and the metal trace layer is a touch metal layer in the touch display panel.

[0033] In this technical solution, the metal trace layer can be reused as the touch metal layer in the touch display panel. This means the touch metal layer in the touch display panel can be reused to transmit source drive signals and / or common voltage signals. This implementation not only facilitates narrow bezels and / or improves display quality in the touch display panel, but also avoids additional hardware costs.

[0034] In some possible implementations, the display panel is a dual-gate driving architecture or a tri-gate driving architecture.

[0035] In a second aspect, a display screen is provided, comprising: a control device, and a display panel as described in the first aspect or any possible embodiment of the first aspect, wherein the control device is used to control the display panel for displaying information. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0037] Figure 2 This is another schematic diagram of the display panel provided in the embodiments of this application.

[0038] Figure 3 This is another schematic diagram of the display panel provided in the embodiments of this application.

[0039] Figure 4 yes Figure 3 A schematic diagram of the area where hole A is located in the embodiment shown.

[0040] Figure 5 yes Figure 4 A schematic diagram of a cross-section of hole A along the A-A' direction.

[0041] Figure 6 yes Figure 4 A schematic diagram of another cross section of hole A along the A-A' direction.

[0042] Figure 7 yes Figure 3 A schematic diagram of the area where hole B is located in the embodiment shown.

[0043] Figure 8 yes Figure 7 A schematic diagram of a cross-section of hole B along the B-B' direction.

[0044] Figure 9 This is another schematic diagram of the display panel provided in the embodiments of this application.

[0045] Figure 10 yes Figure 9 A schematic diagram of the area where hole A is located in the embodiment shown.

[0046] Figure 11 yes Figure 9A schematic diagram of the area where hole C is located in the embodiment shown.

[0047] Figure 12 yes Figure 11 A schematic diagram of a cross-section of the C-hole along the C-C' direction.

[0048] Figure 13 This is another schematic diagram of the display panel provided in the embodiments of this application.

[0049] Figure 14 yes Figure 13 A schematic diagram of the area where hole E is located in the embodiment shown.

[0050] Figure 15 yes Figure 13 A schematic diagram of the area where hole F is located in the embodiment shown.

[0051] Figure 16 This is another schematic diagram of the display panel provided in the embodiments of this application.

[0052] Figure 17 yes Figure 16 A schematic diagram of the area where the H-hole is located in the illustrated embodiment.

[0053] Figure 18 yes Figure 16 Another schematic diagram of the area where the H hole is located in the illustrated embodiment.

[0054] Figure 19 yes Figure 17 and Figure 18 A schematic diagram of a cross-section of the H-hole along the H-H' direction.

[0055] Figure 20 yes Figure 16 A schematic diagram of the area where hole I is located in the embodiment shown.

[0056] Figure 21 yes Figure 20 A schematic diagram of a cross-section of the central hole along the I-I' direction.

[0057] Figure 22 yes Figure 16 A schematic diagram of the area where hole J is located in the embodiment shown.

[0058] Figure 23 yes Figure 22 A schematic diagram of a cross-section of the J-hole along the J-J' direction.

[0059] Figure 24 This is another schematic diagram of the display panel provided in the embodiments of this application. Detailed Implementation

[0060] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0061] This application relates to a display screen, also known as a display panel. The display screen can be applied to various fields and scenarios. As an example, it can be applied to 3C electronic products in the fields of computers, communications, and consumer electronics, including but not limited to televisions, mobile phones, computers, laptops, tablets, personal digital assistants (PDAs), in-vehicle computers, wearable devices, gaming devices, and photographic equipment. This application does not limit the specific type of electronic device in which the display screen is located.

[0062] Furthermore, the display screen involved in this application can be a liquid crystal display (LCD). This LCD screen can be, for example, a thin film transistor (TFT) LCD, which utilizes TFTs to form the driving circuit in the LCD panel. The types of TFTs can include, for example, amorphous silicon (a-Si) TFTs, low-temperature polycrystalline silicon (LTPS) TFTs, low-temperature polycrystalline oxide (LTPO) TFTs, and indium gallium zinc oxide (IGZO) TFTs. Additionally, according to the driving type, LCD screens can include twisted nematic (TN), in-plane switching (IPS), and vertical alignment (VA) types. This application does not limit the specific type of LCD screen.

[0063] Currently, LCD screens are widely used in the automotive field due to their advantages such as high brightness, wide viewing angle, long lifespan, and large size applicability. As automotive screens increasingly pursue integrated large screens and irregular shapes, there is a growing demand for extremely compact screen bezels. Furthermore, as the screen size increases, the display effect is somewhat affected, resulting in display defects such as screen flickering and afterimages.

[0064] In view of this, this application provides a large-size display screen that can compress the display screen bezel or improve the display effect, so that the large-size display screen can be better applied in fields such as automotive.

[0065] Figure 1This diagram illustrates a display panel according to an embodiment of this application. The display panel is the main display component of a screen, and it can be combined with other optical structures such as a backlight and polarizer to form a liquid crystal display.

[0066] like Figure 1 As shown, the display panel 10 includes a lead area 102 and a display area 101. In the lead area 102, a first trace 110 is provided on the gate layer of the display panel 10. The first trace 110 is used to transmit one of a gate drive signal and a common voltage signal. The first trace 110 is connected to a second trace 210 through a first via 111. The second trace 210 is disposed on the source layer or a metal trace layer of the display panel 10. In the display area 101, the second trace 210 is connected to one of a gate drive line in the gate layer and a common electrode layer through a second via 211. As an example, Figure 1 The diagram shows the second trace 210 connected to the gate drive line 120 via the second via 211. Additionally, to distinguish that the first trace 110 and the second trace 210 are located on different layers of the display panel, therefore, in Figure 1 As shown in the related illustrations below, the second line 210 is indicated by a dashed line, but this dashed line does not represent the shape of the second line 210.

[0067] Optionally, the display panel 10 in this embodiment can be a long strip-shaped display panel, which is better suited for the automotive field. As an example, in the display area 101 of the display panel 10, the resolution of the display panel in the length direction is m (i.e., the number of pixels in the length direction of the display area is m), and the resolution in the width direction is n (i.e., the number of pixels in the width direction of the display area is n), where m > 3*n. Optionally, m can be more than 5 times n.

[0068] In this application, the display area can also be called the active area (AA), or simply the AA area. The lead area can also be called the fanout area, or simply the fanout area. The AA area is the normal display area of ​​the display panel, and the multiple pixels used for normal display are distributed in the AA area. The fanout area is the routing area at the edge of the AA area, which is a non-display area. The fanout area can be used to set up the routing between the pixels in the AA area and external control modules (such as chips).

[0069] Pixels in a display panel may include driving circuitry formed by TFTs. A TFT typically includes a gate, a source, and a drain. The gate controls the TFT's on / off state, while one end of the source or drain serves as a data input terminal, and the other as a data output terminal. By controlling the voltage applied to the source or drain, the electric field at the TFT can be controlled, thereby affecting the transmittance of the liquid crystal at that TFT and thus controlling the brightness of the pixel. Furthermore, each pixel may also have corresponding color filter units, allowing it to emit different colors of light signals. For example, a pixel with a red filter unit is called a red pixel and emits red light. A pixel with a green filter unit is called a green pixel and emits green light. A pixel with a blue filter unit is called a blue pixel and emits blue light.

[0070] For ease of description, this application uses the source of a TFT as an example for data input. The display panel may have a source layer, in which the source of the TFT and source driving lines may be formed. The source driving lines can be used to provide data signals to control the emission of pixels. Optionally, in addition to forming the source of the TFT, the source layer may also form the drain of the TFT. Therefore, the source layer may also be called a source-drain layer, or simply an SD layer.

[0071] In addition, the display panel also includes a gate layer, which forms the gate of the TFT and gate drive lines. These gate drive lines can be used to provide control signals to control the on and off of the pixels. In the display panel, the gate layer and the source layer are stacked as a two-layer structure. An insulating layer, also known as a gate insulator (GI), can be disposed between the gate layer and the source layer.

[0072] In a display panel, in addition to the gate layer and the source layer, a common electrode layer can also be provided to provide a stable common voltage, thereby making the light emission display of each pixel in the display panel more stable. This common electrode layer can be disposed above the source layer, and a passivation layer (PVX) and / or an organic layer (ORG) can be disposed between the common electrode layer and the source layer. The passivation layer may include an organic insulating layer such as an oxide.

[0073] In addition to the gate layer and source layer, other metal wiring layers can be provided in the display panel, which can cover the original stacked structure of the display panel. In some embodiments, this metal wiring layer can also be referred to as the M3 layer. The M3 layer can be an additional metal wiring layer of the display panel, or it can also serve as a touch metal layer in a touch display panel.

[0074] In this embodiment, the gate layer of the display panel 10 has a first trace 110 in the Fanout region. This first trace 110 can be connected to the port of a gate driver chip (Gate IC) for transmitting gate drive signals or common voltage signals. The first trace 110 can be connected in the Fanout region to a second trace 210 in the source layer or M3 layer via a first via 111. The extension direction of the second trace 210 can be the same as the extension direction of the source drive trace in the source layer. The second trace 210 can be connected to the gate drive trace or common electrode layer in the gate layer via a second via 211 in the AA region. Gate drive signals can be transmitted to the gate drive trace via the first trace 110 and the second trace 210, or common voltage signals can be transmitted to the common electrode layer via the first trace 110 and the second trace 210.

[0075] In this technical solution, the gate drive signal is transmitted to the source layer or M3 layer using the first trace and the first via in the Fanout area. Therefore, the gate driver chip (GateIC) used to transmit this gate drive signal can be located on the same side of the display panel as the source driver chip (SourceIC) used to transmit the source drive signal, which is beneficial for achieving a narrow bezel design on the other three sides of the display screen. Furthermore, by using the second trace and the second via in the AA area to transmit the common voltage signal to the common electrode layer, the uniformity of the common voltage within the AA area is improved, reducing screen flicker and afterimages, and enhancing the display effect.

[0076] Figure 2 Another schematic diagram of the display panel provided in an embodiment of this application is shown.

[0077] like Figure 2As shown, a common electrode layer (shown as a shaded area in the figure) may be covered in the display area 101 of the display panel 10. In the lead area 102 of the display panel 10, a first trace 110 and a third trace 130 are provided in the gate layer. The first trace 110 and the third trace 130 are respectively used to transmit the common voltage signal of the gate drive signal. The first trace 110 is connected to the second trace 210 through a first via 111, and the third trace 130 is connected to the fourth trace 220 through a third via 131. The second trace 210 and the fourth trace 220 are disposed in the source layer or metal trace layer of the display panel 10. The second trace 210 and the fourth trace 220 are respectively connected to the gate drive line 120 and the common electrode layer in the gate layer.

[0078] As an example, in Figure 2 In the diagram, the first trace 110 is used to transmit the gate drive signal, and the third trace 130 is used to transmit the common voltage signal. The second trace 210 connected to the first trace 110 is connected to the gate drive line 120 in the gate layer through the second via 211, and the fourth trace 220 connected to the third trace 130 is connected to the common electrode layer through the fourth via 221.

[0079] In this technical solution, the transmission of gate drive signals and common voltage signals can be achieved simultaneously using the source layer or metal trace layer through the traces and vias in the Fanout area and AA area. This not only achieves the narrow bezel design of the display panel, but also further improves the uniformity of the common voltage in the AA area, thereby enhancing the display effect.

[0080] The following, with reference to the accompanying drawings, describes the relevant technical solutions for transmitting gate drive signals and common voltage signals using the source layer.

[0081]

Example 1

[0082] Figure 3 Another schematic diagram of the display panel provided in an embodiment of this application is shown.

[0083] like Figure 3 As shown, the display panel 10 can adopt a dual-gate architecture, where a row of pixels in the display panel can be driven by two rows of gate driving lines. The odd-numbered pixels in a row are driven by one row of gate driving lines, and the even-numbered pixels are driven by the other row of gate driving lines. As an example, Figure 3 The diagram illustrates two rows of pixels in a display panel, where the first row of pixels is driven by gate driving lines Gn and Gn+1, and the second row of pixels is driven by gate driving lines Gn+2 and Gn+3.

[0084] In this dual-gate architecture display panel 10, two adjacent columns of pixels can be connected to the same source drive line, and these two adjacent columns of pixels can form a group of pixels. As an example, Figure 3 The diagram illustrates three groups of pixels in the display panel. Adjacent columns of pixels in these groups are connected to source driver lines Sn, Sn+1, and Sn+2, respectively. Additionally, a floating source driver line S' can be placed between adjacent groups of pixels. This floating source driver line S' is not connected to the source driver chip but is placed in the source layer to ensure uniformity of the trace distribution in the display panel 10.

[0085] For a display panel with a resolution of m*n, where m > 3*n, the number of floating source driver lines S' is m / 2, and the number of gate driver lines is 2n. When m > 4*n, the floating source driver lines S' can be used to transmit all gate driver signals to the corresponding gate driver lines in the plane. For example, the i-th floating source driver line S'(i) in the display panel can be used to transmit the gate driver signal of the i-th row to the corresponding i-th gate driver line Gi in the plane, thereby driving the display panel to light up normally.

[0086] In view of this, such as Figure 3 As shown, the source driver chip 103 is connected to multiple source driver lines (e.g., source driver lines Sn, Sn+1, and Sn+2) through traces in the source layer (shown as dashed lines in the figure), and the gate driver chip 104 is connected to multiple floating source driver lines S' through traces in the gate layer (shown as solid lines in the figure). In the Fanout region 102, the traces in the gate layer (an example of the first or third trace in the above embodiment) are connected to the floating source driver lines S' (an example of the second or fourth trace in the above embodiment) in the source layer through via A (an example of the first or third via in the above embodiment). In the AA region 101, the floating source driver lines S' in the source layer are then connected to the gate driver lines through via B (an example of the second or fourth via in the above embodiment), thereby enabling the gate drive signal transmitted by the gate driver chip 104 to be transmitted to the gate driver lines through the floating source driver lines S' in the source layer.

[0087] The technical solution of this application utilizes the excess source drive lines suspended in the source layer as signal traces for transmitting gate drive signals, without the need to add new metal traces. This achieves narrow bezels and good display effects while reducing hardware costs.

[0088] Figure 4 It shows Figure 3 A schematic diagram of the area where hole A is located in the embodiment shown.

[0089] like Figure 4As shown, in the Fanout region, source layer traces and gate layer traces can be spaced apart. The source layer traces connect to the source drive lines in region AA and the source drive chip, and are used to transmit the source drive signal S. The gate layer traces connect to the floating source drive lines in region AA and the gate drive chip, and are used to transmit the gate drive signal G. Figure 4 In this example, the source layer trace can be connected to the source drive line of region AA to form a metal trace. Alternatively, the floating source drive line of region AA can also extend to the Fanout region and be connected to the gate layer trace in the Fanout region through via A.

[0090] Optionally, in Figure 4 In the embodiment shown, the gate layer traces in the Fanout region and the floating source drive lines can be connected through one or more A-holes, thereby improving the reliability of the connection between the two and helping to ensure signal transmission performance.

[0091] Figure 5 It shows Figure 4 A schematic diagram of a cross-section of hole A along the A-A' direction.

[0092] like Figure 5 As shown, the stacked structure of the display panel 10 may include: a substrate 300, a gate layer 100, a gate insulating layer (GI) 400, a source layer 200, a first passivation layer (PVX1) 500, an inorganic insulating layer (ORG) 600, and a second passivation layer (PVX2) 700. Optionally, the substrate 300 may be, for example, glass. The gate layer 100 may be simply referred to as the GE layer, and the source layer 200 may also be referred to as the source-drain layer, or simply the SD layer.

[0093] To achieve the connection between the gate layer trace and the source layer trace, such as Figure 5 As shown, the GI layer 400 covering the GE layer 100 can form a via (i.e., A-hole), which is disposed in the SD layer 200 and connected to the GE layer 100 through the via. PVX1 layer 500, ORG layer 600, and PVX2 layer 700, etc., cover the SD layer 200 and can be used for insulation between the SD layer and other film layers, as well as for planarization of the display panel.

[0094] Figure 6 It shows Figure 4 A schematic diagram of another cross section of hole A along the A-A' direction.

[0095] like Figure 6As shown in the embodiments of this application, the stacked structure of the display panel 10 may further include a pixel electrode layer 800, the material of which may be, for example, an indium tin oxide (ITO) thin film. This pixel electrode layer 800 may be simply referred to as a P-ITO layer. To achieve the connection between the gate layer traces and the source layer traces, vias may be formed not only in the GI layer 400, but also further in the PVX1 layer 500, ORG layer 600, and PVX2 layer 700. The P-ITO layer 800 is connected to the SD layer 200 through the vias in the PVX1 layer 500, ORG layer 600, and PVX2 layer 700. Figure 4 As shown, when the gate layer trace and the source layer trace are connected through multiple vias (A-holes), the electrical connection between the multiple vias can be achieved through the pixel electrode layer 800.

[0096] Figure 7 It shows Figure 3 A schematic diagram of the area where hole B is located in the embodiment shown.

[0097] like Figure 7 As shown, in region AA, the source driving line and the gate driving line extend in two mutually perpendicular directions. A B-hole can be formed at the intersection of the floating source driving line and the gate driving line, thereby realizing the connection between the floating source driving line and the gate driving line.

[0098] Figure 8 It shows Figure 7 A schematic diagram of a cross-section of hole B along the B-B' direction.

[0099] like Figure 8 As shown, to achieve the connection between the gate layer trace and the source layer trace, a via (i.e., a B-hole) can be formed in the GI layer 400 covering the GE layer 100. The SD layer 200 is disposed in this via, and the connection with the GE layer 100 is achieved through this via. Films such as the PVX1 layer 500, ORG layer 600, and PVX2 layer 700 cover the SD layer 200 and can be used for insulation between the SD layer and other film layers, as well as for planarization of the display panel. In addition, in this embodiment, a common electrode layer 900 is formed between the ORG layer 600 and the PVX2 layer 700. The material of this common electrode layer 900 can be, for example, an ITO thin film. This common electrode layer 900 can be simply referred to as a C-ITO layer. Optionally, this common electrode layer 900 can cover the entire AA area of ​​the display panel.

[0100]

Example 2

[0101] Figure 9Another schematic diagram of the display panel provided in an embodiment of this application is shown.

[0102] like Figure 9 As shown, the display panel 10 can be connected with... Figure 3 The illustrated embodiment is similar, employing a dual-gate architecture. In this embodiment, a common electrode layer (shown as a shaded area in the figure) is provided in the AA area 101 of the display panel 10. A common voltage area may be provided in the Fanout area 102 of the display panel 10, which can be used to provide a common voltage Vcom. Optionally, the common voltage Vcom in this common voltage area can be input through other control circuits or controllers connected to the display panel 10.

[0103] In the gate layer of Fanout region 102, traces are provided (shown as solid lines in the diagram, corresponding to...). Figure 1 and Figure 2 The first or third trace in the illustrated embodiment is connected to a common voltage region. This trace can be used to transmit the common voltage Vcom, and the trace can be connected via an A-hole ( Figure 1 and Figure 2 (An example of the first or third via in the illustrated embodiment) is connected to the suspended source drive line S' in the source layer. Figure 1 and Figure 2 (An example of the second or fourth trace in the illustrated embodiment) thereby enabling the transmission of the common voltage Vcom signal through the floating source drive line S' in the source layer. Furthermore, this floating source drive line S' can be transmitted through a C-hole (… Figure 1 and Figure 2 In the illustrated embodiment, the second or fourth via is connected to the common electrode layer in the AA area, thereby providing a common voltage to the AA area and improving the uniformity of the common voltage in the AA area, thus improving the display effect of the display panel.

[0104] Optionally, Figure 9 For illustrative purposes only, this diagram shows a common voltage zone in the display panel and a floating source drive line S' for transmitting Vcom. The display panel can also have multiple common voltage zones distributed throughout. Each common voltage zone can be connected to multiple floating source drive lines S' for transmitting Vcom. These multiple floating source drive lines S' for transmitting Vcom can be evenly distributed within the plane of the AA zone, thereby better ensuring the uniformity of the common voltage within the AA zone.

[0105] In some embodiments, the display panel is provided with multiple floating source drive lines S' for transmitting Vcom. The multiple floating source drive lines S' include multiple sets of floating source drive lines S', each set of floating source drive lines S' includes at least one, and the multiple sets of floating source drive lines S' are arranged in the display panel at fixed intervals.

[0106] exist Figure 9 In the embodiment shown, the floating source drive line S' in the display panel can transmit gate drive signals in addition to transmitting Vcom. The relevant technical solution for transmitting gate drive signals can be found in the relevant description in Embodiment 1 above, and will not be elaborated further here.

[0107] Figure 10 It shows Figure 9 A schematic diagram of the area where hole A is located in the embodiment shown.

[0108] like Figure 10 As shown, in the Fanout region, source layer traces and gate layer traces can be spaced apart. The source layer traces connect to the source drive line and the source drive chip in region AA, and are used to transmit the source drive signal S. The gate layer traces connect to the floating source drive line and the gate drive chip in region AA, or connect to the floating source drive line and the common voltage region in region AA. When the gate layer trace is connected to the gate drive chip, it is used to transmit the gate drive signal G. When the gate layer trace is connected to the common voltage region, it is used to transmit the common voltage signal Vcom.

[0109] exist Figure 10 In the example, the source layer trace can be connected to the source drive line of region AA to form a single metal trace. Alternatively, the floating source drive line of region AA can extend to the Fanout region and connect to the gate layer trace in that Fanout region via via A.

[0110] Optionally, multiple gate layer traces can be used to transmit the gate drive signal G and the common voltage signal Vcom at intervals, for example, as shown below. Figure 10 As shown, after transmitting the gate drive signal G using two gate layer traces, two more gate layer traces are spaced apart to transmit the common voltage signal Vcom, and then two more gate layer traces are set to transmit the gate drive signal G, and so on. This implementation method helps to further improve the uniformity of the in-plane common voltage and also facilitates the trace design of the Fanout region.

[0111] for Figure 9 and Figure 10 In the illustrated embodiment, within the Fanout region, regardless of whether the gate layer trace is used to transmit a gate drive signal or a common voltage signal, the gate layer trace can be connected to the floating source drive line S' via via A. The cross-sectional structure of via A in this Fanout region can be found above. Figure 6 The relevant descriptions of the illustrated embodiments will not be repeated here. Additionally, Figure 9 The cross-sectional structure of hole B in the illustrated embodiment can also be found above. Figure 7 The relevant descriptions of the embodiments shown will not be repeated here.

[0112] Figure 11 It shows Figure 9 A schematic diagram of the area where hole C is located in the embodiment shown.

[0113] like Figure 11 As shown, the C-hole connecting the suspended source driving line S' to the common electrode layer can be located in the projection area of ​​the suspended source driving line S'. In some embodiments, the C-hole can be located in the middle region between two adjacent pixel regions, or in other embodiments, the C-hole can be located in the overlapping region of the suspended source driving line S' and the gate driving line.

[0114] Combination Figure 9 and Figure 11 As shown, the C-hole, which connects the suspended source drive line S' to the common electrode layer, can be positioned adjacent to a blue pixel in the display panel. In this embodiment, the blue pixel has lower brightness compared to the red or green pixel; placing the C-hole next to the blue pixel can reduce its impact on the image display in the AA area.

[0115] Alternatively, in some alternative embodiments, the C-hole connecting the suspended source drive line S' to the common electrode layer can also be arranged adjacent to the red or green pixels in the display panel.

[0116] Figure 12 It shows Figure 11 A schematic diagram of a cross-section of the C-hole along the C-C' direction.

[0117] like Figure 12 As shown, in order to achieve the connection between the source layer trace and the common electrode layer, the PVX1 layer 500 and ORG layer 600 covering the SD layer 200 are provided with vias (i.e., C-holes). The common electrode layer 900 and the PVX2 layer 700 covering the common electrode layer 900 are disposed in the vias, and the connection with the SD layer is achieved through the vias.

[0118] Example 2 above illustrates a technical solution for simultaneously transmitting gate drive signals and common voltage signals using a floating source drive line in the source layer. Optionally, embodiments of this application may also provide a technical solution for transmitting common voltage signals using a floating source drive line in the source layer, without transmitting gate drive signals.

[0119]

Example 3

[0120] Figure 13 Another schematic diagram of the display panel provided in an embodiment of this application is shown.

[0121] like Figure 13 As shown, the display panel 10 can adopt a triple-gate architecture, in which pixels are arranged horizontally instead of vertically as in the traditional configuration. Each row of pixels is connected to a gate driving line (Gn, Gn+1, and Gn+2 are shown in the figure as an example), and each column of pixels is connected to a source driving line (Sn, Sn+1, and Sn+2 are shown in the figure as an example). In this triple-gate architecture, the number of source driving lines is 1 / 3 of that in the traditional single-gate architecture, and the number of gate driving lines is 3 times that of the single-gate architecture. Using this triple-gate architecture can significantly reduce the number of source driving chips used, which is beneficial for cost reduction.

[0122] In some embodiments, the pixels of the display panel can adopt a dual-domain structure. In a dual-domain pixel, the pixel electrode is bent in the middle region to form a bend. Optionally, the bend in the pixel electrode is formed at the central axis. The liquid crystal in the bend of the pixel electrode is generally not controlled by the electric field of the pixel electrode, and therefore has little impact on the display effect of the panel. In view of this, a trace can be provided corresponding to the bend of the pixel electrode, for example, by adding an additional trace in the source layer to transmit the gate drive signal and / or common voltage signal.

[0123] See Figure 13 As shown, multiple additional traces S” are correspondingly set on the central axis of each column of pixels, which can correspond to the bend of the pixel electrode in each column of pixels.

[0124] For a display panel with a resolution of m*n, where m > 3*n, the number of additional traces S” is m, and the number of gate drive lines is n. When m is much larger than n, the additional traces S” can be used to transmit all gate drive signals to the corresponding gate drive lines in the plane. For example, the i-th additional trace S”” in the display panel can be used to transmit the gate drive signal of the i-th row to the i-th gate drive line Gi in the plane, thereby driving the display panel to light up normally.

[0125] In view of this, such as Figure 13 As shown, the source driver chip 103 is connected to multiple source driver lines (e.g., source driver lines Sn, Sn+1, and Sn+2) through traces in the source layer (shown as dashed lines in the figure), and the gate driver chip 104 is connected to multiple additional traces S” through traces in the gate layer (shown as solid lines in the figure). In the Fanout region 102, the traces in the gate layer ( Figure 1 and Figure 2 An example of the first or third trace in the illustrated embodiment) passes through a D-hole ( Figure 1 and Figure 2An example of the first or third via in the illustrated embodiment) is connected to an additional trace S" of the source layer. Figure 1 and Figure 2 In the illustrated embodiment, an example of the second or fourth trace, in region AA 101, the additional trace S” of the source layer passes through via E ( Figure 1 and Figure 2 In the illustrated embodiment, a second or fourth via is connected to the gate drive line, thereby enabling the gate drive signal transmitted by the gate drive chip 104 to be transmitted to the gate drive line through the floating source drive line S' in the source layer.

[0126] In addition, such as Figure 13 As shown, a common electrode layer (shown as shaded area in the figure) is also provided in the AA area 101 of the display panel 10. A common voltage region can also be provided in the Fanout area 102 of the display panel 10, which can be used to provide a common voltage Vcom. A trace is provided in the gate layer of the Fanout area 102. Figure 1 and Figure 2 In the illustrated embodiment, the first trace or another example of the third trace is connected to a common voltage region. This trace can be used to transmit the common voltage Vcom, and it can be connected to an additional trace S” in the source layer via a D-hole, thereby enabling the transmission of the common voltage Vcom signal through the additional trace S” in the source layer. Further, the additional trace S” can be connected via an F-hole (… Figure 1 and Figure 2 In the illustrated embodiment, the second or fourth via (another example) is connected to the common electrode layer in the AA area, thereby providing a common voltage to the AA area, improving the uniformity of the common voltage in the AA area, and thus improving the display effect of the display panel.

[0127] Optionally, Figure 13 For illustrative purposes only, this diagram shows a common voltage zone in the display panel and an additional trace S for transmitting Vcom. The display panel can also have multiple common voltage zones distributed throughout. One common voltage zone can be connected to multiple additional traces S" for transmitting Vcom. These multiple additional traces S" for transmitting Vcom can be evenly distributed within the surface of the AA zone, thereby better ensuring the uniformity of the common voltage within the AA zone.

[0128] In some embodiments, the display panel is provided with multiple additional traces "S" for transmitting Vcom. The multiple additional traces "S" include multiple sets of additional traces "S", each set of additional traces "S" includes at least one additional trace, and the multiple sets of additional traces "S" are arranged in the display panel at fixed intervals.

[0129] Through the technical solution of the embodiments of this application, an additional trace S” corresponding to the central axis of a row of 2domain type pixels can be set in the source layer. The gate drive signal or common voltage signal is transmitted by the additional trace S”, which has little impact on the pixel display effect. Moreover, the additional trace S” in the source layer can also be implemented by a mask, which will not bring high hardware cost.

[0130] Figure 14 It shows Figure 13 A schematic diagram of the area where hole E is located in the embodiment shown.

[0131] like Figure 14 As shown, in region AA, the source driving line and the gate driving line extend in two mutually perpendicular directions. An additional trace is located between the two source driving lines and at the central axis of the pixel. An E-hole can be formed at the intersection of the additional trace and the gate driving line to achieve the connection between the additional trace and the gate driving line.

[0132] Figure 15 It shows Figure 13 A schematic diagram of the area where hole F is located in the embodiment shown.

[0133] Combination Figure 13 and Figure 15 As shown, the F-hole connecting the additional trace S” to the common electrode layer can be arranged adjacent to the blue pixel in the display panel. In this embodiment, placing the F-hole next to the blue pixel can reduce the impact of the F-hole on the image display in the AA area. Alternatively, in some alternative embodiments, the F-hole connecting the additional trace S” to the common electrode layer can also be arranged adjacent to the red or green pixel in the display panel.

[0134] In this embodiment, the distribution and cross-sectional structure of the aforementioned hole D in the Fanout region can be found in the relevant technical solutions for hole A in embodiments 1 and 2 above. The cross-sectional structure of the aforementioned hole E can be found in the relevant technical solutions for hole B in embodiments 1 and 2 above. The cross-sectional structure of the aforementioned hole F can be found in the relevant technical solutions for hole C in embodiments 1 and 2 above.

[0135] Example 3 above illustrates a technical solution for simultaneously transmitting gate drive signals and common voltage signals using additional traces in the source layer. Optionally, embodiments of this application may also provide a technical solution for transmitting common voltage signals using additional traces in the source layer, without transmitting gate drive signals. Alternatively, embodiments of this application may also provide a technical solution for transmitting gate drive signals using additional traces in the source layer, without transmitting common voltage signals.

[0136] Example 3 above illustrates a display panel with a three-gate architecture. Optionally, the display panel in Example 3 can also be a two-gate architecture or a conventional single-gate architecture. The above-described technique of using additional traces to transmit gate drive signals and / or common voltage signals can be applied to any display panel with a 2-domain pixel structure.

[0137] The foregoing, with reference to the accompanying drawings, describes the technical solutions provided in this application for transmitting gate drive signals and / or common voltage signals using a source layer. Below, with reference to the accompanying drawings, the technical solutions provided in this application for transmitting gate drive signals and / or common voltage signals using a metal trace layer are described.

[0138] [Example 4] Gate drive signal and common voltage signal are transmitted using the traces in the metal trace layer M3.

[0139] Figure 16 Another schematic diagram of the display panel provided in an embodiment of this application is shown.

[0140] like Figure 16 As shown, the display panel 10 can be connected with... Figure 13 The illustrated embodiment is similar, employing a triple-gate architecture. Optionally, the pixels in the display panel 10 can be in a 2-domain configuration, or a 1-domain configuration, or other configurations; this application embodiment does not limit this.

[0141] In the display panel 10, an additional metal trace layer M3 is provided. This M3 layer can be disposed above the common electrode layer in the display panel, and an insulating layer is provided between the M3 layer and the common electrode layer to provide electrical isolation between them. In area AA 101, multiple M3 traces (e.g., Mn, Mn+1, and Mn+2 as shown in the figure) can be provided in the M3 layer. The M3 traces can be correspondingly arranged with the source drive lines in the source layer (e.g., Sn, Sn+1, and Sn+2 as shown in the figure). In some examples, the orthographic projection of the M3 traces in the source layer can overlap with the source drive lines; in other words, such as... Figure 16 As shown, the source drive line can be located in the orthographic projection of the M3 trace in the source layer.

[0142] For a display panel with a resolution of m*n, where m > 3*n, where m corresponds to the number of source drive lines and n corresponds to the number of gate drive lines, the number of M3 traces in the M3 layer can be less than or equal to m and greater than or equal to n. In this case, all gate drive signals can be transmitted to the corresponding gate drive lines within the plane using the M3 traces in the M3 layer. Furthermore, the common voltage signal can be transmitted to the common electrode layer within the plane using the M3 traces in the M3 layer.

[0143] like Figure 16 As shown, the source driver chip 103 is connected to multiple source driver lines (e.g., source driver lines Sn, Sn+1, and Sn+2) through traces in the source layer (shown as dashed lines in the figure), and the gate driver chip 104 is connected to multiple M3 traces (e.g., Mn, Mn+1, and Mn+2) in the M3 layer through traces in the gate layer (shown as solid lines in the figure). In the Fanout region 102, the traces in the gate layer ( Figure 1 and Figure 2 An example of the first or third trace in the illustrated embodiment) passes through an H-hole ( Figure 1 and Figure 2 An example of the first or third via in the illustrated embodiment is connected to the M3 trace on the M3 layer. Figure 1 and Figure 2 In the illustrated embodiment (an example of the second or fourth trace), in area AA 101, the M3 trace passes through an I-hole ( Figure 1 and Figure 2 In the illustrated embodiment, a second or fourth via is connected to the gate drive line, thereby enabling the gate drive signal transmitted by the gate drive chip 104 to be transmitted to the gate drive line through the M3 trace in the M3 layer.

[0144] Additionally, a common electrode layer (shown as a shaded area in the figure) is provided in the AA area 101 of the display panel 10. A common voltage region may be provided in the Fanout area 102 of the display panel 10, which can be used to provide a common voltage Vcom. Traces (shown as solid lines in the figure) are provided in the gate layer of the Fanout area 102. Figure 1 and Figure 2 In the illustrated embodiment, the first or third trace (another example) is connected to the common voltage region. This trace can be connected to the M3 trace of the M3 layer via an H-hole, thereby enabling the transmission of the common voltage Vcom signal through the M3 trace of the M3 layer. Furthermore, this M3 trace can be connected via a J-hole (… Figure 1 and Figure 2 (Another example of the second or fourth via in the illustrated embodiment) is connected to the common electrode layer in the AA region, thereby providing a common voltage to the plane of the AA region.

[0145] The technical solution of this application embodiment designs the traces in the M3 trace layer to be consistent with the source drive lines in the source layer. When using the M3 traces to transmit the gate drive signal to the in-plane area of ​​the display panel, the gate drive chip for transmitting the gate drive signal can be located on the same side as the source drive chip for transmitting the source drive signal, which is beneficial for achieving a narrow bezel design of the display screen. When using the M3 traces to transmit the common voltage signal to the in-plane area of ​​the display panel, it is beneficial for achieving uniformity of the common voltage in the in-plane area, thus improving the display effect of the display panel.

[0146] Optionally, in some embodiments, the M3 layer can be reused as a touch metal layer in the touch display panel. This means the M3 layer in the touch display panel can be reused to transmit source drive signals and / or common voltage signals. This implementation not only facilitates narrow bezels and / or improves display quality in the touch display panel but also avoids additional hardware costs.

[0147] Optionally, Figure 16 This illustration only shows a common voltage zone in the display panel and an M3 trace for transmitting Vcom. The display panel can also have multiple common voltage zones distributed throughout. One common voltage zone can be connected to multiple M3 traces for transmitting Vcom. These multiple M3 traces for transmitting Vcom can be evenly distributed within the plane of the AA zone, thereby better ensuring the uniformity of the common voltage within the AA zone.

[0148] In some embodiments, the display panel is provided with multiple M3 traces for transmitting Vcom. The multiple M3 traces include multiple groups of M3 traces, each group of M3 traces includes at least one M3 trace, and the multiple groups of M3 traces are arranged in the display panel at fixed intervals.

[0149] Figure 17 It shows Figure 16 A schematic diagram of the area where the H-hole is located in the illustrated embodiment.

[0150] like Figure 17 As shown, in the Fanout region, the M3 trace can cover the gate layer trace. Optionally, the gate layer trace can be located as the orthogonal projection of the corresponding M3 layer trace onto the gate layer. The gate layer trace can be connected to the gate driver chip for transmitting the gate drive signal G. Additionally, a source layer trace can also be provided in the Fanout region, connecting to the source drive line in the AA region and the source driver chip, and this source layer trace is used to transmit the source drive signal S. Figure 17 In the example, the source layer trace can be connected to the source drive line of region AA as a single metal trace. The M3 trace can extend from region Fanout to region AA, and the M3 trace located in region AA can be configured to correspond with the source drive line in region AA.

[0151] The M3 trace located in the Fanout region can be connected via an H-hole to the gate layer trace used to transmit the gate drive signal G, thereby enabling the transmission of the gate drive signal G to the AA region. Optionally, in some embodiments, the common voltage signal Vcom can also be transmitted through the gate layer trace. In this embodiment, the M3 trace located in the Fanout region can also be connected via an H-hole to the gate layer trace used to transmit the common voltage signal Vcom, thereby enabling the transmission of the common voltage signal Vcom to the AA region.

[0152] exist Figure 17 In the example shown, multiple gate layer traces used to transmit the gate drive signal G can be arranged adjacently. Similarly, multiple gate layer traces used to transmit the common voltage signal Vcom can also be arranged adjacently. Correspondingly, multiple M3 traces used to transmit the gate drive signal G can be arranged adjacently, and multiple M3 traces used to transmit the common voltage signal Vcom can also be arranged adjacently. In this embodiment, the gate layer traces and M3 traces used to transmit the same signal can be arranged close together, which is beneficial for the arrangement and distribution of traces in the Fanout area, improving the uniformity of metal traces within the display panel, thereby improving the overall performance of the display panel.

[0153] Figure 18 It shows Figure 16 Another schematic diagram of the area where the H hole is located in the illustrated embodiment.

[0154] like Figure 18 As shown, in the Fanout region, the gate layer traces, source layer traces, and M3 traces are basically the same as those described above. Figure 17 The example shown is similar, the difference being that... Figure 18 In the example shown, the Vcom signal can be directly transmitted using the M3 trace. This M3 trace can be connected to the common voltage area of ​​the display panel to achieve Vcom signal transmission. In this implementation, the M3 trace used to transmit Vcom does not need to be connected to the gate layer trace through an H-hole. For the M3 trace transmitting the gate drive signal, as described above... Figure 17 Similarly, it needs to be connected to the gate layer trace used to transmit the gate drive signal G via the H-hole.

[0155] Optionally, in Figure 18 In the example shown, multiple M3 traces for transmitting the gate drive signal G and multiple M3 traces for transmitting the common voltage signal Vcom are arranged alternately. This embodiment ensures that the traces for transmitting the Vcom signal and the traces for transmitting the gate drive signal G are evenly distributed in the AA area of ​​the display panel, which helps improve the uniformity of Vcom within the display screen.

[0156] Optionally, in the above Figure 17 and Figure 18 In the illustrated embodiment, the M3 trace in the Fanout region and the gate layer trace can be connected through one or more H-holes, thereby improving the reliability of the connection between the two and helping to ensure signal transmission performance.

[0157] Figure 19 It shows Figure 17 and Figure 18 A schematic diagram of a cross-section of the H-hole along the H-H' direction.

[0158] like Figure 19 As shown, the stacked structure of the display panel 10 may include: a substrate 300, a gate layer 100, a gate insulating layer (GI) 400, a first passivation layer (PVX1) 500, an inorganic insulating layer 600, a second passivation layer (PVX2) 700, a pixel electrode layer (P-ITO) 800, a third passivation layer (PVX3) 1000, and an M3 layer 1100.

[0159] To achieve the connection between the gate layer trace and the M3 layer trace, such as Figure 19 As shown, the GI layer 400, PVX1 layer 500, ORG layer 600, PVX2 layer 700 and PVX3 layer 1000 covering the GE layer 100 can form vias (i.e. H-holes). The P-ITO layer 800 and M3 layer 1100 are disposed in the vias, and the M3 layer 1100 is connected to the GE layer 100 through the P-ITO layer 800.

[0160] Figure 20 It shows Figure 16 A schematic diagram of the area where hole I is located in the embodiment shown.

[0161] like Figure 20 As shown, in region AA, the source driving line and the gate driving line extend in two mutually perpendicular directions. The M3 trace extends in the same direction as the source driving line and is correspondingly positioned to it. At a corner of the pixel region, the gate driving line has a first protrusion perpendicular to the gate driving line, and the M3 trace has a second protrusion perpendicular to the M3 trace. The two protrusions have an intersection area, and an I-hole for connecting the M3 trace and the gate driving line can be located in this intersection area.

[0162] With the technical solution of this embodiment, the I-hole used to connect the M3 trace and the gate drive line can be set in the corner area of ​​the pixel, which can reduce the impact on the display effect of the pixel.

[0163] Figure 21 It shows Figure 20 A schematic diagram of a cross-section of the central hole along the I-I' direction.

[0164] like Figure 21As shown, the stacked structure of the display panel 10 may further include a source layer (SD) 200 and a common electrode layer (C-ITO) 900. To achieve the connection between the gate layer traces and the M3 layer traces, vias (i.e., I-holes) can be formed in the GI layer 400, PVX1 layer 500, ORG layer 600, PVX2 layer 700, C-ITO layer 900, and PVX3 layer 1000 covering the GE layer 100. The M3 layer 1100 is disposed in these vias to achieve connection with the GE layer 100. In this embodiment, the aperture of the via at the C-ITO layer 900 is larger than the apertures of the vias in other layers. The C-ITO layer 900 does not contact the M3 layer 1100 to prevent signals on the M3 layer 1100 from interfering with the common voltage signal on the C-ITO layer 900.

[0165] Figure 22 It shows Figure 16 A schematic diagram of the area where hole J is located in the embodiment shown.

[0166] like Figure 22 As shown, the M3 trace in the figure can be used to transmit a common voltage signal. In area AA, the M3 trace used to transmit the common voltage signal can be connected to the common electrode layer through a J-hole. This J-hole can correspond to the source drive line; for example, the J-hole can be located in the orthographic projection area of ​​the source drive line.

[0167] In this embodiment, the J-hole used to connect the M3 trace and the common electrode layer is located in the area of ​​the source drive line, rather than the pixel area. This does not affect the aperture ratio of the pixels in the display panel and helps to ensure the display effect of the pixels.

[0168] Combination Figure 16 and Figure 22 As shown, the J-hole can be positioned adjacent to a blue pixel in the display panel. In this embodiment, placing the J-hole next to the blue pixel reduces its impact on the image display in the AA area. Alternatively, in some alternative embodiments, the J-hole can also be positioned adjacent to a red or green pixel in the display panel.

[0169] Figure 23 It shows Figure 22 A schematic diagram of a cross-section of the J-hole along the J-J' direction.

[0170] like Figure 23 As shown, in order to achieve the connection between the M3 layer trace and the common electrode layer, the PVX3 layer 1000 covering the common electrode layer (C-ITO) 900 can be formed with a via (i.e., J-hole), and the M3 layer 1100 is disposed in the via to achieve the connection with the C-ITO layer 900.

[0171] Example 4 above illustrates a technical solution for simultaneously transmitting gate drive signals and common voltage signals using the M3 trace in the M3 layer. Optionally, embodiments of this application may also provide a technical solution for transmitting common voltage signals using the M3 trace without transmitting gate drive signals. Alternatively, embodiments of this application may also provide a technical solution for transmitting gate drive signals using the M3 trace without transmitting common voltage signals.

[0172] Furthermore, in Embodiment 4 above, a three-gate architecture for the display panel was used as an example. Optionally, the display panel in Embodiment 4 could also be a two-gate architecture or a conventional single-gate architecture. This application does not limit the specific architecture of the display panel.

[0173] Figure 24 Another schematic diagram of the display panel provided in an embodiment of this application is shown.

[0174] like Figure 24 As shown, the display panel 10 can be connected to multiple source driver chips 103 and multiple gate driver chips 104 on the same long side. In addition, multiple common voltage regions (shown as Vcom in the figure) are provided between the multiple gate driver chips 104.

[0175] In the Fanout area 102, gate layer traces (shown as solid lines in the figure) can be connected to multiple gate driver chips 104 and multiple common voltage regions respectively, thereby transmitting gate drive signals and common voltage signals respectively. In this embodiment, the gate layer traces connected to each common voltage region can be located between the gate layer traces connected to two gate driver chips 104. In the AA area, the source layer traces or M3 traces used for transmitting the common voltage signal can be distributed among the source layer traces or M3 traces used for transmitting the gate layer traces, so that the source layer traces used for transmitting the common voltage signal can be uniformly disposed within the AA area of ​​the display panel, improving the uniformity of the common voltage.

[0176] Furthermore, multiple source driver chips 103 can be connected to source driver lines via source layer traces (shown as dashed lines in the figure) to control the brightness of pixels within the display panel 10. Further, the multiple source driver chips 103 can be connected to at least one circuit board 105. For example, for a long display panel, two or more circuit boards can be used to connect multiple source driver chips 103. This circuit board 105 can be connected to the same control chip or control circuit board 106. The control chip may include, for example, a timing controller (TCON) chip, used to provide relevant timing information and pixel data signals (source signals) for the display panel 10.

[0177] Figure 24This is just an example to illustrate how... Figure 16 The structure of the display panel shown is as follows: Figure 23 The distribution of multiple source driver chips 103, multiple gate driver chips 104, and multiple common voltage regions can also be applied to the architecture of the display panel provided in any of the above embodiments, for example, in the application of... Figure 1 , Figure 2 , Figure 3 , Figure 9 and Figure 13 The architecture of the display panel in any of the embodiments.

[0178] This application also provides a display screen, which may include the display panel provided in any of the embodiments described above. Further, the display screen may also include a control device for controlling the display panel. Optionally, the control device may include any one or more of the following control chips: a source driver chip, a gate driver chip, and a TCON chip.

[0179] This application also provides an electronic device, which may include the display screen in the above embodiments. The display screen may be a liquid crystal display screen. The electronic device may be any electronic device equipped with a liquid crystal display screen. As an example, the electronic device may be an in-vehicle electronic device, which may include: a central control screen, an instrument panel, a head-up display (HUD), etc. The embodiments of this application do not limit the specific application form of the electronic device.

[0180] The directional terms used in the above description refer to the directions shown in the figures and are not intended to limit the specific structure of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0181] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists, A and B exist simultaneously, and B exists.

[0182] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the description, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy.

[0183] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0184] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0185] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, The display panel includes a lead area and a display area. In the display area, the resolution of the display panel in the length direction is m, and the resolution in the width direction is n, where m > 3*n. In the lead area, the gate layer of the display panel is provided with a first trace, which is used to transmit one of the gate drive signal and the common voltage signal. The first trace is connected to a second trace through a first via. The second trace is provided in the source layer or the metal trace layer of the display panel. In the display area, the second trace is connected to one of the gate drive line in the gate layer and the common electrode layer through a second via.

2. The display panel according to claim 1, characterized in that, In the lead area, the gate layer is further provided with a third trace, which is used to transmit the other of the gate drive signal and the common voltage signal. The third trace is connected to a fourth trace through a third via, and the fourth trace is provided in the source layer or the metal trace layer. In the display area, the fourth trace is connected to the gate drive line in the gate layer and another in the common electrode layer through a fourth via.

3. The display panel according to claim 1, characterized in that, The second trace is disposed on the metal trace layer, the metal trace layer is located above the common electrode layer, and an insulating layer is provided between the metal trace layer and the common electrode layer; The orthogonal projection of the second trace in the source layer overlaps with the source drive line in the source layer.

4. The display panel according to claim 3, characterized in that, The second trace is used to transmit a common voltage signal. In the display area, the second via is disposed in the insulating layer between the metal trace layer and the common electrode layer, and is located in the orthogonal projection area of ​​the source drive line. The second trace in the metal trace layer is disposed in the second via and is connected to the common electrode layer.

5. The display panel according to claim 4, characterized in that, The second via is disposed adjacent to the pixel area of ​​the blue pixel in the display panel.

6. The display panel according to claim 3, characterized in that, The second trace is used to transmit gate drive signals. In the display area, the second via is disposed in a plurality of insulating layers between the gate layer and the metal trace layer. The second trace in the metal trace layer is disposed in the second via and connected to the gate drive line in the gate layer.

7. The display panel according to claim 6, characterized in that, The second via is located at the corner of the pixel area of ​​the pixel in the display panel.

8. The display panel according to any one of claims 3 to 7, characterized in that, In the lead area, the first trace is connected to the common voltage area of ​​the display panel or the gate driver chip. The first via is disposed in a plurality of insulating layers between the gate layer and the metal trace layer. The second trace in the metal trace layer is disposed in the first via and connected to the first trace in the gate layer.

9. The display panel according to any one of claims 3 to 7, characterized in that, In the lead area, the gate layer is provided with N1 first traces and N2 third traces. The N1 first traces are connected to the same gate driver chip, and the N2 third traces are connected to the common voltage area of ​​the display panel. N1 and N2 are positive integers greater than 1. Wherein, the N1 first traces and the N2 third traces are arranged alternately; or, the N1 first traces are arranged adjacent to each other, and the N2 third traces are arranged adjacent to each other.

10. The display panel according to claim 1, characterized in that, The second trace is located on the source layer; Wherein, the second trace is located between two adjacent rows of pixels in the display panel, and the second trace is a floating source driver line in the source layer, the floating source driver line not receiving source driver signals; or, The second trace corresponds to the bend in the pixel electrode of a row of pixels in the display panel.

11. The display panel according to claim 10, characterized in that, The second trace is used to transmit a common voltage signal. In the display area, the second via is disposed in the insulating layer between the source layer and the common electrode layer. The common electrode layer is disposed in the second via and connected to the second trace in the source layer.

12. The display panel according to claim 10, characterized in that, The second trace is used to transmit a gate drive signal. In the display area, the second via is disposed in the insulating layer between the gate layer and the source layer, and is located in the intersection area of ​​the second trace and the gate drive line. The second trace in the source layer is disposed in the second via and is connected to the gate drive line in the gate layer.

13. The display panel according to claim 12, characterized in that, The second via is disposed adjacent to the pixel area of ​​the blue pixel in the display panel.

14. The display panel according to any one of claims 10 to 13, characterized in that, In the lead area, the first trace is connected to the common voltage area of ​​the display panel or the gate driver chip, the first via is disposed in the insulating layer between the gate layer and the source layer, and the second trace in the source layer is disposed in the first via and connected to the first trace in the gate layer.

15. The display panel according to any one of claims 10 to 13, characterized in that, In the lead region, the gate layer is provided with a plurality of first traces, and the source layer is provided with a plurality of source drive lines, the plurality of first traces and the plurality of source drive lines being arranged sequentially at intervals.

16. The display panel according to any one of claims 1 to 7 and 10 to 13, characterized in that, In the display area, a plurality of second traces are connected to the common electrode layer. The plurality of second traces include multiple groups of second traces, each group of second traces includes at least one second trace, and the multiple groups of second traces are arranged in the display panel at fixed intervals.

17. The display panel according to any one of claims 1 to 7 and 10 to 13, characterized in that, The display panel has multiple gate driver chips and multiple source driver chips connected to the same long side. The display panel has multiple common voltage regions between the multiple gate driver chips, and the common voltage regions are used to provide a common voltage signal.

18. The display panel according to any one of claims 1 to 7 and 10 to 13, characterized in that, The display panel is a touch display panel, and the metal trace layer is the touch metal layer in the touch display panel.

19. The display panel according to any one of claims 1 to 7 and 10 to 13, characterized in that, The display panel is a dual-gate driving architecture or a tri-gate driving architecture.

20. A display screen, characterized in that, Includes: control device, and, The display panel as described in any one of claims 1 to 19, wherein the control device is used to control the display of the display panel.

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