Programmable logic-based proportional-integral-derivative parallel computing system and method

Abstract

The application discloses a proportional-integral-derivative parallel computing system and method based on programmable logic, and belongs to the technical field of motor motion control, and comprises the following steps: a PID parallel operation architecture containing a core operation unit and a plurality of parameter cache units is built, working condition information and feedback signals of a plurality of motors are collected, real-time levels are divided according to walking shafts, lifting shafts and steering shafts, and operation priorities are distributed, PID operation input values are generated through synchronous alignment and parameter processing; the core operation unit adopts a five-stage pipeline time-sharing multiplexing mode to perform parallel calculation on proportional, integral and derivative terms and complete limiting processing, and outputs PID control initial values; consistency verification of change rates and output constraints is performed through two independent verification channels, if the verification is passed, a control instruction is output, if the verification is not passed, a safety value is output and an alarm is reported, and feedback data is returned to form a closed loop; the application improves control real-time performance, parallelism and operation reliability, and meets the high-precision and high-stability control requirements of four-way vehicles with multi-shaft motors.

Description

Technical Field

[0001] This invention belongs to the field of motor motion control technology, specifically a proportional-integral-differential parallel computing system and method based on programmable logic. Background Technology

[0002] As a core handling equipment in warehousing and logistics systems, four-way vehicles require the simultaneous operation of multiple motors for walking, lifting, and steering, placing stringent demands on the real-time performance, parallelism, and stability of motor control. Traditional PID control often employs a microcontroller or DSP serial computing architecture, which has certain limitations in multi-motor parallel control scenarios: a single computing core performs PID calculations for each motor, resulting in long control cycles and slow response times, making it difficult to meet the rapid adjustment requirements of hard real-time axes such as the walking axis; and the lack of independent buffering for multiple parameters easily leads to data conflicts and timing misalignments, resulting in decreased control accuracy.

[0003] While existing programmable logic devices can achieve parallel computing, they are mostly simple multi-channel replications, resulting in high resource consumption, poor scalability, and a lack of mechanisms to prioritize operations based on motor function and real-time level. Non-critical axes such as lifting and steering consume a large amount of computing power, leading to insufficient control resources for critical axes. Furthermore, traditional solutions lack output consistency verification, making PID outputs prone to sudden changes and overshooting, causing motor vibration and operational instability, affecting the positioning accuracy and operational safety of the four-way vehicle.

[0004] To address the aforementioned issues, a parallel PID computing method based on programmable logic is urgently needed to improve computational efficiency, ensure reliable output, and meet the high-precision, high-reliability, and high-real-time collaborative control requirements of multiple motors in a four-way vehicle. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a parallel proportional-integral-derivative (PID) computing system and method based on programmable logic. It constructs a PID parallel computing architecture containing a core computing unit and multiple parameter buffer units, collects operating condition information and feedback signals from multiple motors, classifies real-time levels according to the traveling axis, lifting axis, and steering axis, and assigns computing priorities. After synchronization alignment and parameter processing, it generates PID calculation input values. The core computing unit uses a five-stage pipeline time-division multiplexing mode to perform parallel calculations of the proportional, integral, and derivative terms and completes amplitude limiting processing, outputting initial PID control values. Dual independent verification channels are used to verify the consistency between the rate of change and output constraints. If the verification passes, a control command is output; otherwise, a safety value is output and an alarm is reported, while feedback data is simultaneously transmitted to form a closed loop. This invention improves control real-time performance, parallelism, and operational reliability, meeting the high-precision and high-stability control requirements of multi-axis motors in four-way vehicles.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] Parallel computation methods for proportional-integral-differential operations based on programmable logic include:

[0008] S1: Construct a PID parallel computing architecture based on programmable logic devices; the PID parallel computing architecture includes one core computing unit and a multi-path parameter cache unit;

[0009] S2: Collect the operating condition information and feedback signals of each motor of the four-way vehicle, classify the operating condition information and assign calculation priorities, synchronize and align the feedback signals and input them into the parameter buffer unit, and generate PID calculation input values ​​for each motor in combination with preset control parameters.

[0010] S3: The core computing unit performs parallel operations on the PID input values ​​of each path in the parameter buffer unit in a pipeline time-sharing mode according to the operation priority, and outputs the initial PID control values ​​of each motor.

[0011] S4: Perform consistency verification on the initial values ​​of each PID control path, generate the final PID control command and output it to the corresponding motor of the four-way vehicle, and at the same time send the feedback data of motor control back to S2.

[0012] Specifically, the construction of the PID parallel computing architecture based on programmable logic devices includes:

[0013] S1.1: The arithmetic logic link of the core operation unit is constructed based on the digital signal processing unit inside the field-programmable gate array (FPGA), and the parameter cache unit is constructed based on the block random access memory inside the FPGA; the arithmetic logic link is configured as a cascaded structure including multiplier subunits, adder subunits and accumulator subunits; the parameter cache unit is used to store the proportional coefficient, integral coefficient and differential coefficient corresponding to each motor.

[0014] S1.2: Input the proportional coefficient and deviation value of the current motor in the multi-path parameter buffer unit into the multiplier subunit, and the multiplier subunit outputs the proportional calculation result; input the deviation value into the accumulator subunit to obtain the accumulated deviation value, and then input the accumulated deviation value and integral coefficient into the multiplier subunit, and the multiplier subunit outputs the integral calculation result; input the differential coefficient and deviation change rate into the multiplier subunit, and the multiplier subunit outputs the differential calculation result; input the proportional calculation result, integral calculation result and differential calculation result in parallel into the adder subunit, and the accumulated sum result output by the adder subunit is used as the initial value for PID control of the current motor.

[0015] Specifically, the acquisition of operating condition information and feedback signals of each motor of the four-way vehicle includes;

[0016] S2.1: The rotor angular displacement signal of each motor is collected based on the incremental photoelectric encoder, the three-phase winding current signal of each motor is collected based on the Hall current sensor, and the winding temperature signal of each motor is collected based on the temperature sensor. The rotor angular displacement signal, the three-phase winding current signal and the winding temperature signal are summarized into operating condition information.

[0017] S2.2: Receive the target speed commands of each motor sent from the four-way vehicle upper motion controller, and calculate the difference between the target speed commands of each motor and the differential value of the rotor angular displacement signal to generate a feedback signal.

[0018] Specifically, the operating condition information is classified and assigned computational priorities, including:

[0019] S2.3: Receive the real-time command status of the travel axle motor group, lifting axle motor group and steering axle motor group sent by the upper motion controller of the four-way vehicle, and associate and bind the real-time command status with the working condition information;

[0020] S2.4: Based on the response time requirements of the travel axis motor group, lifting axis motor group and steering axis motor group, the working condition information is divided into hard real-time, soft real-time and non-real-time categories;

[0021] S2.5: Assign the highest priority to the travel axle motor group belonging to the hard real-time category, assign the second highest priority to the lifting axle motor group belonging to the soft real-time category, assign the default priority to the steering axle motor group belonging to the non-real-time category, and output the assignment result to the core computing unit.

[0022] Specifically, the input parameter buffer unit for synchronizing and aligning the feedback signal includes:

[0023] S2.6: Generate a global sampling clock based on the phase-locked loop inside the field-programmable gate array;

[0024] S2.7: Using the global sampling clock as the trigger edge, perform first-stage synchronization processing based on triggers on the feedback signals of each motor collected;

[0025] S2.8: Input the signal after the first-stage synchronization processing to the shift register chain for the second-stage synchronization processing over multiple clock cycles to obtain the measured value variables of each motor, and at the same time obtain the corresponding set value variables from the target speed command;

[0026] S2.9: The measured value variables of each motor after the second-level synchronization processing are subtracted from the corresponding set value variables in the comparator to obtain the deviation value of the current cycle, and the deviation value of the current cycle is written into the parameter cache unit of the corresponding motor.

[0027] Specifically, the step of generating PID calculation input values ​​for each motor by combining preset control parameters includes:

[0028] S2.10: Read the preset values ​​of the proportional coefficient, integral coefficient, and derivative coefficient, as well as the intermediate result of the integral accumulation of the previous cycle from the parameter cache unit;

[0029] S2.11: Multiply the deviation value of the current period by the preset value of the proportional coefficient to generate the proportional term input value; multiply the deviation value of the current period by the preset value of the integral coefficient and then add it to the intermediate result of the integral accumulation of the previous period to generate the integral term input value; multiply the difference between the deviation value of the current period and the deviation value of the previous period by the preset value of the differential coefficient to generate the differential term input value.

[0030] S2.12: Package the proportional term input value, integral term input value and derivative term input value into PID calculation input value and store them in the storage location of the current motor in the parameter cache unit.

[0031] Specifically, the steps of S3 include:

[0032] S3.1: The core operation unit is divided into instruction read level, operand read level, multiply-accumulate operation level, result accumulation level and write-back level;

[0033] S3.2: Construct a time-slot cycle counter, set the modulus of the time-slot cycle counter to the maximum number of motor paths supported by the parameter cache unit, and map the allocated operation priority to the traversal order of the time-slot cycle counter;

[0034] S3.3: In the instruction read level, according to the current count value of the time slot cycle counter, the motor identification code corresponding to the current time slot is retrieved from the allocated operation priority, and the motor identification code is transmitted to the operand read level;

[0035] S3.4: In the operand reading stage, a reading address for the parameter cache unit bound to the corresponding motor is generated based on the received motor identification code. The PID calculation input value stored in S2.12 is retrieved from the reading address and passed to the multiply-accumulate operation stage. At the same time, the motor identification code and PID calculation input of the next motor corresponding to the next time slot are preloaded in the operand reading stage.

[0036] Specifically, the steps of S3 further include:

[0037] S3.5: In the multiply-accumulate stage, the proportional, integral, and derivative terms in the PID operation input value are multiplied and accumulated in parallel within one clock cycle, and the three calculation results are output to the result accumulation stage. At the same time, the operand reading stage synchronously executes the operand reading of the next motor.

[0038] S3.6: In the result accumulation stage, the received three calculation results are aligned and added together to generate a fixed-point number in binary two's complement form as the initial control value of the corresponding motor, and the initial control value is passed to the write-back stage;

[0039] S3.7: In the write-back stage, the received initial control value is subjected to a limiting judgment: if the initial control value is greater than a preset positive saturation threshold, the initial control value is assigned to the positive saturation threshold; if the initial control value is less than a preset negative saturation threshold, the initial control value is assigned to the negative saturation threshold; if the initial control value is between the negative saturation threshold and the positive saturation threshold, the original value is maintained; the initial control value after the limiting judgment is latched into the output result register corresponding to the corresponding motor.

[0040] S3.8: When the time slot cycle counter has traversed all the motors corresponding to the operation priority level, repeat S3.3 to S3.7 to complete the PID operation task of multiple motors in each complete control cycle, and use the control initial value in the output result register as the PID control initial value of each motor.

[0041] Specifically, the process of verifying the consistency of the initial values ​​of each PID control circuit, generating the final PID control command, and outputting it to the corresponding motor of the four-way vehicle includes:

[0042] S4.1: Read the initial PID control values ​​of each motor from the output result register of the write-back stage, and send the initial PID control values ​​to two independent verification channels at the same time, namely the first verification channel and the second verification channel.

[0043] S4.2: In the first verification channel, the initial value of the PID control of the corresponding motor is differentially calculated with the historical PID control output value stored in the previous control cycle to obtain the rate of change of the control quantity. The rate of change is compared with the preset maximum allowable rate of change threshold. If the rate of change is less than or equal to the maximum allowable rate of change threshold, the first verification is passed. If the rate of change is greater than the maximum allowable rate of change threshold, the first verification failure flag is triggered.

[0044] S4.3: In the second verification channel, the initial value of the PID control of the corresponding motor is compared with the upper limit constraint value and the lower limit constraint value of the output stored in the parameter cache unit corresponding to the corresponding motor. If the initial value of the PID control is between the lower limit constraint value and the upper limit constraint value of the output, the second verification is passed. If the initial value of the PID control is less than the lower limit constraint value or greater than the upper limit constraint value of the output, the second verification failure flag is triggered.

[0045] Specifically, the step of performing consistency verification on the initial values ​​of each PID control path, generating the final PID control command, and outputting it to the corresponding motor of the four-way vehicle also includes:

[0046] S4.4: Input the verification results of the first verification channel and the verification results of the second verification channel to the arbitrator. If both the first and second verification channels pass, mark the current PID control initial value as a valid control command. If any verification channel fails, mark the current PID control initial value as an invalid control command.

[0047] S4.5: When the arbitrator outputs a valid control command, the initial PID control value of the corresponding motor is output as the final PID control command to the corresponding motor drive interface. At the same time, the final PID control command is written into the historical PID control output value storage unit for differential calculation in the next control cycle.

[0048] S4.6: When the arbitrator outputs an invalid control command, it prohibits the output of the current PID control initial value, and instead reads the safety default control value of the corresponding motor from the parameter cache unit as the final PID control command and outputs it to the corresponding motor drive interface. At the same time, it reports an alarm message of consistency verification failure to the upper motion controller.

[0049] S4.7: Simultaneously send the final PID control command or the safe default control value output back to the feedback data storage area in the parameter buffer unit as the input of the feedback signal in the next control cycle.

[0050] A parallel computing system for proportional-integral-differential computation based on programmable logic includes:

[0051] The parallel computing architecture module includes a core computing unit and a multi-path parameter caching unit, which are used to construct the arithmetic logic links of the core computing unit.

[0052] The signal processing module is used to collect the operating condition information of the motor, receive the target speed command from the upper motion controller and generate feedback signals, generate a global sampling clock based on the FPGA phase-locked loop to complete signal synchronization and alignment, calculate the deviation value and generate PID calculation input value in combination with preset control parameters;

[0053] The priority scheduling module is used to classify motors into hard real-time, soft real-time, and non-real-time categories, and to assign corresponding operation priorities to the travel axis motor group, lifting axis motor group, and steering axis motor group, which are mapped to the traversal order of the time slot cycle counter.

[0054] The parallel computing module is used to sequentially complete the PID calculation input value reading, multiplication and addition, result accumulation and limit writing back in a pipeline time-sharing mode according to the calculation priority, and output the initial PID control values ​​of each motor.

[0055] The verification output module is used to perform dual verification of the rate of change and output limit of the initial value of PID control. If the verification is successful, the final PID control command is output. If an anomaly occurs, the safe default control value is switched, an alarm is reported, and feedback data is sent back.

[0056] Compared with the prior art, the beneficial effects of the present invention are:

[0057] 1. This invention proposes a parallel computing method based on programmable logic proportional-integral-differential (PI-DE). Through a PID parallel computing architecture built on FPGA and a pipelined time-sharing computing mechanism, the control tasks of multiple motors of a four-way vehicle can be scheduled in real-time hierarchical manner, significantly improving the parallelism and computing efficiency of multi-motor control. At the same time, it avoids non-critical axes from occupying core computing power, ensures the rapid response of hard real-time units such as the traveling axes, effectively reduces control latency, and improves the real-time performance and computing resource utilization of the multi-axis collaborative control of the four-way vehicle.

[0058] 2. This invention proposes a parallel proportional-integral-derivative (PI-DE) calculation method based on programmable logic. It employs dual independent verification channels and an arbitration mechanism to perform dual consistency verification on the PID output for both rate of change and amplitude. In case of anomalies, it automatically switches to a safety output and reports an alarm, effectively avoiding faults such as sudden changes in control quantity and over-amplitude, thereby improving the stability and reliability of system operation. At the same time, through closed-loop feedback and parameter caching design, it ensures control accuracy and data synchronization, achieving high-precision, high-stability, and high-safety collaborative control of multiple motors in a four-way vehicle. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the proportional-integral-differential parallel computing method based on programmable logic according to the present invention;

[0060] Figure 2 This is a flowchart illustrating the principle of the proportional-integral-differential parallel computing method based on programmable logic of the present invention.

[0061] Figure 3 This is a diagram of the proportional-integral-differential parallel computing system architecture based on programmable logic according to the present invention. Detailed Implementation

[0062] Example 1:

[0063] Please see Figure 1 and Figure 2 The present invention provides an embodiment of a proportional-integral-differential parallel computing method based on programmable logic, the method comprising S1~S4, including the following steps:

[0064] S1: Construct a PID parallel computing architecture based on programmable logic devices; the PID parallel computing architecture includes one core computing unit and a multi-path parameter cache unit;

[0065] Furthermore, the aforementioned PID parallel computing architecture, based on programmable logic devices, utilizes a Field-Programmable Gate Array (FPGA) as the core hardware carrier. It fully leverages the configurable hardware resources and parallel processing capabilities of the FPGA to construct a PID parallel computing architecture adapted to the multi-motor collaborative control of a four-way vehicle. This architecture differs from the serial computing mode of traditional microcontrollers and digital signal processors, enabling independent computation and result output of PID algorithms for multiple motors within the same control cycle, ensuring the synchronization and real-time performance of the four-way vehicle's multi-axis movements such as walking, lifting, and steering. The PID parallel computing architecture is physically divided into two core modules: a core computing unit responsible for all PID mathematical operations and a multi-path parameter cache unit responsible for data temporary storage, parameter configuration, and intermediate result storage. These two units interact via a high-speed interconnect bus within the FPGA, with bus transmission latency controlled at the nanosecond level, preventing data transmission from becoming a performance bottleneck in the entire computing process.

[0066] Furthermore, this embodiment uses a four-way shuttle vehicle applied in warehousing and logistics scenarios as an example. This four-way shuttle vehicle is equipped with a total of 8 drive motors, including 4 travel axis motors, 2 lifting axis motors, and 2 steering axis motors. All motors adopt permanent magnet synchronous servo drive. Based on the actual hardware configuration of this four-way shuttle vehicle, the PID parallel computing architecture built in this embodiment supports parallel computing processing of up to 16 motors, fully covering the control requirements of 8 motors, while reserving expansion interfaces to meet the usage scenarios of four-way shuttle vehicle function upgrades and increased motor numbers.

[0067] The construction of the PID parallel computing architecture based on programmable logic devices includes:

[0068] S1.1: The arithmetic logic link of the core operation unit is constructed based on the digital signal processing unit inside the field-programmable gate array (FPGA), and the parameter cache unit is constructed based on the block random access memory inside the FPGA; the arithmetic logic link is configured as a cascaded structure including multiplier subunits, adder subunits and accumulator subunits; the parameter cache unit is used to store the proportional coefficient, integral coefficient and differential coefficient corresponding to each motor.

[0069] Furthermore, the Field-Programmable Gate Array (FPGA) integrates a Digital Signal Processing Unit (DSPSlice) capable of performing basic operations such as multiplication, addition, and accumulation in a single clock cycle. This embodiment utilizes an industrial-grade, high-reliability FPGA chip, which integrates 96 DSPSlices. Each DSPSlice supports 18×18-bit signed multiplication and 36-bit addition and accumulation operations, fully meeting the numerical accuracy and speed requirements of the proportional, integral, and derivative operations in the PID algorithm. Based on these hardware resources, the DSPSlices are grouped and cascaded to construct the arithmetic logic link of the core computing unit. This link employs a fully hardware-based computational flow, eliminating the need for software instruction scheduling and achieving computational efficiency far exceeding that of traditional processors.

[0070] Furthermore, the cascaded structure of the arithmetic logic link is arranged in an orderly manner according to the mathematical logic of the PID algorithm, and is divided into three functional sub-modules: a multiplier sub-unit, an adder sub-unit, and an accumulator sub-unit. These three sub-modules are directly connected in a pipelined hardware manner. The calculation result of the previous sub-module is directly used as the input data of the next sub-module, without needing to pass through registers, thus minimizing computational latency. The multiplier sub-unit consists of four digital signal processing units connected in parallel, used to complete the multiplication operations of the proportional coefficient with the deviation value, the integral coefficient with the accumulated deviation value, and the derivative coefficient with the rate of change of deviation in the PID algorithm. This can be performed simultaneously within one clock cycle. The system completes four sets of multiplication operations simultaneously, meeting the requirements of parallel operation of multiple motors. The adder subunit consists of six digital signal processing units, divided into two groups: one group is used for accumulating the deviation value in the integral operation, and the other group is used for calculating the deviation change rate in the differential operation. It also undertakes the preliminary summation function of the proportional, integral, and differential operation results. The accumulator subunit consists of two high-performance digital signal processing units. Its core function is to perform the final parallel accumulation of the proportional operation result, integral operation result, and differential operation result, and output the complete PID control output value. The three sub-modules cooperate with each other to form a hardware operation link without interruption or waiting.

[0071] Furthermore, the Block Random Access Memory (BRAM) inside the Field Programmable Gate Array (FPGA) is a dedicated on-chip high-speed storage resource for the FPGA, characterized by fast read / write speeds, high data stability, and support for parallel access. In this embodiment, the on-chip BRAM is partitioned into 16 independent storage blocks, each corresponding to the parameter cache space of one motor, forming a multi-channel parameter cache unit. The capacity of each storage block is set to 1024×32 bits, which can stably store key data such as the preset values ​​of the proportional coefficient, integral coefficient, and derivative coefficient of the motor, the deviation value of the previous cycle, the intermediate result of the integral accumulation of the previous cycle, the upper limit constraint value of the output, the lower limit constraint value of the output, the historical PID control output value, and the safety default control value. All data is stored in 32-bit fixed-point format to ensure the accuracy of calculations while adapting to the data format requirements of FPGA hardware operations.

[0072] Furthermore, the multi-channel parameter cache unit adopts a parallel access architecture, supporting the core computing unit to simultaneously read and write different storage blocks. It can read data from eight motors and write calculation results from four motors at the same time, without any storage access conflicts. Simultaneously, each storage block is equipped with an independent address decoder and data buffer. The address decoder quickly locates the storage address of the target data, while the data buffer temporarily stores data to be read or written, further improving data access efficiency. A point-to-point data transmission channel is used between the parameter cache unit and the core computing unit, with each motor corresponding to an independent data transmission channel. This avoids interference and delays during multi-channel data transmission, ensuring that PID calculation input data can be delivered to the core computing unit quickly and accurately.

[0073] S1.2: Input the proportional coefficient and deviation value of the current motor in the multi-path parameter buffer unit into the multiplier subunit, and the multiplier subunit outputs the proportional calculation result; input the deviation value into the accumulator subunit to obtain the accumulated deviation value, and then input the accumulated deviation value and integral coefficient into the multiplier subunit, and the multiplier subunit outputs the integral calculation result; input the differential coefficient and deviation change rate into the multiplier subunit, and the multiplier subunit outputs the differential calculation result; input the proportional calculation result, integral calculation result and differential calculation result in parallel into the adder subunit, and the accumulated sum result output by the adder subunit is used as the initial value for PID control of the current motor.

[0074] Furthermore, in the hardware operation process, the core operation unit first synchronously inputs the proportional coefficient and the deviation value calculated in the current cycle into the two operation ports of the multiplier subunit. The multiplier subunit completes the multiplication operation of the two within one system clock cycle and directly outputs the proportional operation result. This result represents the proportional adjustment component of the current deviation, which is the most basic adjustment term in PID control. Moreover, the proportional operation process is automatically executed by the hardware without any software intervention. The proportional operation result is transmitted to the input port of the adder subunit in real time.

[0075] Furthermore, the integral operation is performed by the accumulator subunit. Combining the deviation value of the current cycle, the accumulator subunit first performs the accumulation processing of the deviation value to obtain the latest accumulated deviation value. Then, the integral coefficient and the accumulated deviation value are input to the operation port of the multiplier subunit to complete the compound operation of multiplication and addition, and output the integral operation result. The integral operation result represents the elimination component of the static deviation of the system, which can effectively solve the steady-state error problem in the four-way vehicle motor control. The accumulator subunit will limit the accumulated deviation value to avoid integral saturation due to long-term accumulation of deviation, thus ensuring the stability of the integral operation.

[0076] Furthermore, the differential operation first calculates the difference between the current cycle deviation value and the previous cycle deviation value through the adder subunit to obtain the deviation change rate. This value reflects the changing trend of the motor control deviation. Then, the differential coefficient and the deviation change rate are input into the multiplier subunit for multiplication, and the differential operation result is output. The differential operation result can respond to the changing trend of the deviation in advance, quickly suppress sudden disturbances of the four-way vehicle motor, and improve the dynamic response performance of the system. The adder subunit will filter the deviation change rate to filter high-frequency noise interference and avoid drastic fluctuations in the differential operation.

[0077] Furthermore, after the proportional, integral, and derivative calculation results are generated, they are transmitted in parallel to the three input ports of the adder subunit via independent hardware lines. The adder subunit adopts a summation architecture, completing the alignment and accumulation of the three results within one clock cycle. The output sum is the initial value of the PID control for the current motor. This initial value is a 32-bit fixed-point number that incorporates the combined effects of proportional, integral, and derivative adjustments, directly reflecting the required control output size for the current motor. While outputting the result, the adder subunit performs a preliminary overflow check. If a numerical overflow occurs, an overflow flag is immediately triggered to ensure the validity of the calculation result.

[0078] S2: Collect the operating condition information and feedback signals of each motor of the four-way vehicle, classify the operating condition information and assign calculation priorities, synchronize and align the feedback signals and input them into the parameter buffer unit, and generate PID calculation input values ​​for each motor in combination with preset control parameters.

[0079] The acquisition of operating condition information and feedback signals from each motor of the four-way vehicle includes;

[0080] S2.1: The rotor angular displacement signal of each motor is collected based on the incremental photoelectric encoder, the three-phase winding current signal of each motor is collected based on the Hall current sensor, and the winding temperature signal of each motor is collected based on the temperature sensor. The rotor angular displacement signal, the three-phase winding current signal and the winding temperature signal are summarized into operating condition information.

[0081] Furthermore, this embodiment uses an incremental photoelectric encoder with a resolution of 1024 lines. This incremental photoelectric encoder is fixedly installed on the rotor shaft end of each motor. As the motor rotor rotates synchronously, it continuously outputs three-phase pulse signals A, B, and Z. Among them, the A and B phase pulse signals have a 90-degree phase difference and are used to determine the rotation direction of the motor rotor and calculate the angular displacement. The Z phase pulse signal is the zero position signal, and one pulse is output for each revolution of rotation, which is used for zero position calibration of the motor rotor. The FPGA receives the pulse signals output by the incremental photoelectric encoder in real time. By counting the number of pulses and judging the phase, it accurately calculates the rotor angular displacement signal of the motor. The measurement accuracy of the rotor angular displacement signal can reach 0.35 degrees.

[0082] Furthermore, the Hall current sensor adopts a closed-loop Hall current sensor, which is connected in series in the three-phase winding drive circuit of each motor to collect the working current signals of the U, V, and W three-phase windings in real time. The closed-loop Hall current sensor has the characteristics of wide measurement range, high accuracy, and fast response speed. It can accurately collect the current change of the motor from no-load to full-load. The collected three-phase winding current signal is an analog signal. After being converted into a digital signal by the analog-to-digital conversion module inside the FPGA, it becomes the core operating condition data reflecting the motor load status. When the motor has abnormal conditions such as overload or stall, the three-phase winding current will rise sharply.

[0083] Furthermore, a surface-mount PT100 platinum resistance temperature sensor is selected for the temperature sensor. It is directly attached to the surface of the stator winding of each motor to monitor the operating temperature of the winding in real time, so as to avoid damage to the motor due to excessive temperature caused by long-term operation. The analog signal output by the temperature sensor is converted into a digital temperature value after analog-to-digital conversion. This value can intuitively reflect the thermal state of the motor and is a key operating condition information for the safe operation of the motor.

[0084] Furthermore, the acquisition of operating condition information adopts a synchronous acquisition mode. All sensors are triggered uniformly by the global sampling clock inside the FPGA to ensure that the acquisition time of the three signals is completely consistent and there is no time deviation. The acquired operating condition information will first enter the signal preprocessing unit inside the FPGA to complete signal filtering, noise reduction, amplitude calibration and other processing, filtering out noise signals caused by electromagnetic interference and mechanical vibration in the storage environment, obtaining clean and stable operating condition data, and then performing classification and priority allocation operations.

[0085] S2.2: Receive the target speed commands of each motor sent from the four-way vehicle upper motion controller, and calculate the difference between the target speed commands of each motor and the differential value of the rotor angular displacement signal to generate a feedback signal.

[0086] Furthermore, the four-way vehicle's upper-level motion controller is responsible for receiving scheduling instructions from the warehouse management system and generating target speed instructions for each motor based on the cargo handling task. The target speed instructions are digital control instructions, which are transmitted to the FPGA main control chip via CAN bus communication. CAN bus communication adopts an industrial-grade communication protocol, which has the characteristics of stable communication and strong anti-interference ability, and can ensure that the target speed instructions reach the PID calculation unit accurately and in real time. The instruction transmission delay is controlled at the millisecond level, which meets the real-time control requirements of the four-way vehicle.

[0087] Furthermore, the host motion controller generates a corresponding target speed command for each motor based on parameters such as the four-way vehicle's running trajectory, cargo weight, and running speed. The target speed commands for the travel axis motor, lifting axis motor, and steering axis motor are independent of each other and do not interfere with each other, ensuring that each motor can work collaboratively according to the preset motion logic. After receiving the target speed command, the FPGA first verifies the target speed command to determine its completeness and validity. If a verification error occurs in the target speed command, it immediately sends a retransmission request to the host motion controller to ensure the accuracy of the target speed command.

[0088] Furthermore, the feedback signal is used to calculate the deviation between the actual operating state of the motor and the target state. In this embodiment, the differential value of the rotor angular displacement signal is used as the actual speed signal of the motor. Because the rate of change of the rotor angular displacement signal collected by the incremental photoelectric encoder with time directly corresponds to the actual speed of the motor, the rotor angular displacement signal is differentially calculated in real time by the differential operation unit inside the FPGA to obtain the real-time actual speed signal of each motor. The differential formula of displacement with respect to time is the prior art in this field and is not an inventive solution of this application, so it will not be described in detail here.

[0089] Furthermore, the target speed command issued by the host motion controller and the calculated actual speed signal are input into the comparator inside the FPGA. The difference between the two is obtained through subtraction, and this difference is the feedback signal. The magnitude of the feedback signal reflects the degree of deviation between the actual motor speed and the target speed. A positive value indicates that the actual motor speed is lower than the target speed, and the control output needs to be increased; a negative value indicates that the actual motor speed is higher than the target speed, and the control output needs to be decreased; a value of zero indicates that the motor speed has reached the target value, and the control output remains stable.

[0090] The operating condition information is categorized and assigned computational priorities, including:

[0091] S2.3: Receive the real-time command status of the travel axle motor group, lifting axle motor group and steering axle motor group sent by the upper motion controller of the four-way vehicle, and associate and bind the real-time command status with the working condition information;

[0092] Furthermore, the host motion controller sends real-time command status of the three motor groups to the FPGA in real time, including the operating status of motor start, stop, acceleration, deceleration, reversing, lifting, and lowering. This real-time command status is transmitted synchronously with the target speed command, jointly reflecting the expected working status of the motors. The status parsing unit inside the FPGA parses the real-time command status in real time, clarifying the current working mode and control requirements of each motor, such as the travel axis motor being in a high-speed operating state, the lifting axis motor being in a constant-speed lifting state, and the steering axis motor being in a standby state.

[0093] Furthermore, the real-time command status obtained from the parsing is associated and bound one by one with the previously collected operating condition information, establishing an independent state-operating condition data mapping relationship for each motor. That is, the operating condition information such as rotor angular displacement, winding current, and winding temperature of each motor are all bound to the current real-time command status of that motor. This association and binding method allows the PID calculation unit to clearly understand the operating requirements and actual status of each motor, avoiding control errors caused by data confusion.

[0094] Furthermore, the associated and bound data is stored in the dedicated storage area of ​​the parameter cache unit, and integrated with the motor's control parameters, feedback signals and other data to form a complete motor control dataset. The motor control dataset is updated in real time as the motor's operating status changes, ensuring the timeliness and accuracy of the data.

[0095] S2.4: Based on the response time requirements of the travel axis motor group, lifting axis motor group and steering axis motor group, the working condition information is divided into hard real-time, soft real-time and non-real-time categories;

[0096] Furthermore, the control response time requirements of different motor units vary during the operation of the four-way vehicle, and this difference determines the real-time level classification of the operating condition information. For example, the travel axis motor unit is the core drive component of the four-way vehicle, responsible for its horizontal movement, and directly related to the vehicle's operating speed, positioning accuracy, and driving safety. If the control response is not timely, serious problems such as the four-way vehicle colliding with the shelf or excessive positioning deviation may occur. Therefore, the control response time requirement is extremely high, and the calculation and control output must be completed within microseconds, which is a hard real-time control requirement.

[0097] Furthermore, the lifting shaft motor unit is responsible for driving the lifting and lowering of goods. Its control response speed requirement is lower than that of the travel shaft motor unit, and millisecond-level control delay is allowed. As long as the lifting and lowering of goods is smooth and without shaking, it will not cause serious safety accidents. Therefore, it belongs to the soft real-time control requirement. The steering shaft motor unit only works when the four-way vehicle needs to change direction. It is in standby mode during normal operation. The response time requirement for the reversing operation is lower, and a longer delay is allowed. It belongs to the non-real-time control requirement.

[0098] Furthermore, based on the response time requirements of different motor sets, the corresponding operating information is classified. The operating information of the travel axis motor set, such as rotor angular displacement, winding current, and winding temperature, is classified as hard real-time data, which must be processed and calculated first. The operating information of the lifting axis motor set is classified as soft real-time data, which is processed after the hard real-time data is processed. The operating information of the steering axis motor set is classified as non-real-time data, which is processed when the system is idle. The classification of the three types of data strictly follows the control requirements of the motor set to ensure the priority execution of core control tasks.

[0099] S2.5: Assign the highest priority to the travel axle motor group belonging to the hard real-time category, assign the second highest priority to the lifting axle motor group belonging to the soft real-time category, assign the default priority to the steering axle motor group belonging to the non-real-time category, and output the assignment result to the core computing unit.

[0100] Furthermore, the computational priority is the ordering basis for the core computing unit to execute computational tasks in the PID parallel computing architecture. The higher the priority of the motor group, the earlier it obtains the computing resources of the core computing unit and the earlier it completes the PID calculation and control output. In this embodiment, the hard real-time type travel axis motor group is set to the highest priority, numbered as priority 0. The core computing unit will prioritize processing the PID calculation tasks of the four motors of this motor group to ensure the real-time performance of travel control. The soft real-time type lifting axis motor group is set to the second highest priority, numbered as priority 1, and is processed immediately after the travel axis motor calculation is completed. The non-real-time type steering axis motor group is set to the default priority, numbered as priority 2, and is executed when the core computing unit is idle. The three priority types are independent of each other, and there is no priority preemption conflict.

[0101] Furthermore, the operation priority allocation result is stored in the priority configuration register of the parameter cache unit in the form of a digital code, and is simultaneously transmitted to the scheduling control unit of the core operation unit in real time. The scheduling control unit schedules the operation tasks of each motor in an orderly manner according to the priority code, and executes the operation strictly in the order of priority 0, priority 1, and priority 2 to ensure the reasonable allocation of core operation resources and avoid operation delays and chaos caused by multi-task competition.

[0102] Furthermore, the priority allocation result supports online dynamic adjustment. The upper-level motion controller can modify the value of the priority configuration register through communication commands according to the actual operating scenario of the four-way vehicle. For example, when the four-way vehicle makes an emergency stop, the priority of the lifting shaft motor group can be temporarily raised to the highest priority to ensure the safety of the cargo. The dynamic adjustment process does not require restarting the system, which improves the flexibility and adaptability of the architecture.

[0103] The input parameter buffer unit that synchronizes and aligns the feedback signal includes:

[0104] S2.6: Generate a global sampling clock based on the phase-locked loop inside the field-programmable gate array;

[0105] Furthermore, the phase-locked loop (PLL) inside the field-programmable gate array (FPGA) is a dedicated hardware module for clock management and frequency synthesis. It features clock multiplication, division, and phase calibration functions, enabling the generation of stable, high-precision clock signals. In this embodiment, the PLL uses an external 50MHz active crystal oscillator as a reference clock. After frequency multiplication, it generates a 200MHz global sampling clock with a period of 5 nanoseconds and a jitter of less than 50 picoseconds. This clock exhibits extremely high stability and accuracy, providing a unified time reference for the entire signal acquisition, data synchronization, and PID calculation process.

[0106] S2.7: Using the global sampling clock as the trigger edge, perform first-stage synchronization processing based on triggers on the feedback signals of each motor collected;

[0107] It should be noted that the collected motor feedback signals come from different sensors and communication interfaces. Although a synchronous acquisition mode is used, there are still slight time deviations and phase shifts. If these are used directly for calculation, the accuracy of PID control will decrease. Therefore, multi-level synchronization alignment processing is required. The first-level synchronization processing uses the rising edge of the global sampling clock as the trigger edge and is implemented using D-type flip-flops inside the FPGA. D-type flip-flops are the most basic synchronous sequential logic units. They can latch and output the input signal when the clock trigger edge arrives, filtering out metastability and glitches in the signal.

[0108] Furthermore, an independent D-type flip-flop is configured for the feedback signal of each motor. All D-type flip-flops are triggered uniformly by a 200MHz global sampling clock. At each rising edge of the clock, the feedback signal is latched to the output of the D-type flip-flop to complete the first stage of synchronization processing. After the first stage of synchronization processing, the timing of the feedback signal is completely aligned with the global sampling clock, eliminating the slight time deviation caused by signal transmission, while filtering out high-frequency noise and signal glitches to obtain a stable synchronization signal.

[0109] Furthermore, the specific steps in S2.7 include:

[0110] (1) Obtain the global sampling clock;

[0111] (2) Before starting the first-level synchronization processing, a dedicated synchronization processing channel is configured for the feedback signal of each motor. In this embodiment, the four-way vehicle has a total of 8 motors. Therefore, a total of 8 independent synchronization processing channels are configured. Each channel corresponds to the feedback signal of one motor. The channels do not interfere with each other, and the data transmission paths are completely independent to avoid signal crosstalk.

[0112] (3) Each synchronous processing channel is equipped with a dedicated D flip-flop as the core device of the first-level synchronous processing. All D flip-flops in all channels are driven by the same global sampling clock. The clock input of all flip-flops is connected to the global clock network of the field programmable gate array to ensure that the clock signal can reach each flip-flop simultaneously without deviation.

[0113] (4) The motor feedback signal after front-end acquisition and preliminary filtering is connected to the data input terminal of the D-type flip-flop of the corresponding channel. The feedback signal does not undergo any logical operation before entering the flip-flop, but only maintains the original acquired level state to ensure that the data entering the flip-flop remains true and complete.

[0114] (5) All D-type flip-flops are uniformly configured as rising edge trigger mode. In rising edge trigger mode, the flip-flop will only perform data latching operation when the global sampling clock has a rising edge that jumps from low level to high level. At other times, the flip-flop will keep the data state latched in the previous cycle unchanged.

[0115] (6) During normal operation of the system, the global sampling clock continuously outputs a stable clock pulse at a frequency of 200MHz, and generates a rising edge every 5 nanoseconds. Whenever the rising edge of the global sampling clock reaches the clock input of all flip-flops, each flip-flop will immediately latch the feedback signal level state on the current data input terminal and output the level state stably to the output terminal of the flip-flop.

[0116] (7) During the time period before the rising edge of the global sampling clock arrives, the output of the D flip-flop remains unchanged and does not change with the instantaneous fluctuation of the input feedback signal, thereby filtering out the glitches and metastable fluctuations in the feedback signal.

[0117] (8) After each feedback signal is latched by the corresponding flip-flop, the output signal is the synchronization signal that completes the first stage of synchronization processing. The transition time of the synchronization signal is completely aligned with the rising edge of the global sampling clock. The synchronization signals of all 8 motors are strictly consistent in time, and there is no time deviation between channels.

[0118] (9) After the first-level synchronization processing is completed, the synchronization signal output by each flip-flop is directly sent to the next level shift register chain. The entire first-level synchronization processing process only occupies one global sampling clock cycle, and the processing delay is fixed at 5 nanoseconds.

[0119] S2.8: Input the signal after the first-stage synchronization processing to the shift register chain for the second-stage synchronization processing over multiple clock cycles to obtain the measured value variables of each motor, and at the same time obtain the corresponding set value variables from the target speed command;

[0120] Furthermore, the second-level synchronization processing is implemented using a multi-level shift register chain. In this embodiment, four levels of shift registers are connected in series to form a shift register chain. Each level of register is triggered by a global sampling clock. The signal after the first-level synchronization processing is sequentially latched by the four levels of registers. After a delay of four clock cycles, or 20 nanoseconds, the metastability of the signal is completely eliminated, and the timing stability reaches the optimal state. The output signal is the measured value variable of each motor. This measured value variable is a precise digital representation of the actual speed of the motor.

[0121] Furthermore, while performing the second-level synchronization processing, the instruction parsing unit inside the FPGA extracts the target speed value corresponding to the current motor from the target speed command sent by the upper motion controller. After format conversion and data calibration, the target speed value generates a setpoint variable. The setpoint variable represents the expected operating speed of the motor and corresponds one-to-one with the measured value variable. The timing of the two is completely synchronized, both based on the global sampling clock.

[0122] Furthermore, the specific steps in S2.8 include:

[0123] (1) The system builds an independent shift register chain for the signal after the first stage of synchronous processing of each motor. In this embodiment, the four-way vehicle contains 8 drive motors, so a total of 8 identical and independent shift register chains are built. Each shift register chain only processes the signal of the corresponding motor. The channels are completely isolated and there is no data interaction or signal interference.

[0124] (2) Each shift register chain consists of four D-type flip-flops connected in series. The number of stages is fixed in the hardware and is not dynamically adjusted. The four flip-flops are named in sequence as first-stage shift flip-flop, second-stage shift flip-flop, third-stage shift flip-flop, and fourth-stage shift flip-flop. The four flip-flops are connected in the order of signal flow. The output of the previous stage flip-flop is directly connected to the data input of the next stage flip-flop.

[0125] (3) The clock input of each stage of the shift register chain is connected to the global clock network of the field programmable gate array, driven by a global sampling clock of 200MHz, and all are configured to rise edge trigger mode. This trigger mode is a fixed configuration.

[0126] (4) After the first stage of synchronization processing is completed, the signal is connected to the data input terminal of the first stage shift flip-flop in the corresponding shift register chain. After the signal is connected, no logic operation or level conversion is performed, and the original stable level state is maintained before entering the shift processing flow.

[0127] (5) When the first rising edge of the global sampling clock arrives, the first stage shift flip-flop latches the first stage synchronous processing signal at the input terminal and transmits the signal to its own output terminal. At this time, the signal completes the shift of the first clock cycle and the signal state is stabilized.

[0128] (6) When the second rising edge of the global sampling clock arrives, the second-stage shift flip-flop latches the signal at the output of the first-stage shift flip-flop and transmits the signal to its own output. The signal completes the shift of the second clock cycle, and the stability of the signal is further improved.

[0129] (7) When the third rising edge of the global sampling clock arrives, the third-stage shift flip-flop latches the signal at the output of the second-stage shift flip-flop and transmits the signal to its own output, and the signal completes the shift for the third clock cycle;

[0130] (8) When the fourth rising edge of the global sampling clock arrives, the fourth-stage shift flip-flop latches the signal at the output of the third-stage shift flip-flop and outputs the signal stably to its own output, and the signal completes the shift for the fourth clock cycle;

[0131] (9) After continuous shifting processing by the four-stage shift trigger, the signal undergoes a total delay of four global sampling clock cycles. The total delay length is fixed at 20 nanoseconds. At this time, the signal obtained from the output of the fourth-stage shift trigger is the stable and metastable measured value variable of the motor. This variable directly reflects the real-time operating status of the corresponding motor.

[0132] (10) During the entire process of performing shift register chain synchronization processing on the first-level synchronization processing signal, the parsing and variable extraction of the target speed command are performed synchronously. This process maintains the same timing rhythm as the second-level synchronization processing and uses the same 200MHz global sampling clock as the timing reference.

[0133] (11) Read the target speed command issued by the host motion controller from the communication receiving unit of the field programmable gate array, and set the data bit width to 32 bits;

[0134] (12) According to the preset instruction parsing rules, extract the target speed value corresponding to the currently processed motor from the 32-bit target speed instruction data. The instruction parsing rules are fixed configurations, with each motor corresponding to a fixed position of the value segment in the target speed instruction data, and the length of the value segment is fixed at 32 bits.

[0135] (13) Extract the target speed value, and after uniform format normalization, the parameter of the format normalization is completely consistent with the value format of the measured value variable. The value obtained after normalization is the set value variable corresponding to the current motor.

[0136] (14) Ensure that the measured value variable obtained by each motor after the second-level synchronization processing is completely aligned with the set value variable extracted from the target speed command in terms of timing, and the generation time of the two variables is no more than one global sampling clock cycle, that is, 5 nanoseconds.

[0137] S2.9: The measured value variables of each motor after the second-level synchronization processing are subtracted from the corresponding set value variables in the comparator to obtain the deviation value of the current cycle, and the deviation value of the current cycle is written into the parameter cache unit of the corresponding motor.

[0138] Furthermore, the comparator is a combinational logic unit inside the FPGA, which has high-speed numerical comparison and subtraction functions. In this embodiment, each motor is equipped with an independent 32-bit comparator, which supports fixed-point subtraction. The measured value variable and the set value variable after synchronization and alignment are simultaneously input into the two operation ports of the comparator. The comparator completes the subtraction operation within one clock cycle and outputs the deviation value of the current control cycle. The magnitude and sign of the deviation value directly reflect the deviation state of the motor speed.

[0139] Furthermore, the calculated deviation value is the core input data for PID operation and needs to be immediately written into the parameter cache unit of the corresponding motor. It is stored in a dedicated storage address for the deviation value, adjacent to control parameters such as proportional coefficient and integral coefficient, so that the core operation unit can quickly read it. Moreover, the writing operation of the deviation value is performed synchronously with the operation, and the writing delay is controlled within one clock cycle to ensure that the deviation value of the current cycle can be used for the PID operation of the current cycle in a timely manner, so as to achieve closed-loop control without delay.

[0140] The process of generating PID calculation input values ​​for each motor by combining preset control parameters includes:

[0141] S2.10: Read the preset values ​​of the proportional coefficient, integral coefficient, and derivative coefficient, as well as the intermediate result of the integral accumulation of the previous cycle from the parameter cache unit;

[0142] Furthermore, the read operation of the parameter buffer unit uses the 200MHz global sampling clock generated inside the field programmable gate array as a unified timing reference. The clock period is fixed at 5 nanoseconds, and the timing control of all read operations strictly follows the clock cycle.

[0143] Furthermore, the parameter caching unit adopts a block-based partitioned storage structure, with each motor corresponding to an independent dedicated storage block. In this embodiment, the four-way vehicle includes 8 drive motors, so the parameter caching unit is divided into 8 completely equal and independent dedicated motor storage blocks. The capacity of each storage block is set to 1024×32 bits, which is used to store all control parameters and intermediate calculation data of the corresponding motor.

[0144] Furthermore, each motor-specific storage block is functionally divided according to address segments. The address segment division rules are fixed in hardware. Specifically, the preset value of the proportional coefficient is stored in the starting address segment of each dedicated storage block, the preset value of the integral coefficient is stored in the continuous address segment following the preset value of the proportional coefficient, the preset value of the derivative coefficient is stored in the continuous address segment following the preset value of the integral coefficient, and the intermediate result of the integral accumulation of the previous cycle is stored in the continuous address segment following the preset value of the derivative coefficient. The address offset of the four types of data in each motor storage block is completely consistent, and the address offset length is set to 32 bits to ensure the uniformity of the read address generation rules.

[0145] Furthermore, before initiating the reading operation, the system first acquires the motor identification code currently being processed. This identification code is generated by mapping the current count value output by the time slot cycle counter. There is a unique correspondence between the identification code and the motor's dedicated storage block. The system directly locates the dedicated storage block to which the target motor belongs based on the motor identification code, without performing unnecessary address retrieval operations. After locating the target storage block, the parameter reading process begins. First, the system reads the preset value of the proportional coefficient. The system sends the address signal within the corresponding block to the parameter buffer unit. Upon receiving the address signal, the parameter buffer unit reads the preset value of the proportional coefficient within one global sampling clock cycle and transmits it to the data output bus. The proportional coefficient preset value is stored in 32-bit fixed-point number format. The preset values ​​are set separately for the different control characteristics of the travel axis, lifting axis, and steering axis. Specifically, the preset value for the proportional coefficient of the travel axis motor is set to 8192, the preset value for the lifting axis motor is set to 4096, and the preset value for the steering axis motor is set to 2048. After the proportional coefficient preset value is read, the integral coefficient preset value read operation is immediately initiated. The read address is an address segment offset 32 ​​bits from the proportional coefficient preset value address. The read timing is continuous with the proportional coefficient preset value, with no idle waiting period in between. The integral coefficient preset value is also stored in 32-bit fixed-point number format. The integral coefficient preset values ​​for the travel axle motor, lifting axle motor, and steering axle motor are set to 256, 128, and 64 respectively. After reading the integral coefficient preset values, the system continues to read the derivative coefficient preset values. The read address is an address segment offset 32 ​​bits from the integral coefficient preset value address. The read time is also one global sampling clock cycle. The derivative coefficient preset values ​​are stored in a 32-bit fixed-point number format, with the derivative coefficient preset values ​​for the travel axle motor set to 128, lifting axle motor to 64, and steering axle motor to 32. After reading the derivative coefficient preset values, the system... The system reads the last data item, which is the intermediate result of the integral accumulation in the previous cycle. The read address is an address segment offset 32 ​​bits from the preset value of the differential coefficient. This data is the intermediate value generated and written back by the integral operation in the previous cycle. It is stored in 32-bit fixed-point format. The value changes dynamically with the result of the previous cycle and has no fixed preset value. The reading process is completed within one global sampling clock cycle. The reading operation of the four types of data adopts a pipelined continuous reading method. From the preset value of the proportional coefficient to the end of the intermediate result of the integral accumulation, the entire reading process takes four global sampling clock cycles. The total reading time is fixed at 20 nanoseconds. No address conflict or data blocking occurs during the reading process.

[0146] Furthermore, after completing the reading of the four types of data for the current motor, the system immediately preloads the storage block location information and reading address of the next motor based on the next count value of the time slot cycle counter, preparing for the next round of reading operations and ensuring the continuity and efficiency of reading parameters from multiple motors.

[0147] S2.11: Multiply the deviation value of the current period by the preset value of the proportional coefficient to generate the proportional term input value; multiply the deviation value of the current period by the preset value of the integral coefficient and then add it to the intermediate result of the integral accumulation of the previous period to generate the integral term input value; multiply the difference between the deviation value of the current period and the deviation value of the previous period by the preset value of the differential coefficient to generate the differential term input value.

[0148] S2.12: Package the proportional term input value, integral term input value and derivative term input value into PID calculation input value and store them in the storage location of the current motor in the parameter cache unit.

[0149] S3: The core computing unit performs parallel operations on the PID input values ​​of each path in the parameter buffer unit in a pipeline time-sharing mode according to the operation priority, and outputs the initial PID control values ​​of each motor.

[0150] The specific steps of S3 include:

[0151] S3.1: The core operation unit is divided into instruction read level, operand read level, multiply-accumulate operation level, result accumulation level and write-back level;

[0152] Furthermore, hardware resources for constructing the instruction fetch level are allocated within the field-programmable gate array's digital signal processing unit array. These hardware resources include a time-slot cyclic counter, a set of priority mapping registers, and a set of data output flip-flops. The modulus of the time-slot cyclic counter is set to 16 according to the maximum number of motors supported by the parameter buffer unit, and the bit width of the time-slot cyclic counter is set to 4 bits, enabling it to perform cyclic counting from 0 to 15. The storage depth of the priority mapping register is set to 16, with each storage unit corresponding to the priority code of one motor, and the storage bit width is set to 2 bits, distinguishing between the highest priority, the second highest priority, and the default priority. All hardware resources in the instruction fetch level are directly driven by a 200MHz global sampling clock, and the data output flip-flops adopt a rising edge triggering mode, completing the latched output of motor identification and priority information once per clock cycle.

[0153] Furthermore, the operand read stage, located adjacent to the instruction read stage's output, is responsible for generating the parameter cache unit address and reading the PID calculation input value. The system allocates three types of hardware resources to the operand read stage: an address decoder, a parameter cache unit interface controller, and data output registers. The address decoder has a 4-bit input width to receive the motor identification signal transmitted from the instruction read stage, and a 32-bit output width to generate the complete physical address of the corresponding motor storage block in the parameter cache unit. The parameter cache unit interface controller has a 64-bit transmission width, consistent with the read / write width of the parameter cache unit, supporting the reading of the PID calculation input value in a single clock cycle. Two sets of data output registers are used: one set latches the PID calculation input value of the current motor, and the other set preloads the PID calculation input value of the next motor. All data output registers have a 64-bit storage width and are driven synchronously by the global sampling clock.

[0154] Furthermore, the multiply-accumulate stage handles parallel multiply-accumulate operations for the proportional, integral, and differential terms. The system allocates 12 independent digital signal processing (DSP) sub-units from the FPGA's digital signal processing unit to construct the multiply-accumulate stage. Four DSP sub-units form the first multiplier group, four form the first adder group, and four form the second multiplier group. The first multiplier group performs multiplication of the proportional coefficient and the deviation value, with a bit width of 32 bits. The first adder group performs accumulation and multiplication operations related to the integral, with a bit width of 32 bits. The second multiplier group performs multiplication of the deviation rate of change and the differential coefficient, with a bit width of 32 bits. All DSP sub-units operate synchronously within the same clock cycle, supporting parallel execution of three operations, and all are configured in signed fixed-point arithmetic mode, maintaining a precision of 32 bits.

[0155] Furthermore, the result accumulation stage, located immediately adjacent to the output of the multiply-accumulate stage, is responsible for aligning and summing the results of the three operations. The system allocates a 32-bit parallel adder array and a set of numerical alignment triggers to the result accumulation stage. The parallel adder array contains three input ports and one output port. The three input ports receive the proportional, integral, and differential terms from the multiply-accumulate stage, respectively, with a bit width of 32 bits, enabling the accumulation of the three values ​​within a single clock cycle. The numerical alignment triggers are used to unify the bit format of the three input data. Three sets of numerical alignment triggers, each with a bit width of 32 bits, ensure that the sign bit and value bit are aligned before accumulation, following the standard format of a 32-bit signed fixed-point number.

[0156] Furthermore, the write-back stage, located at the end of the entire computational pipeline, is responsible for limiting the computation results and latching the output. The system allocates a limiting judgment logic unit, a result register group, and a saturation threshold register to the write-back stage. The limiting judgment logic unit has a 32-bit input width and receives the initial control value output from the result accumulation stage. It integrates two numerical comparators, used for comparing the positive and negative saturation thresholds respectively. The positive saturation threshold register stores a fixed value of 32767, and the negative saturation threshold register stores a fixed value of -32768. Both thresholds are stored in a 32-bit signed fixed-point format. The number of result register groups corresponds to the number of motor paths and is set to 8, with each register having a 32-bit width. These registers latch the valid initial control value after limiting processing. All registers perform data latching and holding under the drive of the global sampling clock.

[0157] Furthermore, after the computational stages are partitioned, the system sets up a synchronous data transfer trigger between adjacent stages. The number of triggers matches the data bit width of each stage, used to isolate timing interference between upper and lower stages, ensuring that each stage completes its function only within the current clock cycle and does not affect the work of other stages. All stages and intermediate triggers are driven by a unified 200MHz global sampling clock. The execution time of each stage is fixed at one clock cycle, or 5 nanoseconds. A complete five-stage pipeline operation takes 5 clock cycles, with a total duration of 25 nanoseconds.

[0158] S3.2: Construct a time-slot cycle counter, set the modulus of the time-slot cycle counter to the maximum number of motor paths supported by the parameter cache unit, and map the allocated operation priority to the traversal order of the time-slot cycle counter;

[0159] Furthermore, the time slot cycle counter is the scheduling core of the core computing unit, used to control the timing of pipeline operations and the order of motor operations. In this embodiment, the parameter buffer unit supports a maximum of 16 motors, so the modulus of the time slot cycle counter is set to 16. The counter starts counting from 0, increments sequentially to 15, and then cycles back to zero to form a continuous time slot sequence.

[0160] Furthermore, the previously allocated computational priorities are mapped to the traversal order of the time slot cycle counter. The highest priority travel axis motor corresponds to time slots 0-3, the second highest priority lifting axis motor corresponds to time slots 4-5, the default priority steering axis motor corresponds to time slots 6-7, and the remaining time slots are reserved for backup. Each count of the time slot cycle counter corresponds to one time slot, and each time slot processes the PID calculation of one motor. The traversal strictly follows the priority order to ensure the reasonable allocation of core computing resources.

[0161] S3.3: In the instruction read level, according to the current count value of the time slot cycle counter, the motor identification code corresponding to the current time slot is retrieved from the allocated operation priority, and the motor identification code is transmitted to the operand read level;

[0162] Furthermore, at the beginning of each time slot, the instruction read stage reads the current count value of the time slot cycle counter. Based on the mapping relationship between the count value and priority, it retrieves the unique identifier code of the motor corresponding to the current time slot. The motor identifier code contains the motor number, motor group type, priority information, etc. This identifier code is passed to the operand read stage through the pipeline register to provide an address index for data reading.

[0163] S3.4: In the operand reading stage, a reading address for the parameter cache unit bound to the motor is generated based on the received motor identification code. The PID calculation input value stored in S2.12 is retrieved from the reading address and passed to the multiply-accumulate operation stage. At the same time, the motor identification code and PID calculation input value of the next motor corresponding to the next time slot are preloaded in the operand reading stage.

[0164] Furthermore, the specific steps in S3.4 include:

[0165] (1) When the operand reading stage receives the motor identification code from the instruction reading stage, it first starts the address generation process. The motor identification code consists of 4 bits of binary logic level and has a unique correspondence with the motor being processed in the current time slot. The system inputs the 4-bit motor identification code into the address decoder inside the operand reading stage. The input bit width of the address decoder is fixed at 4 bits and the output bit width is fixed at 32 bits, which can complete the complete conversion from the motor identification code to the physical address of the parameter cache unit.

[0166] (2) The address decoder has a preset address mapping rule. The address mapping rule is configured during hardware deployment and is not modified during operation. The storage block capacity allocated to each motor by the parameter cache unit is uniformly set to 1024×32 bits. The storage starting address of each motor is directly determined by the motor identification code. For each increase of the value corresponding to the motor identification code, the storage starting address is shifted backward by 1024 storage units to ensure that the storage areas of each motor are independent and do not overlap.

[0167] (3) The address decoder calculates and outputs a 32-bit physical read address within one global sampling clock cycle according to the received motor identification code and address mapping rules. The physical read address accurately points to the dedicated storage unit in the parameter cache unit of the current motor used to store the PID calculation input value. The PID calculation input value is the 64-bit data packaged and stored in the previous step. Its storage address forms a fixed binding relationship with the current motor identification code, and there will be no address offset or misalignment.

[0168] (4) After receiving the 32-bit physical read address sent by the operand read stage, the parameter cache unit immediately reads the data from the memory unit pointed to by the physical read address. The read timing of the parameter cache unit is synchronized with the global sampling clock. The data read operation is completed within one global sampling clock cycle. The read data is a 64-bit PID operation input value, which contains complete packaged information of the proportional term input value, integral term input value and derivative term input value.

[0169] (5) After the operand reading stage obtains the PID operation input value, it sends it to the data output register of this stage. The bit width of the data output register is set to 64 bits, which is completely matched with the bit width of the PID operation input value. The register completes data latching on the rising edge of the global sampling clock. After latching, the stable 64-bit PID operation input value is passed to the next stage of multiply-accumulate operation.

[0170] (6) During the entire process of generating the current motor address, reading data and transmitting data, the operand reading level synchronously starts the preloading operation of the relevant data of the next motor. The preloading operation is executed in parallel with the current operation, without occupying an extra clock cycle, and without affecting the normal processing of the current data. The system first reads the next count value of the time slot cycle counter. The modulus of the counter is fixed at 16. The next count value is the result of adding 1 to the current count value and taking the remainder of 16. Based on the next count value, the system obtains the motor identification code corresponding to the next motor through the priority mapping relationship. The priority mapping relationship is preset by hardware. The walking axis motor corresponds to the highest priority, the lifting axis motor corresponds to the second highest priority, and the steering axis motor corresponds to the default priority.

[0171] (7) After obtaining the motor identification code of the next motor, the operand reading stage sends the motor identification code to the preload input port of the address decoder. While processing the current address, the address decoder calculates the 32-bit physical read address corresponding to the next motor in parallel and temporarily stores the address in the address decoder.

[0172] (8) The parameter caching unit prepares to read the input value of the next motor PID calculation in advance according to the address in the address decoder, and temporarily stores the value in the data output register. The bit width of the data output register is set to 64 bits, which matches the bit width of the PID calculation input value. The preloading operation is completed in the background and does not affect the normal reading and transmission of the current data.

[0173] (9) When the global sampling clock enters the next clock cycle, the preloaded next motor identification code and PID calculation input value are immediately switched to the current processing data, without having to re-execute address calculation and data reading, thus achieving seamless connection of pipeline operation.

[0174] S3.5: In the multiply-accumulate stage, the proportional, integral, and derivative terms in the PID operation input value are multiplied and accumulated in parallel within one clock cycle, and the three calculation results are output to the result accumulation stage. At the same time, the operand reading stage synchronously executes the operand reading of the next motor.

[0175] S3.6: In the result accumulation stage, the three calculation results received in S3.5 are aligned and added together to generate a fixed-point number in binary two's complement form as the initial control value of the motor. The initial control value is then passed to the write-back stage.

[0176] Furthermore, the result accumulation stage receives the three calculation results output from the multiply-accumulate stage. It first performs bit alignment processing on the three results to ensure that the number of bits is consistent. Then, it completes the accumulation operation of the three results through a parallel adder array to generate a 32-bit fixed-point number in binary two's complement form, which is the initial value for PID control of the motor. The binary two's complement format can conveniently represent positive and negative numbers, which is suitable for the requirements of forward and reverse rotation control of the motor. After the result accumulation stage completes the calculation, it immediately transmits the initial control value to the write-back stage.

[0177] S3.7: In the write-back stage, the initial control value received in S3.6 is subjected to a limiting judgment: if the initial control value is greater than a preset positive saturation threshold, the initial control value is assigned to the positive saturation threshold; if the initial control value is less than a preset negative saturation threshold, the initial control value is assigned to the negative saturation threshold; if the initial control value is between the negative saturation threshold and the positive saturation threshold, the original value is maintained; the initial control value after the limiting judgment is latched into the output result register corresponding to the motor. In this embodiment, the positive saturation threshold is set to 32767, and the negative saturation threshold is set to -32768.

[0178] S3.8: When the time slot cycle counter has traversed all the motors corresponding to the operation priority level, repeat S3.3 to S3.7 to complete the PID operation task of multiple motors in each complete control cycle, and use the control initial value in the output result register as the PID control initial value of each motor.

[0179] S4: Perform consistency verification on the initial values ​​of each PID control path, generate the final PID control command and output it to the corresponding motor of the four-way vehicle, and at the same time send the feedback data of motor control back to S2.

[0180] It should be noted that the feedback signal is a processed signal collected by the sensor, synchronized and aligned, and used to calculate the deviation value and generate the input value for PID calculation. Its core is the input signal that drives the PID calculation. The feedback data is the final output PID control command or safety default control value. Its core is the closed-loop data returned after the control command is executed, which is used to generate the feedback signal in the next round S2. The former is the input signal before the calculation, and the latter is the closed-loop data after the control.

[0181] The process of verifying the consistency of the initial values ​​of each PID control path, generating the final PID control command, and outputting it to the corresponding motor of the four-way vehicle includes:

[0182] S4.1: Read the initial PID control values ​​of each motor from the output result register of the write-back stage, and send the initial PID control values ​​to two independent verification channels at the same time, namely the first verification channel and the second verification channel.

[0183] S4.2: In the first verification channel, the initial value of the PID control of the motor is differentially calculated with the historical PID control output value stored in the previous control cycle to obtain the rate of change of the control quantity. The rate of change is compared with the preset maximum allowable rate of change threshold. If the rate of change is less than or equal to the maximum allowable rate of change threshold, the first verification is passed. If the rate of change is greater than the maximum allowable rate of change threshold, the first verification failure flag is triggered.

[0184] Furthermore, when the first verification channel starts working, it first receives the initial value of the current motor PID control from the write-back stage output result register. At the same time, the first verification channel reads the historical PID control output value stored in the previous control cycle from the historical output value storage area inside the parameter cache unit. The reading operation is completed within one global sampling clock cycle.

[0185] Furthermore, the first verification channel is equipped with a dedicated 32-bit signed subtraction unit. The signed subtraction unit is used to perform the difference operation between the initial control value and the historical output value. In this embodiment, the system connects the current PID control initial value to the minuend input port of the signed subtraction unit and the historical PID control output value to the subtrahend input port of the signed subtraction unit. The signed subtraction unit performs the subtraction operation under the drive of the global sampling clock, subtracting the historical PID control output value from the current PID control initial value to obtain the difference between the two. This difference is the change in the control quantity, and the change is also output in the form of a 32-bit signed fixed-point number.

[0186] Furthermore, the first verification channel is equipped with a dedicated rate of change conversion logic unit. In this embodiment, the duration of a single complete control cycle is set to 50 microseconds. The rate of change conversion logic unit divides the calculated change in control quantity by the fixed control cycle duration to obtain the rate of change of control quantity. The numerical format of the rate of change is maintained as a 32-bit signed fixed-point number.

[0187] Furthermore, the first verification channel is pre-configured with a maximum permissible rate of change threshold storage unit. The maximum permissible rate of change threshold storage unit is a read-only storage structure. The value is written during hardware deployment and is not supported for modification or updating during operation. The maximum permissible rate of change threshold is set in stages according to the physical operating characteristics of each motor of the four-way vehicle. Specifically, the maximum permissible rate of change threshold corresponding to the travel axis motor is set to 800, the maximum permissible rate of change threshold corresponding to the lifting axis motor is set to 400, and the maximum permissible rate of change threshold corresponding to the steering axis motor is set to 200. All of them are stored in 32-bit signed fixed-point number format.

[0188] Furthermore, the calculated rate of change of the control quantity is sent to one input port of a 32-bit signed number comparator, and the maximum allowable rate of change threshold matching the current motor type is sent to the other input port of the comparator. This comparator is a dedicated hardware comparison unit that can complete the value judgment within one global sampling clock cycle. The comparator first determines whether the rate of change of the control quantity is less than or equal to the maximum allowable rate of change threshold. The judgment process is only performed on the absolute value and does not introduce additional logic correction. When the comparator outputs a judgment result that the rate of change of the control quantity is less than or equal to the maximum allowable rate of change threshold, the first verification channel outputs a verification pass signal. The verification pass signal is a fixed high-level logic state, indicating that the change amplitude of the current PID control initial value meets the system safety requirements. When the comparator outputs a judgment result that the rate of change of the control quantity is greater than the maximum allowable rate of change threshold, the first verification channel immediately triggers the first verification failure flag. The first verification failure flag is a fixed low-level logic state, indicating that the current PID control initial value has a sudden abnormality and does not meet the verification conditions.

[0189] S4.3: In the second verification channel, the initial value of the PID control of the motor is compared with the upper limit constraint value and the lower limit constraint value of the output stored in the parameter cache unit corresponding to the motor. If the initial value of the PID control is between the lower limit constraint value and the upper limit constraint value of the output, the second verification is passed. If the initial value of the PID control is less than the lower limit constraint value or greater than the upper limit constraint value of the output, the second verification failure flag is triggered.

[0190] Furthermore, when the second verification channel starts working, it first receives the initial value of the current motor PID control from the write-back stage output result register. At the same time, the second verification channel reads the pre-stored upper limit constraint value and lower limit constraint value from the parameter cache unit according to the motor identification code currently being processed. Both constraint values ​​are stored in 32-bit signed fixed-point number format.

[0191] Furthermore, each motor is assigned an independent constraint value storage address in the parameter cache unit. The storage addresses of the upper and lower limit output constraint values ​​are fixedly bound to the motor identification code. The address offset is fixed during the hardware deployment phase and remains unchanged during operation. In this embodiment, corresponding constraint values ​​are set for different types of motors. The upper limit output constraint value for the travel axis motor is set to 32767, and the lower limit output constraint value is set to -32768. The upper limit output constraint value for the lifting axis motor is set to 16384, and the lower limit output constraint value is set to -16385. The upper limit output constraint value for the steering axis motor is set to 8192, and the lower limit output constraint value is set to -8193. All constraint values ​​are written to the parameter cache unit during the hardware initialization phase and are not dynamically modified during operation.

[0192] Furthermore, the second verification channel integrates two completely independent and synchronously operating 32-bit signed number comparators, named the upper limit comparator and the lower limit comparator, respectively. The hardware structure and operational performance of the two comparators are completely identical, performing comparison operations synchronously within the same global sampling clock cycle, with no timing deviation. The system sends the current initial PID control value to the first input port of the upper limit comparator and the read output upper limit constraint value to the second input port. The upper limit comparator determines in real time whether the initial PID control value is greater than the output upper limit constraint value. Simultaneously, the system sends the current initial PID control value to the first input port of the lower limit comparator and the read output lower limit constraint value to the second input port. The lower limit comparator determines in real time whether the initial PID control value is less than the output lower limit constraint value. After the two comparison operations are completed, the second verification... The verification channel initiates a comprehensive logic judgment to determine whether the initial value of the PID control is between the lower and upper output constraint values. When the upper limit comparator determines that the initial value of the PID control is not greater than the upper output constraint value, and the lower limit comparator determines that the initial value of the PID control is not less than the lower output constraint value, the initial value of the PID control is determined to be within the valid range, and the second verification channel outputs a verification pass signal. This signal is a fixed high-level logic state, indicating that the current initial value of the PID control meets the output range constraint requirements. When the upper limit comparator determines that the initial value of the PID control is greater than the upper output constraint value, or the lower limit comparator determines that the initial value of the PID control is less than the lower output constraint value, as long as either of these conditions is met, the second verification channel immediately triggers the second verification failure flag. The second verification failure flag is a fixed low-level logic state, indicating that the current initial value of the PID control exceeds the allowable output range and does not meet the verification conditions.

[0193] S4.4: Input the verification results of the first verification channel and the verification results of the second verification channel to the arbitrator. If both the first and second verification channels pass, mark the current PID control initial value as a valid control instruction. If any verification channel fails, mark the current PID control initial value as an invalid control instruction. The arbitrator is prior art in this field and is not an inventive solution of this application. It will not be described in detail here.

[0194] S4.5: When the arbitrator outputs a valid control command, the initial PID control value of the motor is used as the final PID control command and output to the corresponding motor drive interface. At the same time, the final PID control command is written to the historical PID control output value storage unit for differential calculation in the next control cycle.

[0195] S4.6: When the arbitrator outputs an invalid control command, it prohibits the output of the current PID control initial value, and instead reads the safe default control value of the motor from the parameter cache unit as the final PID control command and outputs it to the corresponding motor drive interface. At the same time, it reports an alarm message of consistency verification failure to the upper motion controller.

[0196] S4.7: Simultaneously send the final PID control command or the safe default control value output back to the feedback data storage area in the parameter buffer unit as the input of the feedback signal in the next control cycle.

[0197] Example 2:

[0198] Please see Figure 3 Another embodiment of the present invention provides: a proportional-integral-differential parallel computing system based on programmable logic, comprising:

[0199] Parallel computing architecture module 10 includes a core computing unit and a multi-path parameter cache unit. The arithmetic logic link of the core computing unit is built based on the DSP unit inside the FPGA, and the multi-path parameter cache unit is built based on the block RAM. It is used to carry the hardware foundation for parallel computing of PID of multiple motors, and stores the proportional coefficient, integral coefficient and derivative coefficient of each motor, providing hardware support and data temporary storage space for parallel computing.

[0200] The signal processing module 20 collects the motor's operating condition information through an incremental photoelectric encoder, a Hall current sensor, and a temperature sensor. It receives the target speed command from the upper-level motion controller and generates a feedback signal. Based on the FPGA phase-locked loop, it generates a global sampling clock to complete signal synchronization and alignment. It calculates the deviation value and generates the PID calculation input value by combining it with preset control parameters.

[0201] The priority scheduling module 30 associates the real-time command status and working condition information of the host computer, divides the motors into hard real-time, soft real-time and non-real-time categories according to the response time requirements, assigns corresponding computing priorities to the walking axis motor group, lifting axis motor group and steering axis motor group, and maps them to the traversal order of the time slot cycle counter to ensure that the core computing unit schedules computing resources according to priority.

[0202] Parallel computing module 40 divides the core computing unit into a five-stage pipeline. It adopts a pipeline time-sharing mode to complete the PID operation input value reading, multiplication and addition, result accumulation and limit writing back in sequence according to the operation priority. It calculates the proportional term, integral term and derivative term in parallel in a single clock cycle to realize the efficient output of initial values ​​for multi-channel motor PID control.

[0203] The verification output module 50 includes dual independent verification channels and an arbitrator. It performs dual verification on the rate of change and output limit of the initial value of PID control. If the verification is successful, it outputs the final PID control command. If an anomaly occurs, it switches to the safe default control value and reports an alarm. At the same time, it sends back feedback data to form a control closed loop, ensuring stable and reliable control output.

[0204] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the present invention. All of these variations are within the protection scope of the present invention.

Claims

1. A parallel computation method for proportional-integral-differential computation based on programmable logic, characterized in that: include: S1: Build a PID parallel computing architecture based on programmable logic devices; The PID parallel computing architecture includes one core computing unit and a multi-path parameter cache unit; S2: Collect the operating condition information and feedback signals of each motor of the four-way vehicle, classify the operating condition information and assign calculation priorities, synchronize and align the feedback signals and input them into the parameter buffer unit, and generate PID calculation input values ​​for each motor in combination with preset control parameters. S3: The core computing unit performs parallel operations on the PID input values ​​of each path in the parameter buffer unit in a pipeline time-sharing mode according to the operation priority, and outputs the initial PID control values ​​of each motor. S4: Perform consistency verification on the initial values ​​of each PID control path, generate the final PID control command and output it to the corresponding motor of the four-way vehicle, and at the same time send the feedback data of motor control back to S2.

2. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 1, characterized in that, The construction of the PID parallel computing architecture based on programmable logic devices includes: S1.1: The arithmetic logic link of the core operation unit is constructed based on the digital signal processing unit inside the field-programmable gate array (FPGA), and the parameter cache unit is constructed based on the block random access memory inside the FPGA; the arithmetic logic link is configured as a cascaded structure including multiplier subunits, adder subunits and accumulator subunits; the parameter cache unit is used to store the proportional coefficient, integral coefficient and differential coefficient corresponding to each motor. S1.2: Input the proportional coefficient and deviation value of the current motor in the multi-path parameter buffer unit into the multiplier subunit, and the multiplier subunit outputs the proportional calculation result; input the deviation value into the accumulator subunit to obtain the accumulated deviation value, and then input the accumulated deviation value and integral coefficient into the multiplier subunit, and the multiplier subunit outputs the integral calculation result; input the differential coefficient and deviation change rate into the multiplier subunit, and the multiplier subunit outputs the differential calculation result; input the proportional calculation result, integral calculation result and differential calculation result in parallel into the adder subunit, and the accumulated sum result output by the adder subunit is used as the initial value for PID control of the current motor.

3. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 2, characterized in that, The acquisition of operating condition information and feedback signals from each motor of the four-way vehicle includes; S2.1: The rotor angular displacement signal of each motor is collected based on the incremental photoelectric encoder, the three-phase winding current signal of each motor is collected based on the Hall current sensor, and the winding temperature signal of each motor is collected based on the temperature sensor. The rotor angular displacement signal, the three-phase winding current signal and the winding temperature signal are summarized into operating condition information. S2.2: Receive the target speed commands of each motor sent from the four-way vehicle upper motion controller, and calculate the difference between the target speed commands of each motor and the differential value of the rotor angular displacement signal to generate a feedback signal.

4. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 3, characterized in that, The operating condition information is categorized and assigned computational priorities, including: S2.3: Receive the real-time command status of the travel axle motor group, lifting axle motor group and steering axle motor group sent by the upper motion controller of the four-way vehicle, and associate and bind the real-time command status with the working condition information; S2.4: Based on the response time requirements of the travel axis motor group, lifting axis motor group and steering axis motor group, the working condition information is divided into hard real-time, soft real-time and non-real-time categories; S2.5: Assign the highest priority to the travel axle motor group belonging to the hard real-time category, assign the second highest priority to the lifting axle motor group belonging to the soft real-time category, assign the default priority to the steering axle motor group belonging to the non-real-time category, and output the assignment result to the core computing unit.

5. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 4, characterized in that, The input parameter buffer unit that synchronizes and aligns the feedback signal includes: S2.6: Generate a global sampling clock based on the phase-locked loop inside the field-programmable gate array; S2.7: Using the global sampling clock as the trigger edge, perform first-stage synchronization processing based on triggers on the feedback signals of each motor collected; S2.8: Input the signal after the first-stage synchronization processing to the shift register chain for the second-stage synchronization processing over multiple clock cycles to obtain the measured value variables of each motor, and at the same time obtain the corresponding set value variables from the target speed command; S2.9: The measured value variables of each motor after the second-level synchronization processing are subtracted from the corresponding set value variables in the comparator to obtain the deviation value of the current cycle, and the deviation value of the current cycle is written into the parameter cache unit of the corresponding motor.

6. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 5, characterized in that, The process of generating PID calculation input values ​​for each motor by combining preset control parameters includes: S2.10: Read the preset values ​​of the proportional coefficient, integral coefficient, and derivative coefficient, as well as the intermediate result of the integral accumulation of the previous cycle from the parameter cache unit; S2.11: Multiply the deviation value of the current period by the preset value of the proportional coefficient to generate the proportional term input value; multiply the deviation value of the current period by the preset value of the integral coefficient and then add it to the intermediate result of the integral accumulation of the previous period to generate the integral term input value; multiply the difference between the deviation value of the current period and the deviation value of the previous period by the preset value of the differential coefficient to generate the differential term input value. S2.12: Package the proportional term input value, integral term input value and derivative term input value into PID calculation input value and store them in the storage location of the current motor in the parameter cache unit.

7. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 6, characterized in that, The specific steps of S3 include: S3.1: The core operation unit is divided into instruction read level, operand read level, multiply-accumulate operation level, result accumulation level and write-back level; S3.2: Construct a time-slot cycle counter, set the modulus of the time-slot cycle counter to the maximum number of motor paths supported by the parameter cache unit, and map the allocated operation priority to the traversal order of the time-slot cycle counter; S3.3: In the instruction read level, according to the current count value of the time slot cycle counter, the motor identification code corresponding to the current time slot is retrieved from the allocated operation priority, and the motor identification code is transmitted to the operand read level; S3.4: In the operand reading stage, a reading address for the parameter cache unit bound to the corresponding motor is generated based on the received motor identification code. The PID calculation input value stored in S2.12 is retrieved from the reading address and passed to the multiply-accumulate operation stage. At the same time, the motor identification code and PID calculation input value of the next motor corresponding to the next time slot are preloaded in the operand reading stage.

8. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 7, characterized in that, The specific steps of S3 also include: S3.5: In the multiply-accumulate stage, the proportional, integral, and derivative terms in the PID operation input value are multiplied and accumulated in parallel within one clock cycle, and the three calculation results are output to the result accumulation stage. At the same time, the operand reading stage synchronously executes the operand reading of the next motor. S3.6: In the result accumulation stage, the received three calculation results are aligned and added together to generate a fixed-point number in binary two's complement form as the initial control value of the corresponding motor, and the initial control value is passed to the write-back stage; S3.7: In the write-back stage, the received initial control value is subjected to a limiting judgment: if the initial control value is greater than a preset positive saturation threshold, the initial control value is assigned to the positive saturation threshold; if the initial control value is less than a preset negative saturation threshold, the initial control value is assigned to the negative saturation threshold; if the initial control value is between the negative saturation threshold and the positive saturation threshold, the original value is maintained; the initial control value after the limiting judgment is latched into the output result register corresponding to the corresponding motor. S3.8: When the time slot cycle counter has traversed all the motors corresponding to the operation priority level, repeat S3.3 to S3.7 to complete the PID operation task of multiple motors in each complete control cycle, and use the control initial value in the output result register as the PID control initial value of each motor.

9. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 8, characterized in that, The process of verifying the consistency of the initial values ​​of each PID control path, generating the final PID control command, and outputting it to the corresponding motor of the four-way vehicle includes: S4.1: Read the initial PID control values ​​of each motor from the output result register of the write-back stage, and send the initial PID control values ​​to two independent verification channels at the same time, namely the first verification channel and the second verification channel. S4.2: In the first verification channel, the initial value of the PID control of the corresponding motor is differentially calculated with the historical PID control output value stored in the previous control cycle to obtain the rate of change of the control quantity. The rate of change is compared with the preset maximum allowable rate of change threshold. If the rate of change is less than or equal to the maximum allowable rate of change threshold, the first verification is passed. If the rate of change is greater than the maximum allowable rate of change threshold, the first verification failure flag is triggered. S4.3: In the second verification channel, the initial value of the PID control of the corresponding motor is compared with the upper limit constraint value and the lower limit constraint value of the output stored in the parameter cache unit corresponding to the corresponding motor. If the initial value of the PID control is between the lower limit constraint value and the upper limit constraint value of the output, the second verification is passed. If the initial value of the PID control is less than the lower limit constraint value or greater than the upper limit constraint value of the output, the second verification failure flag is triggered.

10. The proportional-integral-differential parallel computing method based on programmable logic as described in claim 9, characterized in that, The process of verifying the consistency of the initial values ​​of each PID control path, generating the final PID control command, and outputting it to the corresponding motor of the four-way vehicle also includes: S4.4: Input the verification results of the first verification channel and the verification results of the second verification channel to the arbitrator. If both the first and second verification channels pass, mark the current PID control initial value as a valid control command. If any verification channel fails, mark the current PID control initial value as an invalid control command. S4.5: When the arbitrator outputs a valid control command, the initial PID control value of the corresponding motor is output as the final PID control command to the corresponding motor drive interface. At the same time, the final PID control command is written into the historical PID control output value storage unit for differential calculation in the next control cycle. S4.6: When the arbitrator outputs an invalid control command, it prohibits the output of the current PID control initial value, and instead reads the safety default control value of the corresponding motor from the parameter cache unit as the final PID control command and outputs it to the corresponding motor drive interface. At the same time, it reports an alarm message of consistency verification failure to the upper motion controller. S4.7: Simultaneously send the final PID control command or the safe default control value output back to the feedback data storage area in the parameter buffer unit as the input of the feedback signal in the next control cycle.

11. A proportional-integral-differential parallel computing system based on programmable logic, used to implement the proportional-integral-differential parallel computing method based on programmable logic as described in any one of claims 1-10, characterized in that, include: The parallel computing architecture module includes a core computing unit and a multi-path parameter caching unit, which are used to construct the arithmetic logic links of the core computing unit. The signal processing module is used to collect the operating condition information of the motor, receive the target speed command from the upper motion controller and generate feedback signals, generate a global sampling clock based on the FPGA phase-locked loop to complete signal synchronization and alignment, calculate the deviation value and generate PID calculation input value in combination with preset control parameters; The priority scheduling module is used to classify motors into hard real-time, soft real-time, and non-real-time categories, and to assign corresponding operation priorities to the travel axis motor group, lifting axis motor group, and steering axis motor group, which are mapped to the traversal order of the time slot cycle counter. The parallel computing module is used to sequentially complete the PID calculation input value reading, multiplication and addition, result accumulation and limit writing back in a pipeline time-sharing mode according to the calculation priority, and output the initial PID control values ​​of each motor. The verification output module is used to perform dual verification of the rate of change and output limit of the initial value of PID control. If the verification is successful, the final PID control command is output. If an anomaly occurs, the safe default control value is switched, an alarm is reported, and feedback data is sent back.

Images