Integrated processing system for i / o signals in industrial automation control systems

Abstract

The application relates to the technical field of measurement data processing, and discloses an I / O signal comprehensive processing system in an industrial automation control system.The system comprises a multi-modal input and output acquisition module, a real-time monitoring and fault diagnosis module, a virtual instrument module and a hierarchical experiment and teaching management module.The hierarchical experiment and teaching management module writes a topological field into registers of an adaptive range switching unit and a multi-scale feature extraction unit through a topological description file parser and a hardware resource configurator; a measurement data processing and signal detection module weights multi-scale features through an attention weighted fusion subunit; and a virtual instrument module performs timestamp correction on a state synchronization matrix through a delay compensation register group.The system solves the problem of static binding of bottom-layer hardware configuration and upper-layer algorithm logic, realizes joint dynamic reconstruction of hardware conditioning parameters and feature extraction logic, and eliminates the time deviation between physical pin state changes and virtual instrument model display.

Description

Technical Field

[0001] This invention relates to the field of measurement data processing technology, and discloses an integrated I / O signal processing system for industrial automation control systems. Background Technology

[0002] Existing industrial automation input / output signal processing platforms typically employ a discrete hardware board architecture for data acquisition and monitoring. In conventional solutions, digital signals, analog signals, and serial communication signals are each connected to separate acquisition boards. Each board has its own built-in signal conditioning circuitry, such as fixed amplification factors and filter cutoff frequencies. The acquisition boards transmit the converted raw data to a host computer, which runs dedicated monitoring software that performs simple threshold comparisons and waveform displays according to preset data processing logic. In teaching, training, or industrial testing scenarios, operators need to manually replace the corresponding acquisition boards based on different equipment types and reconfigure independent software project files on the host computer. The data channels and processing parameters between each hardware board and the host computer software remain statically bound.

[0003] In industrial process analysis and environmental monitoring scenarios, an increasing number of optical analytical instruments, spectral sensors, and electrochemical detection devices are being integrated into automated control systems. Their output signals are typical analog or digital I / O signals. These detection devices, based on the analysis of the physicochemical properties of materials or media, also face the problem of static binding between the underlying hardware conditioning parameters and the upper-level feature extraction logic. Existing systems struggle to dynamically adjust the sampling range, filtering methods, and feature extraction operators according to different analytical principles and signal characteristics.

[0004] Furthermore, the static binding architecture between various acquisition boards and host computer software in existing technologies prevents the system from dynamically reconstructing the underlying hardware conditioning parameters and upper-level feature extraction logic when facing multi-scenario tasks that require frequent switching of device types and signal topologies. When sensors with different ranges or actuators with different protocols are connected in industrial settings or educational training, the fixed hardware conditioning circuit cannot adaptively adjust the signal amplification factor and filtering characteristics, and the statically bound data processing logic cannot change the wavelet decomposition parameters and multi-scale feature extraction operators according to the new signal type. This results in a technical problem where the underlying hardware configuration and upper-level algorithm logic are disconnected when the input / output signal processing platform switches between different industrial and educational training scenarios. Summary of the Invention

[0005] The purpose of this invention is to provide an integrated I / O signal processing system for industrial automation control systems, which can solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The I / O signal integrated processing system in industrial automation control system includes a multi-modal I / O acquisition module, a measurement data processing and signal detection module, a real-time monitoring and fault diagnosis module, a virtual instrument module, and a hierarchical experiment and teaching management module; The multimodal I / O acquisition module includes a digital input / output interface, an analog input / output interface, and a serial communication interface, which are used to acquire and output multimodal I / O signals from external industrial equipment. The measurement data processing and signal detection module is connected to the multimodal I / O acquisition module and is used to perform filtering, scaling transformation and feature extraction processing on the multimodal I / O signal; The real-time monitoring and fault diagnosis module is connected to the measurement data processing and signal detection module, and is used to receive the processed data and perform abnormal state identification and fault location. The virtual instrument module is connected to the real-time monitoring and fault diagnosis module and is used to call the virtual instrument component to visualize and reconstruct the multimodal I / O signals and fault data. The hierarchical experiment and teaching management module is connected to the multimodal I / O acquisition module, the measurement data processing and signal detection module, the real-time monitoring and fault diagnosis module, and the virtual instrument module, respectively, and is used to issue configuration commands and record interactive data, thus constituting the system.

[0007] Preferably, the multimodal I / O acquisition module further includes a signal conditioning unit and an adaptive range switching unit; The signal conditioning unit is connected to the digital input / output interface, the analog input / output interface and the serial communication interface respectively. The signal conditioning unit includes an opto-isolation circuit, a low-pass filter circuit and a level conversion circuit. The adaptive range switching unit is connected to the analog input / output interface and the signal conditioning unit. The adaptive range switching unit includes a multi-channel analog switch matrix and a relay array. The input terminal of the multi-channel analog switch matrix is ​​connected to the output terminal of the signal conditioning unit, and the output terminal of the multi-channel analog switch matrix is ​​connected to the control terminal of the relay array. The contact terminals of the relay array are connected to a precision voltage divider resistor network with different resistance values ​​to adjust the amplitude of the analog signal input to the measurement data processing and signal detection module.

[0008] Preferably, the measurement data processing and signal detection module includes a wavelet noise reduction unit and a multi-scale feature extraction unit; The input of the wavelet noise reduction processing unit is connected to the output of the multimodal I / O acquisition module, and the wavelet noise reduction processing unit has an embedded wavelet basis function library and a decomposition layer configuration register. The multi-scale feature extraction unit is connected to the output of the wavelet denoising processing unit. The multi-scale feature extraction unit includes a time-domain statistics calculation operator, a frequency-domain fast Fourier transform operator, and a time-frequency domain joint analysis operator. The time-domain statistics calculation operator and the frequency-domain fast Fourier transform operator are connected in parallel to the input channel of the multi-scale feature extraction unit. The outputs of the time-domain statistics calculation operator, the frequency-domain fast Fourier transform operator, and the time-frequency domain joint analysis operator are connected to the feature splicing bus of the multi-scale feature extraction unit. The feature splicing bus is connected to the real-time monitoring and fault diagnosis module.

[0009] Preferably, the real-time monitoring and fault diagnosis module includes a time-series sliding window segmentation unit and an abnormal state identification unit; The input of the time-series sliding window segmentation unit is connected to the output of the measurement data processing and signal detection module. The time-series sliding window segmentation unit is equipped with a window step size register and an overlap register. The abnormal state identification unit is connected to the output of the temporal sliding window segmentation unit, and the abnormal state identification unit includes an isolated forest detector and a dynamic time warping matcher. The input of the isolated forest detector is connected to the first output branch of the time-series sliding window segmentation unit, the input of the dynamic time warping matcher is connected to the second output branch of the time-series sliding window segmentation unit, the outputs of the isolated forest detector and the dynamic time warping matcher are respectively connected to the input of a logic OR gate, and the output of the logic OR gate is connected to the virtual instrument module.

[0010] Preferably, the virtual instrument module includes a digital twin mapping unit and a dynamic waveform rendering unit; The input end of the digital twin mapping unit is connected to the output end of the real-time monitoring and fault diagnosis module. The digital twin mapping unit is equipped with a three-dimensional geometric model library of industrial equipment and a physical pin mapping table. The dynamic waveform rendering unit is connected to the digital twin mapping unit, and the dynamic waveform rendering unit includes a graphics rendering engine, a video memory allocation pool, and a frame synchronization controller. The graphics rendering engine preloads oscilloscope controls and spectrum analyzer controls through the video memory allocation pool. The input of the frame synchronization controller is connected to the status refresh signal of the digital twin mapping unit. The output of the frame synchronization controller is connected to the rendering trigger of the graphics rendering engine. The video output of the graphics rendering engine is connected to the signal input of the display.

[0011] Preferably, the hierarchical experiment and teaching management module includes a role permission resolution unit and an experiment topology dynamic arrangement unit; The role permission parsing unit is equipped with a role-based access control matrix and a token generator. The output of the role permission parsing unit is connected to the permission verification end of the experimental topology dynamic orchestration unit. The experimental topology dynamic orchestration unit includes a topology description file parser and a hardware resource configurator. The topology description file parser receives an externally input experimental topology file at its input end, and its output end is connected to the hardware resource configurator. The output end of the hardware resource configurator is connected to the configuration register of the multimodal I / O acquisition module, the parameter register of the measurement data processing and signal detection module, the threshold register of the real-time monitoring and fault diagnosis module, and the control attribute register of the virtual instrument module, respectively.

[0012] Preferably, the adaptive range switching unit further includes a programmable gain amplifier network and an analog-to-digital converter; The input terminal of the programmable gain amplifier network is connected to the contact terminal of the relay array. The programmable gain amplifier network includes multiple cascaded instrumentation amplifiers and digital potentiometers. The gain control terminal of the multiple cascaded instrumentation amplifiers is connected to the adjustment terminal of the digital potentiometer, and the sliding terminal control interface of the digital potentiometer is connected to the first group of general-purpose input / output pins of the field-programmable gate array. The analog input terminal of the analog-to-digital converter is connected to the output terminal of the programmable gain amplifier network. The digital output terminal of the analog-to-digital converter is connected to the second set of general-purpose input / output pins of the field-programmable gate array (FPGA) via a high-speed serial peripheral interface bus. The parallel data bus of the FPGA is connected to the data input terminal of the measurement data processing and signal detection module.

[0013] Preferably, the multi-scale feature extraction unit further includes an attention-weighted fusion subunit; The input of the attention-weighted fusion subunit is connected to the feature splicing bus; The attention-weighted fusion subunit includes a fully connected mapping layer, a soft maximum activation layer, and an element-wise multiplier. The number of input nodes of the fully connected mapping layer matches the bit width of the feature splicing bus. The output of the fully connected mapping layer is connected to the input of the soft maximum activation layer. The output of the soft maximum activation layer is connected to the first input of the element-wise multiplier. The second input of the element-wise multiplier is connected to the data branch of the feature splicing bus. The output of the element-wise multiplier forms the fused feature output of the multi-scale feature extraction unit. The fused feature output is connected to the real-time monitoring and fault diagnosis module.

[0014] Preferably, the digital twin mapping unit further includes a state synchronization matrix and a delay compensation register group; The row vectors of the state synchronization matrix correspond to the physical pin numbers in the physical pin mapping table, and the column vectors of the state synchronization matrix correspond to the virtual node numbers in the industrial equipment three-dimensional geometric model library. The delay compensation register group is connected in parallel to the data refresh channel of the state synchronization matrix. The delay compensation register group includes a multi-level first-in-first-out buffer and a timestamp calibration counter. The data input terminal of the multi-level FIFO buffer is connected to the output terminal of the real-time monitoring and fault diagnosis module, the clock input terminal of the timestamp calibration counter is connected to an external high-precision clock source, the data output terminal of the multi-level FIFO buffer is connected to the input terminal of the state synchronization matrix, and the output terminal of the state synchronization matrix is ​​connected to the dynamic waveform rendering unit.

[0015] Preferably, the experimental topology dynamic orchestration unit further includes a syntax checker and a hardware address mapping table; The input of the syntax validator is connected to the preprocessing output of the topology description file parser, and the syntax validator embeds an abstract syntax tree generation module and a semantic conflict detection state machine. The query interface of the hardware address mapping table is connected to the post-processing output of the topology description file parser. The storage array of the hardware address mapping table is pre-set with the base address offset of the multi-modal I / O acquisition module and the memory mapping address of the measurement data processing and signal detection module. The first output of the hardware resource configurator is connected to the output of the syntax checker, and the second output of the hardware resource configurator is connected to the data output of the hardware address mapping table. The hardware resource configurator directly writes the parsed topology field into the configuration register of the multimodal I / O acquisition module.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention, through the topology description file parser and hardware resource configurator in the hierarchical experiment and teaching management module, directly writes the experimental topology fields into the corresponding registers of the multimodal input / output acquisition module and the measurement data processing and signal detection module, realizing the joint dynamic reconstruction of the underlying hardware conditioning network and the upper-level multi-scale feature extraction logic. The experimental topology dynamic orchestration unit, combined with a syntax checker and a hardware address mapping table, after confirming the topology logic is correct through a semantic conflict detection state machine, controls the gain of the instrumentation amplifier in the programmable gain amplification network by adjusting the digital potentiometer through the first set of general-purpose input / output pins of the field-programmable gate array. Simultaneously, it configures the analog-to-digital converter through the second set of general-purpose input / output pins, and, in conjunction with the multi-channel analog switch matrix and relay array in the adaptive range switching unit, changes the access state of the precision voltage divider resistor network. This enables the system to automatically and synchronously switch the hardware amplification factor and data sampling parameters when receiving input / output signals of different ranges and types, breaking the limitation of static binding between hardware configuration and algorithm logic in existing technologies.

[0017] 2. This invention sets up an attention-weighted fusion subunit in the multi-scale feature extraction unit, uses a fully connected mapping layer and a soft-maximum activation layer to generate weight coefficients, and performs weighted fusion of time-domain statistics, frequency-domain fast Fourier transform, and time-frequency joint analysis features through an element-wise multiplier, thus unifying the expression dimension of the fused feature output data. After the fused features are input to the abnormal state recognition unit, the isolated forest detector and the time-series sliding window segmentation unit cooperate, combined with a dynamic time warping matcher and a logic OR gate circuit to complete the state determination, and the determination result is transmitted to the virtual instrument module. The digital twin mapping unit imports the state data into the state synchronization matrix according to the physical pin mapping table. The multi-level first-in-first-out buffer and the timestamp calibration counter in the delay compensation register group perform timestamp calibration on the matrix refresh channel according to the high-precision clock source. The frame synchronization controller triggers the graphics drawing engine to update the oscilloscope control and spectrum analyzer control according to the refresh signal of the state synchronization matrix, thus eliminating the time deviation between the physical pin state change and the display of the virtual instrument's three-dimensional geometric model. Attached Figure Description

[0018] Figure 1 A flowchart illustrating the overall architecture of an integrated input / output signal processing system in an industrial automation control system. Figure 2 Flowchart for multimodal signal acquisition and adaptive range switching; Figure 3 Flowchart for multi-scale feature extraction and attention-weighted fusion; Figure 4 Flowchart for abnormal state identification and fault location; Figure 5 Flowchart for digital twin mapping and dynamic waveform rendering; Figure 6 This is a flowchart for the dynamic arrangement of experimental topologies. Detailed Implementation

[0019] Please refer to the attached document. Figure 1This embodiment provides an integrated I / O signal processing system for industrial automation control systems. The system is deployed on hardware carriers in industrial settings and teaching training platforms. These hardware carriers are built upon field-programmable gate arrays (FPGAs) and embedded processors. The system includes a multi-modal I / O acquisition module, a measurement data processing and signal detection module, a real-time monitoring and fault diagnosis module, a virtual instrument module, and a hierarchical experiment and teaching management module. The multi-modal I / O acquisition module includes digital input / output interfaces, analog input / output interfaces, and a serial communication interface. Its external interface connects to the signal terminals of external industrial equipment, while its internal data terminal connects to the input terminal of the measurement data processing and signal detection module. Specifically, the digital input / output interface includes a bidirectional level conversion circuit and an input debouncing circuit. The input terminal of the digital input interface is connected to the switch signal output terminal of external industrial equipment, including passive contact signals and active level signals from proximity switches, photoelectric sensors, limit switches, and relay auxiliary contacts. The debouncing circuit of the digital input interface performs edge detection and debouncing processing on the input switch signals. The debouncing time parameter can be modified through configuration commands issued by the hierarchical experiment and teaching management module. The output terminal of the digital output interface is connected to the switch control terminal of external industrial equipment, including the control circuit of contactor coils, solenoid valve drives, indicator lights, and alarm devices. The output status of the digital output interface is set and reset by the control signals of the real-time monitoring and fault diagnosis module or by commands issued by the hierarchical experiment and teaching management module. The analog input / output interface includes differential input circuits and output drive circuits. The input terminals of the analog input interface are connected to the output terminals of analog sensors of external industrial equipment, including pressure sensors, temperature sensors, flow sensors, liquid level sensors, and standard current and voltage signals output by optical sensors, spectral analysis modules, and electrochemical detection sensors used for media or material property analysis. The analog input interface transmits the acquired continuous analog signals to the back-end signal processing link. The output terminals of the analog output interface are connected to the analog control terminals of external industrial equipment, including the frequency setpoint terminal of the frequency converter, the opening control terminal of the electric regulating valve, and the voltage setting terminal of the programmable power supply. The analog output interface converts digital control data into continuous analog signals and outputs them to external devices. The serial communication interface includes RS232 transceiver circuits, RS485 transceiver circuits, and protocol parsing logic. The bus end of the serial communication interface connects to the serial communication bus of external industrial equipment and supports Modbus-RTU, Modbus-ASCII, Profibus-DP, and CANopen standard industrial communication protocols. The serial communication interface completes the transmission and reception of bus data, frame parsing and verification, and transmits the parsed valid data to the measurement data processing and signal detection module. At the same time, it receives control commands from the upper-layer module and encapsulates them into bus frames of the corresponding protocol and sends them to the external industrial equipment.The multimodal I / O acquisition module completes the acquisition and output of multimodal I / O signals from external industrial equipment, realizing full coverage of industrial field signals and bidirectional data interaction.

[0020] The measurement data processing and signal detection module is connected to the multimodal I / O acquisition module and is used to perform filtering, scaling transformation, and feature extraction on the multimodal I / O signals. Specifically, the input of the measurement data processing and signal detection module receives the raw acquisition data output by the multimodal I / O acquisition module, including the state data of digital signals, the sampled data of analog signals, and the bus data parsed by the serial communication interface. The measurement data processing and signal detection module first filters the raw acquisition data. The filtering process uses a moving average filtering algorithm to smooth the continuously acquired analog sampled data and eliminate random noise introduced during the sampling process. For digital signals, the filtering process uses state-keeping verification logic to check the consistency of the digital state over multiple consecutive sampling periods. Only when the state remains consistent over multiple consecutive sampling periods is the valid state value of the digital signal updated, eliminating state jumps caused by electromagnetic interference in the industrial environment. After filtering, the measurement data processing and signal detection module performs scaling transformation on the sampled data of the analog signal, converting the digital encoded value after analog-to-digital conversion into the actual engineering value of the corresponding physical quantity. The scaling transformation adopts linear transformation logic, and presets corresponding upper and lower limits of the range and upper and lower limits of the engineering value for different types of analog input signals to complete the mapping conversion from digital quantity to engineering value. The calculation logic of the scaling transformation is implemented through the following formula:

[0021] in, The physical quantity is the engineering value after scaling transformation. This refers to the lower limit of the engineering range of a physical quantity. This refers to the upper limit of the engineering range of a physical quantity. This is the encoded digital value after filtering by analog-to-digital conversion. Input the digital encoding value corresponding to the lower limit of the input range to the analog-to-digital converter. Input the digital encoding value corresponding to the upper limit of the input range to the analog-to-digital converter.

[0022] After scaling transformation, the measurement data processing and signal detection module performs feature extraction on the processed signal data. For digital signals, it extracts feature parameters such as state transition time, transition frequency, and duration; for analog signals, it extracts feature parameters such as mean, peak value, valley value, and rate of change; and for serial communication bus data, it extracts feature parameters such as frame interval, frame length, and data payload distribution. After feature extraction, the measurement data processing and signal detection module transmits the processed valid data and extracted feature parameters to the real-time monitoring and fault diagnosis module.

[0023] The real-time monitoring and fault diagnosis module is connected to the measurement data processing and signal detection module to receive processed data and perform abnormal state identification and fault location. Specifically, the input of the real-time monitoring and fault diagnosis module receives processed data and feature parameters output from the measurement data processing and signal detection module. The module first monitors the received data in real time, comparing the acquired signal data with a preset normal operating threshold range. When the signal data exceeds the preset threshold range, an abnormal state flag is triggered. Simultaneously, the module identifies abnormal states in the extracted feature parameters, comparing them with a preset normal state feature library. When the deviation between the feature parameters and the normal state feature library exceeds a preset range, abnormal state identification is completed. After abnormal state identification, the module performs fault location. Based on the interface number, signal type, and feature parameter deviation type corresponding to the abnormal signal, it matches a preset fault knowledge base to determine the fault location, fault type, and fault cause corresponding to the abnormal state, completing the fault location process. The real-time monitoring and fault diagnosis module transmits the real-time monitored signal data, abnormal state identification results, and fault location data to the virtual instrument module.

[0024] The virtual instrument module connects to the real-time monitoring and fault diagnosis module, and is used to call virtual instrument components to perform visual reconstruction of multimodal I / O signals and fault data. Specifically, the virtual instrument module contains a library of callable virtual instrument components, which includes pre-installed oscilloscope components, digital multimeter components, spectrum analyzer components, logic analyzer components, data logger components, and fault alarm panel components. The virtual instrument module receives signal data, abnormal state identification results, and fault location data transmitted from the real-time monitoring and fault diagnosis module. According to the configuration instructions issued by the hierarchical experiment and teaching management module, it calls the corresponding virtual instrument components, maps the received data to the input channels of the virtual instrument components, and completes waveform plotting, numerical display, spectrum analysis, and logic state display of multimodal I / O signals. At the same time, it provides alarm prompts, displays fault information, and marks fault locations for fault data, realizing the visual reconstruction of multimodal I / O signals and fault data. The visualization output data of the virtual instrument module is transmitted to an external display device to present the visualization content.

[0025] The hierarchical experiment and teaching management module is connected to the multimodal I / O acquisition module, measurement data processing and signal detection module, real-time monitoring and fault diagnosis module, and virtual instrument module, respectively. It is used to issue configuration commands and record interactive data, forming a complete system. Specifically, the hierarchical experiment and teaching management module receives externally input configuration commands and experiment task files. After parsing the configuration commands and experiment task files, it issues interface configuration and sampling parameter configuration commands to the multimodal I / O acquisition module; filtering parameters, scaling transformation range, and feature extraction type configuration commands to the measurement data processing and signal detection module; monitoring threshold, fault knowledge base update, and anomaly identification parameter configuration commands to the real-time monitoring and fault diagnosis module; and component invocation, display parameters, and visualization layout configuration commands to the virtual instrument module. Simultaneously, the hierarchical experiment and teaching management module collects real-time operating status data, signal processing data, configuration modification records, and control command interaction data from each module. It stores, archives, and traces the collected interaction data, achieving data traceability and management throughout the entire system operation process. The tiered experiment and teaching management module achieves unified scheduling of system hardware resources and software processing logic through unified configuration and data management of each module, thus forming a complete I / O signal integrated processing system in the industrial automation control system.

[0026] Table 1. Relationship between Multimodal I / O Signal Types and Interface Mapping

[0027] This table defines the mapping relationship between all types of signals supported by the multimodal I / O acquisition module and their corresponding interfaces. It clarifies the access device type, effective range, and update cycle of each type of signal, providing a standardized reference for system interface configuration and parameter settings. This ensures that those skilled in the art can correctly connect and configure the interfaces between external industrial equipment and the system based on the table's contents.

[0028] In this embodiment, a multimodal I / O acquisition module enables unified acquisition and output of all types of I / O signals in the industrial field. A measurement data processing and signal detection module completes the standardized processing and feature extraction of the acquired signals. A real-time monitoring and fault diagnosis module enables real-time monitoring of signals and identification and location of abnormal faults. A virtual instrument module completes the visual reconstruction of signal and fault data. A hierarchical experiment and teaching management module enables unified configuration and data management of all system modules. This constructs a complete I / O signal integrated processing system, realizing the full-link processing and control of multimodal I / O signals in industrial automation scenarios.

[0029] refer to Figure 2In a preferred embodiment, the multi-mode I / O acquisition module further includes a signal conditioning unit and an adaptive range switching unit. The signal conditioning unit is connected to the digital input / output interface, the analog input / output interface, and the serial communication interface, and includes an opto-isolation circuit, a low-pass filter circuit, and a level conversion circuit. Specifically, the opto-isolation circuit is constructed using high-speed optocouplers and is connected to the signal link of the digital input / output interface, the front-end link of the analog input / output interface, and the bus transceiver link of the serial communication interface. The opto-isolation circuit achieves electrical isolation between the internal circuits of the system and external industrial equipment, eliminating the impact of common-mode interference, ground potential difference, and surge impacts on the internal circuits of the system in industrial environments. The isolation performance of the opto-isolation circuit meets the electrical safety requirements of industrial environments. The low-pass filter circuit is connected to the signal link of the analog input / output interface and the bus link of the serial communication interface. For analog input signals, the low-pass filter circuit uses a cascaded structure of a passive RC filter network and an active operational amplifier filter circuit to attenuate high-frequency interference components in the analog input signal. The cutoff frequency of the low-pass filter circuit can be adjusted by configuring external RC parameters. For serial communication bus signals, the low-pass filter circuit uses a differential filter network to filter out high-frequency glitches and radio frequency interference in the bus signal, ensuring the stability of bus communication. The level conversion circuit is connected to the signal link of the digital input / output interface and the bus link of the serial communication interface. For digital input signals, the level conversion circuit converts different amplitude level signals input from external industrial equipment, including industrial standard levels, into level signals compatible with the system's internal circuitry. For digital output signals, the level conversion circuit converts the level signals output from the system's internal circuitry into the drive level signals required by external industrial equipment. For the bus signals of the serial communication interface, the level conversion circuit performs bidirectional conversion between TTL level and RS232 level and RS485 differential level, achieving signal compatibility matching between different level standards.

[0030] The adaptive range switching unit connects the analog input / output interface and the signal conditioning unit. The adaptive range switching unit includes a multi-channel analog switch matrix and a relay array. The input of the multi-channel analog switch matrix is ​​connected to the output of the signal conditioning unit, and the output of the multi-channel analog switch matrix is ​​connected to the control terminal of the relay array. The contacts of the relay array are connected to a precision voltage divider network of different resistance values ​​to adjust the amplitude of the analog signal input to the measurement data processing and signal detection module. Specifically, the multi-channel analog switch matrix is ​​constructed using cascaded multi-channel single-pole multi-throw analog switch chips. The number of channels in the multi-channel analog switch matrix corresponds to the number of channels in the analog input interface. Each analog input signal corresponds to an independent analog switch channel. The channel selection state of the multi-channel analog switch matrix is ​​controlled by the control signal output from the field-programmable gate array. Based on the amplitude range of the input analog signal, the corresponding analog switch channel is selected, and the corresponding control signal is output to the relay array. The relay array is constructed using multiple sets of single-pole double-throw electromagnetic relays. Each set of relays corresponds to one analog input channel. The relay coil control terminal is connected to the corresponding output channel of a multi-channel analog switch matrix. The relay contacts are connected to different voltage divider branches of a precision voltage divider resistor network. This network uses low-temperature drift, high-precision metal film resistors. Different voltage divider branches correspond to different voltage division ratios, allowing for different voltage division ratios of the input analog signal. This adjusts a wide range of input analog signals to an amplitude range compatible with the back-end processing circuitry. The output signal amplitude of the precision voltage divider resistor network is calculated using the following formula:

[0031] in, The output signal amplitude of the precision voltage divider resistor network. The amplitude of the analog input signal output by the signal conditioning unit. The resistance value of the upper voltage divider resistor in the voltage divider branch is... This is the resistance value of the lower voltage divider resistor in the voltage divider branch. This represents the total resistance of the voltage divider branch.

[0032] Furthermore, the adaptive range switching unit also includes a programmable gain amplifier network and an analog-to-digital converter. The input terminal of the programmable gain amplifier network is connected to the contact terminal of the relay array. The programmable gain amplifier network includes multiple cascaded instrumentation amplifiers and digital potentiometers. The gain control terminals of the multiple cascaded instrumentation amplifiers are connected to the adjustment terminals of the digital potentiometers. The sliding terminal control interface of the digital potentiometers is connected to the first group of general-purpose input / output pins of the field-programmable gate array. Specifically, the instrumentation amplifiers are constructed using low-noise, high-input-impedance, and high common-mode rejection ratio instrumentation amplifier chips. The cascaded instrumentation amplifiers can achieve a wide range of gain adjustment. The first-stage instrumentation amplifier buffers and amplifies the input signal, while the second-stage instrumentation amplifier performs fine gain adjustment of the signal. The gain control terminals of both instrumentation amplifiers are connected to the corresponding digital potentiometers. Adjusting the resistance value of the digital potentiometers changes the feedback resistance ratio of the instrumentation amplifiers, thereby adjusting the amplification factor of the instrumentation amplifiers. The digital potentiometer is constructed using a non-volatile digital potentiometer chip. Its slider control interface is a serial peripheral interface. The clock line, data line, and chip select line of the serial peripheral interface are connected to the first group of general-purpose input / output pins of the field-programmable gate array (FPGA). The FPGA sends resistance adjustment commands to the digital potentiometer through the serial peripheral interface, changing the position of the slider and thus adjusting the gain coefficient of the instrumentation amplifier. The total gain coefficient of the programmable gain amplifier network is calculated using the following formula:

[0033] in, The total gain coefficient of the programmable gain amplifier network. This represents the gain coefficient of the first-stage instrumentation amplifier. This is the gain coefficient of the second-stage instrumentation amplifier.

[0034] The analog input of the analog-to-digital converter (ADC) is connected to the output of the programmable gain amplifier network (PGA). The digital output of the ADC is connected to the second set of general-purpose input / output pins of the field-programmable gate array (FPGA) via a high-speed serial peripheral interface bus. The parallel data bus of the FPGA is connected to the data input of the measurement data processing and signal detection module. Specifically, the ADC is constructed using successive approximation or Σ-Δ ADC chips to meet the high-precision, high-speed sampling requirements of analog signals in industrial environments. The analog input of the ADC receives the analog signal output from the PGA and completes the conversion from analog to digital encoding. The converted digital data is transmitted to the FPGA via the high-speed serial peripheral interface bus, ensuring real-time transmission of the sampled data. The FPGA buffers, converts, and preprocesses the received ADC data before transmitting the processed sampled data to the data input of the measurement data processing and signal detection module via the parallel data bus, completing the entire process of analog signal acquisition and digitization.

[0035] Table 2. Correspondence between adaptive range switching unit range settings and hardware configurations

[0036] This table defines the full range of the adaptive range switching unit and the corresponding hardware configuration parameters. It clarifies the correspondence between the relay contact state, voltage divider resistor ratio, and programmable gain amplification factor under different input signal ranges. This provides a clear quantitative basis for those skilled in the art to understand the implementation logic of adaptive range switching, and also provides a standardized reference for the system's range configuration and parameter debugging.

[0037] Preferably, the field-programmable gate array (FPGA) internally incorporates a range-adaptive control state machine. The input of this state machine receives sampled data from the analog-to-digital converter (ADC). Based on the amplitude range of the sampled data, the state machine automatically adjusts the channel selection states of the multi-channel analog switch matrix, the contact states of the relay array, and the resistance values ​​of the digital potentiometers, thereby achieving adaptive range switching. When the amplitude of the sampled data remains below a fixed percentage of the current lower range limit, the range-adaptive control state machine automatically switches to a lower range, increasing the signal amplification factor and improving sampling resolution. Conversely, when the amplitude of the sampled data remains above a fixed percentage of the current upper range limit, the range-adaptive control state machine automatically switches to a higher range, reducing the signal voltage division ratio and amplification factor to avoid signal saturation distortion and ensure the accuracy of the sampled data.

[0038] In this embodiment, the opto-isolation circuit, low-pass filter circuit, and level conversion circuit of the signal conditioning unit achieve electrical isolation, interference filtering, and level compatibility of input and output signals, improving the system's operational stability in complex electromagnetic environments in industrial settings. The adaptive range switching unit, with its multi-channel analog switch matrix, relay array, and precision voltage divider resistor network, enables adaptive adjustment of the analog input signal range. Combined with a programmable gain amplifier network and analog-to-digital converter, it achieves high-precision digital conversion of a wide range of analog signals, solving the problem that fixed hardware conditioning circuits cannot adapt to different range sensor signals and enabling dynamic reconstruction of hardware conditioning parameters.

[0039] refer to Figure 3 In another preferred embodiment, the measurement data processing and signal detection module includes a wavelet denoising unit and a multi-scale feature extraction unit. The input of the wavelet denoising unit is connected to the output of the multi-modal I / O acquisition module, and the wavelet denoising unit embeds a wavelet basis function library and a decomposition level configuration register. Specifically, the wavelet denoising unit receives the raw sampled data output from the multi-modal I / O acquisition module, performs wavelet decomposition, thresholding, and wavelet reconstruction on the sampled data, eliminates noise components contained in the sampled data, and retains the effective feature components of the signal. The wavelet basis function library has a variety of commonly used wavelet basis functions pre-set, including Haar wavelets, Daubechies series wavelets, Symlets series wavelets, and Coiflets series wavelets. The corresponding wavelet basis function and decomposition level can be selected according to the type and characteristics of the input signal through the decomposition level configuration register. The configurable range of the decomposition level configuration register meets the denoising processing requirements of different types of signals. The multi-level wavelet decomposition of the sampled signal is achieved through the following formula:

[0040] in, The input is the original sampled signal. The maximum number of wavelet decomposition levels. For the first Approximation coefficients of the layer For the first The scaling function of the layer, For the first The detail factor of the layer, For the first Wavelet basis functions of the layer is the translation factor for the coefficient.

[0041] The wavelet denoising unit's processing flow is as follows: First, the original sampled signal is decomposed into multiple layers using wavelet basis functions to obtain approximation coefficients and detail coefficients for different decomposition layers. Then, the detail coefficients are thresholded using a soft thresholding function, setting detail coefficients below a preset threshold to zero and shrinking those above the preset threshold to eliminate high-frequency detail coefficients corresponding to noise. Finally, wavelet reconstruction is performed on the thresholded approximation coefficients and detail coefficients to obtain the denoised effective signal. The calculation logic of the soft thresholding function is implemented using the following formula: in, The detail coefficients after thresholding. These are the original detail coefficients obtained from wavelet decomposition. The preset threshold, It is a symbolic function.

[0042] The multi-scale feature extraction unit is connected to the output of the wavelet denoising processing unit. The multi-scale feature extraction unit includes a time-domain statistical calculation operator, a frequency-domain fast Fourier transform operator, and a time-frequency domain joint analysis operator. This feature extraction method is suitable for time-frequency feature modeling of signals with material or medium property analysis characteristics, such as optical absorption spectra and electrochemical response curves, providing feature inputs for process analysis based on physicochemical properties. The time-domain statistical calculation operator and the frequency-domain fast Fourier transform operator are connected in parallel to the input channel of the multi-scale feature extraction unit. The outputs of the time-domain statistical calculation operator, the frequency-domain fast Fourier transform operator, and the time-frequency domain joint analysis operator are connected to the feature splicing bus of the multi-scale feature extraction unit. The feature splicing bus is connected to the real-time monitoring and fault diagnosis module. Specifically, the multi-scale feature extraction unit receives the denoised effective signal output by the wavelet denoising processing unit and extracts the signal's feature parameters from different domain spaces through the time-domain statistical calculation operator, the frequency-domain fast Fourier transform operator, and the time-frequency domain joint analysis operator, respectively. The time-domain statistics calculation operator performs statistical calculations on the input time-domain signal, extracting feature parameters including mean, variance, root mean square (RMS), peak value, kurtosis, skewness, margin factor, waveform factor, and impulse factor. The output of the time-domain statistics calculation operator is a one-dimensional time-domain feature vector. The frequency-domain Fast Fourier Transform (FFT) operator performs a Fast Fourier Transform on the input time-domain signal, converting it to a frequency-domain signal. Extracted feature parameters include spectral peak value, peak frequency, centroid frequency, MMS frequency, frequency variance, and spectral kurtosis. The output of the frequency-domain FFT operator is a one-dimensional frequency-domain feature vector. The time-frequency domain joint analysis operator uses wavelet packet transform to perform multi-resolution time-frequency decomposition on the input time-domain signal, obtaining the signal energy distribution characteristics within different frequency bands and time windows. The extracted feature parameters are the energy value and energy percentage of each time-frequency sub-band. The output of the time-frequency domain joint analysis operator is a one-dimensional time-frequency domain feature vector. The time-domain feature vectors output by the time-domain statistics calculation operator, the frequency-domain feature vectors output by the frequency-domain fast Fourier transform operator, and the time-frequency-domain feature vectors output by the time-frequency joint analysis operator are spliced ​​together through a feature splicing bus to form a multi-scale fused feature vector, which is then transmitted to the real-time monitoring and fault diagnosis module.

[0043] Table 3 Comparison of Output Feature Parameters of Multi-Scale Feature Extraction Operators

[0044] This table provides a comprehensive definition of the feature parameters output by various operators in the multi-scale feature extraction unit, clarifying the dimension, calculation method, and corresponding physical meaning of each feature parameter. It provides a quantitative reference for those skilled in the art to understand the implementation logic of multi-scale feature extraction, and also provides a standardized basis for the selection and configuration of feature parameters.

[0045] Furthermore, the multi-scale feature extraction unit also includes an attention-weighted fusion subunit. The input of the attention-weighted fusion subunit is connected to the feature concatenation bus; the attention-weighted fusion subunit includes a fully connected mapping layer, a soft-maximum activation layer, and an element-wise multiplier. The number of input nodes of the fully connected mapping layer matches the bit width of the feature concatenation bus. The output of the fully connected mapping layer is connected to the input of the soft-maximum activation layer, the output of the soft-maximum activation layer is connected to the first input of the element-wise multiplier, the second input of the element-wise multiplier is connected to the data branch of the feature concatenation bus, and the output of the element-wise multiplier forms the fused feature output of the multi-scale feature extraction unit. The fused feature output is connected to the real-time monitoring and fault diagnosis module. Specifically, the attention-weighted fusion subunit receives the multi-scale spliced ​​feature vector output from the feature splicing bus. It then performs a linear mapping on the spliced ​​feature vector through a fully connected mapping layer to obtain the mapping value for each feature dimension. This mapping value is normalized through a soft-maximum activation layer to generate an attention weight coefficient for each feature dimension. The attention weight coefficient is then multiplied with the original spliced ​​feature vector using an element-wise multiplier to obtain the weighted fused feature vector. This fused feature vector is then transmitted to the real-time monitoring and fault diagnosis module through the fused feature output. The calculation logic for the attention weight coefficient is implemented using the following formula:

[0046] in, For the first Attention weight coefficients corresponding to each feature dimension The output of the fully connected mapping layer is the first The mapping values ​​corresponding to each feature dimension This represents the total dimension of the concatenated feature vectors output by the feature concatenation bus. It is a natural exponential function.

[0047] The weighted fused feature vector is calculated using the following formula:

[0048] in, The first eigenvector in the weighted fusion is the eigenvector of ... Feature values ​​in each dimension For the first Attention weight coefficients corresponding to each feature dimension The first element in the original spliced ​​feature vector output by the feature splicing bus is... Feature values ​​in each dimension.

[0049] refer to Figure 4The real-time monitoring and fault diagnosis module includes a time-series sliding window segmentation unit and an abnormal state identification unit. The input of the time-series sliding window segmentation unit is connected to the output of the measurement data processing and signal detection module. The unit contains a window step size register and an overlap register. Specifically, the time-series sliding window segmentation unit receives the fused feature vector and processed time-series signal data output from the measurement data processing and signal detection module. It then segments the time-series data using a sliding window to generate time-series data segments of fixed length. The window step size register configures the step size of each slide of the sliding window, and the overlap register configures the data overlap ratio between two adjacent sliding windows. The window step size and overlap can be dynamically configured according to the signal's sampling frequency and variation characteristics. The window length can also be configured according to the signal's sampling frequency and variation characteristics to meet the segmentation requirements of different types of time-series signals. The time-series sliding window segmentation unit divides the segmented time-series data segments into two output branches. The first output branch outputs to the isolated forest detector of the abnormal state identification unit, and the second output branch outputs to the dynamic time warping matcher of the abnormal state identification unit. The overlap between adjacent sliding windows is calculated using the following formula:

[0050] in, The overlap between adjacent sliding windows. The length of the sliding window. This represents the step size of the sliding window.

[0051] The anomaly detection unit is connected to the output of the time-series sliding window segmentation unit. The anomaly detection unit includes an isolated forest detector and a dynamic time warping matcher. The input of the isolated forest detector is connected to the first output branch of the time-series sliding window segmentation unit, and the input of the dynamic time warping matcher is connected to the second output branch of the time-series sliding window segmentation unit. The outputs of the isolated forest detector and the dynamic time warping matcher are respectively connected to the input of a logic OR gate circuit, and the output of the logic OR gate circuit is connected to the virtual instrument module. Specifically, the isolated forest detector uses an ensemble learning model constructed from multiple isolated trees to detect anomalies in the feature vectors corresponding to the input time-series data segments. The isolated forest detector isolates each sample by randomly partitioning the feature space, resulting in shorter average path lengths for anomalous samples. By calculating the anomaly score of the sample, it determines whether the sample is in an anomalous state. The output of the isolated forest detector is a binary anomaly determination result. When the anomaly score exceeds a preset threshold, a high-level anomaly marker signal is output; otherwise, a low-level normal marker signal is output. The anomaly score of the sample is calculated using the following formula:

[0052] in, For the sample Abnormal scores, This represents the total number of training samples for the isolated forest. For the sample Path length in an isolated tree For the sample The mean path length in all isolated trees. For the sample size The average path length of a binary search tree.

[0053] The dynamic time warping matcher performs dynamic time warping calculations on the input time series data segment and the preset normal state template time series data to obtain the warped distance between the two time series sequences. When the warped distance exceeds a preset distance threshold, the current time series data segment is determined to be in an abnormal state, and a high-level abnormality marker signal is output; otherwise, a low-level normality marker signal is output. The dynamic time warping matcher uses dynamic programming to calculate the optimal matching path between two time series sequences of different lengths, eliminating the influence of time series stretching and offset on the time axis, and improving the accuracy of abnormal state identification. The dynamic time warped distance between two time series sequences is calculated using the following formula:

[0054] in, Time series With time series The dynamic time-warped distance between them The input is the time series data segment to be detected. This is a preset normal state template timing sequence. This represents the normalized path between two time series. To normalize the path length, For the regularized path, the first The Euclidean distance between two sequence elements corresponding to a point.

[0055] The anomaly marker signals output by the isolated forest detector and the dynamic time warping matcher are respectively input to the two inputs of a logic OR gate. The logic OR gate performs a logical OR operation on the two anomaly marker signals. When either detector outputs a high-level anomaly marker signal, the output of the logic OR gate outputs a high-level anomaly state determination signal, which is transmitted to the virtual instrument module. Only when both detectors output low-level normal marker signals does the output of the logic OR gate output a low-level normal state determination signal. By using the parallel OR structure of the two detectors, the coverage of anomaly state identification can be effectively improved, and the probability of missed detection can be reduced.

[0056] In this embodiment, the wavelet denoising unit achieves adaptive denoising of the acquired signal, effectively preserving the effective feature components of the signal and eliminating noise interference. The multi-scale feature extraction unit utilizes time-domain, frequency-domain, and time-frequency domain joint analysis operators to achieve comprehensive extraction of multi-dimensional signal features. Combined with the attention-weighted fusion subunit, adaptive weighted fusion of multi-scale features is completed, unifying the expression dimensions of feature vectors and improving feature discriminability. The time-series sliding window segmentation unit achieves standardized segmentation of the time-series signal. The parallel structure of the isolated forest detector and the dynamic time warping matcher completes dual identification and judgment of abnormal states, improving the accuracy and reliability of abnormal state identification and realizing the dynamic reconstruction and adaptation of the upper-layer feature extraction logic.

[0057] refer to Figure 5 In another preferred embodiment, the virtual instrument module includes a digital twin mapping unit and a dynamic waveform rendering unit. The input of the digital twin mapping unit is connected to the output of the real-time monitoring and fault diagnosis module, and the digital twin mapping unit contains a 3D geometric model library of industrial equipment and a physical pin mapping table. Specifically, the digital twin mapping unit receives real-time signal data, abnormal state identification results, and fault location data output by the real-time monitoring and fault diagnosis module, and completes the digital twin mapping of external industrial equipment through the 3D geometric model library of industrial equipment and the physical pin mapping table. The 3D geometric model library of industrial equipment contains pre-built 3D geometric models of various commonly used industrial equipment, including sensors, actuators, contactors, relays, frequency converters, regulating valves, motors, and PLC modules. Each 3D geometric model contains corresponding geometric structures, material properties, motion constraints, and virtual nodes. The virtual nodes correspond to the physical pins, control ports, and status indicator components of the equipment. The physical pin mapping table stores the correspondence between the physical interface number and pin number of the system's multimodal I / O acquisition module and the virtual node number in the three-dimensional geometric model of the industrial equipment. Through the physical pin mapping table, the real-time signal data and status data acquired by the physical interface can be mapped to the corresponding virtual node, realizing the synchronous mapping between the physical equipment status and the virtual model status.

[0058] Furthermore, the digital twin mapping unit also includes a state synchronization matrix and a delay compensation register set. The row vectors of the state synchronization matrix correspond to the physical pin numbers in the physical pin mapping table, and the column vectors correspond to the virtual node numbers in the industrial equipment 3D geometric model library. Specifically, the state synchronization matrix is ​​a two-dimensional sparse matrix, where each element is a weight representing the mapping relationship between a physical pin and a virtual node. When a mapping relationship exists between a physical pin and a virtual node, the corresponding matrix element has a value of 1; otherwise, it has a value of 0. Through matrix multiplication, the state data vector of the physical pin can be converted into the state data vector of the virtual node, completing the synchronous mapping from physical state to virtual model. The synchronous mapping from physical state to virtual node is achieved using the following formula:

[0059] in, This is the row vector of virtual node state data. This is a row vector of physical pin status data. This is a state synchronization matrix. The number of rows in the matrix is ​​the same as the number of physical pins, and the number of columns is the same as the number of virtual nodes.

[0060] A delay compensation register group is connected in parallel to the data refresh channel of the state synchronization matrix. The delay compensation register group includes a multi-level FIFO buffer and a timestamp calibration counter. The data input of the multi-level FIFO buffer is connected to the output of the real-time monitoring and fault diagnosis module. The clock input of the timestamp calibration counter is connected to an external high-precision clock source. The data output of the multi-level FIFO buffer is connected to the input of the state synchronization matrix, and the output of the state synchronization matrix is ​​connected to the dynamic waveform rendering unit. Specifically, the delay compensation register group is used to eliminate the time delay between physical signal acquisition, data processing, transmission, and virtual model rendering, ensuring the synchronization between physical state changes and virtual model state updates. Before entering the state synchronization matrix, the state data output by the real-time monitoring and fault diagnosis module is first written into the multi-level FIFO buffer for buffering. Each set of state data corresponds to a high-precision timestamp generated by the timestamp calibration counter, whose clock source is an external high-precision temperature-controlled crystal oscillator to ensure timestamp accuracy. The delay compensation register group timestamps the cached state data according to the frame refresh cycle of the dynamic waveform rendering unit, and selects the state data that matches the timestamp of the current rendering frame to output to the state synchronization matrix, thus eliminating the asynchrony problem caused by data transmission delay and rendering delay. The determination logic for timestamp calibration is implemented through the following formula:

[0061] in, The timestamp corresponding to the cached state data. The timestamp corresponding to the current rendered frame. This is the preset timestamp deviation threshold.

[0062] The dynamic waveform rendering unit is connected to the digital twin mapping unit. The dynamic waveform rendering unit includes a graphics rendering engine, a video memory allocation pool, and a frame synchronization controller. The graphics rendering engine preloads oscilloscope and spectrum analyzer controls through the video memory allocation pool. The input of the frame synchronization controller is connected to the status refresh signal of the digital twin mapping unit, and the output of the frame synchronization controller is connected to the rendering trigger of the graphics rendering engine. The video output of the graphics rendering engine is connected to the signal input of the display. Specifically, the graphics rendering engine is built using an industrial-grade graphics rendering library, supporting 2D waveform rendering and 3D model rendering. The video memory allocation pool allocates contiguous high-speed video memory space for the graphics rendering engine to preload rendering resources for virtual instrument controls, texture resources for 3D geometric models, and vertex data. After the rendering resources of the oscilloscope and spectrum analyzer controls are preloaded into the video memory allocation pool, rapid control invocation and rendering can be achieved, reducing rendering latency. The frame synchronization controller receives the status refresh signal output by the digital twin mapping unit. Based on the frequency of the status refresh signal and the preset rendering frame rate, it generates a rendering trigger signal, controlling the graphics rendering engine to complete waveform drawing and 3D model rendering at a fixed frame rate. The frame rate can be configured according to visualization needs to ensure the smoothness of the visualized content. The graphics rendering engine updates the state of the 3D geometric model, including its position, orientation, color, and display status, based on the virtual node status data output by the digital twin mapping unit. Simultaneously, based on real-time signal data, it updates the waveform display of the oscilloscope control and the spectrum display of the spectrum analyzer control, completing the visualization reconstruction of multi-modal I / O signals and fault data. The rendered video data is transmitted to an external monitor through the video output terminal to complete the presentation of the visualized content.

[0063] refer to Figure 6The hierarchical experiment and teaching management module includes a role-based permission resolution unit and an experiment topology dynamic orchestration unit. The role-based permission resolution unit contains a role-based access control matrix and a token generator. Its output connects to the permission verification end of the experiment topology dynamic orchestration unit. Specifically, the role-based permission resolution unit implements hierarchical permission management. The role-based access control matrix pre-configures permission settings for multiple roles, including administrator, teacher, student, and maintenance roles. Each role corresponds to different system operation permissions, module access permissions, and configuration modification permissions. The token generator generates identity tokens for users logging into the system. These tokens contain the user's role and permission information. The role-based permission resolution unit parses and verifies the submitted identity tokens, extracting the user's role and permission information. The verified permission information is then transmitted to the permission verification end of the experiment topology dynamic orchestration unit. Based on the user's permission information, the experiment topology dynamic orchestration unit grants the corresponding operation and configuration permissions and prohibits operations beyond the permitted scope. The calculation logic for the user permission set is implemented using the following formula:

[0064] in, For users The total set of permissions, For users The collection of characters to which they belong For the role The corresponding set of permissions.

[0065] The experimental topology dynamic orchestration unit comprises a topology description file parser and a hardware resource configurator. The topology description file parser receives the externally input experimental topology file, and its output is connected to the hardware resource configurator. The output of the hardware resource configurator is connected to the configuration registers of the multimodal I / O acquisition module, the parameter registers of the measurement data processing and signal detection module, the threshold registers of the real-time monitoring and fault diagnosis module, and the control attribute registers of the virtual instrument module. Specifically, the experimental topology file is a standardized Extensible Markup Language (XML) file or a JSON format file, containing complete topology information including hardware interface configurations, signal processing logic configurations, fault diagnosis parameter configurations, and virtual instrument visualization configurations required for the experiment. The topology description file parser performs lexical analysis, syntactic analysis, and semantic parsing on the input experimental topology file, resolving the topology fields in the file into system-recognizable configuration parameters, which are then transmitted to the hardware resource configurator. The hardware resource configurator writes the parsed configuration parameters into the corresponding module registers. This includes writing interface enable, sampling parameters, and range configuration parameters to the configuration register of the multimodal I / O acquisition module; writing wavelet basis function, decomposition level, and feature extraction operator configuration parameters to the parameter register of the measurement data processing and signal detection module; writing monitoring threshold, anomaly judgment threshold, and fault knowledge base parameters to the threshold register of the real-time monitoring and fault diagnosis module; and writing control call, display parameters, and rendering configuration parameters to the control attribute register of the virtual instrument module. This enables the joint dynamic reconfiguration of system hardware resources and software processing logic.

[0066] Furthermore, the experimental topology dynamic orchestration unit also includes a syntax checker and a hardware address mapping table. The input of the syntax checker is connected to the preprocessing output of the topology description file parser. The syntax checker embeds an abstract syntax tree generation module and a semantic conflict detection state machine. Specifically, after the topology description file parser preprocesses the experimental topology file, it transmits the preprocessed topology data to the syntax checker. The syntax checker's abstract syntax tree generation module constructs an abstract syntax tree for the topology data, converting each configuration item in the topology file into nodes of the abstract syntax tree. The semantic conflict detection state machine traverses and verifies each node of the abstract syntax tree, detecting whether there are syntax errors, semantic conflicts, hardware resource conflicts, or configuration parameter out-of-bounds issues in the topology file, including duplicate configuration of the same hardware interface, configuration parameters exceeding the configurable range of registers, and link conflicts in signal processing logic. When the semantic conflict detection state machine detects an error or conflict, the syntax checker outputs an error identifier and error location information, terminating the topology file parsing process; when the verification passes, the syntax checker outputs a verification pass identifier and transmits the topology data to the post-processing module of the topology description file parser.

[0067] The query interface of the hardware address mapping table connects to the post-processing output of the topology description file parser. The storage array of the hardware address mapping table pre-sets the base address offset of the multi-modal I / O acquisition module and the memory mapping address of the measurement data processing and signal detection module. Specifically, the hardware address mapping table stores the memory mapping addresses and base address offsets corresponding to the configuration registers, parameter registers, and threshold registers of each system module. The post-processing module of the topology description file parser, based on the parsed topology configuration items, queries the physical address of the register corresponding to the configuration item through the query interface of the hardware address mapping table, and transmits the obtained physical address and configuration parameters to the hardware resource configurator. The first output of the hardware resource configurator connects to the output of the syntax checker, and the second output connects to the data output of the hardware address mapping table. The hardware resource configurator directly writes the parsed topology fields into the configuration register of the multi-modal I / O acquisition module, as well as the register addresses of other modules, completing the full-link configuration of the system. The physical address of the target configuration register is calculated using the following formula:

[0068] in, Configure the physical address of the target register. This is the base address of the corresponding module. This is the address offset of the target register within the module.

[0069] Table 4 Role and Permission Configuration Table for the Layered Experiment and Teaching Management Module

[0070] This table comprehensively defines the permission configurations for each role in the hierarchical experiment and teaching management module, clarifying the accessible modules, configurable scope, and data access permissions for different roles. It provides a clear basis for those skilled in the art to understand the hierarchical permission management logic of the system, and also provides a standardized reference for the system's role configuration and permission management.

[0071] In this embodiment, the state synchronization mapping between physical industrial equipment and virtual models is achieved through the industrial equipment 3D geometric model library, physical pin mapping table, and state synchronization matrix of the digital twin mapping unit. This, combined with the delay compensation register group, eliminates the time deviation between physical state changes and virtual model display. The graphics rendering engine, video memory allocation pool, and frame synchronization controller of the dynamic waveform rendering unit enable smooth visualization and reconstruction of multimodal I / O signals and fault data. The role-based permission resolution unit implements hierarchical permission management to meet the operational needs of different roles in teaching and training scenarios. The topology description file parser, hardware resource configurator, syntax checker, and hardware address mapping table of the experimental topology dynamic orchestration unit enable dynamic parsing and verification of experimental topologies and automatic configuration of hardware resources. This completes the joint dynamic reconstruction of the underlying hardware conditioning network and the upper-layer multi-scale feature extraction logic, breaking the limitation of static binding between hardware configuration and algorithm logic in existing technologies.

Claims

1. An I / O signal integrated processing system in an industrial automation control system, characterized in that, It includes a multimodal I / O acquisition module, a measurement data processing and signal detection module, a real-time monitoring and fault diagnosis module, a virtual instrument module, and a hierarchical experiment and teaching management module; The multimodal I / O acquisition module includes a digital input / output interface, an analog input / output interface, and a serial communication interface, which are used to acquire and output multimodal I / O signals from external industrial equipment. The measurement data processing and signal detection module is connected to the multimodal I / O acquisition module and is used to perform filtering, scaling transformation and feature extraction processing on the multimodal I / O signal; The real-time monitoring and fault diagnosis module is connected to the measurement data processing and signal detection module, and is used to receive the processed data and perform abnormal state identification and fault location. The virtual instrument module is connected to the real-time monitoring and fault diagnosis module and is used to call the virtual instrument component to visualize and reconstruct the multimodal I / O signals and fault data. The hierarchical experiment and teaching management module is connected to the multimodal I / O acquisition module, the measurement data processing and signal detection module, the real-time monitoring and fault diagnosis module, and the virtual instrument module, respectively, and is used to issue configuration commands and record interactive data, thus constituting the system.

2. The I / O signal integrated processing system in the industrial automation control system according to claim 1, characterized in that, The multimodal I / O acquisition module also includes a signal conditioning unit and an adaptive range switching unit; The signal conditioning unit is connected to the digital input / output interface, the analog input / output interface and the serial communication interface respectively. The signal conditioning unit includes an opto-isolation circuit, a low-pass filter circuit and a level conversion circuit. The adaptive range switching unit is connected to the analog input / output interface and the signal conditioning unit. The adaptive range switching unit includes a multi-channel analog switch matrix and a relay array. The input terminal of the multi-channel analog switch matrix is ​​connected to the output terminal of the signal conditioning unit, and the output terminal of the multi-channel analog switch matrix is ​​connected to the control terminal of the relay array. The contact terminals of the relay array are connected to a precision voltage divider resistor network with different resistance values ​​to adjust the amplitude of the analog signal input to the measurement data processing and signal detection module.

3. The I / O signal integrated processing system in the industrial automation control system according to claim 1, characterized in that, The measurement data processing and signal detection module includes a wavelet noise reduction unit and a multi-scale feature extraction unit. The input of the wavelet noise reduction processing unit is connected to the output of the multimodal I / O acquisition module, and the wavelet noise reduction processing unit has an embedded wavelet basis function library and a decomposition layer configuration register. The multi-scale feature extraction unit is connected to the output of the wavelet denoising processing unit. The multi-scale feature extraction unit includes a time-domain statistics calculation operator, a frequency-domain fast Fourier transform operator, and a time-frequency domain joint analysis operator. The time-domain statistics calculation operator and the frequency-domain fast Fourier transform operator are connected in parallel to the input channel of the multi-scale feature extraction unit. The outputs of the time-domain statistics calculation operator, the frequency-domain fast Fourier transform operator, and the time-frequency domain joint analysis operator are connected to the feature splicing bus of the multi-scale feature extraction unit. The feature splicing bus is connected to the real-time monitoring and fault diagnosis module.

4. The I / O signal integrated processing system in the industrial automation control system according to claim 1, characterized in that, The real-time monitoring and fault diagnosis module includes a time-series sliding window segmentation unit and an abnormal state identification unit. The input of the time-series sliding window segmentation unit is connected to the output of the measurement data processing and signal detection module. The time-series sliding window segmentation unit is equipped with a window step size register and an overlap register. The abnormal state identification unit is connected to the output of the temporal sliding window segmentation unit, and the abnormal state identification unit includes an isolated forest detector and a dynamic time warping matcher. The input of the isolated forest detector is connected to the first output branch of the time-series sliding window segmentation unit, the input of the dynamic time warping matcher is connected to the second output branch of the time-series sliding window segmentation unit, the outputs of the isolated forest detector and the dynamic time warping matcher are respectively connected to the input of a logic OR gate, and the output of the logic OR gate is connected to the virtual instrument module.

5. The I / O signal integrated processing system in the industrial automation control system according to claim 1, characterized in that, The virtual instrument module includes a digital twin mapping unit and a dynamic waveform rendering unit; The input end of the digital twin mapping unit is connected to the output end of the real-time monitoring and fault diagnosis module. The digital twin mapping unit is equipped with a three-dimensional geometric model library of industrial equipment and a physical pin mapping table. The dynamic waveform rendering unit is connected to the digital twin mapping unit, and the dynamic waveform rendering unit includes a graphics rendering engine, a video memory allocation pool, and a frame synchronization controller. The graphics rendering engine preloads oscilloscope controls and spectrum analyzer controls through the video memory allocation pool. The input of the frame synchronization controller is connected to the status refresh signal of the digital twin mapping unit. The output of the frame synchronization controller is connected to the rendering trigger of the graphics rendering engine. The video output of the graphics rendering engine is connected to the signal input of the display.

6. The I / O signal integrated processing system in the industrial automation control system according to claim 1, characterized in that, The hierarchical experiment and teaching management module includes a role permission resolution unit and an experiment topology dynamic arrangement unit; The role permission parsing unit is equipped with a role-based access control matrix and a token generator. The output of the role permission parsing unit is connected to the permission verification end of the experimental topology dynamic orchestration unit. The experimental topology dynamic orchestration unit includes a topology description file parser and a hardware resource configurator. The topology description file parser receives an externally input experimental topology file at its input end, and its output end is connected to the hardware resource configurator. The output end of the hardware resource configurator is connected to the configuration register of the multimodal I / O acquisition module, the parameter register of the measurement data processing and signal detection module, the threshold register of the real-time monitoring and fault diagnosis module, and the control attribute register of the virtual instrument module, respectively.

7. The I / O signal integrated processing system in the industrial automation control system according to claim 2, characterized in that, The adaptive range switching unit also includes a programmable gain amplifier network and an analog-to-digital converter; The input terminal of the programmable gain amplifier network is connected to the contact terminal of the relay array. The programmable gain amplifier network includes multiple cascaded instrumentation amplifiers and digital potentiometers. The gain control terminal of the multiple cascaded instrumentation amplifiers is connected to the adjustment terminal of the digital potentiometer, and the sliding terminal control interface of the digital potentiometer is connected to the first group of general-purpose input / output pins of the field-programmable gate array. The analog input terminal of the analog-to-digital converter is connected to the output terminal of the programmable gain amplifier network. The digital output terminal of the analog-to-digital converter is connected to the second set of general-purpose input / output pins of the field-programmable gate array (FPGA) via a high-speed serial peripheral interface bus. The parallel data bus of the FPGA is connected to the data input terminal of the measurement data processing and signal detection module.

8. The I / O signal integrated processing system in the industrial automation control system according to claim 3, characterized in that, The multi-scale feature extraction unit also includes an attention-weighted fusion subunit; The input of the attention-weighted fusion subunit is connected to the feature splicing bus; The attention-weighted fusion subunit includes a fully connected mapping layer, a soft maximum activation layer, and an element-wise multiplier. The number of input nodes of the fully connected mapping layer matches the bit width of the feature splicing bus. The output of the fully connected mapping layer is connected to the input of the soft maximum activation layer. The output of the soft maximum activation layer is connected to the first input of the element-wise multiplier. The second input of the element-wise multiplier is connected to the data branch of the feature splicing bus. The output of the element-wise multiplier forms the fused feature output of the multi-scale feature extraction unit. The fused feature output is connected to the real-time monitoring and fault diagnosis module.

9. The I / O signal integrated processing system in the industrial automation control system according to claim 5, characterized in that, The digital twin mapping unit also includes a state synchronization matrix and a delay compensation register group; The row vectors of the state synchronization matrix correspond to the physical pin numbers in the physical pin mapping table, and the column vectors of the state synchronization matrix correspond to the virtual node numbers in the industrial equipment three-dimensional geometric model library. The delay compensation register group is connected in parallel to the data refresh channel of the state synchronization matrix. The delay compensation register group includes a multi-level first-in-first-out buffer and a timestamp calibration counter. The data input terminal of the multi-level FIFO buffer is connected to the output terminal of the real-time monitoring and fault diagnosis module, the clock input terminal of the timestamp calibration counter is connected to an external high-precision clock source, the data output terminal of the multi-level FIFO buffer is connected to the input terminal of the state synchronization matrix, and the output terminal of the state synchronization matrix is ​​connected to the dynamic waveform rendering unit.

10. The I / O signal integrated processing system in the industrial automation control system according to claim 6, characterized in that, The experimental topology dynamic orchestration unit also includes a syntax checker and a hardware address mapping table; The input of the syntax validator is connected to the preprocessing output of the topology description file parser, and the syntax validator embeds an abstract syntax tree generation module and a semantic conflict detection state machine. The query interface of the hardware address mapping table is connected to the post-processing output of the topology description file parser. The storage array of the hardware address mapping table is pre-set with the base address offset of the multi-modal I / O acquisition module and the memory mapping address of the measurement data processing and signal detection module. The first output of the hardware resource configurator is connected to the output of the syntax checker, and the second output of the hardware resource configurator is connected to the data output of the hardware address mapping table. The hardware resource configurator directly writes the parsed topology field into the configuration register of the multimodal I / O acquisition module.

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