A voltage reference circuit
By using a reference circuit composed of a current mirror circuit and an NMOS transistor without amplifiers and transistors, the power consumption and area problems of voltage references in ultra-low power applications are solved, achieving stable voltage output and low-cost circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI LIXIANG TECHNOLOGY CO LTD
- Filing Date
- 2026-05-08
- Publication Date
- 2026-07-14
AI Technical Summary
In existing technologies for ultra-low power applications, the use of amplifiers and transistors leads to additional power consumption and area overhead, makes it difficult to achieve a stable voltage reference, and makes it difficult to determine the appropriate resistor values, thus affecting chip performance.
By employing a design that does not use amplifiers or transistors, a reference voltage is achieved with low power consumption and small area through a positive temperature coefficient current generation circuit and a negative temperature voltage generation circuit, and a reference circuit composed of a current mirror circuit and an NMOS transistor, and the reference voltage is flexibly output.
A low-power and small-area voltage reference circuit was implemented, which can maintain a stable voltage output under temperature changes, reducing the chip's power consumption and footprint.
Smart Images
Figure CN122387261A_ABST
Abstract
Description
Technical Field
[0001] This invention patent relates to the field of analog integrated circuit design, particularly the design of reference voltage circuits. Background Technology
[0002] In integrated circuits, chips face various environmental influences such as manufacturing deviations, temperature variations, and supply voltage fluctuations. In large-scale production and use, chips need to overcome these influences to produce stable functionality. A voltage reference is an integrated circuit design technique that minimizes the impact of manufacturing deviations, operating temperature, and operating voltage, generating a relatively stable voltage to provide a reference for other modules within the chip, thus ensuring stable and reliable performance.
[0003] Figure 1 For existing voltage reference circuits that use operational amplifiers, the additional amplifiers and their voltage biasing circuits bring additional power consumption and area (cost) overhead for ultra-low power (microamp) applications. In fact, the additional power consumption of the amplifiers and their voltage biasing circuits may even exceed that of the core voltage reference circuit itself, which is often not a good choice for ultra-low power applications.
[0004] In addition, the currents in the two branches of the voltage reference circuit can be derived. Where k is the Boltzmann constant, T is the absolute temperature, and q is the unit charge. Under normal circumstances, the value in parentheses in the formula is typically 1.2 volts. For ultra-low power applications, if the system provides a power budget of tens of nanoamps for the voltage reference module, then R3 needs to be in the 100 megaohm range, which is usually difficult or very costly for the chip to achieve. Furthermore, transistors typically occupy a large area in analog circuits.
[0005] For the reasons mentioned above, designing a voltage reference circuit without using amplifiers or transistors is of great practical value in low-power, small-area chip design. Summary of the Invention
[0006] To address the shortcomings of the aforementioned related technologies, this invention proposes a voltage reference circuit that eliminates the need for amplifiers and transistors, thereby further reducing the power consumption and area of the voltage reference. Specifically, this invention provides the following technical solutions.
[0007] A reference voltage circuit includes a positive temperature coefficient current generating circuit and a negative temperature voltage generating circuit.
[0008] The positive temperature coefficient current generating circuit consists of a current mirror circuit and a current source circuit.
[0009] The current mirror circuit consists of a zeroth PMOS transistor, a first PMOS transistor, and a second PMOS transistor. The gates of the three PMOS transistors are connected together, and their sources are connected to the power supply. The gate of the zeroth PMOS transistor is connected to its drain.
[0010] The current source circuit consists of a zeroth NMOS transistor, a first NMOS transistor, and a first resistor. The gates of the zeroth NMOS transistor and the first NMOS transistor are connected together. The source of the zeroth NMOS transistor is connected to ground. The source of the first NMOS transistor is connected to the first resistor. The other end of the first resistor is connected to ground. The gate of the first NMOS transistor is connected to the drain.
[0011] The negative temperature voltage generating circuit is composed of one or more NMOS transistors connected by diodes. When it is composed of multiple NMOS transistors, the connection relationship between the multiple NMOS transistors connected by diodes is in series; where the diodes connected by NMOS refer to the NMOS gate being connected to its drain.
[0012] The zeroth PMOS transistor is connected to the drain of the zeroth NMOS transistor; the first PMOS transistor is connected to the drain of the first NMOS transistor; the second PMOS transistor is connected to one end of the negative temperature voltage generation circuit; the other end of the negative temperature voltage generation circuit is connected to ground.
[0013] The reference voltage is output from the drain of the second PMOS. Attached Figure Description
[0014] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description provided below in conjunction with the accompanying drawings. In the drawings: Figure 1 This is a voltage reference circuit diagram from the prior art; Figure 2 This is a voltage reference circuit diagram provided in Embodiment 1 of the present invention; Figure 3 This is a voltage reference circuit diagram provided in Embodiment 2 of the present invention; Figure 4 This is a voltage reference circuit diagram provided in Embodiment 3 of the present invention.
[0015] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.
[0016] In embodiment 1, this invention provides a voltage reference circuit 100, which includes a current mirror circuit 100A, a current source circuit 100B, and a negative temperature voltage generation circuit 100C. The current mirror circuit 100A includes a zero-threshold PMOS transistor MP0 and a first PMOS transistor MP1. The gates of a second PMOS transistor MP2 are connected together to form the current mirror circuit. The gate of the zero-threshold PMOS transistor MP0 is connected to its drain to generate the bias voltage of the current mirror. The current mirror circuit 100B includes a zero-threshold NMOS transistor MN0 and a first NMOS transistor MN1, a zero-threshold resistor R0, and the gates of the zero-threshold NMOS transistor MN0 and the first NMOS transistor MN1 are connected together. The drain of the zero-threshold NMOS transistor is connected to the drain of the zero-threshold PMOS transistor, and its source is connected to ground. The drain of the first NMOS transistor MN1 is connected to its gate and also connected to the drain of the first PMOS transistor MP1. The source of MN1 is connected to one end of the zero-threshold resistor R0, and the other end of the zero-threshold resistor R0 is connected to ground. Both MN0 and MN1 operate in the subthreshold region, and the width-to-length ratio of MN1 and MN0 is N. The negative temperature coefficient voltage generating circuit 100C includes a second NMOS transistor MN2. The gate of MN2 is connected to the drain, forming a diode connection, and the drain of MN2 is connected to the drain of MP2. The source of MN2 is connected to ground. In this example, the current mirror circuit 100A and the current source circuit 100B constitute a positive temperature voltage (PTV) generating circuit. Its basic principle is as follows: the current mirror circuit 100A forces the two currents in the current source circuit 100B to be completely equal, while MN0 and MN1 of the current source circuit 100B both operate in the subthreshold region. The drain current and the voltages at the three ports have the following relationship: ,in k is Boltzmann's constant, T is the absolute temperature, and q is the unit charge. Gate voltage, Source voltage, The voltage across resistor R0 is the drain voltage. Since the currents in both branches are equal, the voltage across R0 can be calculated as follows: It is easy to obtain the current in the two branches as follows: This generates a positive temperature coefficient current; the negative temperature coefficient voltage generating circuit 100C's MN2 operates in the saturation region, and the relationship between its drain current and gate-drain voltage is as follows: ,in For channel carrier mobility, Where is the gate oxide capacitance density, W is the MN2 channel width, and L is the MN2 channel length. The threshold voltage of MN2; the output reference voltage can be further derived from the above formula. Due to the threshold voltage of the NMOS transistor The overdrive voltage of MN2 decreases as temperature increases. The voltage increases with increasing temperature. With proper parameter design, a voltage reference that changes less with temperature can be obtained.
[0017] Example 2, based on Example 1, the voltage reference circuit 200 in this example further includes a third NMOS transistor MN3; MN3 is diode-connected, its drain is connected to the source of MN2, and the source of MN3 is connected to ground; similar to the derivation process of Example 1, the reference voltage generated in Example 2 can be obtained as follows: .
[0018] In Example 3, based on Example 2, the voltage reference circuit 300 in this example further includes a third NMOS transistor MN4; MN4 is connected as a diode, with its drain connected to the source of MN3, and the source of MN4 connected to ground; Similar to the derivation process in Example 1, the reference voltage generated in Example 3 can be obtained as follows: .
[0019] As can be seen from Examples 1, 2, and 3, the present invention can flexibly output different reference voltages by varying the number of NMOS transistors connected in series.
[0020] Additionally, by designing the threshold voltage of the negative temperature device in Embodiments 1, 2, and 3, the output reference voltage value can be changed. For example, Embodiment 1 can reduce the output reference voltage by using a low threshold voltage NMOS transistor.
[0021] While the embodiments cannot exhaustively list all voltage reference generation circuits, combinations of generating different reference voltage outputs by changing the number of series NMOS transistors in the negative temperature voltage generation circuit of the embodiments and the threshold voltage of the devices in the negative temperature voltage generation circuit are all the contents intended to be protected by this patent.
[0022] It should be noted that the various embodiments described above with reference to the accompanying drawings are only used to illustrate the present invention and not to limit the scope of the present invention. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the present invention.
Claims
1. A voltage reference circuit, characterized in that, The circuit includes a positive temperature coefficient current generating circuit and a negative temperature voltage generating circuit. The positive temperature coefficient current generating circuit includes a current mirror circuit and a current source circuit; the current mirror circuit is composed of a PMOS transistor, and the current source circuit is composed of an NMOS transistor operating in the subthreshold region and a resistor. The negative temperature voltage generating circuit is composed of one or more NMOS transistors connected by diodes.
2. The NMOS transistor constituting the negative temperature voltage generating circuit according to claim 1, characterized in that, The NMOS transistor can be a high threshold voltage NMOS transistor, a normal threshold voltage NMOS transistor, or a low threshold voltage NMOS transistor.
3. The NMOS transistor with multiple diodes connected to form a negative temperature voltage generating circuit according to claim 1, characterized in that, The connection between multiple NMOS transistors is in series.
4. The current source generating circuit according to claim 1, characterized in that, The NMOS transistor with its source connected to a resistor is N times the size of the NMOS transistor with its source connected to ground, where N is an integer greater than one.