High-precision fixed-point complex number analogy circuit and method for pipelined circuits

Abstract

This invention relates to the field of digital signal processing and integrated circuit technology, and provides a pipelined high-precision fixed-point complex modulus calculation circuit and method. After in-depth analysis, reasoning and verification based on the principles of the CORDIC algorithm, a new fixed-point complex modulus calculation circuit logic is improved and designed, which can use simple addition, subtraction and shift operations to replace complex Euclidean norm operations, greatly simplifying the circuit logic structure, thereby significantly reducing the hardware resource consumption of modulus calculation operations, and finally forming a high-efficiency and low-resource-consumption fixed-point modulus calculation operation. Moreover, the circuit supports pipelined operation to ensure calculation speed.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing and integrated circuit technology, and relates to a pipelined high-precision fixed-point complex modulus calculation circuit and method. Background Technology

[0002] In radar signal processing, wireless communication (such as channel estimation and beamforming in 5G / 6G systems), audio and image processing, and various real-time sensor data analysis, complex modulus calculation (i.e., calculating the amplitude |z|=a of the complex number z=a+jb) is crucial. 2 +b 2 (Here, a and b are the real and imaginary parts of the complex number z, respectively) is a fundamental and computationally intensive core operation. For example, calculating the signal spectrum amplitude, detecting the signal envelope, evaluating channel quality, or performing target detection all require fast and continuous modulo operations on a large number of complex sampling points.

[0003] Currently, the main hardware implementation methods for complex modulus calculation are lookup table-based methods: pre-compute a... 2 +b 2 The square root values ​​of all possible combinations are stored. In fixed-point representation, the required storage table grows quadratically when the operand bit width is large. Approximation algorithms and polynomial fitting: These methods approximate the amplitude using the maximum value plus a correction term or a low-order polynomial. These methods are fast and consume fewer resources, but it is difficult to simultaneously achieve high accuracy and low error across the entire input range. These hardware implementation methods, while pursuing high accuracy and high real-time performance, all face the challenge of excessive hardware resource consumption (logic units, multipliers, memory, and computational power consumption).

[0004] Furthermore, in fixed-point implementations, careful handling of the dynamic range and bit width expansion of intermediate steps (especially the sum of squares) is required to prevent overflow and maintain sufficient precision. This further increases the bit width of registers, multipliers, and data paths, consuming more hardware resources. Therefore, existing technologies face a significant contradiction between computational efficiency, resource consumption, and accuracy when dealing with the demands of high throughput, high precision, and low latency in real-time signal processing. An innovative solution is urgently needed that can effectively balance these three aspects and achieve efficient fixed-point complex modulus calculation with limited hardware resources. Summary of the Invention

[0005] To address the problems existing in the above-mentioned traditional methods, this invention proposes a pipelined high-precision fixed-point complex modulus calculation circuit and a pipelined high-precision fixed-point complex modulus calculation method, which can effectively balance computational efficiency, resource consumption and accuracy, and achieve efficient fixed-point complex modulus calculation with limited hardware resources.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a high-precision fixed-point complex modulus calculation circuit is provided, comprising: The data preprocessing module is used to preprocess the input fixed-point complex numbers to ensure that the input fixed-point complex numbers are located in the first quadrant or the fourth quadrant; The sign bit extension module is used to extend the sign bit of the preprocessed fixed-point complex number. If the data of the fixed-point complex number is greater than zero, 2 bits of 0 are added to the highest bit of the data. If the data of the fixed-point complex number is less than zero, 2 bits of 1 are added to the highest bit of the data. The rotation iteration module is used to perform rotation iteration operations on the data after the sign bit has been extended. The final result calculation module is used to right-shift the real part of the input fixed-point complex number based on the bit position of the 1 bit in the binary number corresponding to the quantized micro-rotation modulus compensation factor, and finally add the shifted values ​​to obtain the final modulus result.

[0007] In one embodiment, when preprocessing the input fixed-point complex number, if the sign of the highest bit of the real part of the input fixed-point complex number is 1, the real part is inverted; if the sign of the highest bit of the real part of the input fixed-point complex number is 0, no transformation is required.

[0008] In one embodiment, when performing a rotation iteration operation on the data after sign bit extension, if the first... The imaginary part of the input in the next iteration If the sign of the number is positive, then the first... The result of the next iteration If the first one equals 1, then the second one is equal to 1. The imaginary part of the input in the next iteration If the sign of the number is negative, then the first... The result of the next iteration It equals -1.

[0009] In one embodiment, during the rotation iteration operation, the number of iterations M is equal to the bit width of the input fixed-point complex number minus 2.

[0010] In one embodiment, the micro-rotational modulus compensation factor K = 0.607252935.

[0011] In one embodiment, the circuit for implementing the rotation iteration operation is a cyclic shift butterfly operation unit with a multiplexer, the cyclic shift butterfly operation unit including a first operation branch and a second operation branch; The first operational branch is used to process the... The imaginary part of the input in the next iteration After circularly shifting left by i bits, and then... The real part of the input in the next iteration Adding them together yields the first intermediate result, while simultaneously processing the second intermediate result. The imaginary part of the input in the next iteration After circularly shifting left by i bits, and then... The real part of the input in the next iteration The subtraction yields the second intermediate result. A multiplexer selects one of the first and second intermediate results as the input data for the next stage based on the control signal. The second operational branch is used to process the first... The real part of the input in the next iteration After circularly shifting left by i bits, and then... The imaginary part of the input in the next iteration Adding them together yields the third intermediate result, while simultaneously applying the first... The real part of the input in the next iteration After circularly shifting left by i bits, and then... The imaginary part of the input in the next iteration The subtraction yields the fourth intermediate result. A multiplexer, based on a control signal, selects one of the third and fourth intermediate results as the input data for the next stage. The control signal is the N+1-bit extended result... The imaginary part of the input in the next iteration N is the bit width of the input fixed-point complex number.

[0012] On the other hand, a high-precision fixed-point complex number modulus calculation method is also provided, including the following steps: Preprocess the input fixed-point complex number to ensure that the input fixed-point complex number is located in the first quadrant or the fourth quadrant; The sign bit of the preprocessed fixed-point complex number is extended; if the data of the fixed-point complex number is greater than zero, 2 bits of 0 are extended to the highest bit of the data; if the data of the fixed-point complex number is less than zero, 2 bits of 1 are extended to the highest bit of the data. Perform a rotation iteration operation on the data after the sign bit is extended; Based on the bit position of the binary number corresponding to the quantized micro-rotation modulus compensation factor that is 1, the real part value after the rotation iteration operation is right-shifted, and finally the shifted values ​​are added together to obtain the final modulus value of the input fixed-point complex number.

[0013] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned high-precision fixed-point complex modulus calculation circuit and method, after in-depth analysis, reasoning and verification based on the principles of the CORDIC algorithm, improved the design of a new fixed-point complex modulus calculation circuit logic. This allows it to replace complex Euclidean norm operations with simple addition, subtraction and shift operations, greatly simplifying the circuit logic structure and significantly reducing the hardware resource consumption of modulus calculation operations. Ultimately, this forms a highly efficient and low-resource-consumption fixed-point modulus calculation operation, and the circuit supports pipelined operation to ensure calculation speed. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the module composition of a high-precision fixed-point complex modulus calculation circuit in one embodiment; Figure 2 This is a circuit block diagram of a rotation iteration operation in one embodiment; Figure 3 This is a diagram illustrating the application of a high-precision pipelined fixed-point complex modulus circuit on an FPGA in one embodiment; wherein, Figure 3 (a) is the signal spectrum calculated by the FPGA. Figure 3 (b) is the signal spectrum calculated by MATLAB. Figure 3 (c) Calculate the absolute error for modulus determination; Figure 4 This is a flowchart illustrating a high-precision fixed-point complex number modulus calculation method for pipelined data in one embodiment. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0017] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0018] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0019] In one embodiment, such as Figure 1 As shown, a high-precision fixed-point complex modulus calculation circuit is provided, comprising: The data preprocessing module is used to preprocess the input fixed-point complex numbers to ensure that the input fixed-point complex numbers are located in the first quadrant or the fourth quadrant; The sign bit extension module is used to extend the sign bit of the preprocessed fixed-point complex number. If the data of the fixed-point complex number is greater than zero, 2 bits of 0 are added to the highest bit of the data. If the data of the fixed-point complex number is less than zero, 2 bits of 1 are added to the highest bit of the data. The rotation iteration module is used to perform rotation iteration operations on the data after the sign bit has been extended. The final result calculation module is used to right-shift the real part of the input fixed-point complex number based on the bit position of the 1 bit in the binary number corresponding to the quantized micro-rotation modulus compensation factor, and finally add the shifted values ​​to obtain the final modulus result.

[0020] It is understandable that in order to quickly complete the modulus calculation of fixed-point complex numbers on hardware circuits (such as, but not limited to, FPGA, DSP, or MCU), reduce resource consumption and enable pipelined operation while ensuring accuracy, this embodiment will design a structure suitable for hardware computing based on the principle of CORDIC (Coordinate Rotation Digital Computer) algorithm. The modulus of a fixed-point complex number can be calculated through simple shift and addition operations after N iterations.

[0021] Specifically, the algorithm formula derivation is shown below, with coordinates during the iteration process ( , The transformation of ) satisfies the following equation: ; ; Among them, if ,but ;if ,but Since each micro-rotation causes a change in the vector magnitude, we introduce... Let represent the modulus compensation factor for the i-th micro-rotation. Then, the actual rotation result for the i-th micro-rotation should be: ; ; Depend on and We can obtain the following formula: ; When i approaches infinity, then K Approaching 0.607252935. After n (n≥∞) rotations, we get: ; ; The following derivation of the formula is performed: ; ; ; ; ; ; Therefore, the magnitude of the initial vector is equal to .

[0022] Based on the structure derived from this algorithm formula, this embodiment proposes the following new design method for a pipelined high-precision fixed-point complex modulus circuit.

[0023] First, the input fixed-point complex number is preprocessed. To ensure that subsequent operations are performed correctly, the initial vector must be in the first or fourth quadrant due to the constraint of micro-rotations. This requires... Therefore, due to symmetry, when the initial vector is, for example, located in the second quadrant, the initial vector is moved to the first quadrant.

[0024] When preprocessing the input fixed-point complex number, further steps are taken: if the sign of the highest bit of the real part of the input fixed-point complex number is 1, the real part is inverted; if the sign of the highest bit of the real part of the input fixed-point complex number is 0, no transformation is required.

[0025] Specifically, if the input fixed-point complex number is The bit width is N, corresponding to bits, and the index is [0…N-1]. The real part of the input is then evaluated. The sign of the highest bit is either 0 or 1. If the highest bit is 1, it represents a negative number and needs to be converted to a positive number. The highest bit being 0 indicates a positive number, and no transformation is needed.

[0026] Next, the preprocessed fixed-point complex number undergoes sign extension. This is to ensure the subsequent... and To prevent data overflow during coordinate rotation iteration operations, the input data needs to be processed. Perform sign bit extension on the real part. The most significant bit is extended by 2 bits of '0' to create an N+2-bit width. (Imaginary part) Extend based on its own sign bit, if the imaginary part If the sign bit is negative, then extend it by 2 bits with '1'; if the imaginary part... If the sign bit is positive, then extend it by 2 bits with '0'.

[0027] Then, a rotation iteration operation is performed on the data after the sign bit is extended. The formula for the rotation iteration is: and ,in, Representing the The result of the iteration, the... The imaginary part of the input in the next iteration If the sign of the number is positive, then the result... Equal to 1, the first The imaginary part of the input in the next iteration If the sign of the number is negative, then the result... It equals -1. One possible block diagram of the rotation iteration implementation circuit is as follows: Figure 2 As shown, the number of iterations M can be chosen according to the required precision of the calculation operation. For example, if a precision of B bits is required, then it needs to meet the following conditions: That is, the number of iterations M > B.

[0028] When considering the overhead of hardware resources in engineering applications, we can further select M = data width (N) - 2. For example, if the input fixed point number is 18 bits, 16 rotation iterations are generally sufficient.

[0029] Finally, the final modulus value is calculated. According to the formula... In the formula Indicates the real part after M iterations of the previous rotation. The value of the micro-rotational modulus compensation factor K The value can be set to 0.607252935, because it is a fixed-point complex number, indicating that a fixed-point quantization is required. The upper right corner mark N It is the bit width of the input fixed-point complex number. No multiplication is needed; only the quantized result is required. K The value (in binary) corresponds to the bit position where 1 is, and the real part after M iterations of the previous rotation. value Perform a right shift operation, and then add them together at the end. For example, for... K If the 29th, 27th, and 25th bits of the value after binary quantization are 1, then... Shift the data left by 29, 27, and 25 bits respectively, and then add the three shifted data to obtain the final modulus value.

[0030] The above-mentioned fixed-point complex modulus calculation circuit with high water precision, through in-depth analysis, reasoning and verification based on the principle of the CORDIC algorithm, improves and designs a new fixed-point complex modulus calculation circuit logic, enabling it to use simple addition, subtraction and shift operations to replace complex Euclidean norm ( ), greatly simplifies the circuit logic structure, thereby significantly reducing the hardware resource consumption of the modulus calculation operation, and finally forms an efficient and low-resource-consuming fixed-point modulus calculation operation. Moreover, this circuit supports pipelined operation to ensure the calculation speed. The test results are as Figure 3 shown, Figure 3 (a) is the signal spectrum calculated by FPGA, Figure 3 (b) is the signal spectrum calculated by MATLAB, Figure 3 (c) is the absolute error of the modulus calculation. <00002*205*In some embodiments, as Figure 2 shown, the implementation circuit of the rotation iteration operation is a cyclic shift butterfly operation unit with a multiplexer. The cyclic shift butterfly operation unit includes a first operation branch and a second operation branch. Each operation branch includes a shift addition operation circuit, a shift subtraction operation circuit and a multiplexer mux.

[0032] The first operation branch is used to circularly left-shift the imaginary part input in the i-th iteration by i bits (i.e., <<<i) and add it to the real part input in the i-th iteration to obtain a first intermediate result. At the same time, circularly left-shift the imaginary part input in the i-th iteration by i bits and subtract it from the real part input in the i-th iteration to obtain a second intermediate result. The multiplexer selects one of the first intermediate result and the second intermediate result as the input data for the next stage according to the control signal.

[0033] The second operation branch is used to circularly left-shift the real part input in the i-th iteration by i bits and add it to the imaginary part input in the i-th iteration to obtain a third intermediate result. At the same time, circularly left-shift the real part input in the i-th iteration by i bits and subtract it from the imaginary part input in the i-th iteration to obtain a fourth intermediate result. The multiplexer selects one of the third intermediate result and the fourth intermediate result as the input data for the next stage according to the control signal. The control signal is the It should be noted that there may be an error in the original text where

[0031] is repeated as <00002*205*>. I translated it as it is shown in the original. If this is a misprint, please correct it for a more accurate translation.The imaginary part of the input in the next iteration (Right now N is the bit width of the input fixed-point complex number.

[0034] The circuit design for the above rotation iteration operation uses shifting instead of multiplication: a barrel shifter can complete the cyclic shift of any number of bits within one clock cycle, significantly reducing hardware overhead and latency compared to a general-purpose multiplier; a symmetrical bidirectional structure is adopted: the upper and lower branches respectively use... and As the main component, it implements bidirectional butterfly computation, suitable for parallel processing of complex data (real part / imaginary part corresponds to...). / A multiplexer (Mux) can be configured based on control signals. It can switch between addition and subtraction results to achieve flexible adaptation to different operation modes, and is suitable for efficient configuration and implementation in hardware such as FPGA, DSP or MCU.

[0035] Each circuit module in the aforementioned high-precision fixed-point complex model calculation circuit can be a corresponding existing module circuit in the field. The original corresponding hardware modules can be replaced by the aforementioned high-precision fixed-point complex model calculation circuit, thereby building a new high-precision fixed-point complex model calculation circuit and achieving a comprehensive improvement in computing performance.

[0036] In one embodiment, such as Figure 4 As shown, a high-precision fixed-point complex number modulus calculation method is also provided, including the following steps: S10: Preprocess the input fixed-point complex number to ensure that the input fixed-point complex number is located in the first quadrant or the fourth quadrant. Specifically, for input fixed-point complex numbers that are not in the first quadrant or the fourth quadrant, the real part of the input fixed-point complex number is inverted to transform it to the first quadrant or the fourth quadrant.

[0037] S12, perform sign bit extension on the preprocessed fixed-point complex number; if the data of the fixed-point complex number (whether the imaginary part or the real part) is greater than zero, then extend the highest bit of the data by 2 bits of 0; if the data of the fixed-point complex number is less than zero, then extend the highest bit of the data by 2 bits of 1.

[0038] S14, perform a rotation iteration operation on the data after sign bit extension; the specific number of iterations M can be selected according to the required precision of the actual calculation operation. For example, if the required precision is B bits, then it needs to meet the following conditions: The number of iterations M > B.

[0039] S16. Based on the bit position of the binary number corresponding to the quantized micro-rotation modulus compensation factor that is 1, the real part value after the rotation iteration operation is right-shifted. Finally, the values ​​obtained after shifting are added together to obtain the final modulus value of the input fixed-point complex number.

[0040] Specifically, it is necessary to adjust the micro-rotational modulus compensation factor. K (For example, a value of 0.607252935) N Position-based quantization N That is, the number of bits (i.e., bit width) of the input fixed-point complex number, and then, based on the positions of the 1 bits in the binary number corresponding to the quantized K value, the value of the real part after the rotation iteration operation is... Perform a right shift operation, and finally, calculate the value obtained after the shift. The two numbers are added together to obtain the final modulus of the input fixed-point complex number; where the number of right shifts is the bit position corresponding to the nth bit 1, and n is the number of bits that are 1 in the binary number.

[0041] The aforementioned high-precision fixed-point complex modulus calculation method, after in-depth analysis, reasoning, and verification based on the principles of the CORDIC algorithm, has been improved and designed into a new fixed-point complex modulus calculation circuit logic. This allows it to use simple addition, subtraction, and shift operations to replace complex Euclidean norm operations, greatly simplifying the circuit logic structure and significantly reducing the hardware resource consumption of the modulus calculation operation. Ultimately, this results in a highly efficient and low-resource-consumption fixed-point modulus calculation operation, and the circuit supports pipelining to ensure calculation speed.

[0042] In one embodiment, when preprocessing the input fixed-point complex number, if the sign of the highest bit of the real part of the input fixed-point complex number is 1, the real part is inverted; if the sign of the highest bit of the real part of the input fixed-point complex number is 0, no transformation is required.

[0043] In one embodiment, during the rotation iteration operation on the data after sign bit extension, if the first... The imaginary part of the input in the next iteration If the sign of the number is positive, then the first... The result of the next iteration If the first one equals 1, then the second one is equal to 1. The imaginary part of the input in the next iteration If the sign of the number is negative, then the first... The result of the next iteration It equals -1.

[0044] In one embodiment, in the rotation iteration operation, the number of iterations M is equal to the bit width of the input fixed-point complex number minus 2.

[0045] It is understood that the explanations of the corresponding features in each embodiment of the above-mentioned high-precision fixed-point complex modulus calculation method can be similarly understood by referring to the explanations of the corresponding features in each embodiment of the above-mentioned high-precision fixed-point complex modulus calculation circuit, and will not be repeated here.

[0046] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0047] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A high-precision fixed-point complex modulus calculation circuit, characterized in that, include: The data preprocessing module is used to preprocess the input fixed-point complex number to ensure that the input fixed-point complex number is located in the first quadrant or the fourth quadrant. Specifically, if the sign of the highest bit of the real part of the input fixed-point complex number is 1, the real part is inverted; if the sign of the highest bit of the real part of the input fixed-point complex number is 0, no transformation is required. The sign bit extension module is used to extend the sign bit of the preprocessed fixed-point complex number. If the data of the fixed-point complex number is greater than zero, 2 bits of 0 are added to the highest bit of the data. If the data of the fixed-point complex number is less than zero, 2 bits of 1 are added to the highest bit of the data. The rotation iteration module is used to perform rotation iteration operations on the data after the sign bit extension; where, if the first... The imaginary part of the input in the next iteration If the sign of the number is positive, then the first... The result of the next iteration If the first one equals 1, then the second one is equal to 1. The imaginary part of the input in the next iteration If the sign of the number is negative, then the first... The result of the next iteration Equals -1; The final result calculation module is used to right-shift the real part of the input fixed-point complex number based on the bit position of the 1 bit in the binary number corresponding to the quantized micro-rotation modulus compensation factor, and finally add the shifted values ​​to obtain the final modulus result. The circuit for implementing the rotation iteration operation is a cyclic shift butterfly operation unit with a multiplexer. The cyclic shift butterfly operation unit includes a first operation branch and a second operation branch. The first operational branch is used to process the... The imaginary part of the input in the next iteration After circularly shifting left by i bits, and then... The real part of the input in the next iteration Adding them together yields the first intermediate result, while simultaneously processing the second intermediate result. The imaginary part of the input in the next iteration After circularly shifting left by i bits, and then... The real part of the input in the next iteration The subtraction yields the second intermediate result. A multiplexer selects one of the first and second intermediate results as the input data for the next stage based on the control signal. The second operational branch is used to process the first... The real part of the input in the next iteration After circularly shifting left by i bits, and then... The imaginary part of the input in the next iteration Adding them together yields the third intermediate result, while simultaneously applying the first... The real part of the input in the next iteration After circularly shifting left by i bits, and then... The imaginary part of the input in the next iteration The subtraction yields the fourth intermediate result. A multiplexer, based on a control signal, selects one of the third and fourth intermediate results as the input data for the next stage. The control signal is the N+1-bit extended result... The imaginary part of the input in the next iteration N is the bit width of the input fixed-point complex number.

2. The high-precision fixed-point complex modulus calculation circuit according to claim 1, characterized in that, In the rotation iteration operation, the number of iterations M is equal to the bit width of the input fixed-point complex number minus 2.

3. The high-precision fixed-point complex modulus calculation circuit according to claim 1, characterized in that, The micro-rotational modulus compensation factor K = 0.607252935.

4. A high-precision fixed-point complex number modulus calculation method for continuous flow, characterized in that, Including the following steps: The input fixed-point complex number is preprocessed to ensure that it is located in the first or fourth quadrant. If the sign of the highest bit of the real part of the input fixed-point complex number is 1, the real part is inverted. If the sign of the highest bit of the real part of the input fixed-point complex number is 0, no transformation is required. The sign bit of the preprocessed fixed-point complex number is extended; if the data of the fixed-point complex number is greater than zero, 2 bits of 0 are extended to the highest bit of the data; if the data of the fixed-point complex number is less than zero, 2 bits of 1 are extended to the highest bit of the data. Perform a rotation iteration operation on the data after the sign bit extension; where, if the first... The imaginary part of the input in the next iteration If the sign of the number is positive, then the first... The result of the next iteration If the first one equals 1, then the second one is equal to 1. The imaginary part of the input in the next iteration If the sign of the number is negative, then the first... The result of the next iteration Equals -1; Based on the bit position of the binary number corresponding to the quantized micro-rotation modulus compensation factor that is 1, the real part value after the rotation iteration operation is right-shifted, and finally the shifted values ​​are added together to obtain the final modulus value of the input fixed-point complex number. The circuit for implementing the rotation iteration operation is a cyclic shift butterfly operation unit with a multiplexer. The cyclic shift butterfly operation unit includes a first operation branch and a second operation branch. The first operational branch is used to process the... The imaginary part of the input in the next iteration After circularly shifting left by i bits, and then... The real part of the input in the next iteration Adding them together yields the first intermediate result, while simultaneously processing the second intermediate result. The imaginary part of the input in the next iteration After circularly shifting left by i bits, and then... The real part of the input in the next iteration The subtraction yields the second intermediate result. A multiplexer selects one of the first and second intermediate results as the input data for the next stage based on the control signal. The second operational branch is used to process the first... The real part of the input in the next iteration After circularly shifting left by i bits, and then... The imaginary part of the input in the next iteration Adding them together yields the third intermediate result, while simultaneously applying the first... The real part of the input in the next iteration After circularly shifting left by i bits, and then... The imaginary part of the input in the next iteration The subtraction yields the fourth intermediate result. A multiplexer, based on a control signal, selects one of the third and fourth intermediate results as the input data for the next stage. The control signal is the N+1-bit extended result... The imaginary part of the input in the next iteration N is the bit width of the input fixed-point complex number.

5. The method for high-precision fixed-point complex number modulus calculation in flow-through according to claim 4, characterized in that, In the rotation iteration operation, the number of iterations M is equal to the bit width of the input fixed-point complex number minus 2.

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