A multiply-add fusion system and chip, processor and electronic device for mixed operations

Abstract

The present disclosure relates to the chip technical field, and particularly relates to a kind of multiply-add fusion system for mixed operation, chip, processor and electronic equipment, the system includes: multiplication unit, for the multiplication of floating point operand, obtain the first product result and the second product result not through rounding processing;Operation unit, for the target operation type indicated in operation instruction, the first product result and the second product result are executed with the operation corresponding to the target operation type, obtain intermediate result;Wherein, the operation unit supports the operation of different calculation types, and the operation of different calculation types shares the multiplication unit;Rounding unit, for the rounding processing of intermediate result, obtain operation result.The present disclosure embodiment can effectively reduce the overhead of hardware resources while supporting multiple mixed operation types.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more particularly to a multiply-accumulate fusion system and chip, processor and electronic device for mixed computing. Background Technology

[0002] In fields such as computer graphics processing, digital signal processing, and high-performance computing, fused multiply-add (FMA) is a fundamental and crucial operation. Typically, FMA instructions can complete an operation of a×b+c within a single hardware unit, making it the core hardware foundation for algorithms such as matrix multiplication and convolution.

[0003] In graphics processing, color blending typically requires implementing the operation "current color × current factor op + cached color × cached factor", where "op" can be addition, subtraction, reverse subtraction, maximum or minimum value, etc. For operations like addition, subtraction, and reverse subtraction, the main multiplication and addition function can be implemented using the form a × b + c × d.

[0004] For cases where the op is the maximum or minimum value, it is necessary to first multiply the four input data pairs one by one, and then compare the two product results. In related technologies, while reusing FMA to implement the multiplication of one set of data, an additional multiplication unit is needed to assist in completing the multiplication calculation of another set of data, and then the comparison is performed externally. Since the multiplication unit is the most resource-intensive part of FMA, adding an extra multiplication unit will introduce significant hardware resource consumption.

[0005] Furthermore, when reusing existing multiplication units to implement mixed operations, performing intermediate rounding during the multiplication stage can lead to a decrease in operational precision; introducing additional rounding during the addition stage can affect operational latency. Therefore, how to support multiple mixed operation types while balancing hardware resource consumption, operational precision, and operational latency has become a technical problem that needs to be solved. Summary of the Invention

[0006] In view of this, this disclosure proposes a multiply-accumulate fusion technology for mixed operations.

[0007] According to one aspect of this disclosure, a multiply-accumulate fusion system for mixed operations is provided, comprising:

[0008] The multiplication unit is used to perform multiplication operations on floating-point operands to obtain the first product result and the second product result without rounding.

[0009] The arithmetic unit is configured to perform an operation corresponding to the target operation type on the first product result and the second product result according to the target operation type indicated in the arithmetic instruction, and obtain an intermediate result; wherein, the arithmetic unit supports operations of different calculation types, and the operations of different calculation types share the multiplication unit;

[0010] The rounding unit is used to perform rounding processing on the intermediate results to obtain the calculation result.

[0011] In one possible implementation, the arithmetic unit includes:

[0012] The arithmetic operation module is used to perform arithmetic operations on the first product result and the second product result when the target operation type is an arithmetic operation type, to obtain the intermediate result.

[0013] In one possible implementation, the arithmetic operation module is used for:

[0014] Based on the exponent difference between the first product result and the second product result, the first product result and the second product result are shifted and aligned before being added together to obtain the intermediate result.

[0015] In one possible implementation, the arithmetic unit further includes:

[0016] The first selector is used to select the output of the arithmetic operation module as the data to be processed when the target operation type is an arithmetic operation type; and to select the first product result as the data to be processed when the target operation type is a comparison operation type.

[0017] In one possible implementation, when the target operation type is the comparison operation type, the operation unit controls the input of the arithmetic operation module to be set to zero.

[0018] In one possible implementation, the system further includes:

[0019] The first normalization unit is used to normalize the data to be processed when the target operation type is the arithmetic operation type, and output the first normalization result.

[0020] The second normalization unit is used to normalize the first product result and the second product result respectively when the target operation type is the comparison operation type, and output the second normalization result and the third normalization result.

[0021] In one possible implementation, the arithmetic unit further includes:

[0022] The comparison module is used to compare the second normalization result and the third normalization result according to the comparison operation type when the target operation type is the comparison operation type, so as to obtain a sign comparison result;

[0023] The second selector is configured to output the sign comparison result when the target operation type is the comparison operation type; and to output the sign operation result when the target operation type is the arithmetic operation type.

[0024] A third selector is configured to output the exponent comparison result when the target operation type is the comparison operation type; and to output the exponent operation result when the target operation type is the arithmetic operation type.

[0025] The fourth selector is used to output the mantissa comparison result when the target operation type is the comparison operation type; and to output the mantissa operation result when the target operation type is the arithmetic operation type.

[0026] In one possible implementation, the system is integrated into a graphics processor for performing graphics blending operations, wherein the floating-point operands include color blending operation parameters in graphics processing, and the operation result includes the color blending operation result.

[0027] According to another aspect of this disclosure, a chip is provided that includes the multiply-accumulate fusion system described above.

[0028] According to another aspect of this disclosure, a processor is provided that includes the multiply-accumulate fusion system described above.

[0029] According to another aspect of this disclosure, an electronic device is provided, including the multiply-accumulate fusion system described above.

[0030] In this embodiment, the multiply-accumulate fusion system includes a multiplication unit, an arithmetic unit, and a rounding unit. The multiplication unit performs multiplication on floating-point operands to obtain a first product result and a second product result without rounding. The arithmetic unit performs an operation corresponding to the target operation type indicated in the arithmetic instruction on the first and second product results to obtain an intermediate result. The arithmetic unit supports operations of different calculation types, and these different calculation types share the multiplication unit. The rounding unit performs rounding on the intermediate result to obtain the final result. Therefore, by avoiding intermediate rounding during multiplication by the multiplication unit, precision loss during the multiplication stage is avoided. Simultaneously, the rounding unit performs rounding before the final output, ensuring the accuracy of the result while avoiding the latency overhead of multiple rounding operations. The arithmetic unit performs operations corresponding to the target operation type on the first and second product results according to the target operation type indicated in the arithmetic instruction. The arithmetic unit supports operations of different calculation types, and the multiplication unit is shared by different calculation types. This allows operations of different calculation types, such as summation and comparison, to reuse the same multiplication unit to complete the parallel calculation of the two product results without having to set up separate multiplication units for each calculation type. Thus, while supporting multiple mixed operation types, it effectively reduces the overhead of hardware resources and realizes a high-precision, low-latency, and small-area mixed arithmetic unit.

[0031] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0032] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0033] Figure 1 A block diagram of a multiply-accumulate fusion system for mixed operations according to an embodiment of the present disclosure is shown.

[0034] Figure 2 A block diagram of a multiply-accumulate fusion system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0035] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0036] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0037] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0038] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0039] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0040] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0041] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0042] In scenarios such as graphics processing, digital signal processing, and high-performance computing, fused multiply-add (FMA) is the core hardware foundation for implementing algorithms such as matrix multiplication and convolution. Taking color blending operations in graphics processing as an example, it typically requires multiplying the current color by a factor, multiplying the cached color by a factor, and then performing addition, subtraction, or comparison operations.

[0043] While traditional FMA units can perform the operation a×b+c with a single instruction, they cannot directly support mixed operations requiring four inputs, two multiplications, and then addition. For operations where the op is addition, subtraction, or reverse subtraction, the main multiplication and addition function can be implemented using the form a×b+c×d. However, for operations where the op is the maximum or minimum value, it is necessary to first multiply the four input data pairwise, and then compare the two product results.

[0044] In related technologies, while reusing the FMA (Flexible Multiplication Model) to perform multiplication of one set of data, an additional multiplication unit is needed to assist in the multiplication of another set of data, which is then compared externally. Since the multiplication unit is the most resource-intensive part of the FMA, adding an extra multiplication unit introduces significant hardware resource consumption. Furthermore, when reusing existing multiplication units to implement mixed operations, performing intermediate rounding during the multiplication stage leads to a decrease in computational precision; introducing additional rounding during the addition stage affects computational latency.

[0045] In view of this, this disclosure provides a multiply-accumulate fusion system for mixed operations. This system can perform pairwise multiplication of four data points within a single module without rounding the results. Based on the target operation type indicated in the input operation instruction (e.g., arithmetic or comparison operation), it performs the corresponding operation on the two product results. Different types of operations share the same multiplication unit, requiring only a small amount of additional logic to implement maximum and minimum value operations and the necessary intermediate information. Furthermore, rounding is performed only once before the final output, resulting in a high-precision, low-latency, and small-area mixed operation unit. The multiply-accumulate fusion system provided by this disclosure will be described in detail below with reference to the accompanying drawings.

[0046] Figure 1 A block diagram of a multiply-accumulate fusion system for mixed operations according to an embodiment of the present disclosure is shown. Figure 1 As shown, the system includes:

[0047] Multiplication unit 11 is used to perform multiplication operations on floating-point operands to obtain the first product result and the second product result without rounding.

[0048] The arithmetic unit 12 is used to perform an operation corresponding to the target operation type on the first product result and the second product result according to the target operation type indicated in the arithmetic instruction, so as to obtain an intermediate result; wherein, the arithmetic unit 12 supports operations of different calculation types, and the operations of different calculation types share the multiplication unit 11.

[0049] The rounding unit 13 is used to perform rounding processing on the intermediate results to obtain the calculation results.

[0050] This disclosure provides a multiply-accumulate fusion system for mixed-operation computation. This system can be applied to hardware platforms requiring floating-point operations, such as graphics processing units (GPUs), digital signal processors (DSPs), or central processing units (CPUs). The system can be used to perform multiply-accumulate fusion operations on multiple floating-point operands.

[0051] In one application scenario, such as color mixing in graphics processing, the system can receive four floating-point operands (e.g., current color value, current color factor, cached color value, and cached color factor), perform pairwise multiplication, and then perform arithmetic or comparison operations to output the mixed color result.

[0052] Multiplication unit 11 performs multiplication operations on floating-point operands to obtain a first product result and a second product result without rounding. Floating-point operands can be input data that requires mixing operations. In terms of type, floating-point operands can include floating-point numbers of various precisions, such as single-precision, half-precision, or double-precision floating-point numbers. In terms of source, floating-point operands can include color mixing operation parameters in graphics processing, filtering coefficients in digital signal processing, etc. For example, in a color mixing scenario in graphics processing, floating-point operands can include the current color value, the current color factor, a cached color value, and a cached color factor.

[0053] Multiplication unit 11 can perform grouped multiplication operations on multiple floating-point operands. In some possible implementations, multiplication unit 11 can receive four floating-point operands, multiply two of them to obtain a first product, and multiply the other two to obtain a second product. For example, multiplication unit 11 can perform a multiplication operation on the first floating-point operand and the second floating-point operand to obtain the first product; and perform a multiplication operation on the third floating-point operand and the fourth floating-point operand to obtain the second product.

[0054] Multiplication unit 11 does not round the product result when performing multiplication. That is, when multiplication unit 11 outputs the first and second product results, it retains the full product bit width without any truncation or rounding. Taking single-precision floating-point numbers (FP32) as an example, the mantissa (including implicit bits) of each floating-point operand is 24 bits. After multiplication unit 11 performs a 24-bit multiplication operation, it obtains a 48-bit product result. This 48-bit product result can be output as is without intermediate rounding. This setting helps avoid precision loss during the multiplication stage, thereby improving the accuracy of the final calculation result.

[0055] The arithmetic unit 12 is connected to the multiplication unit 11 and is used to receive the first and second product results output by the multiplication unit 11. The arithmetic unit 12 can perform operations corresponding to the target operation type indicated in the arithmetic instruction on the first and second product results to obtain intermediate results. Furthermore, the arithmetic unit 12 supports operations of different calculation types (e.g., arithmetic operations and comparison operations), and these different calculation types can share the same multiplication unit 11. That is, whether it is an arithmetic operation or a comparison operation, the two product results generated by the multiplication unit 11 can be reused, eliminating the need to set up separate multiplication units for each operation type, thereby reducing the overall hardware resource overhead.

[0056] The operation instruction can be a control signal indicating what type of mixed operation needs to be performed. The target operation type can include arithmetic operation type and comparison operation type. For example, the arithmetic operation type can include addition operation, subtraction operation, or reverse subtraction operation; the comparison operation type can include maximum value operation or minimum value operation. In a specific example, when the operation instruction indicates to perform an addition operation, the operation unit 12 can perform an addition operation on the first product result and the second product result, and obtain a sum result as an intermediate result. In another example, when the operation instruction indicates to perform a maximum value operation, the operation unit 12 can compare the size of the first product result and the second product result, and select the larger value as the intermediate result. The specific implementation of the operation unit 12 will be described in detail below, and will not be elaborated here.

[0057] The rounding unit 13 is connected to the arithmetic unit 12 and is used to receive the intermediate results output by the arithmetic unit 12 and perform rounding processing on the intermediate results to obtain the final arithmetic result.

[0058] The rounding unit 13 can perform mantissa rounding and exponent adjustment on intermediate results according to a preset rounding mode. The rounding mode can include various types. For example, the rounding mode can include a round-to-zero mode, which directly truncates the mantissa exceeding the target precision. In one example, the rounding mode can include a round-to-nearest even number mode, which generates a carry based on the values ​​of the guard bit, round bit, and sticky bit, rounding the result to the nearest floating-point value. After performing rounding processing on the intermediate results, the rounding unit 13 outputs the final calculation result conforming to the floating-point representation format.

[0059] Since the multiplication unit 11 does not round the product result during multiplication, and the arithmetic unit 12 does not perform intermediate rounding during arithmetic or comparison operations, the rounding unit 13 only performs rounding once on the final result. In other words, the entire multiply-accumulate fusion system performs a rounding operation only once in the final stage, from receiving floating-point operands to outputting the result. This helps reduce the precision loss that may result from multiple rounding operations and also reduces the computational latency caused by multiple rounding operations, thereby improving computational accuracy and reducing computational latency.

[0060] In this embodiment, the multiply-accumulate fusion system includes a multiplication unit, an arithmetic unit, and a rounding unit. The multiplication unit performs multiplication on floating-point operands to obtain a first product result and a second product result without rounding. The arithmetic unit performs an operation corresponding to the target operation type indicated in the arithmetic instruction on the first and second product results to obtain an intermediate result. The arithmetic unit supports operations of different calculation types, and these different calculation types share the multiplication unit. The rounding unit performs rounding on the intermediate result to obtain the final result. Therefore, by avoiding intermediate rounding during multiplication by the multiplication unit, precision loss during the multiplication stage is avoided. Simultaneously, the rounding unit performs rounding before the final output, ensuring the accuracy of the result while avoiding the latency overhead of multiple rounding operations. The arithmetic unit performs operations corresponding to the target operation type on the first and second product results according to the target operation type indicated in the arithmetic instruction. The arithmetic unit supports operations of different calculation types, and the multiplication unit is shared by different calculation types. This allows operations of different calculation types, such as summation and comparison, to reuse the same multiplication unit to complete the parallel calculation of the two product results without having to set up separate multiplication units for each calculation type. Thus, while supporting multiple mixed operation types, it effectively reduces the overhead of hardware resources and realizes a high-precision, low-latency, and small-area mixed arithmetic unit.

[0061] In one possible implementation, the arithmetic unit includes:

[0062] The arithmetic operation module is used to perform arithmetic operations on the first product result and the second product result when the target operation type is an arithmetic operation type, to obtain the intermediate result.

[0063] The arithmetic unit is a functional module that performs subsequent operations on the product result output by the multiplication unit. The arithmetic unit can contain various arithmetic submodules to accommodate different operation types indicated by different arithmetic instructions. The arithmetic operation module is the submodule within the arithmetic unit used to perform arithmetic operations.

[0064] In terms of functional scope, arithmetic operations can encompass a variety of specific operation types. For example, arithmetic operations can include at least one of addition, subtraction, or reverse subtraction.

[0065] In a specific scenario, such as color mixing in graphics processing, it is necessary to add the result of multiplying the current color by a factor to the result of multiplying the cached color by a factor. In this case, the arithmetic operation module can perform an addition operation. In another example, it is necessary to subtract the result of multiplying the current color by a factor from the result of multiplying the cached color by a factor. In this case, the arithmetic operation module can perform a subtraction operation. In yet another example, it is necessary to subtract the result of multiplying the cached color by a factor from the result of multiplying the current color by a factor. In this case, the arithmetic operation module can perform a reverse subtraction operation. It is understood that subtraction or reverse subtraction can be achieved by inverting one product result and then adding it to the other product result. This disclosure does not limit this.

[0066] The target operation type can be the category of operation to be performed, as indicated in the operation instruction. The target operation type can include arithmetic operation types and comparison operation types. The arithmetic operation type is the type identifier that instructs the arithmetic operation module to perform arithmetic operations. When the target operation type indicated in the operation instruction is an arithmetic operation type, the arithmetic operation module is enabled.

[0067] When performing arithmetic operations, the arithmetic operation module can perform corresponding arithmetic operations on the first and second product results. The first product result can be the output of the multiplication unit after performing multiplication on the first set of floating-point operands. For example, in a scenario with four floating-point operands, the first product result can be the product of the first and second floating-point operands. The second product result can be the output of the multiplication unit after performing multiplication on the second set of floating-point operands. For example, in a scenario with four floating-point operands, the second product result can be the product of the third and fourth floating-point operands.

[0068] When the target operation type indicated in the operation instruction is an arithmetic operation, the arithmetic operation module can receive the first and second product results from the multiplication unit and perform arithmetic operations (e.g., adding the two product results, or inverting one product result and adding it to another to perform subtraction). The result obtained after the operation is provided as an intermediate result to the subsequent rounding unit for processing. The arithmetic operation module does not perform intermediate rounding when performing arithmetic operations, so that the rounding unit can perform rounding processing on the final result in one go. This helps to ensure the accuracy of the operation and reduce latency.

[0069] In this embodiment, the arithmetic unit includes an arithmetic operation module. This module performs arithmetic operations on the first and second product results to obtain the intermediate result when the target operation type is an arithmetic operation. Therefore, by including an arithmetic operation module in the arithmetic unit, when the target operation type indicated in the arithmetic instruction is an arithmetic operation, the module can directly perform arithmetic operations (e.g., addition, subtraction, or reverse subtraction) on the first and second product results output by the multiplication unit, without needing to allocate additional multiplication resources separately for arithmetic operations. Furthermore, the arithmetic operation module is only enabled under arithmetic operation types and can be idled or set to zero under comparison operation types. This allows arithmetic and comparison operation types to reuse the same set of multiplication units and subsequent processing resources (such as rounding units), thereby reducing the overall hardware resource overhead and maintaining consistent computational accuracy.

[0070] In one possible implementation, the arithmetic operation module is used for:

[0071] Based on the exponent difference between the first product result and the second product result, the first product result and the second product result are shifted and aligned before being added together to obtain the intermediate result.

[0072] The exponent difference can be the difference between the exponent values ​​corresponding to the two product results. In floating-point arithmetic, each floating-point operand can be split into a sign bit, an exponent bit, and a mantissa bit. After the multiplication unit performs a multiplication operation on two sets of floating-point operands, the output first product result and the second product result can each contain the corresponding exponent information. For example, the multiplication unit can perform an addition operation on the exponents of the first and second floating-point operands to obtain the exponent sum corresponding to the first product result; and perform an addition operation on the exponents of the third and fourth floating-point operands to obtain the exponent sum corresponding to the second product result. The arithmetic operation module can obtain these two exponent sums and calculate the difference between them, which is the exponent difference.

[0073] Shift alignment adjusts the mantissas of two product results to the same order of magnitude for addition. Since the first and second product results may correspond to different exponent values, directly adding their mantissas can lead to errors. The arithmetic module can determine which product result has the smaller exponent based on the calculated difference in exponents. The module then shifts the mantissa of the product result with the smaller exponent to the right by an amount equal to the absolute value of the exponent difference, aligning its mantissa with that of the product result with the larger exponent. After shift alignment, the mantissas of the two product results are on the same order of magnitude, allowing addition to be performed.

[0074] In a specific example, suppose the sum of the exponents of the first product is 10, and the sum of the exponents of the second product is 8, then the difference in exponents is 2. The arithmetic module can determine that the exponent of the second product is smaller, so it shifts the mantissa of the second product two bits to the right to align it with the mantissa of the first product. After the shift is complete, the arithmetic module can perform an addition operation between the mantissa of the first product and the mantissa of the shifted second product to obtain an intermediate result.

[0075] In some possible implementations, the arithmetic module can also retain extra bits overflowed during the shift alignment process. For example, one overflow bit can be retained to handle carry-overs that may occur during addition. This setting helps to make the addition result more accurate, thus facilitating subsequent normalization processing.

[0076] In this embodiment, the arithmetic operation module is used to: shift and align the first product result and the second product result according to the exponent difference corresponding to the first product result and the second product result, and then add them to obtain the intermediate result. Thus, by calculating the exponent difference and shifting and aligning the mantissa of the product result according to the exponent difference, the arithmetic operation module can adjust two product results with different exponent orders of magnitude to the same order of magnitude before performing the addition operation, which helps reduce the precision loss that may be caused by exponent misalignment, thereby improving the precision of arithmetic operations. At the same time, by retaining the overflow bit during the shifting process, the accuracy of the addition result can be further guaranteed, providing more accurate intermediate data for subsequent normalization and rounding.

[0077] In one possible implementation, the arithmetic unit further includes:

[0078] The first selector is used to select the output of the arithmetic operation module as the data to be processed when the target operation type is an arithmetic operation type; and to select the first product result as the data to be processed when the target operation type is a comparison operation type.

[0079] The first selector can be a data path switching module used to select one output from multiple input data sources to a downstream processing unit based on a control signal. In some possible implementations, the first selector can be a multiplexer (MUX), whose inputs can be connected to the output of an arithmetic operation module or the output of the first product result from a multiplication unit, and whose output can be connected to a subsequent processing unit (e.g., a normalization unit). Its control terminal can receive operation instructions or control signals generated based on operation instructions. Functionally, the first selector's role is to select appropriate data for different operation types and send it to the subsequent processing flow.

[0080] The target operation type can be the category of operation to be performed as indicated in the operation instruction. The target operation type can include arithmetic operation types and comparison operation types. Arithmetic operation types can cover addition, subtraction, or reverse subtraction, etc.; comparison operation types can cover maximum value operations or minimum value operations, etc. The data to be processed can be the data output by the first selector to the downstream processing unit for subsequent operations. The data to be processed can be the arithmetic operation result output by the arithmetic operation module, or the first product result output by the multiplication unit, depending on the current target operation type.

[0081] When the target operation type indicated in the operation instruction is an arithmetic operation, the first selector can choose the output of the arithmetic operation module as the data to be processed. That is, when arithmetic operations such as addition, subtraction, or reverse subtraction are required, and the arithmetic operation module has already performed arithmetic operations on the first and second product results and output the results, the first selector can pass this result to a downstream processing unit (e.g., the first normalization unit) for subsequent normalization and rounding. This configuration allows the arithmetic operation results to directly enter the subsequent processing flow.

[0082] When the target operation type indicated in the operation instruction is a comparison operation, the first selector can choose the first product result as the data to be processed. That is, when a maximum or minimum value operation is required, the output of the arithmetic operation module is not needed; instead, the two product results need to be normalized separately before comparison. The first selector selects the first product result as the data to be processed and passes it to the downstream processing unit for normalization. Simultaneously, the second product result can be normalized via another path (e.g., a second normalization unit). The advantage of this setup is that, under comparison operation types, the first selector can send the first product result to the first normalization unit (e.g., the existing normalization path), while the second product result is processed through the second normalization unit (e.g., a newly added normalization path), thereby achieving parallel normalization processing of the two product results and reducing computational latency.

[0083] In this embodiment, the computation unit further includes a first selector. The first selector is used to select the output of the arithmetic operation module as the data to be processed when the target operation type is an arithmetic operation; and to select the first product result as the data to be processed when the target operation type is a comparison operation. Thus, by selecting the data source according to the target operation type using the first selector, the computation unit can flexibly switch data paths under different operation types, passing data that meets the current computational requirements to subsequent processing units. Under the arithmetic operation type, the operation result of the arithmetic operation module is selected for subsequent processing; under the comparison operation type, the first product result is selected for the normalization path and processed in parallel with the second product result. This data path switching mechanism allows the same set of normalization, rounding, and other subsequent processing resources to be reused for different operation types, eliminating the need to set up independent processing paths for different operation types, thereby reducing the overall hardware resource overhead.

[0084] In one possible implementation, when the target operation type is the comparison operation type, the operation unit controls the input of the arithmetic operation module to be set to zero.

[0085] The target operation type can be the category of operation to be performed as indicated in the operation instruction. The target operation type can include arithmetic operation types and comparison operation types. Comparison operation types can include maximum value operations or minimum value operations. In this case, the arithmetic operation function of the arithmetic operation module may not be needed, because the comparison operation type only needs to compare the results of two products without performing arithmetic operations on them.

[0086] The arithmetic unit, as the core module in the multiply-accumulate fusion system for performing operations, may contain control logic. This control logic can generate corresponding zero-set control signals based on the arithmetic instructions. When the target operation type indicated in the arithmetic instruction is a comparison operation, the control logic inside the arithmetic unit can recognize this situation and generate a zero-set control signal, which is transmitted to the arithmetic operation module to set the input port of the arithmetic operation module to a logic zero value.

[0087] The inputs to the arithmetic operation module can include a first product result and a second product result. In comparison operation types, the operation unit can force these two input ports of the arithmetic operation module to zero using a zero-set control signal. This setting ensures that the circuit nodes inside the arithmetic operation module maintain a fixed voltage level, preventing unnecessary switching.

[0088] The zeroing operation can be implemented in several ways. In some possible implementations, a data selection circuit can be set in the input path of the arithmetic operation module. For example, a 2-to-1 data selector can be set before each input port of the arithmetic operation module. One input of this data selector can receive the product result output by the multiplication unit, and the other input can be grounded or connected to a zero value. When the target operation type indicated in the operation instruction is a comparison operation type, the operation unit can control these data selectors to select the zero value input terminal, thereby sending the zero value to the arithmetic operation module. When the target operation type indicated in the operation instruction is an arithmetic operation type, the operation unit can control these data selectors to select the product result input terminal, enabling the arithmetic operation module to normally receive the first and second product results.

[0089] In some possible implementations, the zeroing operation can be achieved by the enable control within the arithmetic operation module. For example, the arithmetic operation module can be configured with an enable input terminal. When the enable signal is valid, the arithmetic operation module can normally receive input data and perform arithmetic operations; when the enable signal is invalid, the arithmetic operation module can set its internal circuitry to a fixed state and not perform actual arithmetic operations. The operation unit can generate an enable signal according to the operation instruction, and in comparison operation types, set the enable signal to an invalid state, thereby equivalently achieving the effect of zeroing the input.

[0090] By setting the input of the arithmetic operation module to zero, unnecessary circuit switching is avoided during comparison operations, thus reducing dynamic power consumption. Simultaneously, since the input of the arithmetic operation module is fixed at zero, its output remains stable, reducing potential interference to subsequent comparison operations.

[0091] In this embodiment of the disclosure, when the target operation type is the comparison operation type, the operation unit controls the input of the arithmetic operation module to be set to zero. Therefore, by setting the input of the arithmetic operation module to zero under the comparison operation type, it is beneficial to reduce unnecessary circuit switching generated by the arithmetic operation module under this operation type, thereby reducing the dynamic power consumption of the system. Simultaneously, since the output of the arithmetic operation module can remain stable, it is beneficial to reduce interference to the comparison operation under the comparison operation type, thereby ensuring the correctness of the calculation result.

[0092] In one possible implementation, the system further includes:

[0093] The first normalization unit is used to normalize the data to be processed when the target operation type is the arithmetic operation type, and output the first normalization result.

[0094] The second normalization unit is used to normalize the first product result and the second product result respectively when the target operation type is the comparison operation type, and output the second normalization result and the third normalization result.

[0095] Both the first and second normalization units are normalization units, which are processing modules used to adjust intermediate results of floating-point operations to conform to the standard floating-point representation. In floating-point operations, normalization ensures that the mantissa portion meets the requirement that the highest bit is 1, thereby guaranteeing the accuracy of the floating-point representation and the correctness of subsequent operations. The normalization unit may include functional submodules such as leading zero detection, left shift operation, and exponent adjustment.

[0096] The first normalization unit is used to normalize the data to be processed when the target operation type is an arithmetic operation, and outputs a first normalization result. The data to be processed can be the data output after being selected by the first selector. For example, under the arithmetic operation type, the first selector can select the output of the arithmetic operation module as the data to be processed. The data to be processed can be the arithmetic operation result obtained by passing the product of two products output by the multiplication unit through the arithmetic operation module (e.g., performing an addition operation). At this time, the arithmetic operation result may not yet meet the normalization representation requirements of floating-point numbers. The first normalization unit can perform normalization processing on the data to be processed, adjust it to conform to the form of floating-point representation, and output the first normalization result.

[0097] The second normalization unit can be used to normalize the first product result and the second product result respectively when the target operation type is a comparison operation, and output the second normalized result and the third normalized result. The first product result can be the result output by the multiplication unit after performing multiplication on the first set of floating-point operands, and the second product result can be the result output by the multiplication unit after performing multiplication on the second set of floating-point operands. Under the comparison operation type, the first product result and the second product result can directly participate in the comparison operation without going through the arithmetic processing of the arithmetic operation module. The second normalization unit can receive the first product result and the second product result respectively, perform normalization processing on each of the two product results, and output the second normalized result and the third normalized result.

[0098] In a specific example, taking a single-precision floating-point number, the product output by the multiplication unit can include a 48-bit mantissa and the corresponding exponent information. The normalization unit can perform leading zero detection on the mantissa, counting the number of zeros before the most significant 1 in the mantissa, and then shift the mantissa to the left by the number of leading zeros, making the most significant bit of the mantissa 1. Simultaneously, the normalization unit can subtract the shifted number from the exponent to maintain the floating-point value. After this processing, the output normalized result meets the requirements for normalized floating-point representation.

[0099] The first and second normalization units can be independent modules in terms of hardware structure, or they can share some circuit resources. In some possible implementations, the first normalization unit can be the original normalization path of the FMA, used to process the output of the arithmetic operation module or the first product result; the second normalization unit can be a new normalization path added in addition to the original normalization path of the FMA, specifically used to process the second product result. By setting up two sets of normalization units, the normalization processing under arithmetic operation type and comparison operation type can be performed in parallel, which helps to reduce computational latency.

[0100] In this embodiment, the system further includes a first normalization unit and a second normalization unit. The first normalization unit is used to normalize the data to be processed when the target operation type is the arithmetic operation type, and output a first normalization result. The second normalization unit is used to normalize the first product result and the second product result respectively when the target operation type is the comparison operation type, and output a second normalization result and a third normalization result. Therefore, by configuring normalization units for different operation types, the output of the arithmetic operation module (i.e., the data to be processed) can be normalized under the arithmetic operation type, and the two product results can be normalized separately under the comparison operation type. This ensures that the data under different operation types meets the normalization requirements before entering the comparison module, which helps guarantee the accuracy of subsequent calculations. Simultaneously, the two normalization units can work in parallel, which helps reduce overall computational latency.

[0101] In one possible implementation, the arithmetic unit further includes:

[0102] The comparison module is used to compare the second normalization result and the third normalization result according to the comparison operation type when the target operation type is the comparison operation type, so as to obtain a sign comparison result;

[0103] The second selector is configured to output the sign comparison result when the target operation type is the comparison operation type; and to output the sign operation result when the target operation type is the arithmetic operation type.

[0104] A third selector is configured to output the exponent comparison result when the target operation type is the comparison operation type; and to output the exponent operation result when the target operation type is the arithmetic operation type.

[0105] The fourth selector is used to output the mantissa comparison result when the target operation type is the comparison operation type; and to output the mantissa operation result when the target operation type is the arithmetic operation type.

[0106] The comparison module, second selector, third selector, and fourth selector can work together to output corresponding results under different operation types. Specifically, under comparison operation types, they can output the comparison result, and under arithmetic operation types, they can output the corresponding part of the normalized result.

[0107] The comparison module, when the target operation type is a comparison operation, compares the second and third normalized results according to the comparison operation type indicated in the operation instruction (e.g., maximum or minimum value operation) to obtain a signed comparison result. The second normalized result can be understood as the output of the first product result after processing by the second normalization unit, and the third normalized result can be understood as the output of the second product result after processing by the second normalization unit. Under the comparison operation type, the operation instruction can indicate whether a maximum or minimum value operation needs to be performed, and the comparison module can compare the two normalized results according to the comparison rules for floating-point numbers. Floating-point number comparisons can be performed step-by-step in the order of sign bit, exponent bit, and mantissa bit. The comparison module can first compare the sign bits of the two normalized results to obtain a signed comparison result. This signed comparison result represents the relationship between the sign bits of the two normalized results.

[0108] The second selector can be used to output the sign comparison result when the target operation type is a comparison operation, and to output the sign operation result from the first normalized result when the target operation type is an arithmetic operation. The second selector can be a 2-to-1 multiplexer, whose inputs can include the sign comparison result output by the comparison module and the sign operation result from the first normalized result. When the target operation type indicated in the operation instruction is a comparison operation, the second selector can choose to output the sign comparison result, which can be used to indicate the comparison of the sign bits between the two normalized results. When the target operation type indicated in the operation instruction is an arithmetic operation, the second selector can choose to output the sign operation result from the first normalized result, which can be the floating-point sign bit output after processing by the first normalization unit. For example, in the arithmetic operation type, when the system performs an arithmetic operation (e.g., addition), the first normalized result is a complete floating-point number containing a sign bit, exponent bit, and mantissa bit; the second selector can extract and output the sign bit.

[0109] The third selector can be used to output the exponent comparison result when the target operation type is a comparison operation, and to output the exponent operation result from the first normalization result when the target operation type is an arithmetic operation. The third selector can also be a 2-to-1 multiplexer, whose input can include the exponent comparison result output by the comparison module and the exponent operation result from the first normalization result. In the comparison operation type, after the comparison module completes the sign bit comparison, if the sign bits are the same, it can continue to compare the exponent bits of the two normalization results to produce an exponent comparison result. The third selector can choose to output this exponent comparison result, which can indicate the size relationship of the exponent bits between the two normalization results. In the arithmetic operation type, the third selector can choose to output the exponent operation result from the first normalization result, that is, the floating-point exponent bits output after processing by the first normalization unit.

[0110] The fourth selector can be used to output the mantissa comparison result when the target operation type is a comparison operation, and to output the mantissa operation result from the first normalized result when the target operation type is an arithmetic operation. The fourth selector can be a 2-to-1 multiplexer, and its input can include the mantissa comparison result output by the comparison module and the mantissa operation result from the first normalized result. In the comparison operation type, after the comparison module completes the comparison of the sign bit and exponent bit, if both the sign bit and exponent bit are the same, it can continue to compare the mantissa bits of the two normalized results to produce a mantissa comparison result. The fourth selector can choose to output this mantissa comparison result, which can indicate the size relationship of the mantissa bits between the two normalized results. In the arithmetic operation type, the fourth selector can choose to output the mantissa operation result from the first normalized result, that is, the floating-point mantissa bits output after processing by the first normalization unit.

[0111] It should be noted that, under comparison operation types, the sign comparison result, exponent comparison result, and mantissa comparison result generated by the comparison module can be generated sequentially. For example, if the sign bits of the two normalized results are different, the sign comparison result can directly determine their size relationship, and the exponent comparison result and mantissa comparison result do not need to be generated or are set to default values. If the sign bits are the same but the exponent bits are different, the exponent comparison result can determine their size relationship, and the mantissa comparison result does not need to be generated. Only when both the sign bit and the exponent bit are the same is it necessary to generate a mantissa comparison result to determine their size relationship. This sequential comparison method can save power consumption and latency of the comparison logic.

[0112] In some possible implementations, the outputs of the second, third, and fourth selectors can be sent to subsequent modules for use. For example, in comparison operations, the sign comparison, exponent comparison, and mantissa comparison results output by these selectors can be output to a status register for software reading or debugging purposes. In arithmetic operations, the sign, exponent, and mantissa operation results output by these selectors can be sent to the mantissa rounding module, exponent rounding module, and packing module for final rounding and packing processing, respectively.

[0113] In this embodiment of the disclosure, the operation unit further includes a comparison module, a second selector, a third selector, and a fourth selector. The comparison module is used to compare the second normalization result and the third normalization result according to the comparison operation type when the target operation type is the comparison operation type, to obtain a sign comparison result; the second selector is used to output the sign comparison result when the target operation type is the comparison operation type, and to output the sign operation result when the target operation type is the arithmetic operation type; the third selector is used to output the exponent comparison result when the target operation type is the comparison operation type, and to output the exponent operation result when the target operation type is the arithmetic operation type; the fourth selector is used to output the mantissa comparison result when the target operation type is the comparison operation type, and to output the mantissa operation result when the target operation type is the arithmetic operation type.

[0114] Therefore, by setting up a comparison module to compare the two normalized results step by step, and outputting the sign comparison result, exponent comparison result, and mantissa comparison result through the second, third, and fourth selectors respectively, the comparison results can be output for use by other modules, which helps to enhance the observability and debuggability of the system. Simultaneously, in arithmetic operations, these three selectors can output the sign, exponent, and mantissa parts of the first normalized result, allowing the system to reuse the same output path without needing to set up separate output interfaces for different operation types, thus simplifying hardware design and reducing resource overhead. Furthermore, by decoupling the output of the comparison result from the control of data selection, the comparison result can be output independently as a status signal, while data selection is directly completed by other selectors (such as the fifth selector) according to the operation instructions. This design helps to maintain the simplicity and flexibility of the data path.

[0115] In one possible implementation, the system is integrated into a graphics processor for performing graphics blending operations, wherein the floating-point operands include color blending operation parameters in graphics processing, and the operation result includes the color blending operation result.

[0116] A graphics processing unit (GPU) can be a hardware device specifically designed for graphics rendering and image processing. In the graphics rendering pipeline, color blending operations combine the color of the currently drawn pixel with the pixel colors stored in the frame buffer according to certain rules to produce visual effects such as translucency, glow, and shadows. Because color blending operations typically need to be performed on every pixel of every frame, they are computationally intensive and latency-sensitive, thus potentially requiring efficient, low-latency hardware support.

[0117] Graphics blending operations can be the computational operations performed during color blending. For example, graphics blending operations can be implemented in the form of `src × src_factor op dst × dst_factor`, where `src` represents the current pixel color to be drawn, `dst` represents the pixel color stored in the frame buffer, `src_factor` and `dst_factor` represent the corresponding blending factors, and `op` represents the operation type. Operation types can include addition, subtraction, inverse subtraction, maximum value operation, or minimum value operation, etc. In graphics processing, different blending effects can correspond to different operations and blending factor settings. For example, the Multiply effect can use a multiplicative blending mode, the Screen effect can use an additive blending mode, and the Lighten effect can use a maximum value blending mode.

[0118] Floating-point operands can include parameters for color blending operations in graphics processing. These parameters can be input data for the color blending operation. In terms of type, color blending parameters can include the current color value, the current color factor, the cached color value, and the cached color factor. The current color value can represent the numerical value of the pixel to be drawn in each color channel, such as the red, green, blue, and alpha channel values. The current color factor can represent the blending coefficient of the current color value, such as 1.0, 0.0, the alpha value of the current color, or the alpha value of the cached color. The cached color value can represent the numerical value of the pixel in each color channel already stored in the frame buffer. The cached color factor can represent the blending coefficient of the cached color value. These parameters can be represented in floating-point form, such as single-precision floating-point format or half-precision floating-point format.

[0119] The result of the operation can include the color blending result. The color blending result can be the blended color value output after processing by the multiply-accumulate blending system. This result can be written back to the frame buffer for rendering subsequent pixels or for final display output. For example, when using the additive blending mode, the result can be equal to the current color value multiplied by the current color factor plus the cached color value multiplied by the cached color factor; when using the maximum value blending mode, the result can be equal to the larger of the current color value multiplied by the current color factor and the cached color value multiplied by the cached color factor.

[0120] By integrating the multiply-accumulate fusion system into the graphics processor, this system can receive color blending operation parameters as input floating-point operands, perform the corresponding blending operations, and output the color blending operation results. Because this system can complete the multiplication of four data points within a single module, and select between arithmetic operations (e.g., addition) or comparison operations (e.g., maximum value operations) based on the target operation type indicated in the operation instruction, and only performs rounding once on the final result, it can support multiple blending modes while ensuring color blending accuracy, reducing computational latency, minimizing hardware resource consumption, and improving the overall efficiency of graphics rendering.

[0121] In this embodiment, the system is integrated into a graphics processor (GPU) for performing graphics blending operations. The floating-point operands include color blending operation parameters in graphics processing, and the operation result includes the color blending operation result. Therefore, by applying the multiply-accumulate fusion system to the color blending scenario of the GPU, the four-input, two-multiplication, and then-addition or two-multiplication comparison operations in color blending can be efficiently completed within a single module. This helps to reduce the hardware resource consumption of mantissa multiplication in the GPU while ensuring color blending accuracy, reducing computational latency, and improving the overall efficiency of graphics rendering.

[0122] Figure 2 A structural block diagram of a multiply-accumulate fusion system according to an embodiment of the present disclosure is shown. Figure 2 As shown, the multiply-add fusion system may include an unpacking module (UNPACK), a sign generation module (SIGNGEN), a special value determination module (SPENUM), an exponent addition module (EXPADD), a mantissa multiplication module (MANTMUL), an exponent selection module (EXPSEL), a mantissa addition module (MANTADD) (this module can be used to implement the addition function of the arithmetic operation module), a first selector (MMSELs0, i.e., S0), and a first normalization unit (including the original leading zero detection module LZD, the original left shift normalization module LSH, and the original exponent adjustment module LSH). The module consists of the following modules: EXPADJ (full module), second normalization unit (including the newly added leading zero detection module LZD, the newly added left shift normalization module LSH, and the newly added exponent adjustment module EXPADJ), comparison module (MMCMP, including the sign comparison submodule SIGNCMP, the exponent comparison submodule EXPCMP, the mantissa comparison submodule MANTCMP, and the internal selector MMSEL), second selector (S1), third selector (S2), fourth selector (S3), mantissa rounding module (RND), exponent rounding module (EXPRND), and packing module (PACK).

[0123] The multiply-accumulate fusion system can receive four floating-point input data (IN1, IN2, IN3, IN4). For example, in a color mixing scenario in graphics processing, these four floating-point input data can include the current color value, the current color factor, the cached color value, and the cached color factor. The system first performs floating-point decomposition, sign and special value processing, and pairwise multiplication of the exponent and mantissa on these four input data. Then, the first selector (S0) and the fifth selector (MMSEL) switch the data path according to the operation instruction (OP), selecting either the arithmetic operation path or the comparison operation path. Simultaneously, the second selector (S1), the third selector (S2), and the fourth selector (S3) output the sign comparison result, exponent comparison result, and mantissa comparison result generated by the comparison module, respectively. After normalization, exponent adjustment, and comparison selection are performed on both paths, a final rounding and result packaging are performed and output. Throughout the entire process, intermediate results are not rounded; only multiplication resources are reused and a small amount of logic is added, thereby achieving high-precision, low-latency, and small-area fusion operations.

[0124] Specifically, the unpacking module (UNPACK) can receive four floating-point input data, decomposing each input data into sign bits (sign1,2,3,4), exponent bits (exp1,2 and exp3,4), and mant bits (mant1,2 and mant3,4). The unpacking module automatically restores the implicit bits to 1 for normalized numbers and sets them to 0 for denormalized numbers, generating a valid mantissa of uniform width to ensure consistent data bit width in subsequent multiplication and addition trees. The unpacking module can output the decomposed sign bits to the sign generation module (SIGNGEN), the exponent bits to the exponent addition module (EXPADD), and the mantissa bits to the mantissa multiplication module (MANTMUL).

[0125] The sign generation module (SIGNGEN) can receive the four input sign bits from the unpacking module and generate the operator result based on the sign bit values. The sign generation module can also detect whether the input is a special value, perform sign bit correction processing on special values, and output the sign bit result and sign information to the exponent addition module (EXPADD), the comparison module (MMCMP), and each selector.

[0126] The SPENUM module receives four input data points from the unpacking module, determines the presence of special values ​​(such as NaN, infinity, denormalized numbers, etc.), and identifies the specific type of special value. The SPENUM module can output a special value flag to all downstream modules to correct the calculation results when special values ​​are present.

[0127] The exponent addition module (EXPADD) receives four input exponent bits from the unpacking module. It groups the four data points in pairs and performs two sets of exponent addition: adding the exponent of the first input data to the exponent of the second input data to obtain the first exponent sum; and adding the exponent of the third input data to the exponent of the fourth input data to obtain the second exponent sum. The exponent addition module can then output the two sets of exponent sums to the exponent selection module (EXPSEL) and the exponent adjustment module (EXPADJ).

[0128] The mantissa multiplication module (MANTMUL) receives the four mantissa bits from the unpacking module. It groups the four data points pairwise and performs two sets of mantissa multiplication: multiplying the mantissa of the first input data by the mantissa of the second input data to obtain the first product; and multiplying the mantissa of the third input data by the mantissa of the fourth input data to obtain the second product. The mantissa multiplication module retains the full mantissa product bit width. For example, with single-precision floating-point numbers, the mantissa portion (including implicit bits) of each input data is 24 bits, resulting in a 48-bit product. The mantissa multiplication module can output the two sets of mantissa products to the mantissa addition module (MANTADD), the first selector (S0), and the normalization unit.

[0129] The Exponent Selection Module (EXPSEL) receives two sets of exponent sums output by the Exponent Adder Module, calculates the exponent difference between the two products, determines their relative magnitudes, and generates the number of bits to right-shift for the path with the smaller exponent. The Exponent Selection Module can then output the exponent difference and the number of right-shifted bits to the Mantissa Adder Module (MANTADD) and the Exponent Adjustment Module (EXPADJ).

[0130] The mantissa addition module (MANTADD) can receive two sets of mantissa products output by the mantissa multiplication module and the right-shifted bits output by the exponent selection module. The mantissa addition module first right-shifts the mantissa product with the smaller exponent by the exponent difference (including one overflow bit) to align the two mantissa products in terms of digits. Then, it performs a summation operation on the two shifted mantissas and outputs the sum to the first selector (S0). When the target operation type indicated by the operation instruction is a comparison operation type (e.g., maximum or minimum value), the input of the mantissa addition module can be set to zero to save dynamic power consumption.

[0131] The first selector (S0) can receive the first product result (i.e., the product of the first input data and the second input data) output by the mantissa multiplication module and the mantissa sum result output by the mantissa addition module, and select the data to be transmitted downstream according to the operation instruction. When the target operation type indicated by the operation instruction is a comparison operation type, the first selector can select the first product result to be transmitted downstream; when the target operation type indicated by the operation instruction is an arithmetic operation type (e.g., addition, subtraction, or reverse subtraction), the first selector can select the mantissa sum result to be transmitted downstream.

[0132] The first normalization unit may include the original leading zero detection module (LZD), the original left shift normalization module (LSH), and the original exponent adjustment module (EXPADJ). The original leading zero detection module counts the number of leading zeros in the mantissa of the data to be processed: when the target operation type indicated by the operation instruction is an arithmetic operation, it counts the number of leading zeros in the mantissa of the result of multiplying and adding the four inputs pairwise; when the target operation type indicated by the operation instruction is a comparison operation, it counts the number of leading zeros in the mantissa of the first product result (i.e., input 1 × input 2). The original left shift normalization module, based on the number of leading zeros output by the original leading zero detection module, shifts the corresponding mantissa to the left by the corresponding number of bits, discards redundant bits, retains the valid bits and the information bits required for rounding, and outputs the first normalized result. The original exponent adjustment module, based on the number of leading zeros output by the original leading zero detection module, performs a subtraction adjustment on the corresponding exponent, that is, subtracts the number of leading zeros from the original exponent to keep the floating-point value unchanged.

[0133] The second normalization unit may include a new leading zero detection module (LZD), a new left-shift normalization module (LSH), and a new exponent adjustment module (EXPADJ). The new leading zero detection module can consistently count the number of leading zeros in the mantissa of the second product result (i.e., input 3 × input 4). The new left-shift normalization module, based on the number of leading zeros output by the new leading zero detection module, shifts the mantissa of the second product result to the left by the corresponding number of bits, outputting the second normalized result. The new exponent adjustment module, based on the number of leading zeros output by the new leading zero detection module, performs a subtraction adjustment on the exponent corresponding to the second product result, outputting the adjusted exponent.

[0134] The comparison module (MMCMP) can receive arithmetic instructions, the first normalized result output by the first normalization unit, and the second and third normalized results output by the second normalization unit. Internally, the comparison module can include a sign comparison submodule (SIGNCMP), an exponent comparison submodule (EXPCMP), a mantissa comparison submodule (MANTCMP), and a fifth selector (MMSEL). The sign comparison submodule compares the sign bits of two normalized results to produce a sign comparison result; the exponent comparison submodule compares the exponent bits of two normalized results to produce an exponent comparison result; and the mantissa comparison submodule compares the mantissa bits of two normalized results to produce a mantissa comparison result. The fifth selector (MMSEL) can select one of the second and third normalized results as the output result of the comparison module based on the arithmetic instruction. When the target arithmetic type indicated by the arithmetic instruction is a maximum value, the fifth selector can select the larger of the second and third normalized results; when the target arithmetic type indicated by the arithmetic instruction is a minimum value, the fifth selector can select the smaller one.

[0135] The second selector (S1) can receive the symbolic comparison result output by the symbolic comparison submodule and the symbolic operation result in the first normalization result. When the target operation type indicated by the operation instruction is a comparison operation type, the second selector can choose to output the symbolic comparison result; when the target operation type indicated by the operation instruction is an arithmetic operation type, the second selector can choose to output the symbolic operation result in the first normalization result.

[0136] The third selector (S2) can receive the exponent comparison result output by the exponent comparison submodule and the exponent operation result in the first normalization result. When the target operation type indicated by the operation instruction is a comparison operation type, the third selector can choose to output the exponent comparison result; when the target operation type indicated by the operation instruction is an arithmetic operation type, the third selector can choose to output the exponent operation result in the first normalization result.

[0137] The fourth selector (S3) can receive the mantissa comparison result output by the mantissa comparison submodule and the mantissa operation result in the first normalization result. When the target operation type indicated by the operation instruction is a comparison operation type, the fourth selector can choose to output the mantissa comparison result; when the target operation type indicated by the operation instruction is an arithmetic operation type, the fourth selector can choose to output the mantissa operation result in the first normalization result.

[0138] The mantissa rounding module (RND) receives the mantissa and exponent portions from the intermediate result output by the fifth selector (MMSEL), as well as the rounding mode signal. The mantissa rounding module performs rounding adjustments on the mantissa according to a preset rounding mode. For example, when the rounding mode is Round-Toward-Zero (RTZ), the mantissa rounding module can directly truncate the invalid portion of the mantissa; when the rounding mode is Round-to-Nearest-Even (RNE), the mantissa rounding module generates a carry based on the values ​​of the guard bit, round bit, and sticky bit, and passes the carry to the mantissa portion, while simultaneously outputting an exponent adjustment signal to the exponent rounding module (EXPRND).

[0139] The exponent rounding module (EXPRND) can receive the exponent adjustment signal output by the mantissa rounding module and the exponent portion output by the fifth selector (MMSEL). The exponent rounding module can adjust the exponent by ±1 according to the carry of the mantissa rounding module, and at the same time detect whether the exponent exceeds the maximum or minimum representation range of the floating-point number, and set the overflow flag if it exceeds the range.

[0140] The Pack module receives the sign bit from the sign generation module (SIGNGEN), the exponent from the exponent rounding module (EXPRND), and the mantissa from the mantissa rounding module (RND). The Pack module removes implicit bits, discards the highest 1 bit of the mantissa for normalized numbers, and keeps all 0 bits for denormalized numbers. It then compresses the sign bit, exponent, and mantissa bits to the standard floating-point width, re-encodes them into standard floating-point format, and outputs the final floating-point arithmetic result.

[0141] In this embodiment, the multiply-accumulate fusion system decomposes the four input floating-point data through an unpacking module, performs pairwise multiplication of the mantissas through a mantissa multiplication module while retaining the complete product bit width, selects the arithmetic operation path or comparison operation path output according to the operation instruction through a first selector, normalizes the data under different operation types through a first normalization unit and a second normalization unit respectively, achieves precise selection of maximum and minimum values ​​through step-by-step comparison and multi-level selectors within the comparison module, and finally performs a final rounding process through a mantissa rounding module and an exponent rounding module. Thus, the intermediate results are not rounded during the entire processing, only multiplication resources are reused and a small amount of new logic is added, achieving a high-precision, low-latency, and small-area hybrid operation unit.

[0142] According to another aspect of this disclosure, a chip is provided that includes the multiply-accumulate fusion system described above.

[0143] According to another aspect of this disclosure, a processor is provided that includes the multiply-accumulate fusion system described above.

[0144] According to another aspect of this disclosure, an electronic device is provided, including the multiply-accumulate fusion system described above.

[0145] In some embodiments, the functions or modules of the chips, processors and electronic devices provided in this disclosure can be specifically implemented with reference to the description of the system embodiments above, and will not be repeated here for the sake of brevity.

[0146] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0147] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0148] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0149] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0150] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0151] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements have been described above. Of course, these are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0152] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A multiply-accumulate fusion system for mixed operations, characterized in that, include: The multiplication unit is used to perform multiplication operations on floating-point operands to obtain the first product result and the second product result without rounding. The arithmetic unit is configured to perform an operation corresponding to the target operation type on the first product result and the second product result according to the target operation type indicated in the arithmetic instruction, and obtain an intermediate result; wherein, the arithmetic unit supports operations of different calculation types, and the operations of different calculation types share the multiplication unit; The rounding unit is used to perform rounding processing on the intermediate results to obtain the calculation result.

2. The system according to claim 1, characterized in that, The arithmetic unit includes: The arithmetic operation module is used to perform arithmetic operations on the first product result and the second product result when the target operation type is an arithmetic operation type, to obtain the intermediate result.

3. The system according to claim 2, characterized in that, The arithmetic operation module is used for: Based on the exponent difference between the first product result and the second product result, the first product result and the second product result are shifted and aligned before being added together to obtain the intermediate result.

4. The system according to claim 1, characterized in that, The arithmetic unit further includes: The first selector is used to select the output of the arithmetic operation module as the data to be processed when the target operation type is an arithmetic operation type; and to select the first product result as the data to be processed when the target operation type is a comparison operation type.

5. The system according to claim 4, characterized in that, When the target operation type is the comparison operation type, the operation unit controls the input of the arithmetic operation module to be set to zero.

6. The system according to claim 4, characterized in that, The system also includes: The first normalization unit is used to normalize the data to be processed when the target operation type is the arithmetic operation type, and output the first normalization result. The second normalization unit is used to normalize the first product result and the second product result respectively when the target operation type is the comparison operation type, and output the second normalization result and the third normalization result.

7. The system according to claim 6, characterized in that, The arithmetic unit further includes: The comparison module is used to compare the second normalization result and the third normalization result according to the comparison operation type when the target operation type is the comparison operation type, so as to obtain a sign comparison result; The second selector is configured to output the sign comparison result when the target operation type is the comparison operation type; and to output the sign operation result when the target operation type is the arithmetic operation type. The third selector is configured to output an exponential comparison result when the target operation type is the comparison operation type; and to output an exponential operation result when the target operation type is the arithmetic operation type. The fourth selector is used to output the mantissa comparison result when the target operation type is the comparison operation type; and to output the mantissa operation result when the target operation type is the arithmetic operation type.

8. The system according to claim 1, characterized in that, The system is integrated into a graphics processor and is used to perform graphics blending operations. The floating-point operands include color blending operation parameters in graphics processing, and the operation results include color blending operation results.

9. A chip, characterized in that, Includes the multiply-accumulate fusion system as described in any one of claims 1 to 8.

10. A processor, characterized in that, Includes the multiply-accumulate fusion system as described in any one of claims 1 to 8.

11. An electronic device, characterized in that, Includes the multiply-accumulate fusion system as described in any one of claims 1 to 8.

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