Queuing method in instruction transmission, processor, chip and electronic device
By judging the readiness status of instruction source operands and dynamically adjusting thresholds, the instruction queuing strategy is optimized, which solves the problem of wasted instruction issuance queue resources in out-of-order execution architecture and improves CPU execution efficiency and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2026-04-08
- Publication Date
- 2026-07-14
Smart Images
Figure CN122387518A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a queuing method for instruction issuance, a processor, a chip, and an electronic device. Background Technology
[0002] To improve execution efficiency, modern high-performance CPUs commonly employ out-of-order execution technology. In an out-of-order execution architecture, after instruction dispatch, it enters the backend for renaming before being sent to the instruction issue queue to await the readiness of its source operands. Once all source operands are ready, the instruction is selected and issued for execution.
[0003] The instruction issue queue is a critical component of the CPU backend. It needs to continuously monitor the wake-up network to update the state of instruction source operands and support the selection of ready instructions. However, implementing a deep instruction issue queue faces high hardware costs and technical challenges, especially due to the limitations imposed by the critical path from instruction wake-up to ready instruction selection.
[0004] To prevent the instruction dispatching of the entire core from being blocked due to the exhaustion of the instruction issue queue resources of a backend execution module, a non-issue buffer that does not support instruction issuance (FIFO) is usually set up in front of the instruction issue queue. When the instruction issue queue is full, instructions can be temporarily stored in the non-issue buffer to avoid affecting the instruction reception of other backend execution modules. The instruction dispatching unit ensures that dispatched instructions can be received by the execution unit by monitoring the number of remaining items in the non-issue buffer.
[0005] In the prior art, the instruction issuance logic diagram can be found in [reference needed]. Figure 1 As shown, to reduce instruction execution latency, when the instruction issue queue has enough free entries and the non-issue buffer is empty, it is usually possible to bypass the non-issue buffer and directly write the renamed instruction into the instruction issue queue. However, when the instruction issue queue does not have enough free entries or the non-issue buffer is not empty, the renamed instruction will first be written to the non-issue buffer, and then moved to the instruction issue queue according to the order of instructions in the non-issue buffer when there are free entries in the instruction issue queue.
[0006] Because the probability that all source operands of an instruction are ready when it enters the instruction issuance queue is low, most instructions need to wait in the instruction issuance queue to be awakened, thus occupying the instruction issuance queue resources for a period of time. When the instruction issuance queue is occupied by a large number of instructions with incomplete source operands, even if there are instructions in the non-issue buffer that have satisfied the condition of all source operands, they cannot be received by the instruction issuance queue, which leads to a significant waste of valuable instruction issuance queue resources. Summary of the Invention
[0007] In view of this, this application provides a queuing method, processor, chip, and electronic device for instruction issuance to solve at least one of the aforementioned problems.
[0008] To achieve the above objectives, this application adopts the following approach: According to a first aspect of this application, a queuing method for command issuance is provided, comprising: Retrieve the renamed instructions to be processed; Determine whether the source operands of the above instruction to be processed are ready; When the source operand of the above-mentioned instruction to be processed is ready and the preset bypass condition is met, the above-mentioned instruction to be processed is written into the instruction issuance queue through bypass. When the source operand of the above-mentioned instruction to be processed is not ready or the preset bypass condition is not met, the above-mentioned instruction to be processed is written into the non-emit buffer.
[0009] In some embodiments of this application, the preset bypass conditions in the above method include: The occupancy rate of the aforementioned instruction issuance queue exceeds the first preset threshold, and the aforementioned instruction issuance queue still has remaining space; The anti-livelock mechanism is not activated; and The aforementioned non-emission buffer is not empty and its occupancy rate has not reached the second preset threshold.
[0010] In some embodiments of this application, the above method further includes: Record the ROB ID of the above non-launch-buffered squadron leader command; Determine whether the distance between the ROB ID of the above queue head instruction and the ROB queue head is less than a preset distance threshold; When the distance is less than the preset distance threshold, the anti-livelock mechanism is activated, and instructions with ready source operands are prohibited from bypassing the non-emission buffer. When the distance between the ROB ID of the aforementioned non-launch buffer queue head command and the ROB queue head is not less than the aforementioned preset distance threshold, the aforementioned anti-livelock mechanism is turned off.
[0011] In some embodiments of this application, the above method further includes: Monitor the dwell time of the aforementioned non-launch buffer squadron leader command; Determine whether the dwell time of the above-mentioned head command exceeds a preset time threshold; When the dwell time of the above-mentioned head instruction exceeds the preset time threshold, the above-mentioned livelock prevention mechanism is activated, and instructions with ready source operands are prohibited from bypassing the above-mentioned non-launch buffer. If the dwell time of the above-mentioned leader instruction does not exceed the preset time threshold, the above-mentioned anti-livelock mechanism is turned off.
[0012] In some embodiments of this application, the preset bypass condition in the above method further includes: the proportion of source operand ready instructions in the above instruction issuance queue is lower than a preset ready instruction proportion threshold.
[0013] In some embodiments of this application, when the preset bypass condition is met, the idle items in the instruction launch queue are preferentially used to receive renamed pending instructions written through the bypass, thereby temporarily preventing instructions from being read from the non-launch buffer and written into the instruction launch queue.
[0014] In some embodiments of this application, the non-launch buffer in the above method is a first-in-first-out queue, and the method further includes: when the non-launch buffer is not empty and the instruction launch queue has free items, the instructions in the non-launch buffer are moved to the instruction launch queue in the order of instructions.
[0015] According to a second aspect of this application, a processor is provided, comprising: The instruction acquisition unit is used to acquire the renamed instructions to be processed. Instruction queuing control unit, used for: Determine whether the source operands of the above instruction to be processed are ready; When the source operand of the above-mentioned instruction to be processed is ready and the preset bypass condition is met, the above-mentioned instruction to be processed is controlled to be written into the above-mentioned instruction issuance queue through bypass. When the source operand of the instruction to be processed is not ready or the preset bypass condition is not met, the instruction to be processed is written to the non-emission buffer.
[0016] According to a third aspect of this application, a chip is provided, including the processor described above.
[0017] According to a fourth aspect of this application, an electronic device is provided, including the chip described above.
[0018] The instruction issuance queuing method, processor, chip, and electronic device provided in this application can determine whether the source operand of the instruction to be processed is ready after the instruction has been renamed. When the source operand is ready and meets the preset bypass conditions, the instruction is directly written to the instruction issuance queue through bypass. For instructions whose source operand is not ready or do not meet the bypass conditions, they are written to the non-issue buffer. This mechanism prioritizes instructions with ready source operands in the issuance queue when issuance queue resources are scarce, thereby improving the issuance efficiency of the issuance queue, effectively utilizing valuable issuance queue resources, and thus improving the execution performance of the CPU backend. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 A flowchart illustrating a queuing method for command issuance provided in an embodiment of this application; Figure 2 A flowchart illustrating the anti-livelock mechanism provided in this application embodiment; Figure 3 A flowchart illustrating an anti-livelock mechanism provided in another embodiment of this application; Figure 4 This is a schematic diagram of the structure of a processor provided in an embodiment of this application. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain this application, but are not intended to limit this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.
[0021] It should be noted that the terms "first…", "second…", "third…", etc., used in the specification and claims are only for the convenience of distinguishing similar or functionally similar technical features, elements, steps, etc., in the description. The use of "first," "second," etc., does not represent a structural, functional, or priority order, nor does it imply a limitation on a specific quantity or importance. Unless otherwise expressly stated in the specific embodiments or claims, such terms are for ease of expression and understanding only and should not be used to make any actual limitation on the scope of protection or implementation of the present invention.
[0022] Furthermore, the use of the aforementioned terms for ease of explanation does not imply a logical order, temporal sequence, or hierarchical relationship among the named features, components, and steps; it is merely for distinction. Those skilled in the art will fully understand the intent of such terms and their application in the embodiments and claims of this invention.
[0023] like Figure 1The diagram shown is a flowchart illustrating a queuing method for command issuance according to an embodiment of this application. The method includes the following steps: Step S101: Obtain the renamed instructions to be processed.
[0024] In the CPU instruction processing flow, instructions undergo a series of stages before execution. Renaming is a crucial step in out-of-order execution. In this step, the instruction to be processed has completed the register renaming operation. This means that the logical registers in the instruction have been mapped to physical registers, eliminating register-related data dependencies and preparing for out-of-order execution. At this point, this step obtains the renamed instruction, awaiting further processing and issuance.
[0025] Step S102: Determine whether the source operands of the instruction to be processed are ready.
[0026] After obtaining the renamed instruction to be processed, it is necessary to determine whether the execution conditions of the instruction are met. This mainly involves the status of its source operands. The source operands are the data inputs required for instruction execution. Determining whether the source operands are ready means checking whether these required data have been calculated by previous instructions and written to physical registers, or whether they are ready in other available resources. If all source operands corresponding to the instruction are available, the source operands of the instruction are considered ready; otherwise, they are considered not ready.
[0027] Step S103: In response to the fact that the source operand of the instruction to be processed is ready and the current preset bypass condition is met, the instruction to be processed is written into the instruction issuance queue through bypass.
[0028] If step S102 determines that the source operand is ready, this step further evaluates whether preset bypass conditions are met. Bypass conditions are a set of rules that determine whether an instruction can bypass the regular queuing path and directly enter the instruction issue queue. If these preset bypass conditions are met, and the source operand of the instruction to be processed is also ready, then the instruction will bypass the non-issue buffer and be directly "bypassed" into the instruction issue queue. The instruction issue queue is a key structure in the CPU backend responsible for temporarily storing ready instructions and issuing them to functional units for execution. This bypass mechanism aims to accelerate the entry and issuance of ready instructions.
[0029] Step S104: In response to the source operand of the instruction to be processed not being ready or the current preset bypass condition not being met, the instruction to be processed is written into the non-issue buffer.
[0030] Corresponding to step S103, if the judgment result of step S102 is that the source operand is not ready, or even if the source operand is ready but the preset bypass condition is not currently met, then the instruction to be processed will not directly enter the instruction issuance queue. In this case, the instruction will be written to the non-issuance buffer. Instructions in the non-issuance buffer will wait for space in the instruction issuance queue before being moved into the issuance queue in instruction order.
[0031] As described above, the queuing method for instruction issuance provided in this application embodiment can determine whether the source operand of the instruction to be processed is ready after the instruction is renamed. When the source operand is ready and meets the preset bypass conditions, the instruction is directly written into the instruction issuance queue through bypass. For instructions whose source operand is not ready or do not meet the bypass conditions, they are written into the non-issue buffer. In scenarios where issuance queue resources are scarce, this mechanism prioritizes instructions with ready source operands to enter the issuance queue, thereby improving the issuance efficiency of the issuance queue, effectively utilizing valuable issuance queue resources, and thus improving the execution performance of the CPU backend.
[0032] In some embodiments of this application, the preset bypass conditions in steps S103 and S104 above include: the occupancy rate of the command issuance queue exceeds a first preset threshold, and the command issuance queue still has remaining space; the anti-livelock mechanism is not activated; and the non-issuance buffer is not empty and the occupancy rate has not reached a second preset threshold.
[0033] In other words, the preset bypass conditions in this embodiment need to satisfy the above three conditions simultaneously, which will be explained below: 1) The occupancy rate of the command issuance queue exceeds the first preset threshold, and there is still space remaining in the command issuance queue.
[0034] This condition aims to determine whether the command issuance queue is in a state of strain but not full. Specifically, when the number of commands in the command issuance queue reaches or exceeds a pre-set first threshold, it indicates that the issuance queue is already quite busy. Simultaneously, it is necessary to ensure that there is still remaining space in the command issuance queue to receive new commands written via bypass. This threshold is set to activate the bypass mechanism when the issuance queue resources begin to be strained, prioritizing the delivery of ready commands to improve the overall issuance efficiency of the queue. Of course, if the command issuance queue is already close to full capacity, even if there are ready commands, they need to be handled with caution to avoid further exacerbating queue congestion. Therefore, the first preset threshold can be set based on past experience or experimental data.
[0035] 2) The anti-livelock mechanism is not activated.
[0036] The livelock prevention mechanism here aims to prevent younger instructions with ready source operands from continuously bypassing the system and preferentially entering the instruction issue queue. This causes older instructions, whose source operands may also be ready, to remain in the non-issue buffer and be unable to enter the issue queue, thus blocking the entire instruction stream. This prevents resources such as ROBs (Relevant Operating Blocks) from being released in sequence, ultimately impacting program performance. Therefore, when the livelock prevention mechanism is enabled, it means the system is attempting to resolve or avoid the livelock problem. In this case, the bypass mechanism should be disabled to ensure that instructions in the non-issue buffer can enter the issue queue normally. The bypass condition can only be met when the livelock prevention mechanism is disabled.
[0037] 3) The non-emission buffer is not empty and the occupancy rate has not reached the second preset threshold.
[0038] This condition considers the possibility of instruction bypass from the perspective of non-issue buffer.
[0039] If the non-issue buffer is empty, existing solutions typically support bypassing the non-issue buffer and directly writing the renamed instruction into the issue queue. Therefore, the bypass mechanism in this application is only meaningful when the non-issue buffer is not empty, and is used to decide whether to continue writing the instruction into the non-issue buffer or bypass it directly.
[0040] The second preset threshold here is to prevent excessive congestion of the non-issue buffer. If the non-issue buffer occupancy rate is too high, reaching or exceeding the second preset threshold, it may mean that the non-issue buffer is about to be full, potentially blocking the CPU's instruction dispatch unit and preventing the entire core from receiving new instructions. In this case, even if there are instructions with ready operands, enabling the ready instruction bypass mechanism becomes meaningless, as instruction dispatch may soon stop. Therefore, the bypass mechanism can only operate effectively when the non-issue buffer occupancy rate is at a healthy level (not reaching the preset second threshold).
[0041] As described above, this embodiment, by combining the aforementioned preset bypass conditions, can selectively prioritize younger, directly executable instructions to enter the instruction issuance queue in scenarios where issuance queue resources are scarce. This improves the utilization rate of the instruction issuance queue and enhances CPU execution efficiency. This is an effective method for optimizing instruction flow and maximizing the utilization of CPU backend resources while balancing system stability, avoiding livelock risks, and preventing buffer overflows.
[0042] In some embodiments of this application, the method of this application may further include: dynamically adjusting the first preset threshold and the second preset threshold based on real-time monitored key performance indicators.
[0043] During CPU operation, the requirements for instruction issue queues and non-issue buffers vary depending on the application and workload. For example, compute-intensive tasks may require higher issue queue efficiency, while I / O-intensive tasks may have a less dense instruction flow, resulting in different requirements for bypassing. Therefore, fixed first and second preset thresholds may not achieve optimal performance in all situations. This application dynamically adjusts the aforementioned first and second preset thresholds by real-time monitoring of key performance indicators. These key performance indicators include, but are not limited to, CPU utilization, actual occupancy of the instruction issue queue, actual occupancy of the non-issue buffer, instruction issue throughput, and bypass success rate.
[0044] In practical implementation, for example, a performance monitoring unit (PMU) can be integrated into the CPU to monitor key performance indicators in real time. A threshold dynamic adjustment policy manager is then implemented at the operating system level or in the CPU's microcode. This manager periodically (e.g., every 100 milliseconds or after N instructions are completed) retrieves the current performance data from the PMU. First, a default starting value is set for a first preset threshold and a second preset threshold; for example, the first preset threshold is 70%, and the second preset threshold is 80%.
[0045] If current CPU utilization and instruction issue throughput are both low, it may indicate that bypass mechanisms are not being fully utilized, or that the current threshold setting is too conservative. If the instruction issue queue remains at high occupancy for an extended period without a significant increase in issue throughput, the threshold may need to be adjusted to allow for more bypassing. If the non-issue buffer occupancy remains excessively high, the threshold may need to be adjusted to reduce bypassing, prioritizing the clearing of the non-issue buffer to avoid instruction dispatch blocking. Therefore, threshold adjustments can be implemented using preset adjustment rules: for example, preset adjustment rule 1 increases bypass activity (lowers the first preset threshold and increases the second preset threshold), and preset adjustment rule 2 decreases bypass activity (increases the first preset threshold and decreases the second preset threshold). Below are examples of two preset adjustment rules: Preset adjustment rule 1: When CPU utilization is below a certain target value (e.g., 50%) and instruction issue throughput is below the historical average, the policy manager can lower the first preset threshold (e.g., from 70% to 60%), allowing bypass to be triggered even when issue queue occupancy is low. Simultaneously, the second preset threshold can be increased (e.g., from 80% to 90%), allowing bypass to be attempted even when non-issue buffer occupancy is high, in order to alleviate pressure on the non-issue buffer.
[0046] Preset Adjustment Rule 2: When CPU utilization approaches saturation (e.g., above 95%) and non-issue buffer occupancy continues to rise and approaches full load, to avoid blocking instruction dispatch, the policy manager can increase the first preset threshold (e.g., from 70% to 85%), allowing bypassing only when the issue queue is more idle. Simultaneously, the second preset threshold can be decreased (e.g., from 80% to 70%), immediately stopping bypassing once non-issue buffer occupancy reaches a low level, prioritizing clearing the non-issue buffer.
[0047] The new threshold calculated by the policy manager can be written to the CPU's control register through a specific hardware interface, thereby changing the judgment conditions of the bypass mechanism in real time.
[0048] As shown above, by dynamically adjusting the preset threshold, the CPU's instruction scheduling mechanism can: better adapt to workloads, achieving superior performance under different applications and system states; avoid resource waste or performance bottlenecks caused by fixed thresholds; and cope with sudden workload changes, maintaining stable high performance.
[0049] In other embodiments of this application, as described above, to avoid the prolonged retention of old instructions in the non-issue buffer due to the continuous bypassing of young ready instructions, which affects the release of in-order committed resources (such as ROBs) and thus reduces program performance, this method introduces an anti-livelock mechanism. For example... Figure 2 As shown, this anti-livelock mechanism is implemented through the following steps: Step S201: Record the ROB ID of the non-launch buffer squadron head command.
[0050] The non-issue buffer is a first-in, first-out (FIFO) queue used to temporarily store instructions waiting to enter the instruction issue queue. To implement a livelock prevention mechanism, the system needs to continuously monitor the instruction at the front (i.e., the head) of the non-issue buffer. This step records the ROB ID (Reorder Buffer ID) of the instruction currently at the head of the non-issue buffer. The ROB ID is a unique identifier for an instruction in the reorder buffer, representing the instruction's program order (age).
[0051] Step S202: Determine whether the distance between the ROB ID of the queue head instruction and the ROB queue head is less than a preset distance threshold. If it is less, proceed to step S203; otherwise, proceed to step S204.
[0052] After recording the ROB ID of the non-launch buffer head instruction, this step compares it with the ROB ID of the current ROB head instruction to calculate the "distance" between them. This "distance" reflects the age difference between the non-launch buffer head instruction and the oldest instruction in the entire ROB. If the calculated distance is less than a preset "preset distance threshold," it indicates that the head instruction in the non-launch buffer is very close to the head of the ROB, meaning it is a "very old" instruction that is about to complete and commit. In this case, to prevent further delays in commit due to bypassing by younger instructions, the system proceeds to step S203. Conversely, if the distance is greater than or equal to the preset threshold, it indicates that the head instruction is not yet likely to immediately trigger a livelock risk, and the system proceeds to step S204.
[0053] Step S203: Enable the anti-livelock mechanism and prevent instructions with ready source operands from bypassing the non-issue buffer.
[0054] When the distance between the ROB ID of the instruction at the head of the non-issue buffer and the head of the ROB queue is less than a preset distance threshold, the system will activate the livelock prevention mechanism. Once the livelock prevention mechanism is activated, the instruction bypass function will be temporarily disabled. This means that even if new instructions have ready source operands, they can no longer bypass the instruction issue queue directly, but must first enter the non-issue buffer queue like normal instructions. The purpose of this is to prioritize the processing of "older" instructions in the non-issue buffer, ensuring that they can enter the instruction issue queue and be executed as soon as possible, thereby preventing livelock caused by the continuous bypassing of younger instructions, i.e., old instructions cannot be processed for a long time, blocking ROB submission and affecting the overall CPU performance.
[0055] Step S204: Disable the anti-livelock mechanism.
[0056] If the distance between the ROB ID of a non-lead instruction in the launch buffer queue and the ROB queue head is greater than or equal to a preset distance threshold, or if, after a period of processing following the activation of the anti-livelock mechanism in step S203, the distance between the ROB ID of a non-lead instruction in the launch buffer queue and the ROB queue head again becomes greater than the preset distance threshold (indicating that the livelock risk has been eliminated or temporarily mitigated), the system will disable the anti-livelock mechanism. At this time, the bypass function will be re-enabled, allowing instructions with ready source operands to continue to preferentially enter the instruction launch queue through the bypass mechanism, provided other bypass conditions are met, thereby improving overall performance.
[0057] Therefore, the aforementioned livelock prevention mechanism ensures that older instructions in the non-issue buffer will not be delayed indefinitely due to the continuous bypassing of younger instructions. The timely execution of older instructions allows the reorder buffer (ROB) to release resources in sequence, maintaining normal CPU operation. Thus, this application, while ensuring overall performance optimization, dynamically enables / disables the livelock prevention mechanism to ensure all instructions have a chance to be executed, preventing individual instructions from remaining unexecuted and improving program execution efficiency.
[0058] In other embodiments of this application, another anti-livelock mechanism may also be introduced, such as... Figure 3 As shown, this anti-livelock mechanism is implemented through the following steps: Step S301: Monitor the dwell time of the non-launch buffer squadron leader command.
[0059] This step continuously tracks how long the head instruction in the non-launch buffer remains within the non-launch buffer, a first-in, first-out queue where instructions wait to enter the instruction launch queue. The dwell time can be monitored using a timer or similar mechanism, recording the elapsed time from the moment the head instruction enters the non-launch buffer until the current moment.
[0060] Step S302: Determine whether the dwell time of the queue head instruction exceeds the preset time threshold. If it does, proceed to step S303; otherwise, proceed to step S304.
[0061] This step compares the dwell time of the head-of-the-queue instruction detected in step S301 with a pre-set "preset time threshold." This preset time threshold represents the maximum acceptable waiting time for an instruction outside the launch buffer, as determined by the system. If the dwell time of the head-of-the-queue instruction exceeds this threshold, it means that the instruction may not be processed for an extended period due to a continuous bypass mechanism, posing a livelock risk. In this case, the process proceeds to step S303. Conversely, if the dwell time does not exceed the threshold, it is considered that there is no urgent livelock risk, and the process proceeds to step S304.
[0062] Step S303: Enable the anti-livelock mechanism and prevent instructions with ready source operands from bypassing the non-issue buffer.
[0063] When the dwell time of the instruction at the head of the queue exceeds a preset threshold, and the system determines there is a risk of livelock, it will activate the anti-livelock mechanism. Once activated, the instruction bypass function will be temporarily disabled. This means that even if new instructions with ready source operands arrive, they can no longer directly bypass the non-issue buffer to enter the instruction issue queue; instead, they must first enter the non-issue buffer queue. The purpose of this is to pause the bypass's effect on older instructions, forcing the system to prioritize older instructions that have been waiting too long in the non-issue buffer, ensuring they can enter the instruction issue queue and be executed as quickly as possible, thereby resolving the livelock state and preventing the blocking of resources such as the ROB.
[0064] Step S304: Disable the anti-livelock mechanism.
[0065] If the determination result of step S302 is that the dwell time of the head instruction does not exceed a preset threshold, or if after step S303, when the anti-livelock mechanism is enabled and after a period of processing, the head instruction has left the non-issue buffer or its dwell time no longer exceeds the threshold (indicating that the livelock risk has been eliminated), the anti-livelock mechanism will be disabled. At this time, the bypass function will be re-enabled, allowing instructions with ready source operands to continue to enter the instruction issue queue preferentially through the bypass mechanism when other conditions are met, in order to maintain and improve overall performance. This step ensures that the anti-livelock mechanism intervenes only when necessary, avoiding unnecessary performance loss.
[0066] Figure 2 The livelock prevention mechanism in the corresponding embodiment focuses on the age of instructions in the program sequence, identifying livelock risks by determining the distance between the head instruction of the non-issue buffer queue and the head of the ROB queue. It primarily addresses the problem that the continuous bypassing of younger instructions prevents instructions that are old in program sequence but still in the non-issue buffer from being submitted to the ROB in order. In contrast, the livelock prevention mechanism in this embodiment focuses on the waiting time of instructions in the non-issue buffer. It does not directly focus on the absolute order of instructions in the program, but rather on the actual waiting time of the instructions. This means that even if an instruction is not the oldest in program sequence, if it waits for too long in the non-issue buffer (possibly due to too many young instructions continuously bypassing it), the mechanism will be triggered, thus ensuring the eventual completion of all instructions.
[0067] Therefore, the livelock prevention mechanism in this embodiment provides a time-based livelock detection and resolution strategy, which is a solution to... Figure 2 The embodiments are an effective supplement to the livelock prevention mechanism based on the program sequence dimension. The two can be implemented alone or in synergy to more comprehensively protect CPU performance and instruction execution fairness.
[0068] In some embodiments of this application, the aforementioned preset bypass condition may further include: the proportion of source operand ready instructions in the instruction issuance queue is lower than a preset ready instruction proportion threshold.
[0069] The bypass condition added in this embodiment aims to further optimize the efficiency of the launch queue and avoid unnecessary bypass operations. Specifically: If many instructions in the launch queue are already in a ready state, then there is no need to provide ready instructions through ready instruction bypass. Furthermore, enabling ready instruction bypass at this point might disrupt the principle of instruction-by-instruction execution, negatively impacting performance. Therefore, by setting a preset ready instruction percentage threshold, bypass operations can be restricted when the launch queue is already relatively active.
[0070] The bypass mechanism is activated only when the proportion of ready commands in the launch queue is low, indicating a potential efficiency bottleneck. This allows new ready commands to enter first, thus more effectively utilizing the bypass to improve launch efficiency. This is a more refined performance tuning strategy, ensuring that the bypass mechanism is activated only when it is most needed.
[0071] It is evident that introducing a bypass condition where the proportion of ready instructions for the source operand in the instruction issuance queue is lower than a preset ready instruction proportion threshold can make the bypass mechanism more intelligent and targeted, avoiding unnecessary bypass operations when the issuance queue efficiency is still acceptable, thereby better balancing performance optimization and resource management.
[0072] In some embodiments of this application, when the aforementioned preset bypass conditions are met, the idle entries in the instruction issuance queue are preferentially used to receive renamed pending instructions written through the bypass, thereby temporarily preventing the reading of instructions from the non-issuance buffer and their writing into the instruction issuance queue.
[0073] In this embodiment, when a preset bypass condition is met, the free entries in the instruction issue queue will be preferentially used to receive instructions that have been written via the bypass mechanism, have been renamed, and whose source operands are ready. This priority means that even if there are free entries in the instruction issue queue, instructions will not be read from the non-issue buffer and written to the instruction issue queue.
[0074] The purpose of this approach is to prioritize writing instructions with ready source operands directly into the issue queue, thereby minimizing the waiting time of these instructions and improving CPU execution efficiency. This embodiment breaks with the traditional limitation of writing instructions sequentially into the instruction issue queue, allowing for more flexible and efficient instruction scheduling, prioritizing instructions that are ready for execution. By prioritizing ready instructions, the issue queue is prevented from being occupied for extended periods by instructions with unread source operands, thus improving the utilization rate of the issue queue and issue efficiency.
[0075] In short, when the bypass condition is met, the system will prioritize processing those ready instructions, ensuring that they can enter the launch queue and be executed as soon as possible, while temporarily suspending the sequential reading of instructions from the non-launch buffer in order to achieve higher overall execution performance.
[0076] In some embodiments of this application, the non-launch buffer is a first-in-first-out queue. The method of this application further includes: when the non-launch buffer is not empty and the instruction launch queue has free items, the instructions in the non-launch buffer are moved to the instruction launch queue in the order of instructions.
[0077] The non-issue buffer serves as a temporary storage area for instructions when the instruction issue queue is full or other conditions are not met. Once the issue queue becomes free, the non-issue buffer strictly moves instructions into the issue queue in the order they entered (i.e., instruction order). This mechanism runs parallel to the mechanism in this application that allows ready instructions to be bypassed and written to the issue queue. When bypass conditions are not met, or when the issue queue needs to be filled to maintain its efficiency, this mechanism ensures that instructions in the non-issue buffer can enter the issue queue in order.
[0078] like Figure 4 The diagram shown is a schematic representation of a processor according to an embodiment of this application. It includes: an instruction fetch unit 410, an instruction queuing control unit 420, a non-issue buffer 430, and an instruction issue queue 440. The instruction queuing control unit 420 is connected to the instruction fetch unit 410, the non-issue buffer 430, and the instruction issue queue 440, respectively. The non-issue buffer 430 and the instruction issue queue 440 are also connected to each other. The instruction acquisition unit 410 is used to acquire the renamed instruction to be processed.
[0079] Instruction queuing control unit 420, used for: Determine if the source operands of the instruction to be processed are ready; When the source operand of the instruction to be processed is ready and the preset bypass condition is met, the instruction to be processed is controlled to be written into the instruction issuance queue 440 through the bypass. When the source operand of the instruction to be processed is not ready or the preset bypass condition is not met, the instruction to be processed is written to the non-emission buffer 430.
[0080] The specific control method of the instruction queuing control unit 420 can be found in the corresponding description in the foregoing method embodiments, and will not be repeated here.
[0081] As described above, the processor provided in this application embodiment can determine whether the source operand of the instruction to be processed is ready after the instruction is renamed. When the source operand is ready and meets the preset bypass conditions, the instruction is directly written to the instruction issue queue through bypass. For instructions whose source operand is not ready or do not meet the bypass conditions, they are written to the non-issue buffer. In scenarios where issue queue resources are scarce, this mechanism prioritizes instructions with ready source operands to enter the issue queue, thereby improving the issue queue's issuance efficiency, effectively utilizing valuable issue queue resources, and ultimately improving the execution performance of the CPU backend.
[0082] In a further optional implementation, embodiments of this application also provide a chip that includes the processor described above.
[0083] In a further optional implementation, embodiments of this application also provide an electronic device, the electronic chip including the chip described above.
[0084] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0085] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A queuing method for command issuance, characterized in that, include: Retrieve the renamed instructions to be processed; Determine whether the source operand of the instruction to be processed is ready; When the source operand of the instruction to be processed is ready and the preset bypass condition is met, the instruction to be processed is written into the instruction issuance queue through bypass. When the source operand of the instruction to be processed is not ready or the preset bypass condition is not met, the instruction to be processed is written to the non-emission buffer.
2. The queuing method for command issuance as described in claim 1, characterized in that, The preset bypass conditions include: The occupancy rate of the instruction issuance queue exceeds a first preset threshold, and the instruction issuance queue still has remaining space; The anti-livelock mechanism is not activated; and The non-emission buffer is not empty and its occupancy rate has not reached the second preset threshold.
3. The queuing method for command issuance as described in claim 2, characterized in that, The method further includes: Record the ROB ID of the non-launch-buffered squadron head command; Determine whether the distance between the ROB ID of the queue head instruction and the ROB queue head is less than a preset distance threshold; When the distance is less than a preset distance threshold, the anti-livelock mechanism is activated, and instructions with ready source operands are prohibited from bypassing the non-emission buffer. When the distance between the ROB ID of the non-launch buffer head command and the ROB head is not less than the preset distance threshold, the anti-livelock mechanism is turned off.
4. The queuing method for command issuance as described in claim 2, characterized in that, The method further includes: Monitor the dwell time of the non-launch buffer squadron leader command; Determine whether the dwell time of the queue head instruction exceeds a preset time threshold; When the dwell time of the head instruction exceeds a preset time threshold, the anti-livelock mechanism is activated, and instructions with ready source operands are prohibited from bypassing the non-emission buffer. When the dwell time of the queue leader instruction does not exceed the preset time threshold, the anti-livelock mechanism is turned off.
5. The queuing method for command issuance as described in claim 2, characterized in that, The preset bypass condition also includes: the proportion of ready instructions for source operands in the instruction issuance queue is lower than a preset ready instruction proportion threshold.
6. The queuing method for command issuance as described in claim 1, characterized in that, When the preset bypass condition is met, the idle entries in the instruction issuance queue are preferentially used to receive the renamed pending instructions written through the bypass, thereby temporarily preventing instructions from being read from the non-issuance buffer and written to the instruction issuance queue.
7. The queuing method for command issuance as described in claim 1, characterized in that, The non-launch buffer is a first-in-first-out queue, and the method further includes: when the non-launch buffer is not empty and the instruction launch queue has free items, the instructions in the non-launch buffer are moved to the instruction launch queue in the order of instructions.
8. A processor, characterized in that, include: The instruction acquisition unit is used to acquire the renamed instructions to be processed. Instruction queuing control unit, used for: Determine whether the source operand of the instruction to be processed is ready; When the source operand of the instruction to be processed is ready and the preset bypass condition is met, the instruction to be processed is controlled to be written into the instruction issuance queue through bypass. When the source operand of the instruction to be processed is not ready or the preset bypass condition is not currently met, the instruction to be processed is controlled to be written into the non-emission buffer.
9. A chip, characterized in that, Includes the processor as described in claim 8.
10. An electronic device, characterized in that, Includes the chip as described in claim 9.