Storage area wake-up method and device, electronic equipment, chip and storage medium

Abstract

This application discloses a memory region wake-up method, apparatus, electronic device, chip, and storage medium, relating to the field of chips. The method includes: predicting the target memory region type to be accessed by a first transaction initiated by the processor from multiple memory region types based on internal processor information; determining the target memory region to be accessed from multiple memory regions included in the target memory region type based on the address of the first transaction access; and generating a wake-up signal to wake up the target memory region if it is in a dormant state. Therefore, it is possible to predict the target memory region for transaction access based on internal processor information, so that a wake-up signal can be generated in advance if the target memory region is in a dormant state. The wake-up signal can arrive at the memory region much earlier than the transaction access, thus waking up the dormant memory region in advance, reducing the latency of processor access to the memory region, and improving the user experience.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, electronic device, chip, and storage medium for waking up a memory region. Background Technology

[0002] In related technologies, storage devices enter a sleep state to reduce power consumption when they are not accessed for a period of time. During sleep, most of the logic circuitry is shut down, maintaining only the data, or the cached data is lost. When the storage device needs to be accessed, the user must wait for the logic circuitry to recover or the cached data to be rebuilt before normal access can be granted. This results in long waiting times and negatively impacts the user experience. Summary of the Invention

[0003] This application proposes a method, apparatus, electronic device, chip, and storage medium for waking up a storage region, in order to at least partially solve one of the technical problems in the related art.

[0004] One embodiment of this application proposes a memory region wake-up method, comprising: predicting the target memory region type to be accessed by a first transaction initiated by the processor from multiple memory region types based on processor internal information; determining the target memory region to be accessed from multiple memory regions included in the target memory region type based on the address of the first transaction access; and generating a wake-up signal to wake up the target memory region if the target memory region is in a dormant state.

[0005] In some embodiments, the target storage region type to be accessed by the first transaction initiated by the processor is predicted from multiple storage region types based on internal processor information. This includes: determining the target storage region type to be accessed by the first transaction using any one of methods one, two, three, four, five, and six; or predicting according to a specified priority order of multiple methods one, two, three, four, five, and six until the target storage region type to be accessed by the first transaction is determined.

[0006] Method 1: Determine the type of target storage area to be accessed by the first transaction based on the exception level switching information when the processor core executes instructions; Method 2: Determine the type of target memory region to be accessed by the first transaction based on the instruction information executed by the processor core; Method 3: Determine the type of target memory region to be accessed by the first transaction based on the jump direction prediction information in the processor's instruction fetch unit; Method 4: Determine the target storage region type to be accessed by the first transaction based on the address and address type accessed by the first transaction, as well as the differences in the historical access addresses of a preset number of historical transactions that belong to the same address type as the first transaction. Method 5: Determine the target storage region type to be accessed by the first transaction based on the specified fields in the CHI data packet output by the processor core and DSU; Method 6: Based on the storage area types accessed by historical transactions within a preset time period before the first transaction accesses, determine the target storage area type to be accessed by the first transaction.

[0007] In some embodiments, the multiple storage region types include a first type and a second type. Determining the target storage region type to be accessed by the first transaction access based on the exception level switching information when the processor core executes instructions includes: determining whether a security state switch has occurred based on the exception level switching information; if a security state switch has occurred, determining that the target storage region type to be accessed by the first transaction access is the first type; if no security state switch has occurred, determining whether an exception level switch has occurred; if an exception level switch has occurred, obtaining the first address of the first transaction access and the second address of the second transaction access before the exception switch, and determining the target storage region type to be accessed by the first transaction access based on the first address and the second address.

[0008] In some embodiments, determining the target storage region type to be accessed by the first transaction access based on the first address and the second address includes: subtracting the first address and the second address; if the difference is greater than a first threshold, determining the target storage region type to be accessed by the first transaction access to be a first type; if the difference is greater than a second threshold and less than the first threshold, determining the target storage region type to be accessed by the first transaction access to be a second type.

[0009] In some embodiments, determining the type of the target storage region to be accessed by the first transaction access based on the instruction information executed by the processor core includes: determining whether the instruction executed by the processor core is a special instruction based on the instruction information executed by the processor core; if it is a special instruction, obtaining the first instruction address of the instruction preceding the special instruction and the second instruction address of the special instruction, and determining the type of the target storage region to be accessed by the first transaction access based on the first instruction address and the second instruction address.

[0010] In some embodiments, determining the target storage region type to be accessed by the first transaction access based on the first instruction address and the second instruction address includes: subtracting the first instruction address and the second instruction address; if the difference is greater than a first threshold, determining the target storage region type to be accessed by the first transaction access to be a first type; if the difference is greater than a second threshold and less than the first threshold, determining the target storage region type to be accessed by the first transaction access to be a second type.

[0011] In some embodiments, determining the type of the target memory region to be accessed by the first transaction access based on jump direction prediction information in the processor's instruction fetch unit includes: determining whether the direction of the predicted branch instruction is a jump based on the prediction information; if the direction of the predicted branch instruction is a jump, determining the third instruction address of the current instruction and the fourth instruction address of the predicted branch instruction, and determining the type of the target memory region to be accessed by the first transaction access based on the third instruction address and the fourth instruction address.

[0012] In some embodiments, determining the target storage region type to be accessed by the first transaction access based on the third instruction address and the fourth instruction address includes: taking the difference between the third instruction address and the fourth instruction address; if the difference is greater than a first threshold, determining the target storage region type to be accessed by the first transaction access to be a first type; if the difference is greater than a second threshold and less than the first threshold, determining the target storage region type to be accessed by the first transaction access to be a second type.

[0013] In some embodiments, the multiple storage region types include a first type and a second type. The target storage region type to be accessed by the first transaction is determined based on the address and address type of the first transaction access, and the differences in historical access addresses of a preset number of historical transactions belonging to the address type prior to the first transaction access. This includes: determining that the address type of the address accessed by the first transaction is an instruction address; subtracting the address accessed by the first transaction from the historical instruction addresses of the preset number of historical transactions belonging to the instruction address prior to the first transaction access; if all differences are greater than a first threshold, determining that the target storage region type to be accessed by the first transaction access is the first type; if all differences are greater than a second threshold and less than the first threshold, determining that the target storage region type to be accessed by the first transaction access is the second type; and determining that the address type of the address accessed by the first transaction is a data address; subtracting the address accessed by the first transaction from the historical instruction addresses of the preset number of historical transactions belonging to the data address prior to the first transaction access; if all differences are greater than a third threshold, determining that the target storage region type to be accessed by the first transaction access is the first type; if all differences are greater than a fourth threshold and less than the third threshold, determining that the target storage region type to be accessed by the first transaction access is the second type.

[0014] In some embodiments, determining the target storage region type to be accessed by the first transaction access based on a specified field in the CHI transport data packet output by the processor core and DSU includes: determining the transport transaction type based on a first field in the specified fields; and determining the target storage region type to be accessed by the first transaction access based on the transport transaction type.

[0015] In some embodiments, the multiple storage region types include a first type and a second type. Based on the storage region types accessed by historical transactions within a preset time period before the first transaction accesses, the target storage region type to be accessed by the first transaction is determined, including: if the number of historical transactions accessing the first type is greater than the number of historical transactions accessing the second type within the preset time period, the target storage region type to be accessed by the first transaction is determined to be the first type; if the number of historical transactions accessing the first type is less than the number of historical transactions accessing the second type within the preset time period, the target storage region type to be accessed by the first transaction is determined to be the second type.

[0016] In some embodiments, the multiple storage region types include a first type and a second type. Determining the target storage region among the multiple storage regions included in the target storage region type based on the address accessed by the first transaction includes: performing a bitwise AND operation on the valid high-order segment of the address accessed by the first transaction and a mask, followed by XOR reduction to determine a first value of the bit sequence, where the bit sequence includes multiple bits; when the target storage region type is the first type, the multiple values ​​of the bit sequence correspond to multiple storage regions of the first type, and the storage region corresponding to the first value is determined as the target valid region; the target valid region includes multiple storage sub-regions. A bitwise AND operation is performed on the address accessed by the first transaction and a first partition mask, followed by XOR reduction to determine a first parameter; a bitwise AND operation is performed on the address segment of the first transaction and a second partition mask, followed by XOR reduction to determine a second parameter; the target storage sub-region among the multiple storage sub-regions is determined based on the first parameter and the second parameter; when the target storage region type is the second type, the multiple values ​​of the bit sequence correspond to multiple storage regions of the second type, and the storage region corresponding to the first value is determined as the target valid region.

[0017] Another embodiment of this application proposes a storage region wake-up device, comprising: a type determination module, configured to predict, from multiple storage region types, the type of target storage region to be accessed by a first transaction initiated by the processor based on internal processor information; a region determination module, configured to determine, based on the address of the first transaction access, the target storage region to be accessed among multiple storage regions included in the target storage region type; and a wake-up module, configured to generate a wake-up signal to wake up the target storage region if the target storage region is in a dormant state.

[0018] In another aspect of this application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the memory region wake-up method as described in the foregoing aspect.

[0019] Another aspect of this application provides a chip including an interface circuit and a processing circuit coupled to each other, the interface circuit being used to input or output signals, and the processing circuit being configured to perform the memory region wake-up method as described in the preceding aspect.

[0020] In another aspect, this application provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the memory region wake-up method as described in the foregoing aspect.

[0021] Another aspect of this application provides a computer program product having a computer program stored thereon, which, when executed by a processor, implements the memory region wake-up method as described in the foregoing aspect.

[0022] The storage area wake-up method, apparatus, electronic device, chip, and storage medium proposed in this application can predict the target storage area accessed by a transaction based on the processor's internal information, so as to generate a wake-up signal in advance when the target storage area is in a dormant state, thereby improving the efficiency of the processor accessing the storage area, reducing latency, and improving the user experience.

[0023] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic diagram of the structure of a SoC chip provided for an exemplary embodiment of this application; Figure 2A schematic flowchart illustrating a memory region wake-up method provided for an exemplary embodiment of this application; Figure 3 A schematic diagram of another memory region wake-up method provided for an exemplary embodiment of this application; Figure 4 A schematic diagram of yet another memory region wake-up method provided for an exemplary embodiment of this application; Figure 5 A schematic diagram of yet another memory region wake-up method provided for an exemplary embodiment of this application; Figure 6 A schematic diagram of a storage area wake-up device provided for an exemplary embodiment of this application; Figure 7 A schematic diagram of the structure of an electronic device provided for an exemplary embodiment of this application; Figure 8 This is a schematic diagram of the structure of a chip proposed in an exemplary embodiment of this application. Detailed Implementation

[0025] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0026] With advancements in chip design and manufacturing processes, the operating speed of the Central Processing Unit (CPU) has increased significantly. However, the latency of main memory access has not kept pace. The CPU operates at clock frequencies of several GHz, while the access time to main memory is tens or even hundreds of ns. The speed gap between CPU operation and memory access is growing exponentially, making main memory increasingly unable to keep up with the speed at which the CPU processes data. This problem is commonly referred to in the industry as the "memory wall." The solution is to add a multi-level Static Random Access Memory (SRAM) cache between the processor and Double Data Rate (DDR) main memory to bridge the huge speed "gap" between the CPU and DRAM. This structure is a multi-level memory structure commonly used in modern processor design.

[0027] SRAM cache is an integrated circuit with a simple storage array structure. It does not require refresh circuitry during operation, resulting in significantly lower access latency compared to DRAM main memory. Caches are typically organized in a hierarchical structure of 1 to 3 levels, commonly seen in processors as L1 cache, L2 cache, and system layer cache. The characteristics of multi-level caches are that lower-level caches are closer to the processor core, are faster, and have smaller capacities, generally completing access within a few cycles. To allow the processor to simultaneously fetch instructions and access program data, two L1 caches are typically designed internally: one for storing program instructions and one for storing program data. Higher-level storage tiers are further from the core and are usually shared by multiple cores. These caches have larger spaces, but the increased interconnect latency and the need for larger decoders and multiplexers slow down access speeds.

[0028] Modern processor design utilizes the principle of locality to move data that is expected to be used repeatedly within a certain period from more distant main memory to SRAM cache. There are two types of locality: temporal locality and spatial locality. Temporal locality means that if certain data is accessed, it is likely to be accessed again in the near future. Spatial locality means that if certain data is accessed, data at adjacent addresses is likely to be accessed soon as well.

[0029] Therefore, in practice, during program execution, the processor only accesses a small portion of its memory space for a given period of time, and all program execution processes access only a subset of its own data. Within a given timeframe, when executing specific code segments, the program typically exhibits a degree of predictability and continuity in its address accesses. It can be assumed that, within a given period, the processor often only needs to access lower-level caches to support the program's normal operation.

[0030] When higher-level system-level caches and main memory rank have not been accessed for a long time, the SoC chip controller will switch the memory areas that have not been accessed for a long time to a low-power state in order to reduce the overall chip power consumption and improve energy efficiency.

[0031] In related technologies, for DRAM-type volatile memory devices, when in a low-power self-refresh mode, the clocks of most of the internal logic circuits are turned off to save power, with only the periodic refresh circuits that maintain data integrity operating. If the processor runs a section of code where the program instructions or data are not found in the lower-level cache, it needs to access a higher-level memory region that is already in a dormant state. However, switching the memory from dormant to active state requires re-enabling the clock to restore the logic circuits, introducing a wait time of several microseconds.

[0032] Additionally, if Random Access Memory (RAM) that has not been accessed for a long time enters a deep sleep state, the cached data stored in this RAM will be lost. When data in the deep sleep storage device needs to be accessed, the storage device needs to be woken up and the data on the closed RAM needs to be rebuilt. This process usually takes tens of microseconds, and the processor needs to wait even longer.

[0033] Whether RAM is in a light sleep or deep sleep mode, when a processor access command arrives, it hinders the processor from running the program normally. The response latency of the command reduces the processor's performance, thus affecting the user experience. The fast wake-up module predicts the area the processor will access and uses high-level metal hardwires to wake up the memory area in a low-power state before the processor's transaction arrives. This reduces the latency of the processor accessing memory, improves CPU access performance, and thus improves the user experience.

[0034] In related technologies, storage devices enter a sleep state to reduce power consumption when they are not accessed for a period of time. In this sleep state, most of the logic circuitry is shut down, maintaining only the data, or the cached data is lost. When access to the storage device is needed, the logic circuitry must be restored or the cached data rebuilt before normal data access can occur. Using the transaction's accompanying valid bit signal as a wake-up signal for the storage area results in a close proximity between the wake-up signal and the transaction's arrival time in the storage area, leading to minimal performance gains and prolonged waiting times, thus negatively impacting the user experience.

[0035] Based on this, this application proposes a storage region wake-up method, apparatus, electronic device, chip, and storage medium. The method includes: predicting the target storage region type to be accessed by a first transaction initiated by the processor from multiple storage region types based on processor internal information; determining the target storage region to be accessed from multiple storage regions included in the target storage region type based on the address of the first transaction access; and generating a wake-up signal to wake up the target storage region if it is in a dormant state. Thus, the target storage region for transaction access can be predicted based on processor internal information, allowing for the early generation of a wake-up signal even when the target storage region is in a dormant state. The wake-up signal arrives at the storage region much earlier than the transaction access, enabling early wake-up of dormant storage regions, reducing processor latency in accessing storage regions, and improving the user experience.

[0036] The following description, with reference to the accompanying drawings, describes a storage region wake-up method, apparatus, electronic device, chip, and storage medium according to embodiments of this application.

[0037] Before introducing the memory region wake-up method provided in the embodiments of this application, we will first introduce the system-on-chip (SoC) chip system to which the memory region wake-up method provided in the embodiments of this application is applicable.

[0038] like Figure 1 As shown, the SoC chip includes: a central processing unit (CPU), a system level cache (SLC), double data rate synchronous dynamic random access memory (DDR), and a (Unified Bus, UB) bus. The CPU includes a fastwakeup module.

[0039] In some embodiments, the memory region wake-up method provided in this application is executed by the fast wake-up module.

[0040] In some embodiments, the CPU and processor can be interchanged. The storage area and storage device can be interchanged.

[0041] It should be noted that, Figure 1 The structure of the SoC chip shown in the example is for illustrative purposes only and is not intended to limit the specific embodiments of this application. The SoC chip may also include other structures besides those shown in the figure. Figure 1 The various structures can be directly connected or indirectly connected through other structures.

[0042] Figure 2 This is a schematic flowchart of a memory region wake-up method provided for an exemplary embodiment of this application.

[0043] It should be noted that the memory region wake-up method of this application embodiment can be applied to a memory region wake-up device. In some possible embodiments, the memory region wake-up device can be configured in an electronic device or a chip so that the electronic device or chip can perform the memory region wake-up function. In addition, in some possible embodiments, the memory region wake-up device can also be software in an electronic device.

[0044] In any embodiment of this application, the chip can be integrated into an electronic device. The chip includes a Central Processing Unit (CPU), an Image Signal Processing (ISP), an Application-Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), a System-on-Chip (SOC), a Reduced Instruction Set Computer (RISC), etc., which will not be listed here.

[0045] The electronic devices mentioned include, but are not limited to, terminals and personal computers. A terminal is a user-side entity used to receive or transmit signals, such as a mobile phone. Terminals can also be called terminal equipment (UE), user equipment (UE), mobile station (MS), mobile terminal equipment (MT), etc. Terminals can be communication-enabled vehicles, smart cars, mobile phones, wearable devices, tablets, computers with wireless transceiver capabilities, virtual reality (VR) terminals, augmented reality (AR) terminals, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and so on. The embodiments of this application do not limit the specific technology or device form used in the terminal.

[0046] like Figure 2 As shown, the memory region wake-up method may include, but is not limited to, the following steps: S201, based on internal processor information, predicts the target storage region type to be accessed by the first transaction initiated by the processor from multiple storage region types.

[0047] In some embodiments, the storage area type includes multiple types, including a first type and a second type.

[0048] In some embodiments, the first type is DDR. In some embodiments, the second type is SLC.

[0049] In this embodiment of the application, based on the processor's internal information, the target storage region type to be accessed by the first transaction initiated by the processor is predicted from multiple storage region types.

[0050] In this application, relevant information is collected starting from inside the processor to obtain internal processor information. Based on the internal processor information, the target storage region type to be accessed by the first transaction initiated by the processor can be predicted from multiple storage region types.

[0051] In some embodiments, the processor is a CPU.

[0052] In some embodiments, the first transaction access is a transaction access that the processor is about to initiate, or a transaction access that is being initiated, or a transaction access that has already been initiated.

[0053] In some embodiments, the target storage region type to be accessed by the first transaction initiated by the processor is predicted from multiple storage region types based on internal processor information, including: determining the target storage region type to be accessed by the first transaction using any one of mode 1, mode 2, mode 3, mode 4, mode 5, and mode 6; or predicting according to a specified priority order of multiple modes 1, mode 2, mode 3, mode 4, mode 5, and mode 6 until the target storage region type to be accessed by the first transaction is determined.

[0054] In this application, any one of the following methods—method 1, method 2, method 3, method 4, method 5, and method 6—is used to determine the target storage area type required for the first transaction access.

[0055] In this application, predictions are made according to the specified priority order of multiple methods, including method one, method two, method three, method four, method five, and method six, until the target storage area type to be accessed by the first transaction is determined.

[0056] In some embodiments, predictions are performed according to a specified priority order of Method 1 and Method 2 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is either Method 1 (highest) or Method 2 (lowest), or vice versa.

[0057] In one implementation, with the priority order being highest for Method 1 and lowest for Method 2, if Method 1 can determine the type of the target storage area to be accessed by the first transaction, then Method 2 is not needed for prediction; if Method 1 fails to determine the type of the target storage area to be accessed by the first transaction, then Method 2 is used to predict and determine the type of the target storage area to be accessed by the first transaction.

[0058] In some embodiments, prediction is performed according to a specified priority order of Method 1 and Method 3 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 1 highest, Method 3 lowest, or vice versa. In some embodiments, prediction is performed according to a specified priority order of Method 1 and Method 4 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 1 highest, Method 4 lowest, or vice versa. In some embodiments, prediction is performed according to a specified priority order of Method 1 and Method 5 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 1 highest, Method 5 lowest, or vice versa. In some embodiments, prediction is performed according to a specified priority order of Method 1 and Method 6 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 1 highest, Method 6 lowest, or vice versa. In some embodiments, prediction is performed according to a specified priority order of Method 2 and Method 3 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 2 highest, Method 3 lowest, or vice versa. In some embodiments, prediction is performed according to the specified priority order of Methods 2 and 4 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 2 highest, Method 4 lowest, or vice versa. In some embodiments, prediction is performed according to the specified priority order of Methods 2 and 5 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 2 highest, Method 5 lowest, or vice versa. In some embodiments, prediction is performed according to the specified priority order of Methods 2 and 6 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 2 highest, Method 6 lowest, or vice versa. In some embodiments, prediction is performed according to the specified priority order of Methods 3 and 4 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 3 highest, Method 4 lowest, or vice versa. In some embodiments, prediction is performed according to the specified priority order of Methods 3 and 5 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is Method 3 highest, Method 5 lowest, or vice versa. In some embodiments, prediction is performed according to the specified priority order of methods three and six until the target storage region type to be accessed by the first transaction is determined. The specified priority order is that method three is the highest and method six is ​​the lowest, or vice versa. In some embodiments, prediction is performed according to the specified priority order of methods four and five until the target storage region type to be accessed by the first transaction is determined. The specified priority order is that method four is the highest and method five is the lowest, or vice versa.In some embodiments, prediction is performed according to the specified priority order of methods four and six until the target storage region type to be accessed by the first transaction is determined. The specified priority order is that method four is the highest and method six is ​​the lowest, or vice versa. In some embodiments, prediction is performed according to the specified priority order of methods five and six until the target storage region type to be accessed by the first transaction is determined. The specified priority order is that method five is the highest and method six is ​​the lowest, or vice versa.

[0059] In some embodiments, predictions are performed according to a specified priority order of Mode 1, Mode 2, Mode 3, Mode 4, Mode 5, and Mode 6 until the target storage region type to be accessed by the first transaction is determined. The specified priority order is: Mode 1 is the highest, followed by Mode 2, then Mode 3, then Mode 4, then Mode 5, and finally Mode 6 is the lowest.

[0060] It should be noted that the above embodiments are not exhaustive, and this application supports the use of methods including but not limited to the above methods to determine the type of target storage area to be accessed by the first transaction.

[0061] Method 1: Determine the type of target storage area to be accessed by the first transaction based on the exception level switching information when the processor core executes instructions.

[0062] Method 2: Determine the type of target storage area to be accessed by the first transaction based on the instruction information executed by the processor core.

[0063] Method 3: Determine the type of target storage area to be accessed by the first transaction based on the jump direction prediction information in the processor's instruction fetch unit.

[0064] Method 4: Determine the target storage region type to be accessed by the first transaction based on the address and address type of the first transaction, as well as the differences in the historical access addresses of a preset number of historical transactions of the same address type before the first transaction.

[0065] Method 5: Determine the target storage area type to be accessed by the first transaction based on the specified fields in the CHI transport data packet output by the processor core and DSU.

[0066] Method 6: Based on the storage area types accessed by historical transactions within a preset time period before the first transaction accesses, determine the target storage area type to be accessed by the first transaction.

[0067] In some embodiments, the multiple storage region types include a first type and a second type. Method 1: Determining the target storage region type to be accessed by the first transaction based on the exception level switching information when the processor core executes instructions includes: determining whether a security state switch has occurred based on the exception level switching information; if a security state switch has occurred, determining that the target storage region type to be accessed by the first transaction is the first type; if no security state switch has occurred, determining whether an exception level switch has occurred; if an exception level switch has occurred, obtaining the first address of the first transaction access and the second address of the second transaction access before the exception switch, and determining the target storage region type to be accessed by the first transaction based on the first address and the second address.

[0068] In some embodiments, the anomaly level switching information is used to indicate a safe state, an unsafe state, and an anomaly level.

[0069] In some embodiments, the anomaly levels include four types: EL0: User mode, running software for the vast majority of end users. These applications run in a restricted environment to reduce their potential threats to system security and stability; EL1: Operating system kernel mode, where the operating system kernel runs so that it can perform direct operations on hardware resources and manage the global state of the system; EL2: Hypervisor mode. The hypervisor controls the allocation of physical resources to virtual machines and manages their execution, providing a safe and efficient way to increase hardware utilization and support software isolation. EL3: TrustZone. EL3 is used to implement a secure execution environment, protecting sensitive operations and data from interference from other system parts.

[0070] In this application, when the processor core executes instructions, its exception level switching information is sampled and latched.

[0071] In some embodiments, determining the target storage region type to be accessed by the first transaction access based on the first address and the second address includes: subtracting the first address and the second address; if the difference is greater than a first threshold, determining the target storage region type to be accessed by the first transaction access to be a first type; if the difference is greater than a second threshold and less than the first threshold, determining the target storage region type to be accessed by the first transaction access to be a second type.

[0072] In some embodiments, the first threshold is a set threshold for determining access to a first type of storage region, and the second threshold is a set threshold for determining access to a second type of storage region. In some embodiments, the difference between the first address and the second address is calculated by subtracting the high-order bits of the first address and the high-order bits of the second address.

[0073] For example, in the step-by-step switching scenario between EL0 and EL2, the execution instruction address before and after the exception level switch is recorded. The instruction address before and after the exception level switch is subtracted. If the result is greater than the set threshold for determining access to SLC and less than the set threshold for determining access to DDR, the SLC wake-up flag signal is enabled. If the result is greater than the set threshold for determining access to DDR, the DDR wake-up flag signal is enabled. In some embodiments, a flag signal is used to enable DDR wake-up for switching between insecure and secure states.

[0074] As mentioned above, among the four anomaly levels, in most cases, when there is no security state switching involved, the switching of anomaly levels follows a step-by-step jump rule, i.e., EL0->EL1->EL2 or EL2->EL1->EL0. In similar step-by-step jump scenarios, the fast wake-up module records the address before and after the anomaly level switching, calculates the difference between the two addresses, and if the result is greater than the set threshold for determining access to SLC and less than the set threshold for determining access to DDR, then the wake-up flag signal for SLC is enabled; if the result is greater than the set threshold for determining access to DDR, then the wake-up flag signal for DDR is enabled.

[0075] When a switch to a secure state is involved, i.e., from a non-secure state to a secure state, the processor needs to call the EL3 security handling code. At this time, a relatively large code discontinuity occurs. In this embodiment of the application, it is predicted that the instructions and data required for the processor to run need to be obtained from main memory, enabling the wake-up signal of DDR.

[0076] In some embodiments, Method 2: Determining the type of the target storage area to be accessed by the first transaction access based on the instruction information executed by the processor core includes: determining whether the instruction executed by the processor core is a special instruction based on the instruction information executed by the processor core; if it is a special instruction, obtaining the first instruction address of the instruction preceding the special instruction and the second instruction address of the special instruction, and determining the type of the target storage area to be accessed by the first transaction access based on the first instruction address and the second instruction address.

[0077] In some embodiments, the special instructions include at least one of the following: exception instructions, exception return instructions, interrupt instructions, interrupt return instructions, and unpredictable jump instructions.

[0078] In some embodiments, the difference between the first instruction address and the second instruction address is the difference between the high-order bits of the first instruction address and the high-order bits of the second instruction address.

[0079] In some embodiments, the overall pipeline structure of a processor (CPU) can generally be summarized as Instruction Fetch, Instruction Decode, Instruction Execute, Memory Access, and Write-Back. The DPU unit is a module in the processor that completes the decoding, execution, memory access, and write-back steps.

[0080] It should be noted that, for ease of description, this application uses the five-stage pipeline, which is most frequently mentioned in computer architecture, as an example to illustrate the principle. Different processor microarchitecture designs may have different pipeline depths, and the embodiments of this application do not impose specific limitations on this.

[0081] During the instruction execution phase, the system retrieves the instructions that will be executed in the pipeline and identifies special instructions to predict the discontinuity of access addresses.

[0082] In this application, the instruction set implemented by the processor microarchitecture is classified, and instructions such as exception instructions, exception return instructions, interrupt instructions, interrupt return instructions, and uninferable jump instructions are classified as special instructions.

[0083] In some embodiments, determining the target storage region type to be accessed by the first transaction access based on the first instruction address and the second instruction address includes: subtracting the first instruction address and the second instruction address; if the difference is greater than a first threshold, determining the target storage region type to be accessed by the first transaction access to be a first type; if the difference is greater than a second threshold and less than the first threshold, determining the target storage region type to be accessed by the first transaction access to be a second type.

[0084] In some embodiments, the difference between the first instruction address and the second instruction address is the difference between the high-order bits of the first instruction address and the high-order bits of the second instruction address.

[0085] In this application, the instruction addresses before and after executing these special instructions are recorded. The difference between the two addresses before and after the special instruction is calculated. If the result is greater than the set threshold for determining access to SLC and less than the set threshold for determining access to DDR, the SLC wake-up flag signal is enabled. If the result is greater than the set threshold for determining access to DDR, the DDR wake-up flag signal is enabled.

[0086] For example, when the execution unit executes an exception instruction, the processor's program pointer (PC) points to the entry address of the corresponding exception handler in the next clock cycle. The processor then runs the exception handler. The difference between the entry address of the exception handler and the address before entering the exception handler is calculated. If the result is greater than the set threshold for determining access to the SLC and less than the set threshold for determining access to the DDR, the SLC wake-up flag signal is enabled. If the result is greater than the set threshold for determining access to the DDR, the DDR wake-up flag signal is enabled.

[0087] For example, when the execution unit runs to the last instruction of the exception handler, that is, the exception return instruction, the processor's program pointer (PC) points to the address before jumping into the exception handler in the next clock cycle. At this time, a discontinuity in the running code will also occur. The difference between the address of the exception return instruction and the address before jumping into the exception handler is calculated. If the result is greater than the set threshold for determining access to SLC and less than the set threshold for determining access to DDR, the SLC wake-up flag signal is enabled. If the result is greater than the set threshold for determining access to DDR, the DDR wake-up flag signal is enabled.

[0088] It should be noted that when the execution unit executes an interrupt instruction, an interrupt return instruction, or an unpredictable jump instruction, the fast wake-up module handles the situation in a similar way to when the execution unit executes an exception instruction. It calculates the difference between the addresses before and after the jump in the code segment and determines the corresponding wake-up signal to be enabled based on the result of the difference.

[0089] In some embodiments, Method 3: Determining the type of target memory region to be accessed by the first transaction access based on the jump direction prediction information in the processor's instruction fetch unit includes: determining whether the direction of the predicted branch instruction is a jump based on the jump direction prediction information; if the direction of the predicted branch instruction is a jump, determining the third instruction address of the current instruction and the fourth instruction address of the predicted branch instruction, and determining the type of target memory region to be accessed by the first transaction access based on the third instruction address and the fourth instruction address.

[0090] To reduce pipeline cavitation and thus improve performance, modern processors typically employ branch prediction in their instruction fetch units. The branch predictor forecasts whether a branch instruction will result in a jump and the destination address of that jump.

[0091] In some embodiments, the current instruction is the instruction of the current beat, and the predicted branch instruction is the instruction of the next beat predicted after the current beat.

[0092] In some embodiments, determining the target storage region type to be accessed by the first transaction access based on the third instruction address and the fourth instruction address includes: taking the difference between the third instruction address and the fourth instruction address; if the difference is greater than a first threshold, determining the target storage region type to be accessed by the first transaction access to be a first type; if the difference is greater than a second threshold and less than the first threshold, determining the target storage region type to be accessed by the first transaction access to be a second type.

[0093] In some embodiments, the difference between the third instruction address and the fourth instruction address is the difference between the high-order bits of the third instruction address and the high-order bits of the fourth instruction address.

[0094] In this application, the fast wake-up module samples and latches the jump direction prediction information in the instruction fetch unit in the previous and next two cycles, and then parses the instruction information in the previous and next two cycles. When the branch predictor in the instruction fetch unit predicts that the direction of the branch instruction is a jump, and the difference between the predicted jump address and the address of the previous instruction exceeds the first threshold, it is determined that the subsequent instruction cannot be obtained from the local cache, and the wake-up signals of the UB bus and DDR need to be enabled.

[0095] In some embodiments, the multiple storage region types include a first type and a second type. The target storage region type to be accessed by the first transaction is determined based on the address and address type accessed by the first transaction, and the differences in historical access addresses of a preset number of historical transactions belonging to the address type prior to the first transaction access. This includes: The address type of the address accessed by the first transaction is determined to be an instruction address. The address accessed by the first transaction is subtracted from the historical instruction addresses of a preset number of historical accesses that belong to instruction addresses before the first transaction accesses one by one. If the difference is greater than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the first type. If the difference is greater than the second threshold and less than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the second type. The address type of the address accessed by the first transaction is determined to be a data address. The address accessed by the first transaction is then subtracted from the addresses of the historical instructions that were previously data addresses by the first transaction. If the difference is greater than the third threshold, the target storage area type to be accessed by the first transaction is determined to be the first type. If the difference is greater than the fourth threshold and less than the third threshold, the target storage area type to be accessed by the first transaction is determined to be the second type.

[0096] In this application, predicting the memory region accessed by the first transaction based on access address differences includes: establishing two register buffers with configurable depth and width, used to store the high-order bits of instruction addresses and the high-order bits of data addresses accessed within a certain period of time, respectively. After the chip powers on, the processor's access addresses are accumulated over a period of time. Once the two register buffers are filled, it indicates that address collection is complete, and this address information can be used to begin predicting the processor's memory region access. The address of the first transaction access is classified according to its attribute. If it is an instruction address, the high-order bits of the instruction address are extracted and subtracted from all addresses already cached in the instruction buffer (i.e., the historical instruction addresses of the preset number of historical accesses that belong to the instruction address before the first transaction access). If the result is greater than the set SLC threshold for determining access and less than the set DDR threshold for determining access, the SLC wake-up flag signal is enabled. If the result is greater than the set DDR threshold for determining access, the DDR wake-up flag signal is enabled. If it is a data address, the high-order bits of the data address are extracted and subtracted from all addresses already cached in the data buffer. If the result is greater than the set SLC threshold for determining access and less than the set DDR threshold for determining access, the SLC wake-up flag signal is enabled. If the result is greater than the set DDR threshold for determining access, the DDR wake-up flag signal is enabled. At the same time, if the difference meets the judgment condition, the latest address is used to replace the oldest address in the buffer. The replacement logic is the same for both the instruction buffer and the data buffer.

[0097] For example, such as Figure 3 As shown, based on address difference comparison, the predicted memory region to be accessed is quickly woken up. The locations for obtaining the transfer address are at the core exit and the DSU exit, respectively. The prediction results at each location are merged and output within the quick wake-up module. Spatial locality is one of the core principles of modern CPU cache design, and together with temporal locality, it forms the theoretical basis for efficient cache operation. Essentially, when a program accesses certain data, it is very likely to access adjacent data in the near future. CPU caches significantly improve data access efficiency by utilizing this characteristic. Therefore, it can be determined that when the newly initiated access address differs significantly from previously accessed addresses, the target memory region of this access is large, and it is highly unlikely to hit the data in the cache. Therefore, in this embodiment, the target region of this access is determined to be DDR, and the UB bus wake-up and DDR wake-up flag signals need to be enabled.

[0098] In some embodiments of this application, two address buffers with a depth of 16 and a width of 20 bits are established to cache instruction addresses and data addresses, respectively. When txreqflitv is set, the instruction address and data address are sampled and latched. Here, in order to represent that the address span of the later access is larger than that of the previous access, the lower 20 bits of the address need to be truncated. The address difference is compared with MB as the granularity.

[0099] At the initial power-on stage of the chip, the data in the two buffers has not yet been fully collected. The address difference judgment logic is not enabled at this stage. After the program has been running for a period of time, when the two buffers reach full capacity, the address difference judgment logic is enabled.

[0100] In some embodiments of this application, the CPU initiates a new transmission access address, and the new access address is subtracted from all addresses cached in the corresponding buffer according to the instruction address attribute or data address attribute. A configurable address difference threshold is set between the two registers. If the result of each subtraction exceeds the set address difference threshold, the address range of this access is determined to be large.

[0101] In this embodiment, two address difference thresholds are named addr_diff_slc and addr_diff_ddr, respectively, satisfying the condition addr_diff_ddr > addr_diff_slc. When the absolute value of all the differences is greater than addr_diff_slc and less than addr_diff_ddr, the target memory region to be accessed is determined to be SLC, and the UB bus wake-up and SLC wake-up flag signals need to be enabled. When the absolute value of all the differences is greater than addr_diff_ddr, the target memory region to be accessed is determined to be DDR memory, and the UB bus wake-up and DDR wake-up flag signals need to be enabled. The address difference thresholds described in this example can be flexibly configured. All other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention.

[0102] Each time the result of all the above-mentioned subtractions exceeds the address difference threshold, the oldest address stored in the instruction address buffer or data address buffer needs to be removed, and the newly acquired address is stored in the instruction address buffer or data address buffer. This updates the addresses in the two buffers, thereby improving the accuracy of predicting the target storage area.

[0103] It is important to note that in the specific implementation of a SoC chip, a deeper and wider buffer for collecting transmission addresses represents more historical experience collected, resulting in more accurate predictions. However, this leads to increased area overhead. Conversely, a shallower and narrower buffer reduces prediction accuracy while decreasing area overhead. The overall implementation can be traded off based on the specific SoC chip. For ease of description and brevity, this embodiment uses a buffer with a depth of 16 bits and a width of 20 bits as an example. In practical applications, various reasonable values ​​can be used for this depth and width, and such differences in implementation should not be considered beyond the scope of this application.

[0104] In some embodiments, Method 5: Determining the target storage region type to be accessed by the first transaction based on a specified field in the CHI transport data packet output by the processor core and DSU includes: determining the transport transaction type based on a first field in the specified fields; and determining the target storage region type to be accessed by the first transaction based on the transport transaction type.

[0105] This application discloses a method for predicting the storage area accessed by a transaction based on the transaction type initiated by the processor. The specific steps include: when the processor initiates access, sampling the opcode field representing the transaction type, the memory attribute field (memattr) field, the field indicating how the receiving node allocates physical buffers to process the incoming transaction (pbha) field, and the field indicating whether a Table Walk (subsource) is initiated from the AMBA CHI bus. Key information about the transmission transaction is extracted from these fields, identifying ReadNoSnp, PreFetchTgt, and Table Walk transactions. Combining this with the CHI protocol's principle of automatically maintaining multi-core cache consistency, the data routing of the transaction is predicted, thereby selectively waking up the bus, system-level cache, and DDR.

[0106] For example, such as Figure 4 As shown, based on the type of transfer transaction initiated by the CPU, the fast wake-up module predicts the memory area to be accessed. The CHI transfer data packets are obtained at the core exit and the DSU exit, respectively. The prediction results from these two locations are merged and output within the fast wake-up module. It is necessary to sample the CHI transfer data packets when txreqflitv is set, and parse and latch the fields txreqflit.opcode, txreqflit.memattr, txreqflit.pbha, and txreqflit.subsource that help predict the memory area to be accessed.

[0107] Specifically, by identifying the `txreqflit.opcode` field, transmission transactions can be filtered. Combined with the requirements of CHI protocol cache management and data consistency maintenance, ReadNoSnp, PreFetchTgt, and TableWalk transactions can be identified. These transaction types are helpful in predicting the cache areas to be accessed.

[0108] For ReadNoSnp transactions, as defined by the CHI protocol, these read transactions do not require snooping or other caching during transmission. They are mainly used for reading non-cacheable data or data in device memory, data that is known not to be cached in other locations, and data that does not require consistency maintenance.

[0109] The typical process for this type of transaction is as follows: The Requester issues a ReadNoSnp request; the request is directly routed to the target; the target returns a data response without involving any consistency operations.

[0110] txreqflit.pbha is a user-defined field in the AMBA CHI (Coherent Hub Interface) protocol. Its main function is to instruct the receiving node how to allocate physical buffers to handle incoming transactions. In this embodiment, txreqflit.opcode and txreqflit.pbha are used together. When the transaction type is identified as ReadNoSnp and txreqflit.pbha is equal to 0, it can be determined that the transmission accesses DDR and does not need to access SLC to maintain cache consistency. Therefore, it is only necessary to enable the wake-up flags for the ub bus and ddr.

[0111] In the transaction type indicated by txreqflit.opcode, the PreFetchTgt transaction is a prefetch transaction defined in the AMBA CHI (Coherent Hub Interface) protocol. It is primarily used to proactively prefetch data into the target cache to optimize subsequent access performance. In this embodiment, for the PreFetchTgt transaction, it can be determined that this transmission accesses DDR, and there is no need to access SLC to maintain cache consistency. Therefore, it is only necessary to enable the wake-up flags for the ub bus and DDR.

[0112] In the transaction type indicated by txreqflit.opcode, for non-Snoopable transactions, in this embodiment, when it is recognized that txreqflit.pbha is not equal to 0, it can be determined that this transmission accesses the SLC and does not need to access the DDR. Therefore, it is only necessary to enable the wake-up (flag) signal of the UB bus and the SLC.

[0113] `txreqflit.memattr` is a key field in the AMBA CHI (Coherent Hub Interface) protocol, used to define the attributes and behavior of memory access. It affects transaction caching strategies, access permissions, memory types, and consistency management. `txreqflit.memattr` is a cacheable bit, indicating whether the transmission is cacheable. When `txreqflit.memattr` equals 0, it indicates non-cacheable, meaning the receiving node does not need to look up the requested data in its cache. `txreqflit.memattr` is also a device bit, indicating whether the receiving node is of Normal Memory or Device Memory type. `txreqflit.memattr` equals 0, indicating Normal memory type. In this embodiment, for transactions that are Non-Cacheable and access Normal memory, it can be determined that the transmission accesses DDR, and there is no need to access SLC to maintain cache consistency. Therefore, only the wake-up flags for the UB bus and DDR need to be enabled.

[0114] When the `txreqflit.srcattr.subsource` field equals 2'b10, it indicates that the current transfer involves a table walk (page table traversal). Table Walk is a key mechanism in the CHI protocol that works in conjunction with the Memory Management Unit (MMU) to handle page table lookup operations during address translation. When a TLB (Translation Lookaside Buffer) miss occurs, the system needs to access the page table via Table Walk to obtain the mapping from virtual to physical addresses. Therefore, in this embodiment, when `txreqflit.srcattr.subsource` is detected to be equal to 2'b10, the count of the `datasrc` module at the same time is observed. If `cnt_acc_slc` is greater than `cnt_acc_ddr`, it indicates that the majority of hits in the past period were for the SLC, corresponding to enabling the SLC wake-up flag. If `cnt_acc_slc` is less than `cnt_acc_ddr`, it indicates that the majority of hits in the past period were for the DDR, corresponding to enabling the DDR wake-up flag.

[0115] It should be noted that the AMBA CHI protocol is updated to different versions, and the data structure of the transmission data packets described above may differ in different versions of the CHI protocol. The meaning of the field values ​​may also differ in different versions of the protocol. However, those skilled in the art will clearly understand that, for the sake of convenience and brevity, the differences in data structure and field values ​​caused by the protocol version should not be considered to be beyond the scope of this application.

[0116] In some embodiments, the multiple storage region types include a first type and a second type. Method Six: Based on the storage region types accessed by historical transactions within a preset time period before the first transaction accesses, determine the target storage region type to be accessed by the first transaction, including: if the number of historical transactions accessing the first type is greater than the number of historical transactions accessing the second type within the preset time period, determine the target storage region type to be accessed by the first transaction as the first type; if the number of historical transactions accessing the first type is less than the number of historical transactions accessing the second type within the preset time period, determine the target storage region type to be accessed by the first transaction as the second type.

[0117] In this embodiment, predicting the storage area accessed by a transaction based on historical data sources acquired by the processor includes the following specific steps: Establishing a counting window for historical data sources of the processor over a statistical period. Recording the total number of transactions initiated by the processor (cnt_acc_all), the number of data sources from SLC (cnt_acc_slc), and the number of data sources from DDR (cnt_acc_ddr) within this statistical window. At the last frame of the statistical window, based on the distribution of historical data sources, and utilizing the principle of temporal locality of access to the processor cache, predicting the storage area accessed by the next transaction. If the analysis of the statistical data source distribution shows that the trend of the processor accessing SLC is greater than the trend of accessing DDR over a past period, then the SLC wake-up flag is enabled; otherwise, the DDR wake-up flag is enabled.

[0118] For example, such as Figure 5 As shown, historical data distribution information is collected to predict the wake-up memory region. A mapping relationship between bus feedback Data Sources and memory regions is defined. These Data Source values ​​determine which data originates from the System Layer Cache (SLC) and which from DDR. Utilizing the spatial locality principle of the cache, the next access location of the CPU is predicted. To statistically analyze the distribution of data sources over a period of time, three counters are set: cnt_acc_all, cnt_acc_slc, and cnt_acc_ddr. Counter cnt_acc_slc counts data from the SLC, counter cnt_acc_ddr counts data from the DDR, and counter cnt_acc_all counts the total amount of data accessed. When cnt_acc_all reaches its configured period, the access statistics window is closed, all counters are cleared, and a new access statistics window begins. The width of the access statistics window is configurable. At the last access of each access statistics window, compare the sizes of cnt_acc_slc and cnt_acc_ddr. If cnt_acc_slc is greater than cnt_acc_ddr, it means that the CPU has mostly accessed the SLC memory area in the past period, so the next access is more likely to be SLC. Conversely, the next access of the CPU is more likely to be DDR.

[0119] The prediction module determines whether to enable the fastwakeup_slc and fastwakeup_ddr signals based on statistical data and the current SLC and DDR states (whether they are in sleep or active states). For example: When the prediction module determines that fastwakeup_slc needs to be enabled and the SLC is currently in a working state, the fastwakeup_slc signal does not need to be enabled. When the prediction module determines that fastwakeup_slc needs to be enabled and the SLC is currently in a sleep state, then the fastwakeup_slc signal is enabled. The period for statistical data access is configurable. Each time the statistical period is reached, the prediction module makes a decision according to the set rules and resets the three counters to 0.

[0120] The wake-up signal needs to be widened; the level widening length can be configured in software to ensure correct sampling by SLC and DDR. Based on the current access address, determine which DDR region needs to be woken up; DDR is divided into Channel and Rank.

[0121] It should be noted that the statistical period cnt_acc_all described above can be flexibly configured in specific implementations to adapt to different application scenarios. Those skilled in the art can clearly understand that, for the sake of convenience and brevity, such differences in the configuration of the statistical period should not be considered to be beyond the scope of this application.

[0122] Please continue reading Figure 2 After executing S201, continue executing S202.

[0123] S202, based on the address accessed by the first transaction, determine the target storage region among the multiple storage regions included in the target storage region type.

[0124] In some embodiments, the multiple storage region types include a first type and a second type. Determining the target storage region to be accessed from among the multiple storage regions included in the target storage region type, based on the address accessed by the first transaction, includes: Perform a bitwise AND operation between the valid high-order segment of the address accessed by the first transaction and the mask code, and then perform an XOR reduction to determine the first value of the bit sequence, which includes multiple bits. When the target storage area type is the first type, multiple values ​​of the bit sequence correspond to multiple storage areas of the first type, and the storage area corresponding to the first value is determined as the target valid area. The target valid area includes multiple storage sub-areas. A bitwise AND operation is performed based on the address accessed by the first transaction and the first partition mask, and then an XOR reduction is performed to determine the first parameter. A bitwise AND operation is performed based on the address segment accessed by the first transaction and the second partition mask, and then an XOR reduction is performed to determine the second parameter. The target storage sub-area among the multiple storage sub-areas is determined based on the first parameter and the second parameter. When the target storage area type is the second type, multiple values ​​of the bit sequence correspond to multiple storage areas of the second type, and the storage area corresponding to the first value is determined to be the target valid area.

[0125] In this embodiment, considering both performance and power consumption, the SoC chip is designed with 4 SLCs: SLC0, SLC1, SLC2, and SLC3; and 4 DDRs: DDRA, DDRB, DDRC, and DDRD. Each DDR group can be further subdivided into 4 subgroups based on rank and sub-channel. For example, DDRA can be divided into ddra_rank0_sub0, ddrb_rank0_sub1, ddrc_rank1_sub0, and ddrd_rank1_sub1. Therefore, after determining whether the wake-up region is SLC or DDR based on the wake-up strategy described above, it is necessary to further distinguish which SLC or DDR group is being woken up. The interleaving address is calculated using the following formula to determine the target master port to which the data transmission is directed.

[0126] target_group[0] = ^(addr[39:6]&masterinterleave0) target_group[1] = ^(addr[39:6]&masterinterleave1) target_group[2] = ^(addr[39:6]&masterinterleave2) Each master port path is connected to corresponding SLC and DDR storage devices. The calculation result yields 3 bits of target_group information, with the value of target_group ranging from 0 to 7. The mapping relationship with the access channel is as follows: target_group=0 or 4, corresponding to the transmission links master_port0, slc0, ddra; target_group=1 or 5, corresponding to the transmission links master_port1, slc1, ddrb; target_group=2 or 6, corresponding to the transmission links master_port2, slc2, ddrc; target_group=3 or 7, corresponding to the transmission links master_port3, slc3, ddrd; If the strategy in this embodiment determines that the access is to an SLC, then the address is substituted into the above formula to calculate which SLC is being woken up. If the strategy in this embodiment determines that the access is to a DDR, then the above formula is used to calculate which of the four DDR chips is being accessed. Each DDR chip uses rank and sub_channel to distinguish four storage areas. The following formula is used to calculate the corresponding rank and sub_channel of the transaction accessing DDR.

[0127] rank = ^(addr&addr_rank_mask); sub_channel = ^(addr_subch&addr_subch_mask).

[0128] The wake-up strategy proposed in this embodiment can predict whether the target area for each access is SLC or DDR, and then further obtain the specific area for waking up SLC or DDR according to the two sets of formulas provided above.

[0129] S203, if the target storage area is in a dormant state, generate a wake-up signal to wake up the target storage area.

[0130] In this application, when the target storage area to be accessed by the first transaction is determined, if the target storage area is in a dormant state, a wake-up signal is generated to wake up the target storage area. If the target storage area is not in a dormant state, no processing is required.

[0131] In some embodiments, the hibernation state includes a shallow hibernation state and a deep hibernation state.

[0132] The memory region wake-up method provided in this application achieves better performance benefits compared to related technologies by using a valid bit signal as the signal to wake up the memory region. This method can predict the target memory region accessed by a transaction based on the processor's internal information, and generate a wake-up signal in advance when the target memory region is in a dormant state, thereby improving the efficiency of the processor accessing the memory region, reducing latency, and improving the user experience.

[0133] This application addresses the issue of storage devices entering a sleep state to reduce power consumption after a period of inactivity. In related technologies, for RAM-type storage devices, during a shallow sleep state, most logic circuits are shut down, only data is maintained. When the CPU accesses this area, it must wait for the logic circuits to wake up before normal data access can occur. However, during a deep sleep state, because RAM is volatile, the cached data stored in it disappears. When the CPU accesses this area, it needs to rebuild the data in the shut-down RAM, resulting in a longer CPU wait time and thus impacting user experience. Based on this, in the embodiments of this application, when the CPU initiates a new transmission service, it uses the fusion of six predictive wake-up strategies to predictively wake up the target storage area that the CPU will access. Since the extended wake-up signal travels along the high-layer metal traces of the chip, which is shorter than the path for requesting data, and does not require protocol conversion or flow control handshake operations, the wake-up signal will arrive at the target storage area to be accessed in advance, waking up the storage area in a dormant state in advance. Compared with the method without advance wake-up, this reduces the latency of the CPU accessing the target storage area, improves the overall performance of the SoC chip, and thus enhances the user experience.

[0134] To implement the above embodiments, this application also proposes a storage area wake-up device.

[0135] Figure 6 This is a schematic diagram of a storage area wake-up device provided for an exemplary embodiment of this application.

[0136] like Figure 6 As shown, the storage area wake-up device 1 may include: a type determination module 11, a region determination module 12, and a wake-up module 13.

[0137] Among them, the type determination module 11 is used to predict the target storage area type to be accessed by the first transaction initiated by the processor from multiple storage area types based on the processor's internal information.

[0138] The region determination module 12 is used to determine the target storage region to be accessed from among multiple storage regions included in the target storage region type, based on the address accessed by the first transaction.

[0139] The wake-up module 13 is used to generate a wake-up signal to wake up the target storage area if the target storage area is in a dormant state.

[0140] In some embodiments, the type determination module 11 is configured to: determine the type of the target storage area to be accessed by the first transaction using any one of mode 1, mode 2, mode 3, mode 4, mode 5 and mode 6; or predict according to the specified priority order of multiple modes 1, mode 2, mode 3, mode 4, mode 5 and mode 6 until the type of the target storage area to be accessed by the first transaction is determined. Method 1: Determine the type of target storage area to be accessed by the first transaction based on the exception level switching information when the processor core executes instructions; Method 2: Determine the type of target memory region to be accessed by the first transaction based on the instruction information executed by the processor core; Method 3: Determine the type of target memory region to be accessed by the first transaction based on the jump direction prediction information in the processor's instruction fetch unit (IFU). Method 4: Determine the target storage region type to be accessed by the first transaction based on the address and address type accessed by the first transaction, as well as the differences in the historical access addresses of a preset number of historical transactions that belong to the same address type as the first transaction. Method 5: Determine the target storage region type to be accessed by the first transaction based on the specified fields in the CHI data packet output by the processor core and DSU; Method 6: Based on the storage area types accessed by historical transactions within a preset time period before the first transaction accesses, determine the target storage area type to be accessed by the first transaction.

[0141] In some embodiments, the multiple storage region types include a first type and a second type. The type determination module 11 is configured to: determine whether a security state switch has occurred based on the anomaly level switching information; if a security state switch has occurred, determine that the target storage region type to be accessed by the first transaction is the first type; if no security state switch has occurred, determine whether an anomaly level switch has occurred; if an anomaly level switch has occurred, obtain the first address of the first transaction access and the second address of the second transaction access before the anomaly switch, and determine the target storage region type to be accessed by the first transaction based on the first address and the second address.

[0142] In some embodiments, the type determination module 11 is configured to: take the difference between the first address and the second address; if the difference is greater than a first threshold, determine that the target storage area type to be accessed by the first transaction is a first type; if the difference is greater than a second threshold and less than the first threshold, determine that the target storage area type to be accessed by the first transaction is a second type.

[0143] In some embodiments, the type determination module 11 is configured to: determine whether the instruction executed by the processor core is a special instruction based on the instruction information executed by the processor core; if it is a special instruction, obtain the first instruction address of the instruction preceding the special instruction and the second instruction address of the special instruction, and determine the type of the target storage area to be accessed by the first transaction based on the first instruction address and the second instruction address.

[0144] In some embodiments, the type determination module 11 is configured to: take the difference between the first instruction address and the second instruction address; if the difference is greater than a first threshold, determine that the target storage area type to be accessed by the first transaction is a first type; if the difference is greater than a second threshold and less than the first threshold, determine that the target storage area type to be accessed by the first transaction is a second type.

[0145] In some embodiments, the type determination module 11 is configured to: determine whether the direction of the predicted branch instruction is a jump based on the jump direction prediction information; if the direction of the predicted branch instruction is a jump, determine the third instruction address of the current instruction and the fourth instruction address of the predicted branch instruction, and determine the type of the target storage area to be accessed by the first transaction based on the third instruction address and the fourth instruction address.

[0146] In some embodiments, the type determination module 11 is configured to: take the difference between the third instruction address and the fourth instruction address; if the difference is greater than a first threshold, determine that the target storage area type to be accessed by the first transaction is a first type; if the difference is greater than a second threshold and less than the first threshold, determine that the target storage area type to be accessed by the first transaction is a second type.

[0147] In some embodiments, the multiple storage region types include a first type and a second type. The type determination module 11 is configured to: determine that the address type of the address accessed by the first transaction is an instruction address; subtract the address accessed by the first transaction from the historical instruction addresses of a preset number of historical accesses that belong to the instruction address before the first transaction access; if the difference is greater than a first threshold, determine that the target storage region type to be accessed by the first transaction access is the first type; if the difference is greater than a second threshold and less than the first threshold, determine that the target storage region type to be accessed by the first transaction access is the second type; determine that the address type of the address accessed by the first transaction is a data address; subtract the address accessed by the first transaction from the historical instruction addresses of a preset number of historical accesses that belong to the data address before the first transaction access; if the difference is greater than a third threshold, determine that the target storage region type to be accessed by the first transaction access is the first type; if the difference is greater than a fourth threshold and less than the third threshold, determine that the target storage region type to be accessed by the first transaction access is the second type.

[0148] In some embodiments, the type determination module 11 is configured to: determine the type of the target storage area to be accessed by the first transaction access based on a specified field in the CHI transmission data packet output by the processor core and the DSU, including: determining the transmission transaction type based on a first field in the specified field; and determining the type of the target storage area to be accessed by the first transaction access based on the transmission transaction type.

[0149] In some embodiments, the multiple storage area types include a first type and a second type. The type determination module 11 is configured to: if the number of accesses to the first type of historical transactions is greater than the number of accesses to the second type of historical transactions within a preset time period, determine that the target storage area type to be accessed by the first transaction is the first type; if the number of accesses to the first type of historical transactions is less than the number of accesses to the second type of historical transactions within a preset time period, determine that the target storage area type to be accessed by the first transaction is the second type.

[0150] In some embodiments, the multiple storage region types include a first type and a second type. The region determination module 12 is used to perform a bitwise AND operation on the valid high-order segment of the address accessed by the first transaction and the mask, and then perform XOR reduction to determine the first value of the bit sequence, the bit sequence including multiple bits; when the target storage region type is the first type, the multiple values ​​of the bit sequence correspond to multiple storage regions of the first type, and the storage region corresponding to the first value is determined as the target valid region; the target valid region includes multiple storage sub-regions. A bitwise AND operation is performed on the address accessed by the first transaction and the first partition mask, and then XOR reduction is performed to determine the first parameter. A bitwise AND operation is performed on the address segment accessed by the first transaction and the second partition mask, and then XOR reduction is performed to determine the second parameter. The target storage sub-region among the multiple storage sub-regions is determined based on the first parameter and the second parameter; when the target storage region type is the second type, the multiple values ​​of the bit sequence correspond to multiple storage regions of the second type, and the storage region corresponding to the first value is determined as the target valid region.

[0151] It should be noted that the foregoing explanation of any storage area wake-up method embodiment also applies to the storage area wake-up device of this embodiment, and will not be repeated here.

[0152] The beneficial effects achieved by the memory region wake-up device in this application embodiment are the same as those achieved by the memory region wake-up method, and will not be repeated here.

[0153] To implement the above embodiments, this application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the memory region wake-up method as described in any of the foregoing embodiments.

[0154] Figure 7 This is a schematic diagram of the structure of an electronic device provided for an exemplary embodiment of this application. For example, the electronic device 900 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness device, personal digital assistant, etc.

[0155] Reference Figure 7 The electronic device 900 may include one or more of the following components: processing component 902, memory 904, power component 906, multimedia component 908, audio component 910, input / output (I / O) interface 912, sensor component 914, and communication component 916.

[0156] Processing component 902 typically controls the overall operation of electronic device 900, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 902 may include one or more processors 920 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 902 may include one or more modules to facilitate interaction between processing component 902 and other components. For example, processing component 902 may include a multimedia module to facilitate interaction between multimedia component 908 and processing component 902.

[0157] Memory 904 is configured to store various types of data to support the operation of electronic device 900. Examples of this data include instructions for any application or method operating on electronic device 900, contact data, phonebook data, messages, pictures, videos, etc. Memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0158] Power component 906 provides power to various components of electronic device 900. Power component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 900.

[0159] Multimedia component 908 includes a screen that provides an output interface between the electronic device 900 and the user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a Touch Panel, the screen may be implemented as a touchscreen to receive input signals from the user. The Touch Panel includes one or more touch sensors to sense touches, swipes, and gestures on the Touch Panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 908 includes a front-facing camera and / or a rear-facing camera. When the electronic device 900 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0160] Audio component 910 is configured to output and / or input audio signals. For example, audio component 910 includes a microphone (MIC) configured to receive external audio signals when electronic device 900 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 904 or transmitted via communication component 916. In some embodiments, audio component 910 also includes a speaker for outputting audio signals.

[0161] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0162] Sensor assembly 914 includes one or more sensors for providing state assessments of various aspects of electronic device 900. For example, sensor assembly 914 can detect the on / off state of electronic device 900, the relative positioning of components such as the display and keypad of electronic device 900, changes in position of electronic device 900 or a component of electronic device 900, the presence or absence of user contact with electronic device 900, orientation or acceleration / deceleration of electronic device 900, and temperature changes of electronic device 900. Sensor assembly 914 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 914 may also include an optical sensor, such as a complementary metal-oxide-semiconductor (CMOS) or charge-coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, sensor assembly 914 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0163] Communication component 916 is configured to facilitate wired or wireless communication between electronic device 900 and other devices. Electronic device 900 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 916 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 916 also includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), Bluetooth (BT), and other technologies.

[0164] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0165] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, which can be executed by a processor 920 of an electronic device 900 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0166] To implement the above embodiments, this application also proposes a chip, wherein the chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to execute the memory region wake-up method provided in any of the foregoing embodiments.

[0167] Figure 8 This is a schematic diagram of the structure of a chip proposed in an exemplary embodiment of this application. See also... Figure 8 The diagram shown is a schematic representation of the structure of chip 1000, but it is not limited to this.

[0168] Chip 1000 includes processing circuit 1001, which is configured to execute any of the above memory region wake-up methods.

[0169] In some embodiments, the chip 1000 further includes one or more interface circuits 1002. Optionally, the interface circuit 1002 is connected to the memory 1003, and the interface circuit 1002 can be used to receive signals from the memory 1003 or other devices, and the interface circuit 1002 can be used to send signals to the memory 1003 or other devices. For example, the interface circuit 1002 can read instructions stored in the memory 1003 and send the instructions to the processing circuit 1001.

[0170] In some embodiments, the interface circuit 1002 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1001 performs other steps.

[0171] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0172] In some embodiments, chip 1000 further includes one or more memories 1003 for storing instructions. Optionally, all or part of the memories 1003 may be located outside of chip 1000.

[0173] To implement the above embodiments, this application also proposes a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the storage region wake-up method as described in any of the foregoing method embodiments.

[0174] To implement the above embodiments, this application also proposes a computer program product on which a computer program is stored, wherein when the computer program is executed by a processor, it implements the memory region wake-up method as described in any of the foregoing method embodiments.

[0175] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0176] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0177] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0178] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and compact disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0179] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any of the following techniques known in the art, or a combination thereof: discrete logic circuits having logic gates for implementing logical functions on data signals; application-specific integrated circuits (ASICs) having suitable combinational logic gates; programmable gate arrays (PGAs); field-programmable gate arrays (FPGAs); etc.

[0180] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0181] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0182] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for waking up a memory region, characterized in that, include: Based on internal processor information, the target storage region type to be accessed by the first transaction initiated by the processor is predicted from multiple storage region types. Based on the address accessed by the first transaction, determine the target storage region accessed from among the multiple storage regions included in the target storage region type; If the target storage area is in a dormant state, a wake-up signal is generated to wake up the target storage area.

2. The method according to claim 1, characterized in that, The step of predicting the target storage region type to be accessed by the first transaction initiated by the processor from multiple storage region types, based on internal processor information, includes: Use any one of the following methods to determine the type of target storage area to be accessed by the first transaction; or Prediction is performed according to the specified priority order of multiple methods, including Method 1, Method 2, Method 3, Method 4, Method 5, and Method 6, until the target storage area type to be accessed by the first transaction is determined. Method 1: Determine the type of target storage area to be accessed by the first transaction based on the exception level switching information when the processor core executes instructions; Method 2: Determine the type of target storage area to be accessed by the first transaction based on the instruction information executed by the processor core; Method 3: Determine the type of target storage area to be accessed by the first transaction based on the jump direction prediction information in the instruction fetch unit of the processor; Method 4: Determine the target storage region type to be accessed by the first transaction based on the address and address type accessed by the first transaction, and the differences in historical access addresses of a preset number of historical transactions belonging to the address type before the first transaction accesses the first transaction. Method 5: Determine the target storage region type to be accessed by the first transaction based on the specified fields in the CHI transmission data packet output by the processor core and DSU; Method 6: Determine the target storage area type to be accessed by the first transaction based on the storage area types accessed by historical transactions within a preset time period before the first transaction accesses.

3. The method according to claim 2, characterized in that, The multiple storage region types include a first type and a second type. Determining the target storage region type to be accessed by the first transaction based on the exception level switching information during processor core instruction execution includes: Based on the anomaly level switching information, determine whether a security state switch has occurred; If a security state switch occurs, the target storage area type to be accessed by the first transaction is determined to be the first type. If no safety status transition occurs, determine whether an anomaly level transition has occurred; If an anomaly level switch occurs, obtain the first address accessed by the first transaction and the second address accessed by the second transaction before the anomaly switch, and determine the target storage area type to be accessed by the first transaction based on the first address and the second address.

4. The method according to claim 3, characterized in that, The step of determining the target storage region type to be accessed by the first transaction based on the first address and the second address includes: The difference between the first address and the second address is calculated. If the difference is greater than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the first type. If the difference is greater than the second threshold and less than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the second type.

5. The method according to claim 2, characterized in that, The step of determining the type of the target storage region to be accessed by the first transaction based on the instruction information executed by the processor core includes: Based on the instruction information executed by the processor core, determine whether the instruction executed by the processor core is a special instruction; If it is a special instruction, obtain the first instruction address of the instruction preceding the special instruction and the second instruction address of the special instruction, and determine the target storage area type to be accessed by the first transaction based on the first instruction address and the second instruction address.

6. The method according to claim 5, characterized in that, The step of determining the target storage region type to be accessed by the first transaction based on the first instruction address and the second instruction address includes: The difference between the first instruction address and the second instruction address is calculated. If the difference is greater than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the first type. If the difference is greater than the second threshold and less than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the second type.

7. The method according to claim 2, characterized in that, Determining the target storage region type to be accessed by the first transaction based on the jump direction prediction information in the processor's instruction fetch unit includes: Based on the jump direction prediction information, determine whether the direction of the predicted branch instruction is a jump; If the predicted branch instruction is a jump, determine the third instruction address of the current instruction and the fourth instruction address of the predicted branch instruction. Based on the third instruction address and the fourth instruction address, determine the type of the target storage area to be accessed by the first transaction.

8. The method according to claim 7, characterized in that, The step of determining the target storage region type to be accessed by the first transaction based on the third instruction address and the fourth instruction address includes: The difference between the third instruction address and the fourth instruction address is calculated. If the difference is greater than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the first type. If the difference is greater than the second threshold and less than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the second type.

9. The method according to claim 2, characterized in that, The multiple storage region types include a first type and a second type. Determining the target storage region type to be accessed by the first transaction based on the address and address type accessed by the first transaction, and the differences in historical access addresses of a preset number of historical transactions belonging to the address type prior to the first transaction access, includes: The address type of the address accessed by the first transaction is determined to be an instruction address. The address accessed by the first transaction is subtracted from the historical instruction addresses of a preset number of historical accesses that belong to the instruction address before the first transaction accesses one by one. If the difference is greater than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the first type. If the difference is greater than the second threshold and less than the first threshold, the target storage area type to be accessed by the first transaction is determined to be the second type. The address type of the address accessed by the first transaction is determined to be a data address. The address accessed by the first transaction is subtracted from the addresses of the historical instructions that were previously accessed as data addresses by a preset number of historical accesses. If the difference is greater than the third threshold, the target storage area type to be accessed by the first transaction is determined to be the first type. If the difference is greater than the fourth threshold and less than the third threshold, the target storage area type to be accessed by the first transaction is determined to be the second type.

10. The method according to claim 2, characterized in that, The step of determining the target storage region type to be accessed by the first transaction based on specified fields in the CHI transport data packets output by the processor core and DSU includes: The transmission transaction type is determined based on the first field in the specified fields; Based on the transmission transaction type, determine the type of target storage area to be accessed by the first transaction.

11. The method according to claim 2, characterized in that, The multiple storage region types include a first type and a second type. Determining the target storage region type to be accessed by the first transaction based on the storage region types accessed by historical transactions within a preset time period prior to the first transaction access includes: If, within the preset time period, the number of times the historical transaction of the first type is accessed is greater than the number of times the historical transaction of the second type is accessed, the target storage area type to be accessed by the first transaction is determined to be the first type. If, within the preset time period, the number of times the historical transaction accesses the first type is less than the number of times the historical transaction accesses the second type are accessed, the target storage area type required for the first transaction access is determined to be the second type.

12. The method according to any one of claims 1 to 11, characterized in that, The multiple storage region types include a first type and a second type. The step of determining the target storage region to be accessed from among the multiple storage regions included in the target storage region type based on the address accessed by the first transaction includes: Perform a bitwise AND operation between the valid high-order segment of the address accessed by the first transaction and the mask code, and then perform an XOR reduction to determine the first value of the bit sequence, wherein the bit sequence includes multiple bits; When the target storage area type is the first type, the multiple values ​​of the bit sequence correspond to multiple storage areas of the first type, and the storage area corresponding to the first value is determined as the target valid area; the target valid area includes multiple storage sub-areas, and a bitwise AND operation is performed based on the address accessed by the first transaction and the first partition mask, followed by XOR reduction to determine the first parameter, a bitwise AND operation is performed based on the address segment accessed by the first transaction and the second partition mask, followed by XOR reduction to determine the second parameter, and the target storage sub-area among the multiple storage sub-areas is determined based on the first parameter and the second parameter; When the target storage area type is the second type, the multiple values ​​of the bit sequence correspond to multiple storage areas of the second type, and the storage area corresponding to the first value is determined to be the target valid area.

13. A memory region wake-up device, characterized in that, include: The type determination module is used to predict, from multiple storage region types, the target storage region type to be accessed by the first transaction initiated by the processor, based on information inside the processor. The region determination module is used to determine the target storage region to be accessed from among multiple storage regions included in the target storage region type, based on the address accessed by the first transaction. The wake-up module is used to generate a wake-up signal to wake up the target storage area if the target storage area is in a dormant state.

14. The apparatus according to claim 12, characterized in that, The type determination module is used for: Use any one of the following methods to determine the type of target storage area to be accessed by the first transaction; or Prediction is performed according to the specified priority order of multiple methods, including Method 1, Method 2, Method 3, Method 4, Method 5, and Method 6, until the target storage area type to be accessed by the first transaction is determined. Method 1: Determine the type of target storage area to be accessed by the first transaction based on the exception level switching information when the processor core executes instructions; Method 2: Determine the type of target storage area to be accessed by the first transaction based on the instruction information executed by the processor core; Method 3: Determine the type of target storage area to be accessed by the first transaction based on the jump direction prediction information in the instruction fetch unit of the processor; Method 4: Determine the target storage region type to be accessed by the first transaction based on the address and address type accessed by the first transaction, and the differences in historical access addresses of a preset number of historical transactions belonging to the address type before the first transaction accesses the first transaction. Method 5: Determine the target storage region type to be accessed by the first transaction based on the specified fields in the CHI transmission data packet output by the processor core and DSU; Method 6: Determine the target storage area type to be accessed by the first transaction based on the storage area types accessed by historical transactions within a preset time period before the first transaction accesses.

15. A chip, characterized in that, The chip includes an interface circuit and a processing circuit that are coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is used to implement the method of any one of claims 1 to 12.

16. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the method as described in any one of claims 1 to 12.

17. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When executed by a processor, the program instructions implement the steps of the method described in any one of claims 1 to 12.

18. A computer program product, characterized in that, It includes a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 12.

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