Physical interface circuit, chip, method of configuring physical interface circuit and medium

Abstract

A physical interface circuit, a chip, a method for configuring the physical interface circuit, and a medium are disclosed. The physical interface circuit is applied to a chip on which multiple virtual machines run. The physical interface circuit includes: a configuration register group, where different configuration registers store configuration information corresponding to different virtual machines; a selection register, which stores a selection signal indicating the selection of a target virtual machine from the multiple virtual machines; a control circuit, which outputs configuration information from a target configuration register in the configuration register group in response to the selection signal from the selection register; wherein the target configuration register refers to the configuration register storing configuration information corresponding to the target virtual machine; and a configuration circuit, which operates based on the configuration information output by the control circuit. The embodiments of this disclosure can effectively implement the allocation of the physical interface circuit.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and in particular to a physical interface circuit, a chip, a method for configuring the physical interface circuit, and a medium. Background Technology

[0002] Virtualization technology supports the simultaneous running of multiple virtual machines (VMs) on a single chip. The hardware resources in the chip need to be allocated to multiple VMs. Physical interface circuits are important hardware resources in the chip, and how to allocate physical interface circuits is a technical issue worthy of attention for those skilled in the art. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a physical interface circuit, a chip, a method for configuring the physical interface circuit, and a medium.

[0004] According to one aspect of the present disclosure, a physical interface circuit is provided for use on a chip, the chip having multiple virtual machines running on it, the physical interface circuit comprising: A configuration register group, wherein different configuration registers in the configuration register group are used to store configuration information corresponding to different virtual machines; A selection register is used to store a selection signal, which is a signal that indicates the selection of a target virtual machine from a plurality of virtual machines; A control circuit, configured to output configuration information from a target configuration register in the configuration register group in response to a selection signal from the selection register; wherein the target configuration register refers to the configuration register that stores the configuration information corresponding to the target virtual machine; A circuit to be configured, which operates based on the configuration information output by the control circuit.

[0005] According to another aspect of the present disclosure, a chip is provided that includes the physical interface circuit described above.

[0006] According to another aspect of the present disclosure, a method for configuring a physical interface circuit is provided. The physical interface circuit is applied to a chip, on which multiple virtual machines run. The physical interface circuit includes a configuration register group, a selection register, a control circuit, and a circuit to be configured. The configuration method includes: The configuration information corresponding to different virtual machines is stored in different configuration registers in the configuration register group; The selection register stores a selection signal, which is a signal representing the selection of a target virtual machine from among the plurality of virtual machines; The control circuit responds to the selection signal from the selection register and outputs the configuration information from the target configuration register in the configuration register group; wherein, the target configuration register refers to the configuration register that stores the configuration information corresponding to the target virtual machine; The circuit to be configured operates based on the configuration information output by the control circuit.

[0007] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program that is executed by a processor to perform the above-described method for configuring physical interface circuitry.

[0008] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the above-described method for configuring the physical interface circuit.

[0009] According to another aspect of the present disclosure, a computer program product is provided that, when instructions in the computer program product are executed by a processor, performs the above-described method for configuring physical interface circuits.

[0010] Based on the physical interface circuit, chip, method, medium, device, and program product provided in the above embodiments of this disclosure, the software running on the chip to which the physical interface circuit is applied can write corresponding configuration information to each configuration register in the configuration register group and write selection signals to the selection register. The selection register can transmit the registered selection signals to the control circuit. Each configuration register in the configuration register group can transmit the registered configuration information to the control circuit. Accordingly, the control circuit can obtain the selection signals from the selection registers and the configuration information from each configuration register in the configuration register group. It should be noted that the configuration information from each configuration register in the configuration register group can be used as multiple inputs. Based on the selection signals from the selection registers, the control circuit can selectively output multiple inputs. Since the selection signal is used to indicate that the target virtual machine is selected, the configuration register storing the configuration information corresponding to the target virtual machine is the target configuration register. The control circuit can output only the configuration information from the target configuration register and not the configuration information from other configuration registers. The configuration information output by the control circuit can be transmitted to the circuit to be configured. The circuit to be configured can operate based on the configuration information output by the control circuit. For example, the circuit to be configured can operate according to the working mode defined by the configuration information output by the control circuit. This is equivalent to making the physical interface circuit operate according to the working mode corresponding to the target virtual machine, that is, the physical interface circuit is assigned to the target virtual machine. Therefore, in the embodiments of this disclosure, through the coordinated work of the configuration register group, selection register, control circuit, etc., only the configuration information corresponding to the target virtual machine can be passed to the circuit to be configured at the subsequent level, while avoiding the transmission of configuration information corresponding to other virtual machines to the circuit to be configured at the subsequent level. Thus, only the target virtual machine can configure the physical interface circuit; that is, the physical interface circuit is assigned to the target virtual machine. Therefore, the embodiments of this disclosure can effectively realize the allocation of the physical interface circuit. Attached Figure Description

[0011] Figure 1 This is a system architecture diagram to which some exemplary embodiments of this disclosure apply.

[0012] Figure 2 This is one of the schematic diagrams of the physical interface circuit provided in some exemplary embodiments of this disclosure.

[0013] Figure 3 This is the second schematic diagram of the physical interface circuit provided in some exemplary embodiments of this disclosure.

[0014] Figure 4 This is the third schematic diagram of the physical interface circuit provided in some exemplary embodiments of this disclosure.

[0015] Figure 5 This is the fourth schematic diagram of the physical interface circuit provided in some exemplary embodiments of this disclosure.

[0016] Figure 6 This is the fifth schematic diagram of the physical interface circuit provided in some exemplary embodiments of this disclosure.

[0017] Figure 7 This is the sixth schematic diagram of the physical interface circuit provided in some exemplary embodiments of this disclosure.

[0018] Figure 8 This is one of the flowcharts illustrating a method for configuring physical interface circuits provided by some exemplary embodiments of this disclosure.

[0019] Figure 9 This is a second schematic flowchart of a method for configuring physical interface circuits provided by some exemplary embodiments of this disclosure.

[0020] Figure 10 This is the third flowchart illustrating a method for configuring physical interface circuits provided by some exemplary embodiments of this disclosure.

[0021] Figure 11 This is the fourth flowchart illustrating a method for configuring physical interface circuits provided by some exemplary embodiments of this disclosure.

[0022] Figure 12 This is the fifth flowchart illustrating a method for configuring physical interface circuits provided by some exemplary embodiments of this disclosure.

[0023] Figure 13 This is a sixth flowchart illustrating a method for configuring physical interface circuits provided by some exemplary embodiments of this disclosure.

[0024] Figure 14 This is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of this disclosure. Detailed Implementation

[0025] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0026] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0027] Application Overview Currently, chips, as the core hardware for data processing, are widely used in various industries, from cloud data centers to edge intelligent terminals, forming a complete application ecosystem. For example, in the field of driving technology, intelligent driving chips and intelligent cockpit chips are widely used for processing intelligent driving and intelligent cockpit functions. As another example, in the field of image processing, image processing chips are widely used for image processing.

[0028] To enable a single chip to handle tasks that would otherwise require multiple chips more securely, efficiently, and flexibly, virtualization technology can be used to run multiple virtual machines (VMs) on the chip simultaneously. It's important to note that the chip's hardware resources need to be allocated to multiple VMs, and the physical interface circuitry (also known as the physical interface or I / O pad), serving as the communication channel between the chip's internal and external environments, is a crucial hardware resource. How to allocate these physical interface circuits is a technically significant issue for those skilled in the art.

[0029] Exemplary System Figure 1 This is a system architecture diagram to which some exemplary embodiments of this disclosure apply, including multiple physical interface circuits in the chip and multiple virtual machines running on the chip.

[0030] Optionally, the chip can be an application-specific integrated circuit (ASIC), which is a chip designed for a specific purpose, such as, but not limited to, intelligent driving chips, intelligent cockpit chips, image processing chips, etc.

[0031] Optionally, the multiple physical interface circuits in the chip can be N physical interface circuits, represented sequentially as IOPad1, IOPad2, ..., IOPad N .

[0032] Optionally, the multiple virtual machines running on the chip can be S virtual machines, denoted as VM1, VM2, ..., VM... S S and N can be the same or different.

[0033] In the embodiments of this disclosure, N physical interface circuits can be allocated to S virtual machines, so that tasks that originally required multiple chips can be processed simultaneously securely, efficiently, and flexibly based on the S virtual machines. Assuming that S and N are the same, the following allocation method can be adopted: IO Pad1 is allocated to VM1, IO Pad2 is allocated to VM2, ..., and so on. N Assigned to VM SAssuming S and N are different, N is greater than 3, and S is 3, then the following allocation method can be used: allocate IO Pad1 to IO Pad2. N A portion of the IOPads is allocated to VM1, from IOPad1 to IOPad2. N Another portion of the IO Pads is allocated to VM2, from IO Pad1 to IO Pad2. N A portion of the I / O pads are then allocated to VM3. Of course, the allocation method is not limited to this; the specific method can be determined based on the actual situation, and will not be listed here. It should be noted that different allocation methods can result in different product forms for the chip, which is beneficial for improving the robustness and flexibility of the chip software system design.

[0034] Exemplary circuit The embodiments of this disclosure provide a physical interface circuit. The physical interface circuit can be applied to chips, such as, but not limited to, intelligent driving chips, intelligent cockpit chips, image processing chips, etc. The chip on which the physical interface circuit is applied can run multiple virtual machines, for example, S virtual machines; where S can be an integer greater than or equal to 2, such as 2, 3, 4, 5, 6, 8, 10, etc., and will not be listed here.

[0035] like Figure 2 As shown, the physical interface circuit includes: Configuration register group 20, and different configuration registers 201 in configuration register group 20 are used to store configuration information corresponding to different virtual machines; Select register 40 is used to store the select signal, which is a signal that represents the selection of the target virtual machine from multiple virtual machines. Control circuit 60 is used to output configuration information from the target configuration register in configuration register group 20 in response to the selection signal from selection register 40; wherein, the target configuration register refers to configuration register 201 that stores configuration information corresponding to the target virtual machine. The circuit to be configured 80 is used to operate based on the configuration information output by the control circuit 60.

[0036] Optionally, configuration register group 20 is a collection of configuration registers 201. Configuration registers 201 are registers used to store configuration information, which defines the operating mode of the physical interface circuit. This information includes, but is not limited to, defining the signal flow direction, signal processing method, and electrical characteristics of the physical interface circuit. Here, the signal flow direction of the physical interface circuit is defined, for example, whether the input direction of the physical interface circuit is open, i.e., whether a signal from outside the chip can be input into the chip. Another example is defining which hardware circuit or device inside the chip the signal from outside the chip will be input to if the input direction is open. The signal processing method of the physical interface circuit is defined, for example, whether the signal from outside the chip needs to be rectified. The electrical characteristics of the physical interface circuit are defined, for example, the current intensity and waveform quality of the signal output from the physical interface circuit to the outside of the chip. Configuration register group 20 may include multiple configuration registers 201, for example, R configuration registers 201; where R can be an integer greater than or equal to 2, for example, R can be 2, 3, 4, 5, 6, 8, 10, etc., and will not be listed here. For the R configuration registers 201, different configuration registers 201 can store configuration information corresponding to different virtual machines.

[0037] As an example, the S virtual machines can be four virtual machines, represented as VM 1, VM 2, VM 3, and VM 4, respectively. The R configuration registers 201 can be four configuration registers 201, where the first configuration register 201 stores the configuration information for VM 1, the second configuration register 201 stores the configuration information for VM 2, the third configuration register 201 stores the configuration information for VM 3, and the fourth configuration register 201 stores the configuration information for VM 4. Here, the configuration information for any two of VM 1, VM 2, VM 3, and VM 4 can be different.

[0038] Optionally, the selection register 40 is a register used to store the selection signal, which is used to indicate the selected virtual machine (i.e., the target virtual machine) among the S virtual machines. The configuration register 201 that stores the configuration information corresponding to the target virtual machine can also be called the target configuration register, and the configuration registers 201 in the configuration register group 20 other than the target configuration register can also be called other configuration registers. The selection signal can also be called the VM select signal.

[0039] Optionally, the circuit to be configured 80 is a hardware circuit that needs to be configured through configuration information. After the circuit to be configured 80 is configured with the configuration information, the physical interface circuit can work according to the working mode defined by the configuration information.

[0040] Optionally, the control circuit 60 is a circuit capable of selectively outputting multiple inputs; that is, the control circuit 60 can perform the function of a digital switch. The control circuit 60 can be electrically connected to each configuration register 201 in the configuration register group 20, the control circuit 60 can also be electrically connected to the selection register 40, and the control circuit 60 can also be electrically connected to the circuit to be configured 80.

[0041] In the embodiments of this disclosure, the software running on the chip to which the physical interface circuit is applied can write corresponding configuration information to each configuration register 201 in the configuration register group 20, and write selection signals to the selection register 40. The selection register 40 can transmit the registered selection signals to the control circuit 60. Each configuration register 201 in the configuration register group 20 can transmit the registered configuration information to the control circuit 60. Accordingly, the control circuit 60 can obtain the selection signals from the selection register 40 and the configuration information from each configuration register 201 in the configuration register group 20. It should be noted that the configuration information from each configuration register 201 in the configuration register group 20 can be used as multiple inputs. Based on the selection signals from the selection register 40, the control circuit 60 can selectively output the multiple inputs. Since the selection signals are used to indicate that the target virtual machine is selected, the configuration register 201 that stores the configuration information corresponding to the target virtual machine is the target configuration register. The control circuit 60 can output only the configuration information from the target configuration register and not the configuration information from other configuration registers. The configuration information output by the control circuit 60 can be transmitted to the circuit to be configured 80. The circuit to be configured 80 can operate based on the configuration information output by the control circuit 60. For example, the circuit to be configured 80 can operate according to the operating mode defined by the configuration information output by the control circuit 60. This is equivalent to making the physical interface circuit operate according to the operating mode corresponding to the target virtual machine, that is, the physical interface circuit is assigned to the target virtual machine.

[0042] As can be seen, in the embodiments of this disclosure, through the coordinated operation of the configuration register group 20, selection register 40, control circuit 60, etc., only the configuration information corresponding to the target virtual machine can be transmitted to the subsequent configuration circuit 80, while avoiding the transmission of configuration information corresponding to other virtual machines to the subsequent configuration circuit 80. Thus, only the target virtual machine can configure the physical interface circuit; that is, the physical interface circuit is allocated to the target virtual machine. Therefore, the embodiments of this disclosure can effectively achieve the allocation of the physical interface circuit.

[0043] In some optional examples, the number of configuration register groups 20 is multiple, and the target configuration registers include a first target configuration register and a second target configuration register, such as... Figure 3 As shown, the multiple configuration register groups 20 include: The first configuration register group, in which each configuration register 201 stores attribute configuration information; The second configuration register group contains configuration information stored in each configuration register 201, which is function selection configuration information. The control circuit 60 is used to respond to the selection signal from the selection register 40, output attribute configuration information from the first target configuration register in the first configuration register group, and output function selection configuration information from the second target configuration register in the second configuration register group; The circuit to be configured 80 includes: Interface unit 801 is used to operate based on the attribute configuration information output by control circuit 60; Function selector 803 is used to operate based on the function selection configuration information output by control circuit 60.

[0044] Optionally, the interface unit 801 is a unit directly connected to the outside of the chip, serving as a physical bridge between the inside and outside of the chip. The interface unit 801 can also be referred to as a Pad Cell. The interface unit 801 can be electrically connected to the control circuit 60.

[0045] Optionally, the physical interface circuit can be configured to include multiple functions, and the function selector 803 can be a multiplexed device that implements multiple functions. The function selector 803 can also be called a Function Mux. The function selector 803 can be electrically connected to the control circuit 60.

[0046] Optionally, multiple configuration register groups 20 can be represented as U configuration register groups 20; where U can be an integer greater than or equal to 2, such as 2, 3, 4, etc., which will not be listed here. The U configuration register groups 20 can be divided into two categories. In one category, the configuration information registered by each configuration register 201 in the configuration register group 20 is attribute configuration information, and in the other category, the configuration information registered by each configuration register 201 in the configuration register group 20 is function selection configuration information. The former category of configuration register groups 20 can also be called the first configuration register group, and the latter category of configuration register groups 20 can also be called the second configuration register group.

[0047] Here, attribute configuration information refers to configuration information related to attributes, such as, but not limited to, pull-up (PU) configuration information, pull-down (PD) configuration information, Schmitt trigger (ST) configuration information, and drive strength (DS) configuration information. Specifically, the PU configuration information indicates whether the input signal is kept high by default when there is no external signal driving; the PD configuration information indicates whether the input signal is kept low by default when there is no external signal driving; the ST configuration information indicates whether the input signal is rectified; and the DS configuration information indicates the output current intensity. As an example, the PU configuration information can be an attribute configuration parameter. For example, a parameter of 1 indicates that the input signal is kept high by default when there is no external signal driving, while a parameter of 0 indicates that the input signal is not kept high by default when there is no external signal driving. The ST configuration information can also be an attribute configuration parameter. For example, a parameter of 1 indicates that the input signal is rectified, while a parameter of 0 indicates that the input signal is not rectified. Similarly, PD configuration information and DS configuration information can each be a property configuration parameter.

[0048] Here, the function selection configuration information is configuration information related to function selection, which can be used to indicate the selected function among a variety of functions of the physical interface circuit.

[0049] In the embodiments of this disclosure, the selection register 40 can transmit the registered selection signal to the control circuit 60. Each configuration register 201 in the first configuration register group can transmit the registered attribute configuration information to the control circuit 60. Each configuration register 201 in the second configuration register group can transmit the registered function selection configuration information to the control circuit 60. Accordingly, the control circuit 60 can acquire the selection signal from the selection register 40, as well as the attribute configuration information from each configuration register 201 in the first configuration register group and the function selection configuration information from each configuration register 201 in the second configuration register group. It should be noted that the attribute configuration information from each configuration register 201 in the first configuration register group can be used as a first set of inputs including multiple inputs, and the function selection configuration information from each configuration register 201 in the second configuration register group can be used as a second set of inputs including multiple inputs. Based on the selection signal from the selection register 40, the control circuit 60 can selectively output not only the multiple inputs included in the first set of inputs, but also the multiple inputs included in the second set of inputs.

[0050] Since the selection signal is used to indicate that the target virtual machine is selected, configuration register 201 in the first configuration register group, which stores the attribute configuration information corresponding to the target virtual machine, can be used as the first target configuration register. Configuration register 201 in the second configuration register group, which stores the function selection configuration information corresponding to the target virtual machine, can be used as the second target configuration register. For the first set of inputs, control circuit 60 can output only the attribute configuration information from the first target configuration register, without outputting attribute configuration information from other configuration registers. For the second set of inputs, control circuit 60 can output only the function selection configuration information from the second target configuration register, without outputting function selection configuration information from other configuration registers. The attribute configuration information output by control circuit 60 can be transmitted to interface unit 801, and the function selection configuration information output by control circuit 60 can be transmitted to function selector 803.

[0051] Interface unit 801 can operate based on the attribute configuration information output by control circuit 60. For example, if the attribute configuration information output by control circuit 60 includes ST configuration information, and the ST configuration information indicates that the input signal should be rectified, then for signals from outside the chip, interface unit 801 can first rectify the signal and then transmit the rectified signal into the chip. As another example, if the attribute configuration information output by control circuit 60 includes DS configuration information, and the DS configuration information indicates that the output current intensity is X milliamps, then when interface unit 801 outputs a signal to the outside of the chip, it can output according to the output current intensity of X milliamps.

[0052] The function selector 803 can operate based on the function selection configuration information output by the control circuit 60. For example, the physical interface circuit may include various functions such as Serial Peripheral Interface (SPI) communication, Inter-Integrated Circuit (I2C) communication, and Universal Asynchronous Receiver / Transmitter (UART) communication. If the function selection configuration information output by the control circuit 60 indicates that the SPI communication function is selected, the function selector 803 can enable the SPI communication function; if the function selection configuration information output by the control circuit 60 indicates that the I2C communication function is selected, the function selector 803 can enable the I2C communication function.

[0053] In this way, through the coordinated operation of the first configuration register group, the second configuration register group, the selection register 40, the control circuit 60, etc., only the attribute configuration information corresponding to the target virtual machine can be transmitted to the interface unit 801 located at the next level, and the function selection configuration information corresponding to the target virtual machine can be transmitted to the function selector 803 located at the next level. Thus, only the target virtual machine can configure the interface unit 801 and the function selector 803, that is, the physical interface circuit is allocated to the target virtual machine. Therefore, the embodiments of this disclosure can effectively realize the allocation of the physical interface circuit.

[0054] In some optional examples, such as Figure 4 As shown, the control circuit 60 includes: The first multiplexer 601 has different first input terminals electrically connected to different configuration registers 201 in the first configuration register group, a first output terminal electrically connected to the interface unit 801, and a first control terminal electrically connected to the selection register 40. The first multiplexer 601 is used to receive a selection signal from the selection register 40 from the first control terminal, and in response to the selection signal, to turn on the first input terminal and the first output terminal corresponding to the first target configuration register in the first configuration register group, so that the first output terminal outputs the attribute configuration information from the first target configuration register in the first configuration register group to the interface unit 801.

[0055] For example, the first configuration register group may include four configuration registers 201, and the first multiplexer 601 may include four first input terminals, which may be sequentially represented as input terminal P1, input terminal P2, input terminal P3, and input terminal P4. Input terminal P1 may be electrically connected to the first configuration register 201 of the four configuration registers 201, input terminal P2 may be electrically connected to the second configuration register 201 of the four configuration registers 201, input terminal P3 may be electrically connected to the third configuration register 201 of the four configuration registers 201, and input terminal P4 may be electrically connected to the fourth configuration register 201 of the four configuration registers 201. In addition, the first multiplexer 601 may include a first output terminal and a first control terminal. The first output terminal may be represented as output terminal P5, and the first control terminal may be represented as control terminal P6. Output terminal P5 may be electrically connected to interface unit 801, and control terminal P6 may be electrically connected to selection register 40.

[0056] In specific implementation, the selection register 40 can transmit the registered selection signal to the control terminal P6. The selection signal indicates that the target virtual machine is selected. Assuming that the configuration register 201 (i.e., the first target configuration register) that stores the attribute configuration information of the target virtual machine is the first configuration register 201 in the first configuration register group, since the first input terminal corresponding to the first configuration register 201 in the first configuration register group is input terminal P1, under the control of the first multiplexer 601, input terminal P1 is connected to output terminal P5, and input terminals P2, P3, and P4 are not connected to output terminal P5. At this time, only the attribute configuration information from the first configuration register 201 in the first configuration register group can be transmitted to the interface unit 801 after flowing through input terminal P1 and output terminal P5 in sequence. The attribute configuration information from the remaining three configuration registers 201 in the first configuration register group cannot be transmitted to the interface unit 801. In this way, the target virtual machine can configure the interface unit 801 through the attribute configuration information in the first configuration register 201.

[0057] In the embodiments of this disclosure, by introducing a first multiplexer 601, the configuration of the interface unit 801 by the corresponding virtual machine can be achieved simply by connecting the corresponding first input terminal and the first output terminal of the first multiplexer 601 based on the selection signal received from the first control terminal of the first multiplexer 601, thus providing high flexibility. Furthermore, the hardware structure of the control circuit 60 is simple, effectively controlling hardware costs.

[0058] In some optional examples, the interface unit 801 is used to determine the actual number of attribute configuration parameters included in the attribute configuration information output by the first output terminal; determine the numerical relationship between the actual number and the preset number; in response to determining that the attribute configuration information output by the first output terminal meets the preset parameter missing condition based on the numerical relationship, perform attribute configuration parameter completion processing on the attribute configuration information output by the first output terminal to obtain target attribute configuration information including a preset number of attribute configuration parameters; and work according to the target attribute configuration information.

[0059] As described above, PU configuration information, PD configuration information, ST configuration information, and DS configuration information can each be a type of attribute configuration parameter. Therefore, the attribute configuration information output by the first output terminal can include several types of attribute configuration parameters. The interface unit 801 can count the number of attribute configuration parameters included in the attribute configuration information output by the first output terminal to obtain the actual number of attribute configuration parameters. In addition, the interface unit 801 can compare the actual number with a preset number to determine the numerical relationship between the actual number and the preset number. Based on the numerical relationship between the actual number and the preset number, the interface unit 801 can determine whether the attribute configuration information output by the first output terminal meets the preset parameter missing condition. The preset parameter missing condition is a condition used to evaluate whether there are any missing attribute configuration parameters in the attribute configuration information. The preset parameter missing condition can be, for example, that the number of attribute configuration parameters is less than the preset number.

[0060] If the numerical relationship between the actual quantity and the preset quantity indicates that the actual quantity is equal to the preset quantity, the interface unit 801 can determine that the attribute configuration information output by the first output terminal does not meet the preset parameter missing condition.

[0061] If the numerical relationship between the actual quantity and the preset quantity indicates that the actual quantity is less than the preset quantity, the interface unit 801 can determine that the attribute configuration information output by the first output terminal meets the preset parameter missing condition. The interface unit 801 can then perform attribute configuration parameter completion processing on the attribute configuration information output by the first output terminal to obtain target attribute configuration information including the preset number of attribute configuration parameters. For example, if the preset number is four, but the attribute configuration information output by the first output terminal only includes PU configuration information, PD configuration information, and ST configuration information, that is, the actual number of attribute configuration parameters included in the attribute configuration information output by the first output terminal is only three, which is less than four. Therefore, the attribute configuration information output by the first output terminal meets the preset parameter missing condition. In this case, the interface unit 801 can add the preset ST configuration information to the attribute configuration information output by the first output terminal to obtain target attribute configuration information including four attribute configuration parameters. Afterward, the interface unit 801 can operate according to the target attribute configuration information. The specific implementation method of the interface unit 801 working according to the target attribute configuration information can be referred to the relevant introduction above on the specific implementation method of the interface unit 801 working based on the attribute configuration information output by the control circuit 60, and will not be repeated here.

[0062] In the embodiments of this disclosure, by comparing the actual number of attribute configuration parameters included in the attribute configuration information output by the first output terminal with a preset number, it is possible to efficiently and reliably determine whether the attribute configuration information output by the first output terminal meets the preset parameter missing condition. If the attribute configuration information output by the first output terminal meets the preset parameter missing condition, a completion process can be performed to obtain target attribute configuration information including a preset number of attribute configuration parameters, so that the interface unit 801 can operate according to the target attribute configuration information. Thus, even if some attribute configuration parameters are missing from the attribute configuration information output by the first output terminal due to factors such as software misconfiguration, the integrity of the attribute configuration parameters in the attribute configuration information used for the operation of the interface unit 801 can be ensured, thereby ensuring the normal and reliable operation of the interface unit 801.

[0063] In some optional examples, such as Figure 5 As shown, the control circuit 60 includes: The second multiplexer 603 has different second input terminals electrically connected to different configuration registers 201 in the second configuration register group, a second output terminal electrically connected to a function selector 803, and a second control terminal electrically connected to a selection register 40. The second multiplexer 603 is used to receive a selection signal from the selection register 40 from the second control terminal, and in response to the selection signal, to turn on the second input terminal and the second output terminal corresponding to the second target configuration register in the second configuration register group, so that the second output terminal outputs the function selection configuration information from the second target configuration register in the second configuration register group to the function selector 803.

[0064] Optionally, the second configuration register group may include four configuration registers 201, and the second multiplexer 603 may include four second input terminals, which may be sequentially represented as input terminal V1, input terminal V2, input terminal V3, and input terminal V4. Input terminal V1 may be electrically connected to the first configuration register 201, input terminal V2 may be electrically connected to the second configuration register 201, input terminal V3 may be electrically connected to the third configuration register 201, and input terminal V4 may be electrically connected to the fourth configuration register 201. Additionally, the second multiplexer 603 may include a second output terminal and a second control terminal. The second output terminal may be represented as output terminal V5, and the second control terminal may be represented as control terminal V6. Output terminal V5 may be electrically connected to function selector 803, and control terminal V6 may be electrically connected to selection register 40.

[0065] In specific implementation, the selection register 40 can transmit the registered selection signal to the control terminal V6. The selection signal indicates that the target virtual machine is selected. Assuming that the configuration register 201 (i.e., the second target configuration register) that stores the function selection configuration information corresponding to the target virtual machine is the first configuration register 201 in the second configuration register group, since the second input terminal corresponding to the first configuration register 201 in the second configuration register group is input terminal V1, under the control of the second multiplexer 603, input terminal V1 is connected to output terminal V5, and input terminals V2, V3, and V4 are not connected to output terminal V5. At this time, only the function selection configuration information from the first configuration register 201 in the second configuration register group can be transmitted to the function selector 803 after flowing through input terminal V1 and output terminal V5 in sequence. The function selection configuration information from the remaining three configuration registers 201 in the second configuration register group cannot be transmitted to the function selector 803. In this way, the target virtual machine can configure the function selector 803 through the function selection configuration information in the first configuration register 201.

[0066] In the embodiments of this disclosure, by introducing a second multiplexer 603, the configuration of the function selector 803 by the corresponding virtual machine can be achieved simply by connecting the corresponding second input terminal and the second output terminal of the second multiplexer 603 based on the selection signal received from the second control terminal of the second multiplexer 603, thus providing high flexibility. Furthermore, the hardware structure of the control circuit 60 is simple, effectively controlling hardware costs.

[0067] In some optional examples, such as Figure 6 As shown, the function selector 803 is used to determine the target function circuit from the multiple function circuits 90 included in the chip based on the function selection configuration information output from the second output terminal; and to connect the target function circuit to the interface unit 801 so that signal transmission can be performed between the target function module and the interface unit 801.

[0068] Optionally, the functional circuit 90 is a module in the chip where the physical interface circuit is applied, used to support a specific function. The chip where the physical interface circuit is applied may include multiple functional circuits 90, which may include, for example, but are not limited to, an SPI module for supporting SPI communication, an I2C module for supporting I2C communication, and a UART module for supporting UART communication. The multiple functional circuits 90 may be electrically connected to the function selector 803, and the function selector 803 may also be electrically connected to the interface unit 801.

[0069] In the embodiments of this disclosure, the function selector 803 can be configured to include multiple operating modes. In different operating modes, the function selector 803 can connect different functional circuits 90 among multiple functional circuits 90 to the interface unit 801. Here, the function selector 803 can implement the function of a digital switch. As an example, the function selector 803 may include a control unit and a single-pole multi-throw switch. The control unit can be electrically connected to a second output terminal. The single-pole multi-throw switch may include a common terminal and multiple non-common terminals. The common terminal can be electrically connected to the interface unit 801, and the multiple non-common terminals can correspond one-to-one with multiple functional circuits 90. By contacting one of the non-common terminals with the corresponding functional circuit 90 to make it connected, the corresponding functional circuit 90 can be connected to the interface unit 801. Of course, the function selector 803 can also use other hardware circuits that can implement the function of a digital switch; this disclosure does not limit this.

[0070] In the embodiments of this disclosure, the function selection configuration information output from the second output terminal can be transmitted to the function selector 803. The function selector 803 can determine the target function circuit from multiple function circuits 90 based on the function selection configuration information output from the second output terminal. For example, the multiple function circuits 90 can each have a circuit identifier, and the function selection configuration information output from the second output terminal can include the circuit identifier. The function circuit 90 corresponding to this circuit identifier can be used as the target function circuit. Under the selection action of the function selector 803, the target function circuit can be connected to the interface unit 801. Thus, signals from the target function circuit can be output to the outside of the chip after passing through the function selector 803 and the interface unit 801 in sequence, or signals from the outside of the chip can be transmitted to the target function circuit after passing through the interface unit 801 and the function selector 803 in sequence, thereby effectively enabling the function corresponding to the target function circuit. Therefore, by adopting the embodiments of this disclosure, the activation of a specific function can be achieved through a simple hardware structure, thereby supporting the multiplexing of multiple functions.

[0071] In some optional examples, such as Figure 7 As shown, the physical interface circuit may include a first configuration register group, a second configuration register group, a selection register 40, a first multiplexer 601, a second multiplexer 603, an interface unit 801, and a function selector 803.

[0072] The first configuration register group includes multiple configuration registers 201, wherein the number of bits that each configuration register 201 can store can be associated with the number of virtual machines that need to be supported. For example, if the number of virtual machines is four, then each configuration register 201 can store 2 bits. Optionally, the first configuration register group may include four configuration registers 201 electrically connected to the first multiplexer 601; wherein the attribute configuration information stored in the first configuration register 201 is the attribute configuration information corresponding to VM 1, which can be represented as pg_reg_vm1; the attribute configuration information stored in the second configuration register 201 is the attribute configuration information corresponding to VM 2, which can be represented as pg_reg_vm2; the attribute configuration information stored in the third configuration register 201 is the attribute configuration information corresponding to VM 3, which can be represented as pg_reg_vm3; and the attribute configuration information stored in the fourth configuration register 201 is the attribute configuration information corresponding to VM 4, which can be represented as pg_reg_vm4.

[0073] The second configuration register group includes multiple configuration registers 201, wherein the number of bits that each configuration register 201 can store can also be associated with the number of virtual machines that need to be supported. Optionally, the second configuration register group may include four configuration registers 201 electrically connected to the second multiplexer 603; wherein the first configuration register 201 stores the function selection configuration information corresponding to VM 1, which can be represented as func_sel-reg_vm1; the second configuration register 201 stores the function selection configuration information corresponding to VM 2, which can be represented as func_sel-reg_vm2; the third configuration register 201 stores the function selection configuration information corresponding to VM 3, which can be represented as func_sel-reg_vm3; and the fourth configuration register 201 stores the function selection configuration information corresponding to VM 4, which can be represented as func_sel-reg_vm4.

[0074] In addition, the first multiplexer 601 and the second multiplexer 603 can be electrically connected to the selection register 40 respectively. The first multiplexer 601 can also be electrically connected to the interface unit 801, and the second multiplexer 603 can also be electrically connected to the function selector 803. The interface unit 801 can also be electrically connected to the function selector 803.

[0075] In practice, both the first multiplexer 601 and the second multiplexer 603 can receive the vmselect signal from the selection register 40. Assuming the vmselect signal indicates that the selected target register is VM 2, based on the selection signal, the first multiplexer 601 can output only pg_reg_vm2 to the interface unit 801, and the second multiplexer 603 can output only func_sel_reg_vm2 to the function selector 803. Thus, only the selected target virtual machine can configure the physical interface circuitry.

[0076] In summary, the embodiments of this disclosure can effectively allocate physical interface circuits. Since only the selected target virtual machine can be configured with physical interface circuits, the adverse effects of software misoperation can be filtered out from the hardware level. Furthermore, different virtual machines can have different physical interface circuit resources, thereby achieving the purpose of isolation and protection.

[0077] Exemplary chip Embodiments of this disclosure also provide a chip including the aforementioned physical interface circuit. It should be noted that specific implementations of the physical interface circuit can be found in the exemplary circuit section described above, and are not listed individually in this disclosure.

[0078] Since the physical interface circuit has the aforementioned beneficial technical effects, the chip, including the physical interface circuit, also has corresponding beneficial technical effects, which will not be elaborated here.

[0079] Exemplary methods Embodiments of this disclosure also provide a method for configuring a physical interface circuit. The physical interface circuit is applied to a chip, on which multiple virtual machines run. The physical interface circuit includes a configuration register set, a selection register, a control circuit, and a circuit to be configured. Figure 8 As shown, the method for configuring the physical interface circuit includes: Step 810: Register the configuration information corresponding to different virtual machines in different configuration registers in the configuration register group; Step 820: The selection signal is stored in the selection register. The selection signal is a signal that represents the selection of the target virtual machine among multiple virtual machines. Step 830: In response to the selection signal from the selection register, the control circuit outputs the configuration information from the target configuration register in the configuration register group; wherein, the target configuration register refers to the configuration register that stores the configuration information corresponding to the target virtual machine. Step 840: The circuit to be configured operates based on the configuration information output by the control circuit.

[0080] In some optional examples, there are multiple configuration register groups, the target configuration register includes a first target configuration register and a second target configuration register, the multiple configuration register groups include a first configuration register group and a second configuration register group, the configuration information stored in each configuration register in the first configuration register group is attribute configuration information, the configuration information stored in each configuration register in the second configuration register group is function selection configuration information, and the circuit to be configured includes an interface unit and a function selector. like Figure 9 As shown, step 830 includes: Step 910: In response to the selection signal from the selection register, the control circuit outputs the attribute configuration information from the first target configuration register in the first configuration register group. Step 920: In response to the selection signal from the selection register, the control circuit outputs the function selection configuration information from the second target configuration register in the second configuration register group; Step 840 includes: Step 930: The interface unit operates based on the attribute configuration information output by the control circuit; Step 940: The function selector operates based on the function selection configuration information output by the control circuit.

[0081] In some alternative examples, the control circuitry includes a first multiplexer, with different first inputs of the first multiplexer electrically connected to different configuration registers in a first configuration register group, a first output of the first multiplexer electrically connected to an interface unit, and a first control terminal of the first multiplexer electrically connected to a selection register. like Figure 10 As shown, step 910 includes: Step 1010: Receive the selection signal from the selection register from the first control terminal via the first multiplexer; Step 1020: In response to the selection signal, the first multiplexer connects the first input terminal and the first output terminal corresponding to the first target configuration register in the first configuration register group, so that the first output terminal outputs the attribute configuration information from the first target configuration register in the first configuration register group to the interface unit.

[0082] In some optional examples, such as Figure 11 As shown, step 930 includes: Step 1110: Determine the actual number of attribute configuration parameters included in the attribute configuration information output by the first output terminal; Step 1120: Determine the numerical relationship between the actual quantity and the preset quantity; Step 1130: In response to determining that the attribute configuration information output by the first output terminal meets the preset parameter missing condition based on the numerical relationship, the attribute configuration information output by the first output terminal is processed to complete the attribute configuration parameters, so as to obtain target attribute configuration information including a preset number of attribute configuration parameters. Step 1140: Perform the work according to the target attribute configuration information.

[0083] In some optional examples, the control circuitry includes a second multiplexer, with different second inputs of the second multiplexer electrically connected to different configuration registers in the second configuration register group, a second output of the second multiplexer electrically connected to a function selector, and a second control terminal of the second multiplexer electrically connected to a selection register. like Figure 12 As shown, step 920 includes: Step 1210: Receive the selection signal from the selection register from the second control terminal via the second multiplexer; Step 1220: In response to the selection signal, the second multiplexer turns on the second input terminal and the second output terminal corresponding to the second target configuration register in the second configuration register group, so that the second output terminal outputs the function selection configuration information from the second target configuration register in the second configuration register group to the function selector.

[0084] In some optional examples, such as Figure 13 As shown, step 940 includes: Step 1310: Based on the function selection configuration information output from the second output terminal, determine the target function circuit to be selected from the multiple function circuits included in the chip; Step 1320: Connect the target function circuit and the interface unit to enable signal transmission between the target function module and the interface unit.

[0085] In the methods disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed in the exemplary circuit section above can be flexibly selected and combined as needed to achieve the corresponding functions and effects, and this disclosure does not list them all.

[0086] The beneficial technical effects corresponding to the exemplary embodiments of this method can be found in the corresponding beneficial technical effects of the exemplary circuit section described above, and will not be repeated here.

[0087] Exemplary electronic devices Figure 14 The illustration shows a block diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 1400 includes one or more processors 1410 and memory 1420.

[0088] The processor 1410 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1400 to perform desired functions.

[0089] The memory 1420 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1410 may execute one or more computer program instructions to implement the methods for configuring physical interface circuitry of the various embodiments of this disclosure described above, and / or other desired functions.

[0090] In one example, the electronic device 1400 may also include an input device 1430 and an output device 1440, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0091] The input device 1430 may also include, for example, a keyboard, a mouse, etc.

[0092] The output device 1440 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0093] Of course, for the sake of simplicity, Figure 14 Only some of the components of the electronic device 1400 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 1400 may include any other suitable components depending on the specific application.

[0094] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods for configuring physical interface circuitry according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0095] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0096] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the methods for configuring physical interface circuitry according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0097] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0098] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. The specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the specific details described above.

[0099] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A physical interface circuit applied to a chip, the chip running multiple virtual machines, the physical interface circuit comprising: A configuration register group, wherein different configuration registers in the configuration register group are used to store configuration information corresponding to different virtual machines; A selection register is used to store a selection signal, which is a signal that indicates the selection of a target virtual machine from a plurality of virtual machines; A control circuit, configured to output configuration information from a target configuration register in the configuration register group in response to a selection signal from the selection register; wherein the target configuration register refers to the configuration register that stores the configuration information corresponding to the target virtual machine; A circuit to be configured, which operates based on the configuration information output by the control circuit.

2. The physical interface circuit according to claim 1, wherein, The number of configuration register groups is multiple, and the target configuration register includes a first target configuration register and a second target configuration register. The multiple configuration register groups include: The first configuration register group, wherein the configuration information stored in each configuration register of the first configuration register group is attribute configuration information; The second configuration register group, wherein the configuration information stored in each configuration register in the second configuration register group is function selection configuration information; The control circuit is configured to respond to the selection signal from the selection register, output the attribute configuration information from the first target configuration register in the first configuration register group, and output the function selection configuration information from the second target configuration register in the second configuration register group; The circuit to be configured includes: An interface unit, which operates based on the attribute configuration information output by the control circuit; A function selector, which operates based on the function selection configuration information output by the control circuit.

3. The physical interface circuit according to claim 2, wherein, The control circuit includes: A first multiplexer, wherein different first input terminals of the first multiplexer are electrically connected to different configuration registers in the first configuration register group, a first output terminal of the first multiplexer is electrically connected to the interface unit, and a first control terminal of the first multiplexer is electrically connected to the selection register, the first multiplexer being configured to receive a selection signal from the selection register from the first control terminal, and in response to the selection signal, to connect the first input terminal corresponding to the first target configuration register in the first configuration register group to the first output terminal, so that the first output terminal outputs the attribute configuration information from the first target configuration register in the first configuration register group to the interface unit.

4. The physical interface circuit according to claim 3, wherein, The interface unit is used to determine the actual number of attribute configuration parameters included in the attribute configuration information output by the first output terminal; and to determine the numerical relationship between the actual number and the preset number. In response to determining that the attribute configuration information output by the first output terminal satisfies the preset parameter missing condition based on the numerical relationship, the attribute configuration information output by the first output terminal is subjected to attribute configuration parameter completion processing to obtain target attribute configuration information including a preset number of attribute configuration parameters. Work according to the target attribute configuration information.

5. The physical interface circuit according to claim 2, wherein, The control circuit includes: A second multiplexer, wherein different second input terminals of the second multiplexer are electrically connected to different configuration registers in the second configuration register group, a second output terminal of the second multiplexer is electrically connected to the function selector, and a second control terminal of the second multiplexer is electrically connected to the selection register, the second multiplexer being configured to receive a selection signal from the selection register from the second control terminal, and in response to the selection signal, to connect the second input terminal corresponding to the second target configuration register in the second configuration register group to the second output terminal, so that the second output terminal outputs the function selection configuration information from the second target configuration register in the second configuration register group to the function selector.

6. The physical interface circuit according to claim 5, wherein, The function selector is used to determine the target function circuit from the plurality of function circuits included in the chip based on the function selection configuration information output from the second output terminal; and to connect the target function circuit to the interface unit so that signal transmission can be performed between the target function module and the interface unit.

7. A chip comprising the physical interface circuit as described in any one of claims 1-6.

8. A method for configuring a physical interface circuit, the physical interface circuit being applied to a chip, the chip running multiple virtual machines, the physical interface circuit including a configuration register set, a selection register, a control circuit, and a circuit to be configured, the method comprising: The configuration information corresponding to different virtual machines is stored in different configuration registers in the configuration register group; The selection register stores a selection signal, which is a signal representing the selection of a target virtual machine from among the plurality of virtual machines; The control circuit responds to the selection signal from the selection register and outputs the configuration information from the target configuration register in the configuration register group; wherein, the target configuration register refers to the configuration register that stores the configuration information corresponding to the target virtual machine; The circuit to be configured operates based on the configuration information output by the control circuit.

9. A computer-readable storage medium storing a computer program that is executed by a processor to implement the method for configuring physical interface circuitry as described in claim 8.

10. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for configuring the physical interface circuit as described in claim 8.

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