Heterogeneous hardware computing power scheduling method and system

Abstract

The present application relates to computer computing power scheduling technical field, specifically for heterogeneous hardware computing power scheduling method and system;The method comprises: obtaining the task execution data of target task and the hardware constraint data of each heterogeneous hardware, dividing the target task into starting trial calculation section and formal execution section, determining candidate trial calculation hardware set and candidate main calculation hardware set;Control each candidate trial calculation hardware to carry out trial calculation processing to starting trial calculation section, generate reservation state page and determine candidate reservation state page;Identify main calculation access restriction item set and calculate shaping workload, determine target reservation state page and target main calculation hardware, reverse shaping to target reservation state page, obtain main calculation entry state;Generate computing power scheduling instruction, and schedule formal execution section to target main calculation hardware execution.The present application realizes the unified screening of the task front segment trial calculation result under the heterogeneous hardware environment, the accurate determination of the target main calculation hardware and the orderly scheduling of the formal execution section.

Description

Technical Field

[0001] This invention relates to the field of computer computing power scheduling technology, specifically to a method and system for scheduling computing power in heterogeneous hardware. Background Technology

[0002] With the continuous increase in the types of computing tasks and the ongoing evolution of computing platform architecture, heterogeneous computing, which uses central processing units, graphics processing units, neural network processors, and other dedicated acceleration hardware to jointly carry out the execution of the same task, has been widely applied in scenarios such as artificial intelligence inference, data processing, graph computing, industrial control analysis, and real-time scheduling. In such heterogeneous computing scenarios, different hardware differs in terms of execution interfaces, data organization methods, operator connection relationships, and dependency handling methods. Switching between different hardware has become a common means to improve overall computing power utilization and adapt to the processing needs of different task stages. Therefore, how to orderly schedule the task execution process in a heterogeneous hardware environment has become an important research topic in computer task scheduling and resource allocation technology. In scenarios where heterogeneous hardware performs pre-processing of the same task and connects it to subsequent formal execution, there are still problems such as the difficulty in directly connecting the pre-processing results to the subsequent formal execution, and the difficulty in establishing a unified screening basis for multiple pre-processing results. Specifically, on the one hand, the intermediate results, execution points, data layouts, and dependencies formed by different heterogeneous hardware during the pre-processing of the task differ. After the pre-processing is completed, the results often cannot be directly accessed by the subsequent formal execution hardware, which may lead to the need to reorganize the data, readjust the dependencies, or re-establish the execution entry point. On the other hand, when multiple candidate hardware performs the pre-processing of the same task in parallel, the recorded content, field completeness, and correspondence of each pre-processing result are likely to differ, resulting in a lack of a unified comparison basis between different pre-processing results, making it difficult to stably determine the pre-processing result that is more suitable as the basis for subsequent formal execution and its corresponding target hardware. Summary of the Invention

[0003] The purpose of this invention is to provide a method and system for scheduling computing power in heterogeneous hardware, so as to solve the problems mentioned in the background art, such as the difficulty in directly connecting the front-end trial calculation results to the back-end formal execution and the difficulty in establishing a unified screening basis for multiple trial calculation results.

[0004] To achieve the above objectives, the technical solution of the present invention is a heterogeneous hardware computing power scheduling method, comprising: S1. Obtain the task execution data of the target task and the hardware constraint data of each heterogeneous hardware. Divide the target task into the initial trial calculation segment and the formal execution segment according to the preset stage division rules. Determine the candidate trial calculation hardware set and the candidate main calculation hardware set from the heterogeneous hardware, and establish the corresponding trial calculation execution context and main calculation execution context respectively. The initial trial calculation segment is the preliminary trial calculation task segment in the target task; the formal execution segment is the subsequent main calculation task segment in the target task; the candidate trial calculation hardware set is a heterogeneous hardware set used to carry the trial calculation processing of the initial trial calculation segment; and the candidate main calculation hardware set is a heterogeneous hardware set used to carry the main calculation execution of the formal execution segment. S2. Control each candidate trial calculation hardware in the candidate trial calculation hardware set to perform trial calculation processing on the initial trial calculation segment in parallel, generate the reserved status page corresponding to each candidate trial calculation hardware, perform field integrity verification processing on each reserved status page, and determine the candidate reserved status page. Among them, the reserved status page is the status page that carries the trial calculation status information, which includes the intermediate result identifier field, the execution point identifier field, the data layout identifier field, and the dependency identifier field; the candidate reserved status page is the reserved status page whose field integrity meets the preset requirements. S3. Map each candidate reserved state page to each candidate main computing hardware. Identify the corresponding set of main computing access restrictions based on the hardware constraint data of each candidate main computing hardware. Calculate the shaping workload based on the set of main computing access restrictions. Determine the target reserved state page and target main computing hardware according to the order of the number of main computing access restrictions from fewest to most, the shaping workload from fewest to most, and the preset sorting identifier. Then, perform reverse shaping on the target reserved state page based on the set of main computing access restrictions corresponding to the target main computing hardware to obtain the main computing entry state. Among them, the master computing access restriction set is the set of access constraints that exist when the candidate master computing hardware receives the corresponding candidate reserved state page; the shaping workload is the number of shaping actions required to eliminate the master computing access restriction set; reverse shaping is the targeted state adjustment processing performed on the target reserved state page in accordance with the access requirements of the target master computing hardware; the master computing entry state is the execution state that meets the access requirements of the target master computing hardware after reverse shaping; S4. Generate computing power scheduling instructions based on the target main computing hardware, write the main computing entry state into the main computing execution context corresponding to the target main computing hardware, and schedule the formal execution segment to be executed on the target main computing hardware.

[0005] Preferably, in step S1, the initial trial calculation segment is used to output the trial calculation status information corresponding to the reserved status page; the formal execution segment is used to receive the main calculation entry status and execute subsequent task segments of the target task; wherein, the initial trial calculation segment is a continuous task segment starting from the starting execution point of the target task, including the task segment that generates the trial calculation status information corresponding to the reserved status page; the formal execution segment is a continuous task segment starting from the adjacent execution point after the end execution point of the initial trial calculation segment, including subsequent task segments in the target task located after the initial trial calculation segment; the end execution point of the initial trial calculation segment is adjacent to the start execution point of the formal execution segment, and the execution point corresponding to the main calculation entry status is consistent with the start execution point of the formal execution segment; the trial calculation execution context is a context carrying the execution status information corresponding to the initial trial calculation segment and the status information corresponding to the reserved status page; the main calculation execution context is a context carrying the execution status information corresponding to the formal execution segment and the main calculation entry status.

[0006] Preferably, in S2, the trial calculation process is a parallel processing operation that advances the initial trial calculation segment segment by segment according to the execution position order and synchronously writes the trial calculation status information; controlling each candidate trial calculation hardware in the candidate trial calculation hardware set to perform the trial calculation process of the initial trial calculation segment in parallel, specifically: within the trial calculation execution context corresponding to each candidate trial calculation hardware, the initial trial calculation segment is advanced according to the same execution starting point, and after each execution position is completed, the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field are written respectively, and after the initial trial calculation segment is completed, it is encapsulated to form a reserved status page corresponding to each candidate trial calculation hardware; the reserved status page is used to carry the continuable trial calculation status information corresponding to the initial trial calculation segment, and the page data structure of the reserved status page is a page-type data structure composed of a page header identifier area, a field index area, and a status record area. The field index area is used to limit the writing position and reading order of the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the status record area, and each field in the reserved status page is written in the corresponding execution position order.

[0007] Preferably, in step S2, the field integrity verification process is a verification process performed on the field placeholder relationship, field order relationship, and field correspondence relationship in the reserved state page, used to filter candidate reserved state pages that meet the main computation mapping conditions; the field integrity verification process includes field existence verification, field order verification, and field correspondence verification; the candidate reserved state page is a reserved state page that has passed the field integrity verification process and maintains a single-page continuous record relationship; the field integrity verification process is performed on each reserved state page to determine the candidate reserved state page, specifically: reading the page header identifier area, field index area, and status record area in each reserved state page, verifying whether the intermediate result identifier field, execution point identifier field, data layout identifier field, and dependency identifier field all have corresponding index entries in the field index area, verifying whether the arrangement order of each field in the status record area is consistent with the execution point order, verifying whether each field maintains a one-to-one correspondence record relationship under the same execution point, and determining the reserved state page that simultaneously passes the field existence verification, field order verification, and field correspondence verification as the candidate reserved state page.

[0008] Preferably, in step S3, the master computing access restriction set is a set of restrictions characterizing access inconsistencies between candidate reserved state pages and candidate master computing hardware. The master computing access restriction is a restriction characterizing the existence of a single access constraint when the candidate master computing hardware receives the candidate reserved state page. The master computing access restriction includes execution interface restriction, input layout restriction, operator adjacency restriction, branch access restriction, and dependency access restriction. Each candidate reserved state page is mapped to each candidate master computing hardware in the candidate master computing hardware set. Specifically, each candidate reserved state page is paired with each candidate master computing hardware for mapping. The intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the candidate reserved state page are read and compared item by item with the execution interface constraint data, input layout restriction data, operator adjacency restriction data, branch access restriction data, and dependency access restriction data of the corresponding candidate master computing hardware. Inconsistencies in the comparison are determined as master computing access restrictions and aggregated to form the master computing access restriction set corresponding to the mapping combination.

[0009] Preferably, in step S3, the shaping workload is the result of the number of shaping actions required to make the candidate retained state page meet the access constraints of the candidate main computing hardware. The shaping workload is calculated based on the set of main computing access constraints, specifically by: counting the number of execution interface reconfigurations corresponding to the execution interface constraints, the number of data layout corrections corresponding to the input layout constraints, the number of operator adjacency roundings corresponding to the operator adjacency constraints, the number of branch flattenings corresponding to the branch access constraints, and the number of dependency reconnections corresponding to the dependency access constraints, and summing the counts to obtain the shaping workload corresponding to each candidate retained state page and each candidate main computing hardware combination.

[0010] Preferably, in step S3, the preset sorting identifier order is the candidate main computing hardware identifier code in ascending order; the target reserved state page is the candidate reserved state page ranked first after being sorted sequentially according to the number of main computing access restrictions, the shaping workload, and the preset sorting identifier order; the target main computing hardware is the candidate main computing hardware corresponding to the target reserved state page in the same sorting result; the reverse shaping process involves performing interface reconfiguration, data layout correction, operator adjacency rebalancing, branch flattening, and dependency reconnection state adjustment processing on each main computing access restriction corresponding to the target main computing hardware; and the main computing entry state is the target reserved state page after reverse shaping. After shaping, the execution state satisfies the access constraints of the target main computing hardware. Based on the set of main computing access restrictions corresponding to the target main computing hardware, the target reserved state page is subjected to reverse shaping. Specifically, the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the target reserved state page are read. According to the restriction type of the main computing access restriction, the corresponding interface reconfiguration, data layout correction, operator adjacency resetting, branch flattening, and dependency reconnection are performed. The corresponding field records in the target reserved state page are updated, and the execution state corresponding to the updated target reserved state page is determined as the main computing entry state.

[0011] On the other hand, the present invention provides a heterogeneous hardware computing power scheduling system, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the heterogeneous hardware computing power scheduling method described above.

[0012] Compared with the prior art, the above-mentioned technical solution of the present invention has the following beneficial technical effects: 1. In this invention, the reserved state page, the candidate reserved state page screening rules, and the mapping processing between the candidate reserved state page and the candidate main computing hardware formed by the initial trial calculation process can uniformly record, verify, and compare different trial calculation results when multiple heterogeneous hardware perform parallel trial calculations of the same task front end, thus avoiding the problem of difficulty in screening trial calculation results due to inconsistent recorded content, missing fields, or unclear correspondence. 2. In this invention, by identifying the set of main computing access restrictions, calculating the shaping workload, and performing reverse shaping processing on the target main computing hardware, the invention achieves targeted adjustment of the access differences between the front-end trial calculation results and the back-end formal execution hardware. This enables the execution state formed by the front-end trial calculation to be converted into a main computing entry state that the target main computing hardware can directly access, reducing the data reorganization, dependency reconstruction, and execution entry reconstruction processing before subsequent formal execution. Attached Figure Description

[0013] Figure 1 This is a flowchart of an embodiment of the present invention. Detailed Implementation

[0014] Example 1, as Figure 1 As shown, the heterogeneous hardware computing power scheduling method proposed in this invention has the following specific implementation steps: S1. Obtain the task execution data of the target task and the hardware constraint data of each heterogeneous hardware. Divide the target task into the initial trial calculation segment and the formal execution segment according to the preset stage division rules. Determine the candidate trial calculation hardware set and the candidate main calculation hardware set from the heterogeneous hardware, and establish the corresponding trial calculation execution context and main calculation execution context respectively. The initial trial calculation segment is the preliminary trial calculation task segment in the target task; the formal execution segment is the subsequent main calculation task segment in the target task; the candidate trial calculation hardware set is a heterogeneous hardware set used to carry the trial calculation processing of the initial trial calculation segment; and the candidate main calculation hardware set is a heterogeneous hardware set used to carry the main calculation execution of the formal execution segment. S2. Control each candidate trial calculation hardware in the candidate trial calculation hardware set to perform trial calculation processing on the initial trial calculation segment in parallel, generate the reserved status page corresponding to each candidate trial calculation hardware, perform field integrity verification processing on each reserved status page, and determine the candidate reserved status page. Among them, the reserved status page is the status page that carries the trial calculation status information, which includes the intermediate result identifier field, the execution point identifier field, the data layout identifier field, and the dependency identifier field; the candidate reserved status page is the reserved status page whose field integrity meets the preset requirements. S3. Map each candidate reserved state page to each candidate main computing hardware. Identify the corresponding set of main computing access restrictions based on the hardware constraint data of each candidate main computing hardware. Calculate the shaping workload based on the set of main computing access restrictions. Determine the target reserved state page and target main computing hardware according to the order of the number of main computing access restrictions from fewest to most, the shaping workload from fewest to most, and the preset sorting identifier. Then, perform reverse shaping on the target reserved state page based on the set of main computing access restrictions corresponding to the target main computing hardware to obtain the main computing entry state. Among them, the master computing access restriction set is the set of access constraints that exist when the candidate master computing hardware receives the corresponding candidate reserved state page; the shaping workload is the number of shaping actions required to eliminate the master computing access restriction set; reverse shaping is the targeted state adjustment processing performed on the target reserved state page in accordance with the access requirements of the target master computing hardware; the master computing entry state is the execution state that meets the access requirements of the target master computing hardware after reverse shaping; S4. Generate computing power scheduling instructions based on the target main computing hardware, write the main computing entry state into the main computing execution context corresponding to the target main computing hardware, and schedule the formal execution segment to be executed on the target main computing hardware.

[0015] In this embodiment S1, the initial trial calculation segment is used to output the trial calculation status information corresponding to the reserved status page; the formal execution segment is used to receive the main calculation entry status and execute the subsequent task segments of the target task; wherein, the initial trial calculation segment is a continuous task segment starting from the starting execution point of the target task, including the task segment that generates the trial calculation status information corresponding to the reserved status page; the formal execution segment is a continuous task segment starting from the adjacent execution point after the end execution point of the initial trial calculation segment, including the subsequent task segments of the target task located after the initial trial calculation segment; the end execution point of the initial trial calculation segment is adjacent to the start execution point of the formal execution segment, and the execution point corresponding to the main calculation entry status is consistent with the start execution point of the formal execution segment; the trial calculation execution context is a context that carries the execution status information corresponding to the initial trial calculation segment and the status information corresponding to the reserved status page; the main calculation execution context is a context that carries the execution status information corresponding to the formal execution segment and the main calculation entry status.

[0016] In this embodiment S1, the target task is a task object that can be expanded into multiple execution points according to the execution sequence. The task execution data is used to characterize the sequential relationship, segment boundary relationship, and state carrying relationship of the target task during the execution process. The task execution data includes the execution point sequence, the preceding and following connection relationship between points, the input and output relationship corresponding to the points, the data layout information corresponding to the points, the dependency relationship information between points, and the task start position identifier information. The execution point sequence is used to indicate the arrangement order of each processing position within the target task. The preceding and following connection relationship is used to indicate the direct connection state between adjacent execution points. The input and output relationship is used to indicate the data entry relationship and data output relationship corresponding to each execution point. The data layout information is used to indicate the organization method corresponding to the data processing at each execution point. The dependency relationship information is used to indicate the succession relationship between the previous execution point and the next execution point. The task start position identifier information is used to determine the starting execution point of the target task.

[0017] In this embodiment S1, heterogeneous hardware refers to multiple hardware execution objects that differ in processing capability type, execution interface form, data access method, and state acceptance method. Hardware constraint data is used to characterize the bearing conditions and access conditions of each heterogeneous hardware for the task execution process. Hardware constraint data includes execution interface constraint data, input layout constraint data, operator adjacency constraint data, branch access constraint data, and dependency access constraint data. Execution interface constraint data is used to characterize the hardware's acceptance conditions for the task execution entry form, input layout constraint data is used to characterize the hardware's acceptance conditions for the input data organization method, operator adjacency constraint data is used to characterize the hardware's acceptance conditions for adjacent processing relationships, branch access constraint data is used to characterize the hardware's acceptance conditions for branch processing relationships, and dependency access constraint data is used to characterize the hardware's acceptance conditions for preceding and following relationships.

[0018] In this embodiment S1, the preset stage division rule is used to divide the target task into an initial trial calculation segment and a formal execution segment. The preset stage division rule is based on the execution point sequence, the connection relationship between points, and the task segment continuity rule. The task segment continuity rule includes the continuous point arrangement rule, the adjacent point connection rule, and the unidirectional advancement rule. The continuous point arrangement rule is used to limit the execution points within the same task segment to be arranged continuously according to the execution point sequence. The adjacent point connection rule is used to limit the execution point at the end of the previous task segment to be adjacent to the execution point at the beginning of the next task segment. The unidirectional advancement rule is used to limit the sequential advancement direction of each execution point after the task segment is divided to be consistent. When dividing according to this rule, the starting execution point of the target task is first determined, and then the preliminary trial calculation range is determined step by step along the execution point sequence according to the continuous point arrangement rule. When the continuous point sequence reaches the preset trial calculation boundary, the continuous point sequence is determined as the initial trial calculation segment, and the continuous point sequence starting from the adjacent execution point after the end of the continuous point sequence is determined as the formal execution segment.

[0019] In this embodiment S1, the initial trial calculation segment is the preceding trial calculation task segment in the target task, and the initial trial calculation segment undertakes the relationship of the preceding trial calculation state. The initial trial calculation segment starts from the starting execution point of the target task and expands continuously along the execution point sequence, and includes continuous task segments used to form trial calculation state information. The formal execution segment is the subsequent main calculation task segment in the target task, and the formal execution segment undertakes the relationship of the subsequent execution. The formal execution segment starts from the adjacent execution point after the end execution point of the initial trial calculation segment and expands continuously along the execution point sequence, and includes continuous task segments located after the initial trial calculation segment. The end execution point of the initial trial calculation segment is adjacent to the start execution point of the formal execution segment, and the execution point corresponding to the main calculation entry state is consistent with the start execution point of the formal execution segment. After the task segments are divided, the execution order, the point succession, and the task boundary are maintained.

[0020] In this embodiment S1, the determination of the candidate trial calculation hardware set is based on the adaptation judgment between the starting trial calculation segment and each heterogeneous hardware. The adaptation judgment includes whether the execution entry of the starting trial calculation segment meets the execution interface constraints, whether the data layout corresponding to the starting trial calculation segment meets the input layout restrictions, whether the adjacent processing relationship within the starting trial calculation segment meets the operator adjacency restrictions, whether the branch relationship within the starting trial calculation segment meets the branch access restrictions, and whether the dependency relationship within the starting trial calculation segment meets the dependency access restrictions. The adaptation judgment is performed on each heterogeneous hardware one by one, and the heterogeneous hardware that meets all the judgment items is determined as the candidate trial calculation hardware and is collected to form the candidate trial calculation hardware set. The candidate trial calculation hardware set and the starting trial calculation segment maintain a one-to-many bearing relationship, and each candidate trial calculation hardware can perform trial calculation processing on the starting trial calculation segment.

[0021] In this embodiment S1, the trial calculation execution context is a context that carries the execution status information corresponding to the initial trial calculation segment and the status information corresponding to the reserved status page. The content recorded in the trial calculation execution context includes the initial trial calculation segment identifier information, the current execution position information, the position advancement order information, the trial calculation status write position, the field write status information, and the reserved status page association information. The initial trial calculation segment identifier information is used to identify the preceding trial calculation task segment corresponding to the current trial calculation execution context. The current execution position information is used to identify the current position of the trial calculation advancement. The position advancement order information is used to limit the advancement order of each execution position. The trial calculation status write position is used to limit the write position of the trial calculation status information in the subsequent status page. The field write status information is used to identify the completion status of the write of each field in the status page. The reserved status page association information is used to establish the trial calculation execution. The correspondence between the context and the reserved state page; the main computing execution context is the context that carries the execution state information corresponding to the formal execution segment and the main computing entry state; the content recorded in the main computing execution context includes formal execution segment identification information, starting execution point information, main computing entry state access position, subsequent execution point advancement information, and formal execution state acceptance information; the formal execution segment identification information is used to identify the subsequent main computing task segment corresponding to the current main computing execution context, the starting execution point information is used to limit the starting execution position of the formal execution segment, the main computing entry state access position is used to limit the corresponding acceptance position after the main computing entry state is written, the subsequent execution point advancement information is used to limit the advancement order of each execution point in the formal execution segment, and the formal execution state acceptance information is used to establish the state acceptance relationship between the main computing entry state and the formal execution segment.

[0022] In this embodiment S1, the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field have their meanings defined during the task execution data and context establishment phase. The intermediate result identifier field identifies the intermediate result object and its intermediate result position formed after the initial trial calculation segment progresses through each execution position. The execution position identifier field identifies the specific execution position corresponding to the trial calculation status information. The data layout identifier field identifies the data organization method of the intermediate result object at the corresponding execution position. The dependency identifier field identifies the dependency relationship between the current execution position and the preceding and following execution positions. These four types of fields already have fixed meanings and fixed functions before being written to the reserved status page. Specifically, the intermediate result identifier field corresponds to the status result object, the execution position identifier field corresponds to the position sequence object, the data layout identifier field corresponds to the data organization object, and the dependency identifier field corresponds to... The tasks should be sequentially connected; task segmentation, candidate hardware determination, and context establishment should be performed in a unified order. First, the task segmentation basis should be determined based on task execution data and hardware constraint data. Then, candidate trial hardware sets and candidate main computing hardware sets should be determined based on the initial trial segment and the formal execution segment, respectively. Subsequently, the trial execution context should be established based on the correspondence between the initial trial segment and the candidate trial hardware set, and the main computing execution context should be established based on the correspondence between the formal execution segment and the candidate main computing hardware set. Under this order, the task segment boundary, hardware bearing boundary, and state bearing boundary should form a consistent correspondence. The initial trial segment corresponds to the trial execution context, and the formal execution segment corresponds to the main computing execution context. The final execution point in the trial execution context is adjacent to the initial execution point in the main computing execution context. The connection between the trial state information corresponding to the state page and the execution point corresponding to the main computing entry state should be kept consistent.

[0023] In this embodiment S2, the trial calculation process is a parallel processing operation that advances the initial trial calculation segment segment by segment according to the execution point order and synchronously writes the trial calculation status information. This is used to form a reserved state page on each candidate trial calculation hardware that can be used for subsequent main calculation mapping. The process controls each candidate trial calculation hardware in the candidate trial calculation hardware set to perform the trial calculation process on the initial trial calculation segment in parallel. Specifically, within the trial calculation execution context corresponding to each candidate trial calculation hardware, the initial trial calculation segment is advanced according to the same execution starting point. After each execution point is completed, the intermediate result identifier field, execution point identifier field, data layout identifier field, and dependency identifier field are written respectively. After the trial calculation is completed, it is encapsulated to form a reserved status page corresponding to each candidate trial calculation hardware. The reserved status page is used to carry the continuable trial calculation status information corresponding to the starting trial calculation segment. The page data structure of the reserved status page is a page-type data structure consisting of a page header identification area, a field index area, and a status record area. The field index area is used to limit the writing position and reading order of the intermediate result identification field, execution position identification field, data layout identification field, and dependency identification field in the status record area. Each field in the reserved status page is written in the order of execution position to ensure that the trial calculation status information in the same reserved status page maintains a single-page continuous recording relationship.

[0024] In this embodiment S2, the trial calculation process is a parallel advancement process that unfolds around the execution point sequence corresponding to the initial trial calculation segment. Each candidate trial calculation hardware, within its corresponding trial calculation execution context, starts from the same initial execution point and executes the initial trial calculation segment bit by bit according to a consistent execution point advancement order. Each time an execution point is advanced, a write preparation is performed on the trial calculation state information formed by that execution point. The trial calculation state information is not temporarily stored in the form of scattered variables, but is imported into the reserved state page according to the page writing rules. Each candidate trial calculation hardware maintains the same trial calculation start point, the same point sequence, and the same task segment boundary, thereby making the page records formed by different candidate trial calculation hardware comparable. In this embodiment, the parallel relationship is manifested as multiple candidate trial calculation hardware independently advancing the same preceding trial calculation task segment, the trial calculation execution contexts corresponding to each candidate trial calculation hardware being separated from each other, and the page records formed by each candidate trial calculation hardware being independent from each other.

[0025] In this embodiment S2, the trial calculation is advanced by writing each execution point bit by bit. After each execution point is completed, the intermediate result information, current point information, current data organization information, and current dependency inheritance information corresponding to that execution point are immediately extracted from the current trial calculation execution context and written to the corresponding field positions in the reserved status page. When the current point continues to advance to the next execution point, the field records already written at the previous execution point are kept unwritten, and only the field records corresponding to the next execution point are added. After the execution point at the end of the initial trial calculation segment is completed, a continuous field record covering the entire initial trial calculation segment is formed in the reserved status page. After the trial calculation completion mark is written to the top identifier area of ​​the page, the current reserved status page ends writing and enters the subsequent field integrity verification process.

[0026] In this embodiment S2, the reserved status page is a page-style status record object formed after the structured collection of the trial calculation status information of the initial trial calculation segment. The reserved status page carries the page status record corresponding to the initial trial calculation segment. The page status record is organized by the execution position as the main line, the field index as the reading entry point, and the status record as the content. The page data structure of the reserved status page consists of a header identification area, a field index area, and a status record area. The header identification area records the candidate trial calculation hardware identifier, the initial trial calculation segment identifier, the page start execution position, the page end execution position, and the page completion mark. The field index area records the field number, field write position, field read position, and field arrangement order corresponding to the intermediate result identifier field, the execution position identifier field, the data layout identifier field, and the dependency identifier field. The status record area records the actual content of the fields arranged in the order of the execution positions.

[0027] In this embodiment S2, the intermediate result identifier field is used to record the intermediate result object identifier, intermediate result storage location identifier, and intermediate result record sequence number formed after a certain execution point is advanced; the execution point identifier field is used to record the execution point number, execution order number, and adjacent relationship identifier of the current field record; the data layout identifier field is used to record the organization method identifier, arrangement method identifier, and layout position identifier of the output data of the current execution point in the page record; the dependency identifier field is used to record the succession relationship identifier and dependency relationship identifier between the current execution point and the previous and next execution points; the four types of fields are written to the status record area in a fixed arrangement order under the same execution point, and the field index area performs index registration on this fixed arrangement order; a group of four-field records corresponding to the same execution point constitutes a group of point record units, and multiple point record units are arranged end to end according to the execution point order to form a page status record covering the initial trial calculation segment; the page header identifier area, There is a fixed correspondence between the field index area and the status record area; the header identifier area defines the page boundaries and page identity, the field index area defines the field positions and field order, and the status record area carries the actual content of the fields; the page start execution point and the page end execution point in the header identifier area determine the range of task positions covered by the current page, the field number in the field index area and the field write position jointly determine the positioning relationship of each field in the status record area, and the field records in the status record area are arranged continuously according to the execution point order and field order rules; under the same execution point, the intermediate result identifier field, execution point identifier field, data layout identifier field and dependency identifier field maintain the same group arrangement relationship in the status record area; under adjacent execution points, the two groups of field records are arranged continuously in the status record area according to the position order; when reading the page, the header identifier area is read first to determine the page range, then the field index area is read to determine the field position, and finally the status record area is read to extract the corresponding field content.

[0028] In this embodiment S2, when performing parallel control on each candidate calculation hardware in the candidate calculation hardware set, the same starting calculation segment range information and the same position advancement order information are first loaded for each candidate calculation hardware according to the starting execution position, ending execution position, and execution position order of the starting calculation segment. Then, a unified calculation start flag is written to the calculation execution context corresponding to each candidate calculation hardware, and each candidate calculation hardware is triggered to start calculation advancement from the same starting execution position based on the unified calculation start flag. During the calculation advancement process, each candidate calculation hardware executes position by position according to the same execution position order and synchronously executes field writing after each execution position is completed. Before any candidate calculation hardware completes the writing of the field corresponding to the current execution position, it does not switch to the next execution position. After each candidate calculation hardware completes the writing of the field corresponding to the ending execution position of the starting calculation segment, a page completion flag is written, and the page writing status in the corresponding calculation execution context is updated to a verifiable status.

[0029] In this embodiment S2, the method steps for performing trial calculation on the initial trial calculation segment include: reading the starting execution point and the ending execution point of the initial trial calculation segment; determining the current execution point to be calculated according to the execution point order; after the current execution point to be calculated completes the trial calculation progress; extracting the intermediate result information, point identifier information, data layout information, and dependency information corresponding to the current execution point from the trial calculation execution context; writing the extracted results into the intermediate result identifier field, execution point identifier field, data layout identifier field, and dependency identifier field in the reserved state page, respectively; after completing the writing of the fields corresponding to the current execution point, switching to the next execution point to continue execution, until the fields corresponding to the ending execution point of the initial trial calculation segment are written, and encapsulating them to form a reserved state page. The encapsulated reserved state page is then sent to the field integrity verification process. The execution connection between the formal execution segment and the main calculation entry state is as follows: the execution position corresponding to the main calculation entry state is consistent with the starting execution position of the formal execution segment. The formal execution segment continues to advance along the execution position sequence starting from this starting execution position. The position range information and position advancement order information of the formal execution segment are pre-written in the main calculation execution context. After the main calculation entry state is written into the main calculation execution context, the intermediate result correspondence information, position correspondence information, data layout correspondence information, and dependency correspondence information in the main calculation entry state are used as the basis for the inheritance of the starting execution position of the formal execution segment. The main calculation execution context continues to execute the subsequent positions according to the execution position sequence of the formal execution segment.

[0030] In this embodiment S2, the field integrity verification process is a verification process performed on the field placeholder relationship, field order relationship, and field correspondence relationship in the reserved state page, used to filter candidate reserved state pages that meet the main computation mapping conditions; the field integrity verification process includes field existence verification, field order verification, and field correspondence verification; the candidate reserved state page is a reserved state page that has passed the field integrity verification process and maintains a single-page continuous record relationship; the field integrity verification process is performed on each reserved state page to determine the candidate reserved state page, specifically: reading the page header identifier area, field index area, and status record area in each reserved state page, verifying whether the intermediate result identifier field, execution point identifier field, data layout identifier field, and dependency identifier field all have corresponding index entries in the field index area, verifying whether the arrangement order of each field in the status record area is consistent with the execution point order, verifying whether each field maintains a one-to-one correspondence record relationship under the same execution point, and determining the reserved state page that has passed the field existence verification, field order verification, and field correspondence verification simultaneously as a candidate reserved state page.

[0031] In this embodiment S2, the execution site order is an ordered arrangement of execution sites within the target task according to their sequential succession relationship. The execution site order takes the starting execution site of the target task as the starting point, the sequential connection relationship and dependency relationship between the sites as the basis for the arrangement, and records the sequential order of each execution site in a unidirectional advancement manner. The execution site order is used to limit the advancement order of sites in the initial trial calculation segment, the arrangement order of field records in the reserved status page, and the continuation order of sites in the formal execution segment. Among them, the field record corresponding to the previous execution site is located before the field record corresponding to the next execution site, and the dependency relationship record of the previous execution site corresponds to the starting point record of the next execution site. The execution site order is consistent between the initial trial calculation segment, the reserved status page, the candidate reserved status page, the main calculation entry state, and the formal execution segment.

[0032] In this embodiment S2, the field integrity verification process is a page verification process performed around whether the field records within the retained status page are complete, correctly arranged, and consistent. The field integrity verification process includes field existence verification, field order verification, and field correspondence verification. The field existence verification is performed on the field index area to verify whether each execution point record unit simultaneously has an intermediate result identifier field index item, an execution point identifier field index item, a data layout identifier field index item, and a dependency identifier field index item. The field order verification is performed on the status record area to verify whether the arrangement order of each execution point record unit in the status record area is consistent with the execution point sequence, and at the same execution point, whether the internal arrangement order of the four types of fields is consistent with the registration order in the field index area. The field correspondence verification is performed on both the field index area and the status record area to verify whether the four types of fields under the same execution point point to the same point number, the same record group number, and the same page interval.

[0033] In this embodiment S2, the specific process of performing field integrity verification on each reserved state page is as follows: First, read the page start execution point and page end execution point in the page header identifier area to determine the range of points that the current page should cover; then read the field number, field position, and field order in the field index area to determine the set of fields that the current page should have; subsequently, read the point record units in the status record area one by one according to the point range defined by the page header identifier area, and perform field existence verification, field order verification, and field correspondence verification on each point record unit; when the field existence verification passes, it indicates that the current point record unit has a complete four-field record; when the field order verification passes, it indicates that the arrangement order between the current point record unit and the adjacent point record units conforms to the execution point order; when the field correspondence verification passes, it indicates that the four-field records in the current point record unit belong to the same execution point and correspond to each other; only when all point record units within the page coverage area pass the three types of verifications is the current reserved state page determined as a candidate reserved state page.

[0034] In this embodiment S2, the candidate reserved state page is not an ordinary complete page, but a valid page record object formed after page hierarchy field verification. The candidate reserved state page has at least three attributes: complete page coverage, complete field record relationship, and complete position arrangement relationship. Complete page coverage means that there are corresponding position record units within the range from the starting execution position to the ending execution position defined by the header identifier area. Complete field record relationship means that each position record unit contains an intermediate result identifier field, an execution position identifier field, a data layout identifier field, and a dependency identifier field. Complete position arrangement relationship means that all position record units are arranged continuously in the execution position order, and there are no empty positions, skipped positions, or duplicate position records between adjacent position record units. Page record objects that meet the above conditions enter the candidate reserved state page. Select a set of reserved status pages; page record objects that do not meet the above conditions will have their subsequent processing terminated. There is a stable correspondence between the trial execution context and the reserved status pages. Each candidate trial hardware corresponds to a trial execution context, and each trial execution context outputs a reserved status page after the current trial is completed. The current execution position information, position advancement order information, field write status information, and page association information in the trial execution context correspond one-to-one with the page header identification area, field index area, and status record area in the reserved status page. Among them, the current execution position information corresponds to the position record unit boundary in the status record area, the position advancement order information corresponds to the position arrangement order in the status record area, the field write status information corresponds to the field write completion status in the field index area, and the page association information corresponds to the page identity identifier in the page header identification area.

[0035] In this embodiment S2, the roles of the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the page record remain fixed. The intermediate result identifier field corresponds to the result object record after the trial calculation is advanced, the execution position identifier field corresponds to the trial calculation advancement position record, the data layout identifier field corresponds to the result object organization method record, and the dependency identifier field corresponds to the positional relationship record. These four types of fields together form the smallest record unit in the page record. If any of these fields is missing, the current position record unit does not meet the conditions for a complete page record. Therefore, the field integrity verification process targets the page verification process that is jointly performed around the position record unit, the field group relationship, and the page continuity relationship. When candidate trial calculation hardware proceeds in parallel to the initial trial calculation stage, the page record structure, field arrangement order, and verification rules remain consistent. A consistent page data structure constrains the reserved state pages output by different candidate trial calculation hardware to have the same page boundary format, the same field index format, and the same state record format. A consistent field arrangement order constrains the position record units output by different candidate trial calculation hardware to maintain a consistent field order within the state record area. Consistent verification rules constrain the reserved state pages output by different candidate trial calculation hardware to enter the candidate reserved state page set according to the same criteria. Under these conditions, the candidate reserved state pages formed by different candidate trial calculation hardware maintain a consistent recording basis in terms of page structure, field relationships, and position record order.

[0036] In this embodiment S3, the master computing access restriction set is a set of restrictions that characterizes access inconsistencies between candidate reserved state pages and candidate master computing hardware. Master computing access restrictions characterize restrictions that characterize single access constraints when candidate master computing hardware receives candidate reserved state pages. Master computing access restrictions include execution interface restrictions, input layout restrictions, operator adjacency restrictions, branch access restrictions, and dependency access restrictions. Each candidate reserved state page is mapped to each candidate master computing hardware in the candidate master computing hardware set. Specifically, each candidate reserved state page is paired with each candidate master computing hardware for mapping. The intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the candidate reserved state page are read and compared item by item with the execution interface constraint data, input layout constraint data, operator adjacency constraint data, branch access constraint data, and dependency access constraint data of the corresponding candidate master computing hardware. Inconsistencies in the comparison are determined as master computing access restrictions and are collected to form the master computing access restriction set corresponding to the mapping combination.

[0037] In this embodiment S3, a combined mapping relationship is established between candidate reserved state pages and candidate main computing hardware. The combined mapping relationship consists of a single candidate reserved state page and a single candidate main computing hardware forming a mapping combination. The page state record in the candidate reserved state page and the hardware constraint data in the candidate main computing hardware are compared for access consistency within the same mapping combination. The number of mapping combinations is equal to the product of the number of candidate reserved state pages and the number of candidate main computing hardware. All mapping combinations record the constraint results according to the same comparison criteria and form comparable combined mapping results. The page state record in the combined mapping relationship uses the intermediate result identifier field, execution position identifier field, data layout identifier field and dependency identifier field as the state extraction entry point. The hardware constraint data uses the execution interface constraint data, input layout constraint data, operator adjacency constraint data, branch access constraint data and dependency access constraint data as the access judgment entry point.

[0038] In this embodiment S3, the mapping method between candidate reserved state pages and candidate main computing hardware adopts pairwise combination mapping, combination index mapping, or combination number association mapping. Pairwise combination mapping directly forms a mapping combination between each candidate reserved state page and each candidate main computing hardware and records them one by one. Combination index mapping pre-establishes a combination index table between the candidate reserved state page index and the candidate main computing hardware index, and then reads the corresponding page record and the corresponding hardware constraint record item by item according to the combination index table. Combination number association mapping assigns a unique number to each candidate reserved state page and each candidate main computing hardware, and then uses the permutation and combination of the page number and the hardware number as the mapping combination number. In this embodiment, pairwise combination mapping is used, and the comparison content, constraint formation rules, and subsequent shaping workload calculation rules corresponding to combination index mapping and combination number association mapping are consistent.

[0039] In this embodiment S3, the set of main computing access restrictions is identified based on the hardware constraint data of the candidate main computing hardware. This is because the hardware constraint data records the execution interface constraints, input layout constraints, operator adjacency constraints, branch access constraints, and dependency access constraints corresponding to the candidate main computing hardware receiving the page state record; the candidate reserved state page records the intermediate result identifier field, execution point identifier field, data layout identifier field, and dependency identifier field; the page state record provides the field record content of the access object, and the hardware constraint data provides the constraint judgment criteria of the access object. In the same mapping combination, the field record content and the constraint judgment criteria can form a one-to-one access judgment relationship; when the field record content is consistent with the constraint judgment criteria, no restriction item is generated; when the field record content is inconsistent with the constraint judgment criteria, a main computing access restriction item of the corresponding type is generated; after all inconsistent items are collected, the main computing access restriction item corresponding to the mapping combination is formed. The set of restrictions includes: execution interface restrictions, input layout restrictions, operator adjacency restrictions, branch access restrictions, and dependency access restrictions. Each restriction corresponds to a single access difference between the page state record and the hardware access constraints. All restrictions collectively characterize the range of state differences that need to be adjusted before the current mapping combination enters the main computing execution.

[0040] In this embodiment S3, the item-by-item comparison is performed in the order of the restriction type; during the execution interface comparison, the execution position identifier field in the candidate reserved status page is read and compared with the execution interface constraint data in the candidate main computing hardware in terms of interface form, entry position, and access order; during the input layout comparison, the data layout identifier field in the candidate reserved status page is read and compared with the input layout constraint data in the candidate main computing hardware in terms of layout type, layout arrangement, and layout position; during the operator adjacency comparison, the execution position identifier field and dependency identifier field in the candidate reserved status page are read, and... The system performs a comparison of adjacent point connections with the operator adjacency restriction data in the candidate main computing hardware; during branch access comparison, it reads the execution point identifier field and dependency identifier field in the candidate reserved status page and compares them with the branch access restriction data in the candidate main computing hardware to determine the corresponding branch entry and branch merging relationships; during dependency access comparison, it reads the dependency identifier field in the candidate reserved status page and compares it with the corresponding dependency access restriction data in the candidate main computing hardware to determine the corresponding sequential relationships; if any comparison is inconsistent, the record is written to the restriction record area under the corresponding restriction type.

[0041] In this embodiment S3, the master computing access restriction set is an aggregated record of all access inconsistencies between the candidate reserved state page and the candidate master computing hardware. The master computing access restriction item is a single restriction object in this aggregated record. Each master computing access restriction item corresponds to a type of access constraint content and a type of page state record content. The execution interface restriction item corresponds to the inconsistency between the execution position identifier field in the candidate reserved state page and the execution interface constraint data in the candidate master computing hardware. The input layout restriction item corresponds to the inconsistency between the data layout identifier field in the candidate reserved state page and the input layout restriction data in the candidate master computing hardware. The operator adjacency restriction item corresponds to the inconsistency between the execution position identifier field and the dependency identifier field in the candidate reserved state page and the operator adjacency restriction data in the candidate master computing hardware. The branch access restriction item corresponds to the inconsistency between the execution position identifier field and the dependency identifier field in the candidate reserved state page and the branch access restriction data in the candidate master computing hardware. The dependency access restriction item corresponds to the inconsistency between the dependency identifier field in the candidate reserved state page and the dependency access restriction data in the candidate master computing hardware.

[0042] In this embodiment S3, the specific process of mapping each candidate reserved state page to each candidate main computing hardware in the candidate main computing hardware set is as follows: First, read the state records page by page according to the page identifier order of the candidate reserved state pages. Then, read the hardware constraint data one by one according to the hardware identifier order of the candidate main computing hardware. After forming a mapping combination for each candidate reserved state page and each candidate main computing hardware, perform item-by-item comparison. During item-by-item comparison, first read the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the candidate reserved state page. Then read the execution interface constraint data, input layout constraint data, operator adjacency constraint data, branch access constraint data, and dependency access constraint data in the candidate main computing hardware. Compare the field record values ​​and constraint data values ​​one-to-one according to the constraint type. Write the inconsistent field-constraint correspondence in the comparison results into the constraint record area and mark the constraint type, constraint source field, constraint data corresponding to the constraint, and mapping combination number to which the constraint belongs. After all fields are compared with all constraint data, all constraint records in the same mapping combination are collected to form the main computing access constraint set corresponding to the mapping combination.

[0043] In this embodiment S3, the main computing access restriction set maintains the categorized arrangement of restrictions within the set and the unified numbering relationship between sets in terms of recording method. The categorized arrangement of restrictions within the set means that the recording order of execution interface restrictions, input layout restrictions, operator adjacency restrictions, branch access restrictions, and dependency access restrictions in the same set is fixed. The unified numbering relationship between sets means that each main computing access restriction set uses the mapping combination number as a unique corresponding identifier. The total number of restrictions in the same mapping combination is recorded as the number of main computing access restrictions in that mapping combination. Different mapping combinations maintain a corresponding relationship through the mapping combination number, the candidate reserved state page identifier, and the candidate main computing hardware identifier. Thus, the restriction set of each mapping combination can be directly called in the subsequent shaping workload calculation stage and directly compared in the sorting stage.

[0044] In this embodiment S3, the shaping workload is the number of shaping actions required to make the candidate reserved state page meet the candidate master computing hardware access constraints. The shaping workload is calculated based on the master computing access constraint set, specifically: counting the number of execution interface reconfigurations corresponding to the execution interface constraint, the number of data layout corrections corresponding to the input layout constraint, the number of operator adjacency roundings corresponding to the operator adjacency constraint, the number of branch flattenings corresponding to the branch access constraint, and the number of dependency reconnections corresponding to the dependency access constraint, and summing the counts to obtain the shaping workload corresponding to each candidate reserved state page and each candidate master computing hardware combination.

[0045] In this embodiment S3, the shaping workload is the result of the shaping action count corresponding to the adjustment of the mapping combination from the page state record to the main computing access state. The shaping workload corresponds one-to-one with the main computing access restriction set. Each mapping combination forms an independent shaping workload record value. The calculation object of the shaping workload is all the restrictions in the restriction set. The measurement caliber of the shaping workload is the number of shaping actions. There is a fixed correspondence between shaping actions and restriction types. Among them, the execution interface restriction corresponds to the execution interface reconfiguration action, the input layout restriction corresponds to the data arrangement correction action, the operator adjacency restriction corresponds to the operator adjacency resetting action, the branch access restriction corresponds to the branch flattening action, and the dependency access restriction corresponds to the dependency reconnection action. The shaping workload record value is composed of the cumulative number of the above types of actions. Based on the main computing access... The specific process for calculating the integer workload of the input restriction set is as follows: First, read the main computing access restriction set corresponding to the mapping combination number. Then, count the number of execution interface restrictions, input layout restrictions, operator adjacency restrictions, branch access restrictions, and dependency access restrictions according to the restriction type. Record the number of execution interface restrictions as the number of execution interface reconfigurations, the number of input layout restrictions as the number of data layout corrections, the number of operator adjacency restrictions as the number of operator adjacency roundings, the number of branch access restrictions as the number of branch flattenings, and the number of dependency access restrictions as the number of dependency reconnections. After summing the above five types of counts, the integer workload corresponding to the mapping combination is obtained. The integer workload and the number of main computing access restrictions corresponding to the mapping combination are written together into the sorting record area.

[0046] In this embodiment S3, the recording method of the shaping workload is synchronized with the main computing access restriction item set. The sorting record area records at least the mapping combination number, the candidate reserved status page identifier, the candidate main computing hardware identifier, the number of main computing access restriction items, the number of execution interface reconfiguration times, the number of data layout correction times, the number of operator adjacency rounding times, the number of branch flattening times, the number of dependency reconnection times, and the total number of shaping workloads. Each number item comes from the same main computing access restriction item set, and each number item maintains a backtrackable relationship with the total number of shaping workloads, so that the subsequent sorting determination process can compare different mapping combinations based on the same recording caliber. The calculation of the shaping workload is performed group by group according to the mapping combination. First, the main computing access restriction item set corresponding to the current mapping combination is read. Then, the execution restrictions are classified and statistically analyzed in a fixed order: execution interface restrictions, input layout restrictions, operator adjacency restrictions, branch access restrictions, and dependency access restrictions. For each execution interface restriction read, the execution interface reconfiguration count is incremented by one; for each input layout restriction read, the data layout correction count is incremented by one; for each operator adjacency restriction read, the operator adjacency rounding count is incremented by one; for each branch access restriction read, the branch flattening count is incremented by one; and for each dependency access restriction read, the dependency reconnection count is incremented by one. After all restrictions have been read, the counts of the five types of actions are summed to obtain the total number of integer operations for the current mapping combination, and this total count is written to the sorting record area corresponding to the current mapping combination.

[0047] In this embodiment S3, the preset sorting identifier order is the candidate main computing hardware identifier code in ascending order. The target reserved state page is the candidate reserved state page that is ranked first after being sorted according to the number of main computing access restrictions, the shaping workload, and the preset sorting identifier order. The target main computing hardware is the candidate main computing hardware that corresponds to the target reserved state page in the same sorting result. The reverse shaping process is to perform interface reconfiguration, data layout correction, operator adjacency resetting, branch flattening, and dependency reconnection state adjustment processing for each main computing access restriction corresponding to the target main computing hardware. The main computing entry state is the target reserved state page after reverse shaping. The processed execution state satisfies the access constraints of the target main computing hardware. Based on the set of main computing access restrictions corresponding to the target main computing hardware, the target reserved state page is subjected to reverse shaping. Specifically, the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the target reserved state page are read. According to the restriction type of the main computing access restriction, the corresponding interface reconfiguration, data layout correction, operator adjacency resetting, branch flattening, and dependency reconnection are performed. The corresponding field records in the target reserved state page are updated, and the execution state corresponding to the updated target reserved state page is determined as the main computing entry state.

[0048] In this embodiment S3, the preset sorting identifier order is a fixed arrangement of candidate main computing hardware identifier codes from smallest to largest. The sorting object is the sorting record corresponding to all mapping combinations. The sorting order is, in order, the number of main computing access restrictions, the integer workload, and the preset sorting identifier order. During sorting, the main computing hardware is first arranged from smallest to largest according to the number of main computing access restrictions. When the number of main computing access restrictions is the same, it is then arranged from smallest to largest according to the integer workload. When the integer workload is still the same, it is then arranged according to the preset sorting identifier order of candidate main computing hardware identifier codes from smallest to largest. After sorting, the candidate reserved status page corresponding to the mapping combination at the top is determined as the target reserved status page, and the candidate main computing hardware corresponding to the mapping combination at the top is determined as the target main computing hardware. The target reserved status page and the target main computing hardware maintain a unique correspondence through the same mapping combination number.

[0049] In this embodiment S3, the reverse shaping process is a process of adjusting the execution state of each item in the set of main computing access restrictions corresponding to the target main computing hardware. The processing objects of the reverse shaping process are the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the target reserved state page. The processing basis of the reverse shaping process is the restriction type and restriction content recorded in the set of main computing access restrictions corresponding to the target main computing hardware. The execution interface restriction item corresponds to the interface reconfiguration process, which adjusts the execution position identifier field in the target reserved state page to the interface record form consistent with the execution interface constraints of the target main computing hardware. The input layout restriction item corresponds to the data arrangement correction process, which adjusts the target reserved state... The data layout identifier field in the page is adjusted to a layout record format consistent with the input layout constraints of the target main computing hardware. The operator adjacency constraint item corresponds to the operator adjacency rounding process. The operator adjacency rounding process adjusts the execution position identifier field and dependency identifier field in the target reserved state page to an adjacency record format consistent with the operator adjacency constraints of the target main computing hardware. The branch access constraint item corresponds to the branch flattening process. The branch flattening process adjusts the execution position identifier field and dependency identifier field in the target reserved state page to a branch record format consistent with the branch access constraints of the target main computing hardware. The dependency access constraint item corresponds to the dependency reconnection process. The dependency reconnection process adjusts the dependency identifier field in the target reserved state page to a dependency record format consistent with the dependency access constraints of the target main computing hardware.

[0050] In this embodiment S3, the specific process of reverse shaping the target reserved state page based on the set of main computing access restrictions corresponding to the target main computing hardware is as follows: First, all field records in the target reserved state page are read. Then, the set of main computing access restrictions corresponding to the same mapping combination number as the target reserved state page is read. The interface reconfiguration, data layout correction, operator adjacency resetting, branch flattening, and dependency reconnection are executed item by item according to the order of the restrictions in the restriction set. After each item is processed, the corresponding field record in the target reserved state page is updated synchronously and the updated field value and updated field position are written. After all restrictions are processed, the updated intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field are reassembled to form the shaped page state record, and the execution state corresponding to the page state record is determined as the main computing entry state.

[0051] In this embodiment S3, the main computing entry state and the target main computing hardware maintain an access consistency relationship. The access consistency relationship includes execution interface consistency, layout organization consistency, operator adjacency relationship consistency, branch access relationship consistency, and dependency inheritance relationship consistency. Execution interface consistency means that the execution position record in the main computing entry state is consistent with the execution interface constraints of the target main computing hardware. Layout organization consistency means that the data layout record in the main computing entry state is consistent with the input layout constraints of the target main computing hardware. Operator adjacency relationship consistency means that the position adjacency record in the main computing entry state is consistent with the operator adjacency constraints of the target main computing hardware. Branch access relationship consistency means that the branch record in the main computing entry state is consistent with the branch access constraints of the target main computing hardware. Dependency inheritance relationship consistency means that the dependency record in the main computing entry state is consistent with the dependency access constraints of the target main computing hardware. After the main computing entry state is written into the main computing execution context, the formal execution segment continues to execute according to this access consistency relationship.

[0052] In this embodiment S4, the computing power scheduling instruction is a structured instruction record used to drive the target main computing hardware to receive the main computing entry state and execute the formal execution segment. The content recorded in the computing power scheduling instruction includes the target main computing hardware identifier, the formal execution segment identifier, the main computing execution context identifier, the main computing entry state write position, the start execution position of the formal execution segment, the end execution position of the formal execution segment, the execution position advancement order, and the scheduling effective flag. The target main computing hardware identifier is used to limit the hardware object corresponding to the current scheduling instruction, the formal execution segment identifier is used to limit the subsequent main computing task segment corresponding to the current scheduling instruction, the main computing execution context identifier is used to limit the execution state carrying position corresponding to the current scheduling instruction, the main computing entry state write position is used to limit the writing interval of the main computing entry state in the main computing execution context, the start execution position and the end execution position of the formal execution segment are used to limit the boundary of the task segment currently executed by the main computing, the execution position advancement order is used to limit the position advancement order within the formal execution segment, and the scheduling effective flag is used to limit the time point when the current computing power scheduling instruction enters the executable state.

[0053] In this embodiment S4, the specific process of generating a computing power scheduling instruction based on the target main computing hardware is as follows: First, read the mapping combination record at the top of the sorting results, and extract the target main computing hardware identifier, target reserved state page identifier, main computing entry state record, formal execution segment identifier, and the start and end execution positions of the formal execution segment corresponding to the mapping combination; then read the main computing execution context identifier and main computing entry state access position corresponding to the target main computing hardware; subsequently, write the target main computing hardware identifier, formal execution segment identifier, main computing execution context identifier, main computing entry state write position, formal execution segment start execution position, formal execution segment end execution position, and execution position advancement order in sequence according to the fixed instruction field order; after all fields are written, write the scheduling effective flag to the end of the instruction to form the computing power scheduling instruction corresponding to the current target main computing hardware; the computing power scheduling instruction maintains a unique correspondence with the current target main computing hardware, the current main computing execution context, and the current formal execution segment.

[0054] In this embodiment S4, the processing objects for writing the main computing entry state into the main computing execution context are the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field, which are formed after reverse shaping. The main computing execution context is pre-set with a context identifier area, an entry state writing area, a position receiving area, and a subsequent advancement area. The context identifier area records the target main computing hardware identifier and the formal execution segment identifier. The entry state writing area records the field content corresponding to the main computing entry state. The position receiving area records the receiving relationship corresponding to the starting execution position of the formal execution segment. The subsequent advancement area records the advancement order of each execution position in the formal execution segment. When the main computing entry state is written into the main computing execution context, it is written into the entry state writing area in a fixed order of intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field. At the same time, the consistency relationship between the execution position corresponding to the main computing entry state and the starting execution position of the formal execution segment is registered in the position receiving area.

[0055] In this embodiment S4, the specific steps for writing the main computing entry state into the main computing execution context corresponding to the target main computing hardware are as follows: First, locate the main computing execution context corresponding to the target main computing hardware based on the main computing execution context identifier in the computing power scheduling instruction; then, determine the write boundary of the entry state writing area based on the main computing entry state write position in the computing power scheduling instruction; subsequently, read the intermediate result identifier field in the main computing entry state, and write the intermediate result object identifier, intermediate result position identifier, and result record sequence number into the result record position of the entry state writing area; continue to read the execution position identifier field, and write the execution position number, execution order number, and position adjacency relationship identifier into the entry state writing area. The system reads the position record location in the entry status writing area; it then reads the data layout identifier field and writes the layout type identifier, layout arrangement identifier, and layout position identifier into the layout record location in the entry status writing area; it then reads the dependency identifier field and writes the dependency relationship identifier and the succession relationship identifier into the dependency record location in the entry status writing area; after writing the four types of fields, it writes a consistent record between the starting execution position of the formal execution segment and the corresponding execution position of the main computing entry status in the position succession area, and writes the position advancement order record after the starting execution position of the formal execution segment in the subsequent advancement area; after all writing is completed, it updates the context status in the main computing execution context to the pending execution status.

[0056] In this embodiment S4, the process of scheduling the formal execution segment to the target main computing hardware is based on the completion of writing the computing power scheduling instruction and the main computing execution context. At the start of scheduling, the target main computing hardware first reads the corresponding computing power scheduling instruction, and then locates the current main computing execution context and formal execution segment range based on the context identifier and formal execution segment identifier in the computing power scheduling instruction. Subsequently, it reads the entry state write area in the main computing execution context to obtain the intermediate result record, position record, layout record, and dependency record corresponding to the main computing entry state, and uses these four types of records as the basis for accepting the starting execution position of the formal execution segment. Then, based on the consistency relationship registered in the position accepting area, the starting execution position of the formal execution segment is determined as the current execution starting point, and the subsequent execution positions in the formal execution segment are executed one by one according to the position advancement order in the subsequent advancement area. After each execution position is completed, the current execution position record and the subsequent advancement position record in the main computing execution context are updated. The process continues until the execution point at the end of the formal execution segment is completed. When the formal execution segment is scheduled to be executed on the target main computing hardware, the main computing entry state and the formal execution segment maintain field inheritance relationships, position inheritance relationships, layout inheritance relationships, and dependency inheritance relationships. Field inheritance relationship means that the four types of field records in the main computing entry state are completely written into the entry state write area in the main computing execution context. Position inheritance relationship means that the execution point corresponding to the main computing entry state and the starting execution point of the formal execution segment form a consistent registration in the position inheritance area. Layout inheritance relationship means that the data layout record in the main computing entry state is directly used as the layout input record of the starting execution point of the formal execution segment. Dependency inheritance relationship means that the dependency record in the main computing entry state is directly used as the dependency starting point record between the starting execution point of the formal execution segment and subsequent execution points. After the above four types of inheritance relationships are established synchronously in the main computing execution context, the subsequent execution points of the formal execution segment continue to execute in the execution point advancement order.

[0057] In this embodiment S4, the execution of the computing power scheduling instruction and the writing and updating of the main computing execution context maintain a sequential correspondence. The target main computing hardware identifier, main computing execution context identifier, and formal execution segment identifier recorded in the computing power scheduling instruction determine the scheduling object. The main computing entry state writing position, the starting execution point of the formal execution segment, the ending execution point of the formal execution segment, and the execution point advancement order recorded in the computing power scheduling instruction determine the execution boundary and advancement boundary. After the main computing entry state is written into the main computing execution context, the target main computing hardware enters the formal execution state according to the scheduling effective flag. Therefore, when the target main computing hardware executes the formal execution segment, it reads the main computing execution context that has already completed field updates and acceptance registration. The following records the context state records in the main computing execution context, which include the pending write state, pending execution state, executing state, and execution completed state. Before the main computing entry state is written, the context state record is in the pending write state. After the main computing entry state is written and the position acceptance registration is completed, the context state record is updated to the pending execution state. After the target main computing hardware reads the computing power scheduling instruction and starts executing the formal execution segment, the context state record is updated to the executing state. After the final execution position of the formal execution segment is completed, the context state record is updated to the execution completed state. The changes in the context state record are consistent with the scheduling effective flag of the computing power scheduling instruction, the starting execution position of the formal execution segment, and the final execution position.

[0058] Example 2: The heterogeneous hardware computing power scheduling system proposed in this invention is applied to the heterogeneous hardware computing power scheduling method proposed in Example 1. It includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor executes the computer program to implement the heterogeneous hardware computing power scheduling method in Example 1.

[0059] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited thereto. Various changes can be made within the scope of knowledge possessed by those skilled in the art without departing from the spirit of the present invention.

Claims

1. A heterogeneous hardware computing power scheduling method, characterized in that, Includes the following steps: S1. Obtain the task execution data of the target task and the hardware constraint data of each heterogeneous hardware. Divide the target task into the initial trial calculation segment and the formal execution segment according to the preset stage division rules. Determine the candidate trial calculation hardware set and the candidate main calculation hardware set from the heterogeneous hardware, and establish the corresponding trial calculation execution context and main calculation execution context respectively. The initial trial calculation segment is the preliminary trial calculation task segment in the target task; the formal execution segment is the subsequent main calculation task segment in the target task; the candidate trial calculation hardware set is a heterogeneous hardware set used to carry the trial calculation processing of the initial trial calculation segment; and the candidate main calculation hardware set is a heterogeneous hardware set used to carry the main calculation execution of the formal execution segment. S2. Control each candidate trial calculation hardware in the candidate trial calculation hardware set to perform trial calculation processing on the initial trial calculation segment in parallel, generate the reserved status page corresponding to each candidate trial calculation hardware, perform field integrity verification processing on each reserved status page, and determine the candidate reserved status page. Among them, the reserved status page is the status page that carries the trial calculation status information, which includes the intermediate result identifier field, the execution point identifier field, the data layout identifier field, and the dependency identifier field; the candidate reserved status page is the reserved status page whose field integrity meets the preset requirements. S3. Map each candidate reserved state page to each candidate main computing hardware. Identify the corresponding set of main computing access restrictions based on the hardware constraint data of each candidate main computing hardware. Calculate the shaping workload based on the set of main computing access restrictions. Determine the target reserved state page and target main computing hardware according to the order of the number of main computing access restrictions from fewest to most, the shaping workload from fewest to most, and the preset sorting identifier. Then, perform reverse shaping on the target reserved state page based on the set of main computing access restrictions corresponding to the target main computing hardware to obtain the main computing entry state. Among them, the master computing access restriction set is the set of access constraints that exist when the candidate master computing hardware receives the corresponding candidate reserved state page; the shaping workload is the number of shaping actions required to eliminate the master computing access restriction set; reverse shaping is the targeted state adjustment processing performed on the target reserved state page in accordance with the access requirements of the target master computing hardware; the master computing entry state is the execution state that meets the access requirements of the target master computing hardware after reverse shaping; S4. Generate computing power scheduling instructions based on the target main computing hardware, write the main computing entry state into the main computing execution context corresponding to the target main computing hardware, and schedule the formal execution segment to be executed on the target main computing hardware.

2. The heterogeneous hardware computing power scheduling method according to claim 1, characterized in that: In step S1, the initial trial calculation segment is used to output the trial calculation status information corresponding to the reserved status page; the formal execution segment is used to receive the main calculation entry status and execute subsequent task segments of the target task; wherein, the initial trial calculation segment is a continuous task segment starting from the starting execution point of the target task, including the task segment that generates the trial calculation status information corresponding to the reserved status page; the formal execution segment is a continuous task segment starting from the adjacent execution point after the end execution point of the initial trial calculation segment, including subsequent task segments of the target task located after the initial trial calculation segment; the end execution point of the initial trial calculation segment is adjacent to the start execution point of the formal execution segment, and the execution point corresponding to the main calculation entry status is consistent with the start execution point of the formal execution segment; the trial calculation execution context is a context that carries the execution status information corresponding to the initial trial calculation segment and the status information corresponding to the reserved status page; the main calculation execution context is a context that carries the execution status information corresponding to the formal execution segment and the main calculation entry status.

3. The heterogeneous hardware computing power scheduling method according to claim 2, characterized in that: In S2, the trial calculation process is a parallel processing operation that advances the initial trial calculation segment segment by segment according to the execution position order and synchronously writes the trial calculation status information. The process involves controlling each candidate trial calculation hardware in the candidate trial calculation hardware set to perform the initial trial calculation segment in parallel. Specifically, within the trial calculation execution context corresponding to each candidate trial calculation hardware, the initial trial calculation segment is advanced according to the same execution starting point. After each execution position is completed, intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field are written respectively. After the initial trial calculation segment is completed, it is encapsulated to form a reserved status page corresponding to each candidate trial calculation hardware. The reserved status page is used to carry the continuable trial calculation status information corresponding to the initial trial calculation segment. The page data structure of the reserved status page is a page-type data structure consisting of a header identifier area, a field index area, and a status record area. The field index area is used to limit the writing position and reading order of the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the status record area. Each field in the reserved status page is written according to the execution position order.

4. The heterogeneous hardware computing power scheduling method according to claim 3, characterized in that: In S2, the field integrity verification process is a verification method performed on the field placeholder relationship, field order relationship, and field correspondence relationship in the reserved state page, used to filter candidate reserved state pages that meet the main computation mapping conditions. The field integrity verification process includes field existence verification, field order verification, and field correspondence verification. The candidate reserved state page is a reserved state page that has passed the field integrity verification process and maintains a single-page continuous record relationship. The field integrity verification process is performed on each reserved state page to determine the candidate reserved state page. Specifically, the page header identifier area, field index area, and status record area in each reserved state page are read. It is verified whether the intermediate result identifier field, execution point identifier field, data layout identifier field, and dependency identifier field all have corresponding index entries in the field index area. It is verified whether the arrangement order of each field in the status record area is consistent with the execution point order. It is verified whether each field maintains a one-to-one correspondence record relationship under the same execution point. The reserved state page that passes the field existence verification, field order verification, and field correspondence verification at the same time is determined as the candidate reserved state page.

5. The heterogeneous hardware computing power scheduling method according to claim 4, characterized in that: In step S3, the master computing access restriction set is a set of restrictions that characterize inconsistencies in access between candidate reserved state pages and candidate master computing hardware. Master computing access restrictions characterize restrictions that characterize single access constraints when candidate master computing hardware receives candidate reserved state pages. Master computing access restrictions include execution interface restrictions, input layout restrictions, operator adjacency restrictions, branch access restrictions, and dependency access restrictions. Each candidate reserved state page is mapped to each candidate master computing hardware in the candidate master computing hardware set. Specifically, each candidate reserved state page is paired with each candidate master computing hardware for mapping. The intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the candidate reserved state page are read and compared item by item with the execution interface constraint data, input layout constraint data, operator adjacency constraint data, branch access constraint data, and dependency access constraint data of the corresponding candidate master computing hardware. Inconsistencies in the comparison are identified as master computing access restrictions and aggregated to form the master computing access restriction set corresponding to the mapping combination.

6. The heterogeneous hardware computing power scheduling method according to claim 5, characterized in that: In S3, the shaping workload is the number of shaping actions required to make the candidate reserved state page meet the candidate master computing hardware access constraints. The shaping workload is calculated based on the master computing access constraint set, specifically: counting the number of execution interface reconfigurations corresponding to the execution interface constraint, the number of data layout corrections corresponding to the input layout constraint, the number of operator adjacency roundings corresponding to the operator adjacency constraint, the number of branch flattenings corresponding to the branch access constraint, and the number of dependency reconnections corresponding to the dependency access constraint, and summing the counts to obtain the shaping workload corresponding to each candidate reserved state page and each candidate master computing hardware combination.

7. The heterogeneous hardware computing power scheduling method according to claim 6, characterized in that: In S3, the preset sorting identifier order is the candidate main computing hardware identifier code in ascending order. The target reserved state page is the candidate reserved state page that is first after being sorted according to the number of main computing access restriction items, the shaping workload, and the preset sorting identifier order. The target main computing hardware is the candidate main computing hardware that is in the same sorting result as the target reserved state page. The reverse shaping process is to perform interface reconfiguration, data layout correction, operator adjacency resetting, branch flattening, and dependency reconnection state adjustment processing for each main computing access restriction item corresponding to the target main computing hardware. The main computing entry state is the execution state of the target reserved state page after the reverse shaping process that satisfies the target main computing hardware access constraints. Based on the set of main computing access restrictions corresponding to the target main computing hardware, the target reserved state page is subjected to reverse shaping. Specifically, the intermediate result identifier field, execution position identifier field, data layout identifier field, and dependency identifier field in the target reserved state page are read. According to the restriction type of the main computing access restriction, the corresponding interface reconfiguration, data layout correction, operator adjacency resetting, branch flattening, and dependency reconnection are performed. The corresponding field records in the target reserved state page are updated, and the execution status corresponding to the updated target reserved state page is determined as the main computing entry status.

8. A heterogeneous hardware computing power scheduling system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor executes a computer program to implement the heterogeneous hardware computing power scheduling method as described in any one of claims 1-7.

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