Address detection method, load storage unit, processing unit, electronic device

Abstract

The present disclosure provides an address detection method, a load storage unit, a processing unit and an electronic device. The method is applied to a load storage unit, and includes the following steps: splicing a plurality of address operands read from a plurality of address registers of a processing unit to obtain a spliced address, the bit width of the spliced address is greater than the bit width of a virtual address supported by a data storage unit connected to the processing unit; the spliced address includes a low address area corresponding to the bit width of the virtual address and a high extension area located outside the bit width of the virtual address; performing consistency detection on the high extension area to obtain a detection result of the spliced address; in the case that the detection result is passed, generating a virtual address according to the spliced address, and completing data access between a memory file of the processing unit and the data storage unit based on the virtual address. According to the embodiment of the present disclosure, the reliability can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an address detection method, a load storage unit, a processing unit, and an electronic device. Background Technology

[0002] In a graphics processing unit (GPU) or a multi-threaded parallel processor, the load store unit (LSU) typically reads address operands from multiple general-purpose registers and combines them to generate a virtual address to access the memory system.

[0003] In related technologies, errors that occur during the generation of virtual addresses may manifest in an indirect and delayed manner during subsequent caching, address translation lookaside buffers, or memory access, increasing the difficulty of system debugging and reducing system reliability. Summary of the Invention

[0004] This disclosure provides an address detection method, a load storage unit, a processing unit, and an electronic device.

[0005] In a first aspect, this disclosure provides an address detection method applied to a load storage unit (LSU). The address detection method includes: concatenating multiple address operands read from multiple address registers of a processing unit to obtain a concatenated address, wherein the bit width of the concatenated address is greater than the bit width of the virtual address supported by the data storage unit connected to the processing unit; the concatenated address includes a low-order address region corresponding to the bit width of the virtual address and a high-order extension region located outside the bit width of the virtual address; performing a consistency check on the high-order extension region to obtain a detection result of the concatenated address; if the detection result is satisfactory, generating a virtual address based on the concatenated address, and completing data access between the memory file of the processing unit and the data storage unit based on the virtual address.

[0006] In one possible implementation, a consistency check is performed on the high-order extension region to obtain the detection result of the concatenated address, including one or more of the following: if the value of each address bit in the high-order extension region is a preset constant value, the detection result is determined to be passed; if the value of each address bit in the high-order extension region is consistent with the sign bit of the low-order address region, the detection result is determined to be passed; if the value in the high-order extension region is consistent with the preset value corresponding to the type of data storage unit, the detection result is determined to be passed.

[0007] As an implementation approach, this method adapts to different application scenarios by providing various consistency detection rules. Specifically, consistency detection rules based on preset constant values ​​can adapt to scenarios with fixed high-order addresses; consistency detection rules based on the sign bit of the low-order address region can adapt to scenarios with sign addresses; and consistency detection rules based on data storage unit types can adapt to various storage systems. This approach offers greater versatility, better compatibility, higher flexibility, and a wider range of applications.

[0008] In one possible implementation, a virtual address is generated based on the concatenated address, including one or more of the following: truncating the high-order extension of the concatenated address to obtain the virtual address; performing masking on the concatenated address to obtain the virtual address; or reading the low-order address region of the virtual address to obtain the virtual address.

[0009] As one implementation method, by truncating high-order bits, masking, or extracting low-order bits from the concatenated address, invalid information can be eliminated, valid address segments can be quickly obtained, the complexity of address resolution is reduced, and the efficiency of virtual address to physical address conversion is improved. At the same time, it ensures that virtual addresses have a uniform format, thereby guaranteeing the legality and compatibility of virtual addresses and helping to improve the accuracy of data access.

[0010] In one possible implementation, the address detection method further includes performing an exception handling operation if the detection result is unsuccessful.

[0011] As an implementation method, by triggering exception handling operations when the consistency check fails, erroneous addresses can be identified in a timely manner, preventing erroneous addresses from continuing to perform addressing and read / write operations, thus preventing problems such as memory out-of-bounds access and data tampering, and improving the security of data storage unit access process.

[0012] In one possible implementation, performing exception handling operations includes one or more of the following: generating exception information and writing the exception information to a status register; incrementing the value of the access error counter of the data storage unit by one; sending an exception event notification to the debugging or diagnostic unit of the processing unit; and marking the thread, thread group, and / or wavefront accessing the data storage unit.

[0013] As an implementation method, generating exception information and writing it to the status register enables the recording and traceability of exception events. Reading the status register allows for the rapid identification of the type and location of the exception event, providing a basis for troubleshooting. Increasing the access error counter quantifies the frequency of storage access errors, providing data support for risk assessment. Sending exception event notifications to the debugging or diagnostic unit enables real-time reporting of exceptions, facilitating rapid debugging and timely intervention, preventing exception propagation, and improving reliability. Marking the thread, thread group, and / or wavefront of the exception allows for precise identification of the entity experiencing the exception, enabling fault isolation and precise control, further improving reliability.

[0014] In one possible implementation, a consistency check is performed on the high-order extension region to obtain the detection result of the concatenated address, including: determining the access mode for the data storage unit; and, if the access mode is debug mode, performing a consistency check on the high-order extension region to obtain the detection result of the concatenated address.

[0015] As an implementation method, consistency checks on the high-order extension area are only enabled in debug mode, which realizes on-demand enabling of the verification function, reduces unnecessary verification operations, avoids long-term occupation of hardware resources by consistency checks, and helps improve hardware resource utilization.

[0016] In one possible implementation, the address detection method further includes: when the access mode is non-debugging mode, generating a virtual address directly based on the concatenated address after obtaining the concatenated address.

[0017] As an implementation method, in non-debugging mode, the consistency detection process of the high-order extension area is skipped, redundant verification logic is eliminated, the address processing process is simplified, the system performance under normal business scenarios is effectively improved, and the operational efficiency and business real-time requirements are taken into account.

[0018] Secondly, this disclosure provides a load storage unit, including: an address concatenation subunit, an address detection subunit, and an address generation subunit, wherein the address detection subunit is connected between the address concatenation subunit and the address generation subunit; wherein, the address concatenation subunit is configured to concatenate multiple address operands read from multiple address registers of the processing unit to obtain a concatenated address, the bit width of the concatenated address being greater than the bit width of the virtual address supported by the data storage unit of the processing unit; the concatenated address includes a low-order address area corresponding to the bit width of the virtual address and a high-order extension area located outside the bit width of the virtual address; the address detection subunit is configured to perform consistency detection on the high-order extension area to obtain a detection result of the concatenated address; the address generation subunit is configured to generate a virtual address based on the concatenated address if the detection result is successful, and to complete data access between the processor's memory file and the data storage unit based on the virtual address.

[0019] In one possible implementation, the address detection subunit is configured to perform one or more of the following: if the value of each address bit in the high-order extension region is a preset constant value, determine that the detection result is passed; if the value of each address bit in the high-order extension region is consistent with the sign bit in the low-order address region, determine that the detection result is passed; if the value in the high-order extension region is consistent with the preset value corresponding to the type of data storage unit, determine that the detection result is passed.

[0020] In one possible implementation, the address generation subunit is configured to perform one or more of the following: truncate the high-order extension of the concatenated address to obtain the virtual address; mask the concatenated address to obtain the virtual address; and read the low-order address region of the virtual address to obtain the virtual address.

[0021] In one possible implementation, the load storage unit further includes an exception handling subunit. This exception handling subunit is configured to perform exception handling operations if the address detection subunit determines that the detection result is a failure.

[0022] In one possible implementation, the exception handling subunit is configured to perform one or more of the following: generate exception information and write the exception information to a status register; increment the value of the access error counter of the data storage unit; send an exception event notification to the debugging or diagnostic unit of the processing unit; and mark the thread, thread group, and / or wavefront accessing the data storage unit.

[0023] In one possible implementation, the load storage unit further includes a mode configuration subunit; the mode configuration subunit is configured to determine the access mode for the data storage unit; the address detection subunit is further configured to perform consistency detection on the high-order extension area when the access mode is debug mode, and obtain the detection result of the concatenated address.

[0024] In one possible implementation, the address generation subunit is also configured to generate a virtual address directly from the concatenated address after obtaining it, when the access mode is non-debugging mode.

[0025] Thirdly, this disclosure provides a processing unit including a load storage unit (LSU) and a memory file, the memory file including multiple address registers; the load storage unit is configured to concatenate multiple operands read from the multiple address registers to obtain a concatenated address, the bit width of the concatenated address being greater than the bit width of the virtual address supported by the data storage unit connected to the processing unit; the concatenated address includes a low-order address region corresponding to the bit width of the virtual address and a high-order extension region located outside the bit width of the virtual address; a consistency check is performed on the high-order extension region to obtain a check result of the concatenated address; if the check result is successful, a virtual address is generated based on the concatenated address, and data access between the memory file and the data storage unit is completed based on the virtual address.

[0026] Fourthly, this disclosure provides an electronic device comprising: at least one processing unit; and a data storage unit communicatively connected to the at least one processing unit; wherein each processing unit includes a load storage unit (LSU) and a memory file, the memory file including a plurality of address registers, the load storage unit storing one or more computer instructions executable by at least one processor, the one or more computer instructions being executed by the load storage unit to enable the load storage unit to perform the address detection method described above.

[0027] The embodiments provided in this disclosure first concatenate multiple address operands read from multiple address registers of the processing unit to obtain a concatenated address. Then, a consistency check is performed on the high-order extension region of the concatenated address that is outside the virtual address width supported by the data storage unit to obtain the detection result of the concatenated address. Finally, if the detection result is successful, a virtual address is generated based on the concatenated address, and data access between the storage file of the processing unit and the data storage unit is completed based on the virtual address. In this way, by performing a consistency check on the high-order extension region of the concatenated address before generating the virtual address, high-order dirty data introduced due to address calculation errors can be detected and reported in a timely manner in the early stage of storage access, thereby improving the reliability and debuggability of the system.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of detailed exemplary embodiments with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart of an address detection method provided in an embodiment of the present disclosure.

[0031] Figure 2 This is a block diagram of a processing unit provided in an embodiment of the present disclosure.

[0032] Figure 3 This is a block diagram of a load storage unit provided in an embodiment of the present disclosure.

[0033] Figure 4 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0034] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0035] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0036] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0038] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0039] In GPUs or multi-threaded parallel processors, the load storage unit can read address operands from multiple address registers, concatenate the multiple address operands to obtain a concatenated address, and generate a virtual address based on the concatenated address to access the data storage unit.

[0040] Because the bit width of the concatenated address is greater than the bit width of the virtual address supported by the data storage unit, a virtual address needs to be generated based on the concatenated address to access the data storage unit. In related technologies, the load storage unit directly truncates or masks the concatenated address to obtain the virtual address for accessing the data storage unit. For example, the load storage unit reads address operands from two 32-bit address registers, concatenates the two 32-bit address operands into a 64-bit concatenated address, then directly truncates or masks the 64-bit concatenated address to obtain a 48-bit virtual address, and finally accesses the data storage unit based on this 48-bit virtual address.

[0041] In related technologies, high-order address bits exceeding the virtual address width in the concatenated address are directly truncated or masked within the payload storage unit. When upward overflow, sign extension errors, or high-order register contamination occur during address calculation, abnormal high-order information is silently discarded. These errors may not be immediately detected but may manifest indirectly or delayedly during subsequent caching, translation lookaside buffer (TLB), or memory access, increasing the difficulty of system debugging and reducing system reliability. Therefore, an effective mechanism is urgently needed to detect and promptly report high-order anomalies in the virtual address before generating the virtual address within the payload storage unit.

[0042] According to the address detection method of this disclosure, firstly, multiple address operands read from multiple address registers of the processing unit are concatenated to obtain a concatenated address. Then, a consistency check is performed on the high-order extension region of the concatenated address that is outside the virtual address width supported by the data storage unit to obtain the detection result of the concatenated address. Finally, if the detection result is successful, a virtual address is generated based on the concatenated address, and data access between the memory file of the processing unit and the data storage unit is completed based on the virtual address. In this way, by performing a consistency check on the high-order extension region of the concatenated address before generating the virtual address based on the concatenated address, high-order dirty data introduced due to address calculation errors can be detected and reported in a timely manner in the early stage of storage access, thereby improving the reliability and debuggability of the system.

[0043] The execution entity of the address detection method according to embodiments of this disclosure can be a load storage unit in a processing unit. This processing unit can be located in an electronic device such as a terminal device or a server. The terminal device can be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. In some possible implementations, this method can be implemented by the load storage unit calling computer instructions.

[0044] Figure 1 A flowchart illustrating an address detection method provided in an embodiment of this disclosure. (Refer to...) Figure 1 The method includes steps S11 to S13.

[0045] In step S11, multiple address operands read from multiple address registers of the processing unit are concatenated to obtain a concatenated address. The bit width of the concatenated address is greater than the bit width of the virtual address supported by the data storage unit of the processing unit. The concatenated address includes a low-order address area corresponding to the bit width of the virtual address and a high-order extension area located outside the bit width of the virtual address.

[0046] The processing unit can represent an integrated circuit or chip with address calculation and data storage access functions, such as a graphics processing unit (GPU). It integrates components such as memory files, load storage units, and data storage units.

[0047] In this embodiment of the disclosure, the load storage unit is connected between the memory file and the data storage unit to complete data access between the memory file and the data storage unit. For example, in response to a read (load) command, the load storage unit can receive data from the data storage unit and write it to the memory file; in response to a write (store) command, the load storage unit can receive data from the memory file and write it to the data storage unit.

[0048] The memory file is an addressable, high-speed, multi-port array of registers, also known as a register file or register archive, and is a type of miniaturized on-chip high-speed memory. The memory file includes address registers for storing addresses, and may also contain other registers for storing read and write data.

[0049] An address register represents a storage unit within a processing unit used for temporarily storing address operands; it is typically a hardware register. The address register has a fixed bit width, such as 32 bits or 64 bits. This disclosure does not limit the bit width of the address register. Multiple address registers can be configured to collaboratively store complete address-related data for subsequent concatenation, depending on the address calculation requirements. For example, two or four address registers can be configured to collaboratively store complete address-related data. This disclosure does not limit the number of address registers.

[0050] The load storage unit can read address operands from multiple address registers respectively, and then concatenate the read address operands to obtain a concatenated address. In one example, the load storage unit can read address operands when it needs to access the data storage unit, such as when executing a load instruction or a store instruction. In another example, the load storage unit can concatenate the read address operands in a preset order to form a concatenated address. The preset order can be from high-order bits to low-order bits or from low-order bits to high-order bits; this embodiment of the present disclosure does not limit this.

[0051] A data storage unit can represent a unit within a processing unit used to store data, including caches, RAM, etc. The virtual address width supported by a data storage unit is determined by the hardware design. In one example, the virtual address width supported by the data storage unit could be 32 bits or 48 bits, etc.

[0052] Virtual address is relative to physical address. It is the address form that the processing unit maps to the physical address through the address translation mechanism. It is the legal address for accessing data storage unit.

[0053] In this embodiment, the bit width of the address register is smaller than the bit width of the virtual address supported by the data storage unit. Therefore, to obtain the virtual address, address operands read from multiple address registers need to be concatenated. The bit width of the concatenated address is larger than the bit width of the virtual address supported by the data storage unit. Therefore, to obtain the virtual address, the concatenated address needs to be truncated or masked. For example, if the address register has a bit width of 32 bits, the concatenated address obtained by concatenating two 32-bit address operands has a bit width of 64 bits, and the virtual address obtained by truncating or masking the concatenated address has a bit width of 48 bits.

[0054] In this embodiment, the concatenated address includes a low-order address region and a high-order extension region. The low-order address region represents the portion of the concatenated address corresponding to the width of the virtual address, specifically the lower N bits of the concatenated address, where N is the width of the virtual address. The low-order address region is the portion used when generating the virtual address, and its value directly determines the final value of the virtual address. The high-order extension region represents the portion of the concatenated address outside the width of the virtual address, specifically the higher MN bits of the concatenated address, where M is the width of the concatenated address. The high-order extension region does not participate in the generation of the virtual address.

[0055] In one example, assume the processing unit includes address register 1 and address register 2, both 32-bit wide, and the data storage unit of the processing unit supports a virtual address width of 48 bits. The payload storage unit is concatenated in the order of address register 2 and address register 1, with the address operands read from address register 2 placed in the high-order bits and the address operands read from address register 1 placed in the low-order bits, resulting in a 64-bit concatenated address. In this concatenated address, the lower 48 bits are the low-order address region, and the higher 16 bits are the high-order extension region.

[0056] In step S12, a consistency check is performed on the high-order extension region to obtain the detection result of the spliced ​​address.

[0057] Performing consistency checks on the high-order extension region can determine whether there are address calculation errors during the splicing process, such as upward overflow, sign extension errors, or high-order register contamination. In one example, the load storage unit can check each address bit of the high-order extension region separately to see if it conforms to preset rules.

[0058] In step S13, if the detection result is passed, a virtual address is generated based on the concatenated address, and data access between the memory file of the processing unit and the data storage unit is completed based on the virtual address.

[0059] If the detection result of the concatenated address is passed, it indicates that the value of the high-order extension area conforms to the preset rules, the concatenated address is legal, there is no high-order dirty data caused by address calculation errors, and a virtual address can be generated based on the concatenated address to realize normal access to the data storage unit.

[0060] According to the address detection method of this disclosure, firstly, multiple address operands read from multiple address registers of the processing unit are concatenated to obtain a concatenated address. Then, a consistency check is performed on the high-order extension region of the concatenated address that is outside the virtual address width supported by the data storage unit to obtain the detection result of the concatenated address. Finally, if the detection result is successful, a virtual address is generated based on the concatenated address, and data access between the memory file of the processing unit and the data storage unit is completed based on the virtual address. In this way, by performing a consistency check on the high-order extension region of the concatenated address before generating the virtual address based on the concatenated address, high-order dirty data introduced due to address calculation errors can be detected and reported in a timely manner in the early stage of storage access, thereby improving the reliability and debuggability of the system.

[0061] This disclosure provides various consistency detection rules. When the high-order extension region of the concatenated address satisfies any one of these rules, the detection result is determined to be unsuccessful. These consistency detection rules include, but are not limited to, all-zero consistency rules, symbol consistency rules, and storage space-related rules. The high-order extension region consistency detection process is described below in conjunction with various consistency rules. In some embodiments, step S12 performs consistency detection on the high-order extension region to obtain the detection result of the concatenated address, and may include one or more of steps S121 to S123.

[0062] In step S121, if the value of each address bit in the high-order extension region is a preset constant value, the detection result is determined to be passed.

[0063] This step explains the all-zero consistency rule. If the value of each address bit in the high-order extension region is a preset constant value, then the all-zero consistency rule is satisfied. The preset constant value can be fixed data pre-defined by hardware design or software configuration, and its value can be 0 or 1. The preset constant value can be set as needed. It should be understood that when the preset constant value is 1, the all-zero consistency rule can also be called the all-one consistency rule.

[0064] If each address bit in the high-order extension region has a preset constant value, it indicates that the address calculation is correct, and the detection result can be determined as passed. If any one or more address bits in the high-order extension region do not have a preset constant value, it indicates that the read address operands are incorrect, or the concatenation process is incorrect, such as the concatenation order being wrong, and the detection result can be determined as failed.

[0065] In step S122, if the value of each address bit in the high-order extension region is consistent with the sign bit in the low-order address region, the detection result is determined to be passed.

[0066] This step explains the sign consistency rule. If the value of each address bit in the high-order extension region is consistent with the sign bit in the low-order address region, then the sign consistency rule is satisfied. The sign bit in the low-order address region is used to indicate the positive or negative sign of the address, and is usually the highest bit of the low-order address region. Taking a low-order address region with a width of N (N is a positive integer) and including bits N-1 to 0 from high to low as an example, the N-1th bit of the low-order address region is the sign bit. In one example, the sign bit is either 0 or 1; a value of 0 indicates a positive number, and a value of 1 indicates a negative number.

[0067] If the value of each address bit in the high-order extension area matches the sign bit in the low-order address area, the address calculation is correct, and the detection result is considered passed. If the value of any one or more addresses in the high-order extension area does not match the sign bit in the low-order address area, it indicates an address operand concatenation error or an overflow during address calculation, resulting in dirty data in the high-order extension area. In this case, the detection result is considered failed.

[0068] This method is suitable for scenarios where the address operands are signed numbers. When the address operands are extended, the sign extension method needs to be used. In this case, the sign bit of the high-order extension area remains consistent, which can effectively detect problems such as address calculation overflow and concatenation errors, and ensure the legality of the concatenated address.

[0069] In step S123, if the value of the high-order extension region is consistent with the preset value corresponding to the type of data storage unit, the detection result is determined to be passed.

[0070] This step explains the rules related to storage space. If the value of the high-order extension area matches the preset value corresponding to the data storage unit type, it can be determined that the storage space rules are satisfied.

[0071] In one example, the data storage unit type includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), etc. As one implementation of this disclosure, different types of data storage units correspond to different preset values. The preset values ​​can be configured by the processing unit's software or fixed in hardware. This disclosure does not limit the type of data storage unit, nor does it limit the preset values ​​corresponding to each type of data storage unit. It should be understood that the preset values ​​corresponding to different types of data storage units can be the same or different.

[0072] In one example, assume there are two types of data storage units: cache and main memory. The default value for cache is 0x0001, and the default value for main memory is 0x0002. When a load storage unit accesses the cache, if the value of the high-order extension is 0x0001, the detection result is considered passed; otherwise, the detection result is considered failed. When a load storage unit accesses main memory, if the value of the high-order extension is 0x0002, the detection result is considered passed; otherwise, the detection result is considered failed.

[0073] As one implementation of this disclosure, a variety of consistency detection rules are provided for use by the load storage unit. The all-zero consistency rule is adapted to the fixed high-bit scenario, the symbol consistency rule is adapted to the symbol address scenario, and the storage space related rules are adapted to the scenario of multiple storage types, thus taking into account both the comprehensiveness and flexibility of the detection.

[0074] The process of generating a virtual address based on the concatenated address is described below. In some embodiments, generating a virtual address based on the concatenated address in step S13 may include one or more of steps S131 to S133.

[0075] In step S131, the high-order extension region of the concatenated address is truncated to obtain the virtual address.

[0076] If the detection result is satisfactory, it indicates that the value of the high-order extension region conforms to the preset rules and there is no dirty data. Therefore, the high-order extension region in the concatenated address can be directly discarded, and only the low-order address region can be retained as the final virtual address. This method requires no additional processing and can generate virtual addresses simply and efficiently.

[0077] In step S132, the concatenated address is masked to obtain a virtual address.

[0078] Masking refers to performing a bitwise AND operation on the concatenated address using a preset mask value, retaining only the low-order address area corresponding to the bit width of the virtual address in the concatenated address, and masking the high-order address area, thereby obtaining the virtual address.

[0079] In one example, the lower N bits of the preset mask value are all 1, and the higher M bits are all 0, where N is the width of the virtual address and M is the width of the concatenated address. By performing a bitwise AND operation, the lower address bits can be accurately preserved while the higher extension bits are masked, achieving the same effect as truncation. This also avoids address errors caused by hardware truncation logic malfunctions, improving the reliability of the virtual address.

[0080] In step S133, the low-order address area of ​​the virtual address is read to obtain the virtual address.

[0081] In some scenarios, the load storage unit retains the concatenated address unchanged; that is, it does not truncate or mask the concatenated address. In this case, the load storage unit can obtain the virtual address by directly reading the value of the low-order address region. In one example, the load storage unit can read the virtual address from the concatenated address according to the bit width of the virtual address.

[0082] As one implementation of this disclosure, the virtual address is obtained by reading the low-order address region, which eliminates the need for address concatenation processing, reduces virtual address errors caused by errors in concatenation processing, and effectively improves the reliability of the virtual address. The truncation method is simple, direct, and efficient; the masking method can adapt to different bit widths and is highly flexible; and the direct reading method is suitable for scenarios where truncation and masking are not required.

[0083] Meanwhile, as one embodiment of this disclosure, the process of reading the low-order address area of ​​the concatenated address can be directly completed by hardware, resulting in fast response speed and meeting real-time access requirements. Additionally, as another embodiment of this disclosure, consistency checks can be performed on the high-order extension area before address truncation or masking of the concatenated address; alternatively, consistency checks can be performed on the high-order extension area before reading the low-order extension area from the concatenated address. This allows for consistency checks on the high-order extension area before data lookup in the TLB or access to the data storage unit, thereby detecting address high-order anomalies in the early stages of storage access, reducing the possibility of silent propagation of abnormal addresses, and effectively narrowing the spread of high-order address errors.

[0084] In some embodiments, the address detection method provided in this disclosure may further include step S14.

[0085] In step S14, if the detection result is not passed, an exception handling operation is performed.

[0086] If the detection result is unsuccessful, it indicates that the value of the high-order extension region of the concatenated address does not conform to the preset rules, and the concatenated address is abnormal. In this case, if the high-order extension region is directly truncated or masked when generating the virtual address, the abnormal high-order information may be silently discarded. This error may manifest in an indirect or delayed form during subsequent caching, TBL, or memory access, causing significant difficulties for system debugging and reliability.

[0087] Therefore, if the test result is unsuccessful, abnormal operation handling can be performed, and risks can be recorded or reported in a timely manner to improve the reliability of the system and facilitate subsequent troubleshooting and debugging.

[0088] This disclosure provides various executable exception handling methods in its embodiments. The process of performing exception operations is described below. In some embodiments, the exception handling operation in step S14 may include one or more of steps S141 to S144.

[0089] In step S141, an exception message is generated and written to the status register.

[0090] The anomaly information describes the specific circumstances of address detection anomalies. In one example, the anomaly information includes, but is not limited to, the anomaly type, the specific value of the concatenated address, the specific value of the high-order extension region, the consistency check rules, and the anomaly event. The anomaly information can be used for subsequent troubleshooting to help relevant personnel quickly locate the cause of the anomaly. For example, the anomaly type could be that the high-order extension region value differs from the preset constant value, is inconsistent with the sign bit, or is inconsistent with the preset value corresponding to the data storage unit type.

[0091] A status register represents a dedicated register within a processing unit used to store system status and exception information; it is typically a read-write register. The processing unit's register file may include this status register. Personnel use debugging tools to read the exception information in the status register and analyze the cause of the exception.

[0092] In step S142, the value of the access error counter of the data storage unit is incremented by one.

[0093] An access error counter is a counter in the processing unit used to count the number of access errors in the storage unit. In one example, the access error counter can be a hardware counter, initially set to 0. Each time a concatenated address detection fails, the counter value automatically increments by 1. When the counter value accumulates to a preset threshold, such as 10 or 20 times, it indicates frequent address anomalies in the system, possibly caused by hardware failure or software error, triggering a system alert. The access error counter value reflects the frequency of concatenated address errors, providing data support for system reliability assessment and fault early warning.

[0094] In step S143, an abnormal event notification is sent to the debugging unit or diagnostic unit of the processing unit.

[0095] A debugging unit can represent a unit within the processing unit used to perform debugging and troubleshooting operations. The debugging unit can receive abnormal event notifications, pause the current debugging process, and locate the location where the abnormality occurred.

[0096] A diagnostic unit can represent a unit within the processing unit used for automatic system fault diagnosis. The diagnostic unit can receive abnormal event notifications, combine them with abnormal information, automatically analyze the cause of the abnormality, generate a diagnostic report, or trigger corresponding repair operations, such as restarting the address register or load storage unit.

[0097] In step S144, the threads, thread groups, and / or wavefronts that access the data storage unit are marked.

[0098] A thread is the smallest unit of execution within a processing unit that carries out specific instructions. A thread group is a collection of multiple related threads used to perform the same type of task. A wavefront is a group of synchronously executing threads, typically used for parallel data processing.

[0099] When the load storage unit fails the test, it marks the thread, thread group, and / or wavefront that accessed the data storage unit. The thread, thread group, and / or wavefront can then be processed, such as pausing execution, terminating execution, or rescheduling, to reduce the spread of the anomaly.

[0100] As one implementation of this disclosure, multiple exception handling operations are used to achieve full-process management from recording, statistics, reporting to location, which significantly improves the observability and debugging efficiency of address errors (also known as high-order anomalies).

[0101] In some embodiments, step S12 performs a consistency check on the high-order extension region to obtain the detection result of the spliced ​​address, which may include steps S124 and S125.

[0102] In step S124, the access mode for the data storage unit is determined.

[0103] In step S125, when the access mode is debug mode, a consistency check is performed on the high-order extension area to obtain the detection result of the spliced ​​address.

[0104] The access mode of a data storage unit represents the operating mode of the processing unit when accessing the data storage unit. Access modes can be divided into debug mode and non-debug mode. The access mode can be set as needed. For example, during testing, the access mode can be set to debug mode; during batch processing, the access mode can be set to non-debug mode.

[0105] When the access mode is debug mode, the load storage unit needs to perform consistency checks on the high-order extension area in order to detect and eliminate errors in a timely manner.

[0106] In some embodiments, the address detection method provided in this disclosure may further include step S15.

[0107] In step S15, when the access mode is non-debugging mode, a virtual address is generated directly based on the concatenated address after obtaining the concatenated address.

[0108] In non-debugging mode, to improve the access efficiency of data storage units, the consistency check of the high-order extension area can be omitted, and a virtual address can be directly generated based on the concatenated address, thereby enabling fast access to the data storage unit. It should be understood that the method for generating a virtual address based on the concatenated address can be referred to in step S13, and will not be repeated here.

[0109] As one implementation of this disclosure, an access mode is set to enable a consistency check mechanism for the high-order extension region. Consistency checks are performed in debugging scenarios and omitted in non-debugging scenarios, which improves efficiency and reduces resource waste compared to unconditional checks. For example, in mass production scenarios, a non-debugging mode can be enabled to disable the consistency check process for the high-order extension region, effectively reducing the impact of consistency checks on performance.

[0110] The address detection method according to embodiments of this disclosure provides a mechanism for detecting high-order anomalies in virtual addresses within a loaded storage unit. This allows high-order dirty data introduced by address calculation errors to be detected and reported promptly in the early stages of storage access, thereby improving system reliability, tunability, and error location efficiency. Furthermore, the address detection method according to embodiments of this disclosure does not alter the existing instruction set architecture and is transparent to software; the detection mechanism is configurable, its impact on performance is controllable, effectively reducing engineering implementation risks; and it has a wide range of applications and does not depend on specific architectural details.

[0111] The address detection method according to the embodiments of this disclosure can be applied to accessing data storage units in processing tasks such as image processing, voice processing, text processing, and video processing. The data stored in the data storage unit includes any one of images, voice, text, and video, and this disclosure does not limit it.

[0112] The address detection method provided in this disclosure is illustrated below using a graphics processor as an example of a processing unit.

[0113] First, the system environment for this method is introduced. This method is applicable to a graphics processor that supports a unified address space. This graphics processor includes a register file, a payload storage unit, and a data storage unit. The payload storage unit is connected between the register file and the data storage unit. The register file includes two 32-bit address registers, namely the first address register and the second address register. In this graphics processor, both the first address register and the second address register have a bit width of 32 bits, and the virtual address supported by the data storage unit has a bit width of 48 bits.

[0114] The address detection process for the load storage unit in the graphics processor includes steps S21 to S26.

[0115] In step S21, the load storage unit reads 32-bit address operands from the first address register and the second address register respectively, and concatenates the two 32-bit address operands to obtain a 64-bit concatenated address. The lower 32 bits of the concatenated address are the address operands read from the first address register, and the higher 32 bits are the address operands read from the second address register.

[0116] In step S22, before performing truncation processing on the concatenated address, the load storage unit performs a consistency check on the high-order extension region consisting of bits 63 to 48 of the concatenated address to obtain the detection result of the concatenated address.

[0117] In step S23, the load storage unit determines that the consistency detection rule is the all-zero consistency rule, which requires that all address bits of the high-order extension area be a preset constant value and that the preset constant value is zero.

[0118] In step S24, if the detection result is not passed, that is, when any non-zero address bit is detected in the high-order extension area, the load storage unit generates an abnormal information, which is used to indicate an abnormality in the high-order address.

[0119] In step S25, the load storage unit writes the exception information into the status register and simultaneously marks the thread that triggered the exception.

[0120] In step S26, if the detection result is passed, that is, if no non-zero address bits are detected in the high-order extension area, the load storage unit performs a truncation operation on the concatenated address, retains the lower 48 bits of the concatenated address as a virtual address, and completes data access between the memory file and the data storage unit based on the virtual address.

[0121] In some possible implementations, the load storage unit may include an address concatenation subunit, an address detection subunit, an address generation subunit, and an address translation subunit. After obtaining the concatenated address, the address concatenation subunit submits it to the address detection subunit. The address detection subunit performs a consistency check on the high-order extension of the concatenated address; if the check passes, it submits the concatenated address to the address generation subunit. The address generation subunit generates a virtual address based on the concatenation and submits the virtual address to the address translation subunit. The address translation subunit converts the virtual address into a physical address. This physical address can then be used to access data from the data storage unit.

[0122] As one implementation of this disclosure, when a non-zero address bit appears in the high-order extension area due to addition overflow or register contamination during address calculation, the abnormality can be detected in time before the concatenated address is truncated, reducing the possibility of the abnormal address continuing to propagate.

[0123] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0124] In addition, this disclosure also provides a load storage unit, a processing unit, and an electronic device, all of which can be used to implement any of the address detection methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the relevant section of the method and will not be repeated here.

[0125] This disclosure also provides a processing unit. Figure 2 This is a block diagram of a processing unit provided in an embodiment of the present disclosure. (Refer to...) Figure 2 The processing unit may include a load storage unit and a memory file, the memory file including address registers. There may be multiple address registers.

[0126] The storage load unit is configured to concatenate multiple operands read from multiple address registers to obtain a concatenated address. The bit width of the concatenated address is greater than the bit width of the virtual address supported by the data storage unit connected to the processing unit. The concatenated address includes a low-order address area corresponding to the bit width of the virtual address and a high-order extension area located outside the bit width of the virtual address. A consistency check is performed on the high-order extension area to obtain the check result of the concatenated address. If the check result is successful, a virtual address is generated based on the concatenated address, and data access between the memory file and the data storage unit is completed based on the virtual address.

[0127] Reference Figure 2 The processing unit is communicatively connected to the data storage unit. The load storage unit within the processing unit is connected to a register file. The address registers in the register file are configured to store address operands.

[0128] Reference Figure 2The processing unit may further include an exception control and processing unit. The load storage unit within the processing unit is connected to the exception control and processing unit. The load storage unit may also be configured to perform exception handling operations if the detection result of the concatenated address fails. During exception handling, the load storage unit may generate exception information and write it to a status register; increment the access counter of the data storage unit; send an exception event notification to a debugging unit or diagnostic unit; and mark the thread, thread group, and / or wavefront accessing the data storage unit. The exception control and processing unit is configured to receive exception information from the load storage unit and write it to a status register; increment the access counter; receive exception event notifications from the load storage unit and send them to the debugging unit or diagnostic unit; and perform the marking of threads, thread groups, and / or wavefronts.

[0129] The load storage unit provided in this embodiment can be applied to parallel processor and graphics processor architectures. The load storage unit can perform high-order anomaly detection and reporting on virtual addresses.

[0130] Figure 3 This is a block diagram of a load storage unit provided in an embodiment of the present disclosure.

[0131] Reference Figure 3 This disclosure provides a load storage unit 30, which includes an address splicing subunit 31, an address detection subunit 32, and an address generation subunit 33. The address detection subunit 32 is connected between the address splicing subunit 31 and the address generation subunit 33.

[0132] Address splicing subunit 31 is configured to splice multiple address operands read from multiple address registers of the processing unit to obtain a spliced ​​address. The bit width of the spliced ​​address is greater than the bit width of the virtual address supported by the data storage unit of the processing unit. The spliced ​​address includes a low-order address area corresponding to the bit width of the virtual address and a high-order extension area located outside the bit width of the virtual address.

[0133] Address detection subunit 32 is configured to perform consistency detection on the high-order extension area to obtain the detection result of the spliced ​​address.

[0134] Address generation subunit 33 is configured to generate a virtual address based on the concatenated address when the detection result is passed, and to complete data access between the memory file of the processing unit and the data storage unit based on the virtual address.

[0135] In one possible implementation, the address detection subunit 32 is configured to perform one or more of the following: if the value of each address bit in the high-order extension region is a preset constant value, determine that the detection result is passed; if the value of each address bit in the high-order extension region is consistent with the sign bit in the low-order address region, determine that the detection result is passed; if the value in the high-order extension region is consistent with the preset value corresponding to the type of data storage unit, determine that the detection result is passed.

[0136] In one possible implementation, the address generation subunit 33 is configured to perform one or more of the following: truncate the high-order extension of the concatenated address to obtain a virtual address; perform masking on the concatenated address to obtain a virtual address; and read the low-order address area of ​​the virtual address to obtain a virtual address.

[0137] In one possible implementation, the load storage unit 30 further includes an exception handling subunit 34.

[0138] The exception handling subunit 34 is configured to perform an exception handling operation if the address detection subunit 32 determines that the detection result is unsuccessful.

[0139] In one possible implementation, the exception handling subunit 34 is configured to perform one or more of the following: generate exception information and write the exception information to a status register; increment the value of the access error counter of the data storage unit by one; send an exception event notification to the debugging or diagnostic unit of the processing unit; and mark the thread, thread group, and / or wavefront accessing the data storage unit.

[0140] In one possible implementation, the load storage unit 30 further includes a mode configuration subunit 35.

[0141] The mode configuration subunit 35 is configured to determine the access mode for the data storage unit; the address detection subunit 32 is also configured to perform consistency detection on the high-order extension area when the access mode is debug mode, and obtain the detection result of the concatenated address.

[0142] In one possible implementation, the address generation subunit 33 is also configured to generate a virtual address directly from the concatenated address after obtaining it when the access mode is non-debugging mode.

[0143] Figure 4 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0144] Reference Figure 4This disclosure provides an electronic device, which includes: at least one processing unit; and a data storage unit communicatively connected to the at least one processing unit; wherein each processing unit includes a load storage unit and a memory file, the memory file including a plurality of address registers, the load storage unit storing one or more computer instructions executable by the load storage unit, and the one or more computer instructions being executed by the load storage unit to enable the load storage unit to perform the address detection method described above.

[0145] In some embodiments, the processing unit may refer to Figure 2 The load storage unit in the processing unit can be referred to Figure 3 This will not be elaborated upon here.

[0146] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0147] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. An address detection method, characterized in that, The method is applied to a load storage unit (LSU) and includes: Multiple address operands read from multiple address registers of the processing unit are concatenated to obtain a concatenated address. The bit width of the concatenated address is greater than the bit width of the virtual address supported by the data storage unit connected to the processing unit. The concatenated address includes a low-order address area corresponding to the bit width of the virtual address and a high-order extension area located outside the bit width of the virtual address. A consistency check is performed on the high-order extension region to obtain the detection result of the spliced ​​address; If the detection result is passed, the virtual address is generated according to the concatenated address, and data access between the memory file of the processing unit and the data storage unit is completed based on the virtual address.

2. The method according to claim 1, characterized in that, The consistency check performed on the high-order extension region to obtain the detection result of the spliced ​​address includes one or more of the following: If the value of each address bit in the high-order extension region is a preset constant value, the detection result is determined to be passed. If the value of each address bit in the high-order extension region is consistent with the sign bit in the low-order address region, the detection result is determined to be passed. If the value of the high-order extension region is consistent with the preset value corresponding to the type of the data storage unit, the detection result is determined to be passed.

3. The method according to claim 1, characterized in that, The process of generating the virtual address based on the concatenated address includes one or more of the following: The virtual address is obtained by truncating the high-order extension region of the concatenated address; The virtual address is obtained by masking the concatenated address; The virtual address is obtained by reading the low-order address region of the virtual address.

4. The method according to claim 1, characterized in that, The method further includes: If the test result is negative, an exception handling operation is performed.

5. The method according to claim 4, characterized in that, The exception handling operation includes one or more of the following: Generate exception information and write the exception information into the status register; Increment the value of the access error counter of the data storage unit by one; Send an abnormal event notification to the debugging or diagnostic unit of the processing unit; The threads, thread groups, and / or wavefronts that access the data storage unit are marked.

6. The method according to claim 1, characterized in that, The step of performing consistency detection on the high-order extension region to obtain the detection result of the spliced ​​address includes: Determine the access mode for the data storage unit; When the access mode is debug mode, a consistency check is performed on the high-order extension region to obtain the detection result of the spliced ​​address.

7. The method according to claim 6, characterized in that, The method further includes: When the access mode is non-debugging mode, the virtual address is generated directly based on the concatenated address after obtaining the concatenated address.

8. A load storage unit, characterized in that, It includes an address concatenation subunit, an address detection subunit, and an address generation subunit, wherein the address detection subunit is connected between the address concatenation subunit and the address generation subunit; wherein, The address concatenation subunit is configured to concatenate multiple address operands read from multiple address registers of the processing unit to obtain a concatenated address. The bit width of the concatenated address is greater than the bit width of the virtual address supported by the data storage unit connected to the processing unit. The concatenated address includes a low-order address area corresponding to the bit width of the virtual address and a high-order extension area located outside the bit width of the virtual address. The address detection subunit is configured to perform consistency detection on the high-order extension region to obtain the detection result of the concatenated address; The address generation subunit is configured to generate the virtual address based on the concatenated address when the detection result is passed, and to complete data access between the memory file of the processing unit and the data storage unit based on the virtual address.

9. The load storage unit according to claim 8, characterized in that, The address detection subunit is also configured to perform one or more of the following: If the value of each address bit in the high-order extension region is a preset constant value, the detection result is determined to be passed. If the value of each address bit in the high-order extension region is consistent with the sign bit in the low-order address region, the detection result is determined to be passed. If the value of the high-order extension region is consistent with the preset value corresponding to the type of the data storage unit, the detection result is determined to be passed.

10. The load storage unit according to claim 8, characterized in that, The address generation subunit is also configured to perform one or more of the following: The virtual address is obtained by truncating the high-order extension region of the concatenated address; The virtual address is obtained by masking the concatenated address; The virtual address is obtained by reading the low-order address region of the virtual address.

11. A processing unit, characterized in that, The processing unit includes a load storage unit (LSU) and a memory file, wherein the memory file includes multiple address registers; The load storage unit is configured to concatenate multiple operands read from the multiple address registers to obtain a concatenated address. The bit width of the concatenated address is greater than the bit width of the virtual address supported by the data storage unit connected to the processing unit. The concatenated address includes a low-order address region corresponding to the bit width of the virtual address and a high-order extension region located outside the bit width of the virtual address. A consistency check is performed on the high-order extension region to obtain a check result for the concatenated address. If the check result is successful, the virtual address is generated based on the concatenated address, and data access between the memory file and the data storage unit is completed based on the virtual address.

12. An electronic device, characterized in that, include: At least one processing unit; as well as A data storage unit communicatively connected to the at least one processing unit; wherein, Each processing unit includes a load storage unit (LSU) and a memory file, the memory file including a plurality of address registers, the load storage unit storing one or more computer instructions executable by the load storage unit, the one or more computer instructions being executed by the load storage unit to enable the load storage unit to perform the address detection method as described in any one of claims 1-7.

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