A method and system for constructing a verification environment of an image signal processor and a storage medium

Abstract

The application discloses a kind of image signal processor's verification environment construction method, system and storage medium, by the corresponding verification component of each node module in image processing pipeline template design, create the configuration component of unified configuration of verification environment, define unified sequence base class, and based on each verification component, configuration component and sequence base class, create each sub-environment;Unified test base class is set based on the sequence name of each sub-environment and the test case of each node module, the configuration information of each node module is added to unified environment configuration, by test case setting to top-level environment, then issue to each sub-environment, to obtain the verification environment of ISP.The application method is switched seamlessly by unified verification environment framework, realizes node module level and subsystem level verification, and based on the management mechanism of shared item configuration, ensure that sub-environment configuration is consistent, to improve verification efficiency and verification flexibility, reduce configuration management complexity.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit technology, and more particularly to a method, system, and storage medium for constructing a verification environment for an image signal processor. This invention falls under IPC classification number G06F, and therefore belongs to a technical field for which prior review can be requested. Background Technology

[0002] With the rapid development of image processing technology, the structural complexity of image signal processors (ISPs) is constantly increasing, leading to increasingly stringent requirements for their verification.

[0003] In existing technologies, ISP verification environments typically employ a layered verification architecture, fixed verification paths, and distributed configuration management. However, these architectures and implementations suffer from at least the following drawbacks: 1. The layered verification architecture uses different code libraries, directory structures and naming conventions for module-level and subsystem-level verification environments, resulting in significant differences in the interface definitions and implementation details of verification components. This leads to problems such as the separation of module-level and subsystem-level verification components, the inability to unify interfaces, and code redundancy exceeding 80%.

[0004] 2. The fixed verification path approach often takes hours or even days to verify a complete image processing pipeline, and it cannot support parallel verification or on-demand cropping of the verification path. For ISP designs with frequent algorithm iterations, this mode causes the verification cycle to far exceed the design cycle.

[0005] 3. Distributed configuration management, which uses a hierarchical configuration database to pass configuration parameters layer by layer, is complex and prone to errors. Furthermore, different sub-environment configurations are maintained independently, and manual synchronization can easily lead to omissions or version inconsistencies, resulting in unreliable verification results.

[0006] In summary, existing verification architectures and implementation methods suffer from problems such as low verification efficiency, poor flexibility, and complex configuration management, making them difficult to match the chip verification requirements of image signal processors, which involve rapid algorithm iteration and numerous processing nodes. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a method, system and storage medium for constructing a verification environment for an image signal processor, overcoming the defects of low verification efficiency, poor verification flexibility and complex configuration management in the prior art.

[0008] The technical solution adopted by this invention to solve the technical problem is as follows: In a first aspect, the present invention discloses a method for constructing a verification environment for an image signal processor, comprising: The verification components corresponding to each node module in the image processing pipeline are templated to obtain templated verification components corresponding to each node module. Create a unified configuration component for the verification environment and define a unified sequence base class. Based on the templated design of each verification component, the configuration component, and the sequence base class, create sub-environments with unified interfaces. Based on the sequence name of each sub-environment, a unified test base class and test cases for each node module are set. Each test case adds the configuration information of each node module to the unified environment configuration in a preset order. The environment configuration is set to the top-level environment through test cases, so that the top-level environment can automatically build a verification environment suitable for verification with any node of the image signal processor as the starting point and the end point.

[0009] Optionally, the step of template-based design of the verification modules corresponding to each node module in the image processing pipeline, to obtain the template-based design and the verification components corresponding to each node module, includes: The driver obtains the input transaction object from the sequence and assigns the name of the input transaction object using a modular prefix and fixed components. The source of image data in the reference model is uniformly set to the input monitoring port of the monitor, so that the input monitoring port of the monitor and the output port of the driver are the same physical point when the node module is verified. In each sub-environment, the configuration information of the top-level environment is obtained, and the verification components corresponding to each node module are obtained.

[0010] Optionally, the step of creating a unified configuration component for the verification environment includes: A configuration parameter package is defined for each node module; wherein, the configuration items in the configuration parameter package include the node module name, whether to create a sub-environment, whether to drive input, and whether to perform data checking; The receiving module configuration modification instruction is used to modify the driver enable flag of the sub-environment corresponding to the specified starting node module, so that the driver enable flag of the starting node module and the sub-environment of the nodes before it is true, while the driver enable flag of the sub-environment of the nodes after the starting node is false.

[0011] Optionally, the step of defining a unified sequence base class includes: Set up an ISP data item for sharing among multiple components or sequences, so that sequences of node modules corresponding to each sub-environment can be obtained by using this ISP data item as the sequence base class.

[0012] Optionally, the step of creating sub-environments with unified interfaces based on the templated design of each verification component, the configuration component, and the sequence base class includes: Based on the configuration components of each node module, sub-environments are automatically found, created, connected, and configured to obtain sub-environments with unified interfaces.

[0013] Optionally, the step of setting a unified test base class and test cases for each node module based on the sequence name of each sub-environment, and adding the configuration information of each node module to the unified environment configuration according to a preset order, includes: Set up a test base class, and create test cases for each node module based on the test base class; Following the sequence of the image processing pipeline, the configuration information of each node module is added to the environment configuration.

[0014] Optionally, the test case sets the environment configuration to the top-level environment so that the top-level environment automatically constructs a verification environment suitable for verification using any node of the image signal processor as the starting and ending point, according to the environment configuration. This step includes: The test cases distribute the environment configuration to the top-level environment object, which then dynamically creates one or more corresponding sub-environment objects based on the environment configuration to obtain a verification environment suitable for image signal processor verification.

[0015] Optionally, before the step of setting a unified test base class and test cases for each node module based on the sequence name of each sub-environment, the method further includes: Create a top-level environment object and specify it as the top level in the compilation command; wherein the top-level environment is configured to provide corresponding segmented verification configuration information for each individual node module or subsystem, so that each node module or subsystem can independently perform verification based on its own segmented verification configuration information.

[0016] Secondly, the present invention provides a verification environment construction system for an image signal processor, comprising: The templated design module is used to template the verification components corresponding to each node module in the image processing pipeline, resulting in templated designs and verification components corresponding to each node module. The sub-environment creation module is used to create a unified configuration component for the verification environment and define a unified sequence base class. Based on the templated design of each verification component, the configuration component, and the sequence base class, it creates sub-environments with unified interfaces. The environment configuration module is used to set a unified test base class and test cases for each node module based on the sequence name of each sub-environment. Each test case adds the configuration information of each node module to the unified environment configuration in a preset order. The verification environment construction module is used to set the environment configuration to the top-level environment through test cases, so that the top-level environment can automatically build a verification environment suitable for verification with any node of the image signal processor as the starting point and the end point according to the environment configuration.

[0017] Thirdly, the present invention also discloses a computer storage medium, which is a computer-readable storage medium, wherein a computer program is stored in the computer storage medium, and when the computer program is executed by a computer, the computer is used to execute the verification environment construction method of the image signal processor as described.

[0018] Beneficial effects: This invention provides a method, system, and storage medium for constructing a verification environment for an image signal processor. The method involves template-designing verification components corresponding to each node module in the image processing pipeline, resulting in template-designed verification components that are connected to each node module. A unified configuration component for the verification environment is created, along with a unified sequence base class. Based on the template-designed verification components, the configuration component, and the sequence base class, sub-environments with unified interfaces are created. A unified test base class and test cases for each node module are set based on the sequence names of each sub-environment. Each test case, in a preset order, adds the configuration information of each node module to the unified environment configuration. The environment configuration is then set to the top-level environment through the test cases, enabling the top-level environment to automatically construct a verification environment suitable for verifying any node of the image signal processor as both the starting and ending point. The method of this invention achieves seamless switching between node module-level and subsystem-level verification through a unified verification environment architecture and a template-based design. Furthermore, based on a shared item configuration management mechanism, it ensures that the code at the module level and subsystem level is basically consistent, thereby reducing code redundancy by 40%-50%, which improves verification efficiency and flexibility, and reduces configuration management complexity. Attached Figure Description

[0019] Figure 1 A flowchart illustrating the steps of constructing a verification environment for the image signal processor provided by this invention; Figure 2 This is a schematic diagram of the overall framework of the verification environment disclosed in this invention; Figure 3 This is a structural diagram of the submodule environment; Figure 4 A flowchart illustrating the steps involved in generating the verification component in the verification environment construction method provided by this invention; Figure 5 A flowchart illustrating the steps of creating a unified configuration component for the verification environment in the verification environment construction method provided by this invention; Figure 6 This is a schematic diagram of the environment for segmented verification in an embodiment of the present invention; Figure 7 A system structure block diagram is provided for constructing the verification environment of the image signal processor disclosed in this invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] It should be noted that although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart. The terms "first," "second," etc., used in the specification, claims, and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0022] To overcome the shortcomings of low verification efficiency, poor verification flexibility, and complex configuration management in existing verification environments, this invention provides a method, system, and storage medium for constructing a verification environment for an image signal processor. The method involves template-based design of verification modules corresponding to each node module in the image processing pipeline, resulting in template-based designs and corresponding sub-environments for each node module. A unified configuration component for the verification environment is created, along with a unified sequence base class. Based on the template-based sub-environments, the configuration component, and the sequence base class, sub-environments with unified interfaces are created. A unified test base class and test cases for each node module are set based on the sequence names of each sub-environment. Each test case, following a preset order, adds the configuration information of each node module to the unified environment configuration. The environment configuration is then set to the top-level environment, enabling the top-level environment to automatically construct a verification environment suitable for verification using any node of the image signal processor as both the starting and ending point. This invention achieves seamless switching between node module-level and subsystem-level verification through a unified verification environment architecture. Furthermore, a shared item configuration management mechanism ensures consistent sub-environment configurations, thereby improving verification efficiency and flexibility while reducing configuration management complexity.

[0023] The following description, in conjunction with the accompanying drawings, provides a more detailed account of the verification environment construction method, system, and storage medium for an image signal processor disclosed in this embodiment.

[0024] Firstly, this invention discloses a method for constructing a verification environment for an image signal processor, applicable to building a flexibly configurable and reusable verification environment based on UVM (Universal Verification Methodology) for image signal processor verification, such as... Figure 1 The method includes: Step S1: Template the verification components corresponding to each node module in the image processing pipeline to obtain templated design of each verification component corresponding to each node module.

[0025] like Figure 2 This is an overall architecture diagram of a flexibly configurable and reusable verification environment based on UVM for image signal processor verification. The Design Under Test (DUT) is an image signal processor, which connects to an interface layer and then to the verification environment. The verification environment is built in layers, including a top-level environment, sub-environments, a test sequence generation module, and a configuration management module. The configuration management module stores configuration information for the top-level environment objects and sub-environments, including the mapping relationship between node modules and verification components. The test sequence generation module dynamically generates test sequences containing multiple verification steps based on the configuration information, where each verification step corresponds to a verification operation of a verification component on a corresponding node module.

[0026] like Figure 3 As shown, since the nodes in the image processing pipeline mainly involve algorithm modules, the verification environments corresponding to these algorithm modules are quite similar. Therefore, templated verification components for each node module can be automatically generated based on scripts, and then verification personnel can add specific implementation details of each module according to its specific function.

[0027] In detail, this step involves naming the components (such as driver, monitor, scoreboard) of each module (e.g., DPC (Defect Pixel Correction), BLC (Black Level Correction), LSC (Lens Shading Correction)) using the consistent naming convention of "module name_component type". This allows for quick identification of the module to which a component belongs from its name, thereby improving readability and maintainability. Furthermore, similar components from different modules are isolated using prefixes, preventing conflicts even within the same namespace.

[0028] Furthermore, such as Figure 4 As shown, the step of template-designing the verification components corresponding to each node module in the image processing pipeline to obtain template-designed verification components corresponding to each node module includes: Step S11: The driver obtains the input transaction object from the sequence and assigns the name of the input transaction object to a modular prefix and fixed components.

[0029] In practice, the sequence item input to the driver is uniformly named isp_item, and the instantiation name of the component adopts the form of modular prefix plus fixed component, which provides a basis for the reuse of subsystem-level verification environment and automatic search and creation.

[0030] Step S12: Set the source of image data in the reference model to the monitor input port so that the monitor input port and the driver output port are the same physical point when the node module is verified.

[0031] The image data source in the reference model is uniformly placed at the input monitoring port of the monitor. In module-level verification, the monitor input monitoring port and the driver output are at the same physical point to ensure data consistency. In subsystem-level verification, when the driver is not needed, the reference model can also obtain input from the monitor or source data. In this way, the appropriate data source is automatically selected according to the verification level and configuration without modifying the code.

[0032] Step S13: Obtain the configuration information of the top-level environment in each sub-environment to obtain the verification components corresponding to each node module.

[0033] In this step, configuration information from the top-level environment is obtained within the sub-environments to complete the creation and connection of the corresponding components. Specifically, first, the system reads the top-level environment to obtain general verification rules and basic parameters. Second, it overlays the differentiated configurations of the sub-environments. For each sub-environment, it obtains its unique configurations, which may cover some settings of the top-level environment or add new verification component definitions specific to that sub-environment. Finally, each node module, based on the complete configurations obtained from the top-level environment and each sub-environment, instantiates the corresponding verification component for each node module and populates all the details.

[0034] This step uses a template-based design for the verification components to ensure consistency and standardization of the generated code. The generated verification component design can be seamlessly reused in module-level and subsystem-level verification, enabling seamless switching between node-level and subsystem-level verification.

[0035] Specifically, the modules that enable seamless switching include: the top-level verification environment, sub-environment generator, driver, monitor, reference model, scoreboard, and sequence generator. When performing node-level verification, the sub-environment reads the configuration and generates corresponding components based on the node type template. When switching to subsystem-level verification, the sub-environment reads the configuration, and the template automatically generates aggregate components, such as a shared monitor. Since no modification to any test code or the structure of the top-level verification platform is required when switching between node-level and subsystem-level verification, seamless switching can be achieved.

[0036] Step S2: Create a unified configuration component for the verification environment and define a unified sequence base class. Based on the templated design of each verification component, configuration component and sequence base class, create sub-environments with unified interfaces.

[0037] To overcome the problem of inconsistent configurations caused by different sub-environments using different versions of parameters due to scattered configurations, this step creates a unified configuration component and a unified sequence base class to create each sub-environment, thereby achieving a unified verification environment architecture, simplifying environment management, supporting module-level and subsystem-level verification, and enabling automatic creation of sub-environments.

[0038] In detail, such as Figure 5 As shown, the steps for creating a unified configuration component for the verification environment include: Step S21: Define a configuration parameter package for each node module; wherein the configuration items in the configuration parameter package include the node module name, whether to create a sub-environment, whether to drive input, and whether to perform data checking.

[0039] Step S22: Receive module configuration modification instruction, and modify the driver enable flag of the sub-environment corresponding to the specified starting node module according to the module configuration modification instruction, so that the driver enable flag of the starting node module and the node sub-environment before it is true, while the driver enable flag of the node sub-environment after the starting node is false.

[0040] In a specific application example, the environment unified configuration component (isp_env_cfg) can be created using the following procedure: typedef struct { stringname; / / Stagename bitis_create_subenv; / / Whethertocreatesubenvforthisstage bitdrive_input; / / Whethertodriveinputforthisstage(onlystart pointneedsthis); bitdata_check; / / Whethertocheckdataforthisstage }stage_config_t.

[0041] The steps for creating a unified configuration component for the environment mentioned above include: defining a stage_config_t structure, which contains configuration items such as stage (module) name, whether to create a sub-environment, whether to drive input, and whether to perform data checks.

[0042] Key function: add_stage_config; function void isp_env_cfg::add_stage_config(stage_config_t cfg); ... / / Add new module configuration n_stages++; stage_configs = new[n_stages](stage_configs); stage_configs[n_stages-1] = cfg; ... Endfunction.

[0043] When defining configuration components, key functions are also used to support adding and modifying stage configurations at runtime, enabling flexible selection of the verification start node driver for ISPpipeline, while intermediate and end nodes do not require a driver.

[0044] Specifically, the steps for defining a unified sequence base class include: Set up an ISP data item for sharing among multiple components or sequences, so that sequences of node modules corresponding to each sub-environment can be obtained by using this ISP data item as the sequence base class.

[0045] In one implementation, a key method, `set_isp_share_item`, is defined in the base class. During subsystem-level validation, the `set_isp_item` method is implemented using a sequence. All virtual sequences in the module extend this sequence base class. When calling `set_isp_item` within the sequence during segmented validation and full subsystem validation, it ensures that all subenvs share the same configuration item, guaranteeing complete configuration consistency. Modifications to the configuration are automatically synchronized across all subenvs, eliminating the need for manual updates.

[0046] The above implementation achieves configuration sharing through the `set_share_isp_item` method of the `sequence` class, ensuring consistent configuration across all subenvs. Configuration changes are automatically synchronized to all subenvs, eliminating the need for manual configuration updates and centralizing management in a single location, thus reducing maintenance costs and the probability of errors. Furthermore, configuration items that can be shared include `current_subsystem_name` (a string) and `model_parameters` (a parameter package). These items are obtained through a single configuration object or a unified interface, either directly or through its fields. When one component modifies a configuration item, the new value immediately applies to all other components, maintaining consistency and thus achieving configuration item sharing.

[0047] Furthermore, the step of creating sub-environments with unified interfaces based on the configuration component and the sequence base class, according to the template-based design, includes: Based on the configuration components of each node module, sub-environments are automatically found, created, connected, and configured to obtain sub-environments with unified interfaces.

[0048] In this step, the submodule verification and subsystem verification use the same isp_env environment architecture. Based on the configuration parameters of isp_env_cfg, the environment behavior is automatically adjusted, supporting module-level and subsystem-level verification. It can flexibly select any node in the image processing pipeline as the starting point and the ending point.

[0049] All subenvs implement standardized interfaces to ensure that the unified env can correctly identify and manage them. The unified env automatically finds and creates the necessary subenvs based on the configuration in isp_env_cfg to handle the creation, connection and configuration of subenvs, reducing manual intervention. The automatic subenv creation function automatically passes the relevant configuration parameters to the created subenv to ensure configuration consistency.

[0050] The pseudocode for this step is as follows: / / Automatically create sub-environments based on configuration; stage_subenv = new[cfg.n_stages]; for (int i = 0; i <cfg.n_stages; i++) begin; if(cfg.stage_configs[i].is_create_subenv) begin; ... stage_subenv[i] = subenv_type.create_component(subenv_name, this); ... End.

[0051] This step implements a unified verification environment architecture, including automatic sequencer connection functionality. This involves the unified environment automatically discovering sequences from created sub-environments without manual specification, and automatically connecting the discovered sequences to the virtual sequencer for unified management. The implementation code is as follows: / / Connect virtual sequencer to stage sequencers based on configuration; for (int i = 0; i <cfg.n_stages; i++) begin; if (cfg.stage_configs[i].is_create_subenv&&stage_subenv[i] != null)begin; ... if ($cast(sequencer, stage_subenv[i].get_child("sequencer"))) begin; virtual_sequencer.stage_sequencer[i] = sequencer; ... End; End.

[0052] In this step, all levels of verification adopt a unified isp_env architecture, with standardized verification component interfaces designed to ensure that module-level verification components can be directly reused in subsystem-level verification, achieving seamless switching between module-level and subsystem-level verification. Furthermore, the unified architecture reduces code redundancy and significantly lowers maintenance costs.

[0053] Step S3: Based on the sequence name of each sub-environment, set a unified test base class and test cases for each node module. Each test case adds the configuration information of each node module to the unified environment configuration in a preset order.

[0054] This step provides a unified test base class to simplify test case writing and implements the get_sequence() method, which supports obtaining test sequences from command-line arguments. In actual verification, different test sequences can be selected by passing the corresponding sequence names during the simulation phase after a single compilation, reducing compilation time and accelerating verification speed.

[0055] In detail, the step of setting a unified test base class and test cases for each node module based on the sequence name of each sub-environment, and adding the configuration information of each node module to the unified environment configuration according to a preset order for each test case includes: Set up a test base class and create test cases for each node module based on the test base class; add the configuration information of each node module to the environment configuration in the order of the image processing pipeline.

[0056] To facilitate resource management, this step involves designing a base test class to make test cases for each node module more concise and easier to maintain. Furthermore, this step provides unified management of the verification environment's configuration parameters for module-level or subsystem-level test cases, supporting the setting of the start and end points of the image processing pipeline for segmented verification.

[0057] In practical implementation, the following code can be used: function uvm_object isp_base_test::get_sequence(); ... / / Get the sequence name from the simulation command line; if ($value$plusargs("SEQ_NAME=%s", sequence_name)) begin; ... / / Find and create a sequence based on its name; seq_type = uvm_factory::get().find_wrapper_by_name(sequence_name); ... seq_obj = seq_type.create_object(sequence_name); ... return seq_obj; Endfunction.

[0058] The following code is a test case for single-node verification, verifying only the BLC node: function void blc_test::build_phase(uvm_phase phase); ... / / Configure stage-specific settings stage_cfg.name = "blc"; stage_cfg.is_create_subenv = 1; stage_cfg.drive_input = 1; stage_cfg.data_check = 1; cfg.add_stage_config(stage_cfg); ... Endfunction.

[0059] Test cases for segmented or complete subsystem verification are added to a unified environment configuration one at a time, following the sequence of the image processing pipeline. Any node in the image processing pipeline can be set as the start and end point. Note that only the start point requires a driver to drive the data source input. The following code verifies the three sequential nodes: DPC->BLC->LSC: function void sys_test::build_phase(uvm_phase phase); ... Configure each stage dpc_cfg.name = "dpc"; dpc_cfg.is_create_subenv = 1; dpc_cfg.drive_input = 1; dpc_cfg.data_check = 1; cfg.add_stage_config(dpc_cfg); blc_cfg.name = "blc"; blc_cfg.is_create_subenv = 1; blc_cfg.drive_input = 0; blc_cfg.data_check = 1; cfg.add_stage_config(blc_cfg); lsc_cfg.name = "lsc"; lsc_cfg.is_create_subenv = 1; lsc_cfg.drive_input = 0; lsc_cfg.data_check = 1; cfg.add_stage_config(lsc_cfg); ... Endfunction.

[0060] Step S4: The test case sets the environment configuration to the top-level environment so that the top-level environment automatically builds a UVM verification environment suitable for verification with any node of the image signal processor as the starting and ending point, based on the environment configuration.

[0061] After completing the above configuration, the configuration is mounted to the top-level environment via `config_db`. The top-level environment will then create the corresponding sub-environments based on these configurations, and perform actions such as sequencer connection (the process of establishing a TLM (Transaction Management Modeling) port connection between the sequencer and the driver; its core is to establish a data transmission channel from the sequence to the driver, ensuring that transactions generated by the sequence can flow correctly and efficiently to the driver, and thus drive the DUT), etc. The configuration in the above test case completes the creation of a segmented verification environment from DPC->BLC->LSC, as shown below. Figure 6 As shown.

[0062] In detail, the steps of storing the environment configuration in the UVM database and distributing it to the top-level environment object so that the top-level environment object can construct a UVM verification environment suitable for image signal processor verification based on the environment configuration include: The environment configuration information is sent to the top-level environment object, which then dynamically creates one or more corresponding sub-environment objects based on the environment configuration to obtain a UVM verification environment suitable for image signal processor verification.

[0063] It is conceivable that before the step of setting a unified test base class and test cases for each node module based on the sequence names of each sub-environment, the following steps are also included: Create a top-level environment object and specify it as the top level in the compilation command; wherein the top-level environment is configured to provide corresponding segmented verification configuration information for each individual node module or subsystem, so that each node module or subsystem can independently perform verification based on its own segmented verification configuration information.

[0064] The top-level environment in this step is mainly used to generate clock and reset signals, instantiate the design under test (DUT), instantiate the environment interface components, and connect them to the DUT. It also uses the `config_db` mechanism to assign these environment interface components to components in each sub-environment. Each node in this step can be manually implemented using the components of the top-level environment object. If the start and end points of the selected image processing pipeline for verification are different, the corresponding instantiation and connections can be manually implemented. Then, by specifying this top-level environment in the compilation command, verification of different nodes or different consecutive nodes can be implemented within the same environment.

[0065] The method disclosed in this embodiment enables seamless reuse of module-level verification components in subsystem-level verification. By designing standardized component interfaces, it ensures that module-level verification components can be directly reused in subsystem-level verification, reducing redundant development work and improving verification efficiency and consistency. Furthermore, the method of this invention also supports any node in the image processing pipeline as the start and end point, enabling flexible and segmented verification mechanisms, improving verification efficiency, and avoiding redundant verification and task allocation.

[0066] Secondly, the present invention provides a verification environment construction system for an image signal processor, such as... Figure 7 As shown, it includes: The templated design module 710 is used to template the verification components corresponding to each node module in the image processing pipeline, obtain templated designs of each verification component corresponding to each node module, and complete the connection between each verification component; its function is as described in step S1.

[0067] The sub-environment creation module 720 is used to create a unified configuration component for the verification environment and define a unified sequence base class. Based on the templated design of each verification component, configuration component and sequence base class, it creates sub-environments with unified interfaces; its function is as described in step S2.

[0068] The environment configuration module 730 is used to set a unified test base class and test cases for each node module based on the sequence name of each sub-environment. Each test case adds the configuration information of each node module to the unified environment configuration in a preset order; its function is as described in step S3.

[0069] The verification environment construction module 740 is used to set the environment configuration to the top-level environment through test cases, so that the top-level environment can automatically build a verification environment suitable for verification with any node of the image signal processor as the starting point and the end point, according to the environment configuration. Its function is as described in step S4.

[0070] This system can build a unified verification environment. This unified architecture not only reduces code redundancy, but also, based on a module-level environment configuration-driven design, allows environment modifications to only require updating the configuration rather than the code, significantly reducing maintenance costs.

[0071] Thirdly, the present invention also discloses a computer storage medium, which is a computer-readable storage medium, wherein a computer program is stored in the computer storage medium, and when the computer program is executed by a computer, the computer is used to execute the verification environment construction method of the image signal processor as described.

[0072] This invention provides a method, system, and storage medium for constructing a verification environment for an image signal processor. The method involves template-based design of verification modules corresponding to each node module in the image processing pipeline, resulting in template-based designs and corresponding sub-environments for each node module. A unified configuration component for the verification environment is created, along with a unified sequence base class. Based on the template-based design of the verification components, configuration components, and sequence base class, sub-environments with unified interfaces are created. A unified test base class and test cases for each node module are set based on the sequence names of each sub-environment. Each test case, in a preset order, adds the configuration information of each node module to the unified environment configuration. The environment configuration is then set to the top-level environment through the test cases, enabling the top-level environment to automatically construct a UVM verification environment suitable for verifying any node of the image signal processor as both the starting and ending point. This invention achieves seamless switching between node module-level and subsystem-level verification through a unified verification environment architecture. Furthermore, a shared item configuration management mechanism ensures consistent sub-environment configurations, thereby improving verification efficiency and flexibility while reducing configuration management complexity.

[0073] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein.

[0074] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A method for constructing a verification environment for an image signal processor, characterized in that, include: The verification components corresponding to each node module in the image processing pipeline are templated and designed to obtain each templated verification component corresponding to each node module, and the connection between each verification component is completed. Create a unified configuration component for the verification environment and define a unified sequence base class. Based on the templated design of each verification component, configuration component and sequence base class, create sub-environments with unified interfaces. The steps for creating a unified configuration component for the verification environment include: A configuration parameter package is defined for each node module; wherein, the configuration items in the configuration parameter package include the node module name, whether to create a sub-environment, whether to drive input, and whether to perform data checking; The receiving module configuration modification instruction is used to modify the driver enable flag of the sub-environment corresponding to the specified starting node module, so that the driver enable flag of the starting node module and the sub-environment of the nodes before it is true, while the driver enable flag of the sub-environment of the nodes after the starting node is false. Based on the sequence name of each sub-environment, a unified test base class and test cases for each node module are set. Each test case adds the configuration information of each node module to the unified environment configuration in a preset order. The test cases set the environment configuration to the top-level environment so that the top-level environment automatically builds a verification environment suitable for verification with any node of the image signal processor as the starting and ending point, based on the environment configuration.

2. The method for constructing a verification environment for an image signal processor according to claim 1, characterized in that, The step of template-designing the verification components corresponding to each node module in the image processing pipeline to obtain template-designed verification components corresponding to each node module includes: The driver obtains the input transaction object from the sequence and assigns the name of the input transaction object using a modular prefix and fixed components. The source of image data in the reference model is uniformly set to the input monitoring port of the monitor, so that the input monitoring port of the monitor and the output port of the driver are the same physical point when the node module is verified. In each sub-environment, the configuration information of the top-level environment is obtained, and the verification components corresponding to each node module are obtained.

3. The method for constructing a verification environment for an image signal processor according to claim 1, characterized in that, The steps for defining a unified sequence base class include: Set up an ISP data item for sharing among multiple components or sequences, so that sequences of node modules corresponding to each sub-environment can be obtained by using this ISP data item as the sequence base class.

4. The method for constructing a verification environment for an image signal processor according to claim 3, characterized in that, The steps for creating unified sub-environments based on the templated design of each verification component, configuration component, and sequence base class include: Based on the configuration components of each node module, sub-environments are automatically found, created, connected, and configured to obtain sub-environments with unified interfaces.

5. The method for constructing a verification environment for an image signal processor according to claim 3, characterized in that, The step of setting a unified test base class and test cases for each node module based on the sequence name of each sub-environment, and adding the configuration information of each node module to the unified environment configuration according to a preset order for each test case includes: Set up a test base class, and create test cases for each node module based on the test base class; Following the sequence of the image processing pipeline, the configuration information of each node module is added to the environment configuration.

6. The method for constructing a verification environment for an image signal processor according to claim 5, characterized in that, The test cases configure the environment to the top-level environment so that the top-level environment automatically constructs a verification environment suitable for verification using any node of the image signal processor as the starting and ending point, based on the environment configuration. The steps include: The test cases distribute the environment configuration to the top-level environment object, which then dynamically creates one or more corresponding sub-environment objects based on the environment configuration to obtain a verification environment suitable for image signal processor verification.

7. The method for constructing a verification environment for an image signal processor according to claim 1, characterized in that, Before the step of setting a unified test base class and test cases for each node module based on the sequence name of each sub-environment, the following is also included: Create a top-level environment object and specify it as the top level in the compilation command; wherein the top-level environment is configured to provide corresponding segmented verification configuration information for each individual node module or subsystem, so that each node module or subsystem can independently perform verification based on its own segmented verification configuration information.

8. A verification environment construction system for an image signal processor, characterized in that, include: The templated design module is used to template the verification components corresponding to each node module in the image processing pipeline, obtain the templated design of each verification component corresponding to each node module, and complete the connection between each verification component. The sub-environment creation module is used to create a unified configuration component for the verification environment and define a unified sequence base class. Based on the templated design of each verification component, the configuration component, and the sequence base class, it creates sub-environments with unified interfaces. The environment configuration module is used to set a unified test base class and test cases for each node module based on the sequence name of each sub-environment. Each test case adds the configuration information of each node module to the unified environment configuration in a preset order. The verification environment construction module is used to set the environment configuration to the top-level environment through test cases, so that the top-level environment can automatically build a verification environment suitable for verification with any node of the image signal processor as the starting point and the end point according to the environment configuration. The steps for creating a unified configuration component for the verification environment include: A configuration parameter package is defined for each node module; wherein, the configuration items in the configuration parameter package include the node module name, whether to create a sub-environment, whether to drive input, and whether to perform data checking; The receiving module configuration modification instruction is used to modify the driver enable flag of the sub-environment corresponding to the specified starting node module, so that the driver enable flag of the starting node module and the sub-environment of the nodes before it is true, while the driver enable flag of the sub-environment of the nodes after the starting node is false.

9. A computer storage medium, wherein the storage medium is a computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a computer, enables the computer to perform the verification environment construction method for the image signal processor as described in any one of claims 1-7.

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