Processor chip and register state value acquisition method

Abstract

This application discloses a processor chip and a method for acquiring register status values, relating to the field of integrated circuit technology. It is invented to improve the accuracy of analyzing changes in the processor chip system throughout the process of a processor chip malfunction, thereby improving the performance of the processor chip. The processor chip includes: a control unit for configuring the identifier and comparison mode of a target status register; a status value acquisition unit connected to the control unit; the status value acquisition unit sequentially acquiring status values ​​in the target status register at multiple times based on the identifier of the target status register; a comparison unit connected to both the control unit and the status value acquisition unit, used to sequentially determine whether to send the status values ​​at multiple times to a first-in-first-out (FIFO) storage unit based on the comparison mode; and a FIFO storage unit connected to the comparison unit for receiving and storing the status values ​​sent by the comparison unit. This application is applicable to data processing.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a processor chip and a method for obtaining register status values. Background Technology

[0002] In existing processor chip designs such as System-on-Chip (SoC), there are many status registers used to store various states of the processor chip system. When a problem occurs during the operation of the processor chip system, the status values ​​in these status registers can be read to determine what problem has occurred in the processor chip's operation.

[0003] Sometimes, when a processor chip system malfunctions, most of its status registers are dynamically changing and constantly being refreshed. This means that when reading the status values ​​in these registers, the values ​​have already changed. As a result, it is difficult to read the complete status values ​​of these registers before and after the processor chip system malfunctions, making it impossible to accurately analyze the changes in the processor chip system before and after the malfunction. Consequently, it becomes very difficult to debug and analyze the cause of the processor chip malfunction. Summary of the Invention

[0004] In view of this, the present application provides a method for obtaining the status values ​​of a processor chip and its registers, which facilitates improving the accuracy of analyzing the changes in the processor chip system throughout the process of a processor chip malfunction, thereby improving the performance of the processor chip.

[0005] In a first aspect, embodiments of this application provide a processor chip, comprising: a status register; a control unit configured to configure an identifier and comparison mode of a target status register; a status value acquisition unit connected to the control unit; the status value acquisition unit configured to sequentially acquire status values ​​in the target status register at multiple times according to the identifier of the target status register; a comparison unit connected to both the control unit and the status value acquisition unit, configured to sequentially determine whether to send the status values ​​at multiple times to a first-in-first-out (FIFO) storage unit according to the comparison mode; the FIFO storage unit connected to the comparison unit configured to receive the status values ​​sent by the comparison unit and store the status values.

[0006] According to a specific implementation of an embodiment of this application, the state values ​​at multiple times include a first state value; wherein, the comparison unit is specifically configured to: determine whether to send the first state value to the first-in-first-out (FIFO) storage unit based on the first state value and a first threshold; if yes, determine to send the first state value to the FIFO storage unit; or, the comparison unit is specifically configured to: determine whether to send the first state value to the FIFO storage unit based on the first state value and a second state value; the second state value is a state value that is adjacent to and precedes the first state value among the state values ​​at different times; if yes, determine to send the first state value to the FIFO storage unit.

[0007] According to a specific implementation of an embodiment of this application, the control unit is further configured to configure a first mask; the comparison unit is specifically configured to: perform a logical operation on the first state value and the first mask to obtain a new first state value; compare the new first state value with a first threshold; if the new first state value is not equal to the first threshold, determine to send the first state value to the first-in-first-out (FIFO) storage unit; or, the control unit is further configured to configure a second mask; the comparison unit is specifically configured to: perform a logical operation on the first state value and the second mask to obtain a new first state value; perform a logical operation on the second state value and the second mask to obtain a new second state value; compare the new first state value with the new second state value; if the new first state value is not equal to the new second state value, determine to send the first state value to the FIFO storage unit.

[0008] According to a specific implementation of an embodiment of this application, the system further includes: a status register access module, which is used to send an access request; and an arbitration unit, which is connected to the status register access module, the status value acquisition unit, and the target status register, respectively. Specifically, the status value acquisition unit is used to send an acquisition request to the arbitration unit. The arbitration unit is used to receive the acquisition request and the access request sent by the status register access module, and determine the order in which the acquisition request and the access request are sent to the target status register according to a preset arbitration strategy. When the arbitration unit sends the acquisition request to the target status register, the arbitration unit acquires the status value in the target status register and sends the status value to the status value acquisition unit. The status value acquisition unit is specifically used to receive the status value sent by the arbitration unit.

[0009] According to a specific implementation of an embodiment of this application, the arbitration unit is specifically used to, upon receiving the access request and the acquisition request, first send the access request to the target status register, and then send the acquisition request to the target status register.

[0010] According to a specific implementation of an embodiment of this application, the arbitration unit is further configured to associate the status value with the timestamp of acquiring the status value; wherein, the comparison unit is specifically configured to send the associated status value and the timestamp to the first-in-first-out (FIFO) storage unit; the FIFO storage unit is specifically configured to store the associated status value and the timestamp.

[0011] Secondly, embodiments of this application provide a method for obtaining register status values, including: configuring an identifier and a comparison mode for a target status register; sequentially obtaining status values ​​in the target status register at multiple times according to the identifier of the target status register; sequentially determining whether to send the status values ​​at multiple times to a first-in-first-out (FIFO) memory unit according to the comparison mode; and storing the status values ​​in the FIFO memory unit when it is determined that the status values ​​should be sent to the FIFO memory unit.

[0012] According to a specific implementation of an embodiment of this application, the state values ​​at multiple times include a first state value; wherein, the step of determining whether to send the state values ​​at multiple times to the first-in-first-out (FIFO) storage unit according to the comparison mode includes: determining whether to send the first state value to the FIFO storage unit based on the first state value and a first threshold; if yes, then determining to send the first state value to the FIFO storage unit; or, the step of determining whether to send the state values ​​at multiple times to the FIFO storage unit according to the comparison mode includes: determining whether to send the first state value to the FIFO storage unit based on the first state value and a second state value; the second state value is a state value that is adjacent to and precedes the first state value among the state values ​​at different times; if yes, then determining to send the first state value to the FIFO storage unit.

[0013] According to a specific implementation of an embodiment of this application, the method further includes: configuring a first mask; wherein, determining whether to send the first state value to the first-in-first-out (FIFO) storage unit based on the first state value and a first threshold includes: performing a logical operation on the first state value and the first mask to obtain a new first state value; comparing the new first state value with the first threshold; and determining that the first state value should be sent to the FIFO storage unit if the new first state value is not equal to the first threshold; or, the method further includes: configuring a second mask; wherein, determining whether to send the first state value to the FIFO storage unit based on the first state value and a second state value includes: performing a logical operation on the first state value and the second mask to obtain a new first state value; performing a logical operation on the second state value and the second mask to obtain a new second state value; comparing the new first state value with the new second state value; and determining that the first state value should be sent to the FIFO storage unit if the new first state value is not equal to the new second state value.

[0014] According to a specific implementation of an embodiment of this application, the step of sequentially acquiring the status value in the target status register at multiple times based on the identifier of the target status register includes: receiving an acquisition request and an access request; wherein the acquisition request includes the identifier of the target status register; determining the order in which the acquisition request and the access request are sent to the target status register according to a preset arbitration strategy; and acquiring the status value in the target status register when the acquisition request is sent to the target status register.

[0015] According to a specific implementation of an embodiment of this application, determining the order of sending the acquisition request and the access request to the target status register according to a preset arbitration strategy includes: first sending the access request to the target status register, and then sending the acquisition request to the target status register.

[0016] According to a specific implementation of an embodiment of this application, the state values ​​at multiple times include a third state value; after sequentially acquiring the state values ​​in the target state register at multiple times, the method further includes: associating the third state value with the timestamp of acquiring the third state value; wherein, when it is determined that the state value will be sent to the first-in-first-out (FIFO) storage unit, the FIFO storage unit stores the state value, including: when it is determined that the third state value will be sent to the FIFO storage unit, the FIFO storage unit stores the associated third state value and the timestamp.

[0017] This embodiment provides a method for obtaining processor chip and register status values. A status value acquisition unit sequentially acquires the status values ​​in a target status register at multiple times based on the configured identifier of the target status register. A comparison unit sequentially determines whether to send the status values ​​at multiple times to a first-in-first-out (FIFO) storage unit based on a configured comparison mode. The FIFO storage unit receives and stores the status values ​​sent by the comparison unit. Based on the status values ​​in the FIFO storage unit, it is convenient to analyze the changes in the processor chip system during the process of a problem occurring, thereby improving the performance of the processor chip. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a processor chip provided in an embodiment of this application; Figure 2 A flowchart illustrating a method for obtaining register status values ​​according to an embodiment of this application; Figure 3 This is a flowchart illustrating a method for obtaining register status values ​​according to a specific embodiment of this application. Detailed Implementation

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0022] Figure 1 This is a schematic diagram of the structure of a processor chip 1 provided in an embodiment of this application, as shown below. Figure 1As shown, the processor chip 1 in this embodiment may include: a status register 10, a control unit 11, a status value acquisition unit 12, a comparison unit 13, and a first-in-first-out (FIFO) storage unit 14; the status value acquisition unit 12 is connected to the control unit 11; the comparison unit 13 is connected to the control unit 11, the status value acquisition unit 12, and the FIFO storage unit 14 respectively; wherein, the control unit 11 is used to configure the identifier and comparison mode of the target status register; the status value acquisition unit 12 is used to sequentially acquire the status values ​​in the target status register at multiple times according to the identifier of the target status register; the comparison unit 13 is used to sequentially determine whether to send the status values ​​at multiple times to the FIFO storage unit 14 according to the comparison mode; the FIFO storage unit 14 is used to receive the status values ​​sent by the comparison unit 13 and store the status values.

[0023] Processor chip 1 can be a system-on-chip (SoC).

[0024] The status value in status register 10 can identify the status of the processor chip 1 system.

[0025] The number of status registers 10 can be one or more. When there is only one status register 10, the target status register is that status register 10; when there are multiple status registers 10, the target status register can be some or all of the multiple status registers 10.

[0026] When there are multiple target status registers, the status value of each target status register can be distinguished, for example, by adding an identifier to the status value of each target status register.

[0027] In this embodiment, an identifier for the target status register can be configured in the control unit 11. The identifier of the target status register can be the address of the target status register. In order to obtain the status value of any status register 10, the configured identifier of the target status register can be modified, and the modified status value of the target status register can be stored. An enable signal can also be configured in the control unit 11. Based on the enable signal, the status value acquisition unit 12 issues an acquisition request.

[0028] The status value acquisition unit 12 can obtain the identifier of the configured target register from the control unit 11, and based on the identifier, can obtain multiple status values ​​from the target register in real time at multiple times. For example, the status value acquisition unit 12 can obtain status values ​​from the target status register according to the reading time interval configured in the control unit.

[0029] The comparison unit 13 can obtain the configured comparison mode from the control unit 11, and determine which state values ​​among the multiple time-space state values ​​to be sent to the first-in-first-out storage unit 14 and which state values ​​do not need to be sent to the first-in-first-out storage unit 14 according to the comparison mode.

[0030] The state value that is first stored (added) in the first-in, first-out (FIFO) storage unit 14 will also be the first to be retrieved (removed).

[0031] The state value in the first-in-first-out storage unit 14 can be sent to memory to save the state value in memory, or it can be sent to other external interfaces of the processor chip 1, such as Universal Asynchronous Receiver / Transmitter (UART) or Serial Peripheral Interface (SPI), so as to facilitate the transmission of the state value outside the processor chip 1.

[0032] When the state value in the first-in-first-out (FIFO) storage unit 14 can be sent to memory, memory has latency. Due to the configuration of the FIFO storage unit 14, data that cannot be written to memory in time can be cached in the FIFO storage unit 14 first.

[0033] The FIFO (First-In-First-Out) storage unit 14 has several states, such as FIFO empty, FIFO almost full, and FIFO overflow. The control unit 11 controls the status value acquisition unit based on the state of the FIFO storage unit 14 to prevent FIFO overflow. If the FIFO is full, the control unit 11 notifies the status value acquisition unit 12 to pause acquiring status values, thus preventing data loss.

[0034] In some examples, the FIFO storage unit 14 can be controlled by the control unit 11 to read status values ​​from the FIFO storage unit 14; the control unit 11 can also clear the status values ​​in the FIFO storage unit 14. For example, when it is necessary to retrieve status values ​​again, the FIFO can be cleared by the control unit; if the data channel from the FIFO to memory is stuck, the status values ​​in the FIFO can also be read directly for viewing.

[0035] After a problem occurs in the processor chip 1 system, the changes in the processor chip 1 system before, during, and after the problem can be analyzed based on the status values ​​in the first-in-first-out (FIFO) memory unit 14 or the status values ​​stored in memory. For example, when the CPU hangs, the values ​​of some key CPU registers can be saved to the FIFO for problem analysis.

[0036] In this embodiment, the status value acquisition unit 12 acquires the status values ​​in the target status register sequentially at multiple times according to the configured identifier of the target status register. The comparison unit 13 determines sequentially whether to send the status values ​​at multiple times to the first-in-first-out (FIFO) storage unit 14 according to the configured comparison mode. The FIFO storage unit 14 receives the status values ​​sent by the comparison unit 13 and stores the status values. In this way, based on the status values ​​in the FIFO storage unit 14, it is convenient to analyze the changes in the processor chip 1 system before, during, and after the problem occurs when the processor chip 1 system has a problem. Based on the analysis, the design of the processor chip 1 can be optimized and the performance of the processor chip 1 can be improved.

[0037] The comparison mode used to determine whether to send the state values ​​at multiple times to the first-in-first-out storage unit 14 can include multiple modes in a specific implementation. For example, each acquired state value can be compared with a threshold, or the acquired state value can be compared with adjacent state values. The specific mode adopted can be customized according to the characteristics of the target state register.

[0038] As an optional implementation, the state values ​​at multiple times include a first state value; wherein, the comparison unit 13 is specifically used to: determine whether to send the first state value to the first-in-first-out storage unit 14 based on the first state value and a first threshold; if so, determine to send the first state value to the first-in-first-out storage unit 14.

[0039] The first state value can be any of the state values ​​at multiple times.

[0040] In this embodiment, the first threshold can be configured in the control unit 11. The comparison unit 13 can obtain the first threshold from the control unit 11.

[0041] When determining whether to send the first state value to the first-in-first-out storage unit 14 based on the first state value and the first threshold, the first state value and the first threshold can be compared. If they are not equal, the first state value is sent to the first-in-first-out storage unit 14; if they are equal, the first state value is not sent to the first-in-first-out storage unit 14, that is, the first state value is not stored.

[0042] The state value of the target register contains some bits with values ​​of 0 or 1, and the changes in these bits do not represent the state of the processor chip 1 system. That is, in this application, the values ​​of these state bits and their changes are not important. In order to reduce the number of bits compared each time, in one embodiment, the control unit 11 is also used to configure a first mask; the comparison unit 13 is specifically used to: perform a logical operation on the first state value and the first mask to obtain a new first state value; compare the new first state value with a first threshold; if the new first state value is not equal to the first threshold, then determine to send the first state value to the first-in-first-out storage unit 14.

[0043] The first mask can be set for bits that are not important or need to be masked. For example, if bit mask = 0xFF, then the value changes of bits [7:0] will be ignored, and even if the value of [7:0] changes, the first state value will not be written to the first-in-first-out storage unit 14.

[0044] Through logical operations, a specified bit in the first state value can be masked, and the unmasked bits in the first state value can be compared with a first threshold.

[0045] The first threshold can be determined based on the specific definition of the register to be captured. For example, in the status register, the [1:0] bits of the status value, where 00 represents the normal state, 01 represents the abnormal state, and 10 represents another state, can be used to determine the first threshold as 00. That is, the first threshold can be the value of the target bit of the status value that represents the normal state. The target bit is the bit that is retained after performing a logical operation between the first status value and the first mask.

[0046] As an alternative implementation, the state values ​​at multiple times include a first state value; the comparison unit 13 is specifically used to: determine whether to send the first state value to the first-in-first-out storage unit 14 based on the first state value and the second state value; the second state value is the state value that is adjacent to the first state value and precedes the first state value among the state values ​​at different times; if so, determine to send the first state value to the first-in-first-out storage unit 14.

[0047] When determining whether to send the first state value to the first-in-first-out storage unit 14 based on the first state value and the second state value, the first state value and the second state value can be compared. If they are not equal, the first state value is sent to the first-in-first-out storage unit 14; if they are equal, the first state value is not sent to the first-in-first-out storage unit 14, that is, the first state value is not stored.

[0048] Similar to the previous embodiments, specified bits in the status value of the target register can be masked, thereby reducing the number of bits compared each time. In one embodiment, the control unit 11 is also used to configure a second mask; the comparison unit 13 is specifically used to: perform a logical operation on the first status value and the second mask to obtain a new first status value; perform a logical operation on the second status value and the second mask to obtain a new second status value; compare the new first status value with the new second status value; if the new first status value and the new second status value are not equal, then determine that the first status value is sent to the first-in-first-out storage unit 14.

[0049] The second mask can be the same as the first mask, or it can be different from the first mask.

[0050] Through logical operations, specified bits in the first state value and specified bits in the second state value can be masked to obtain new first state value and new second state value, respectively.

[0051] If the new first state value and the new second state value are not equal, it indicates that the state value has changed, and the first state value can be sent to the first-in-first-out storage unit 14.

[0052] In some examples, during the operation of processor chip 1, the core or other IP modules in processor chip 1 may access the target status register. The status value acquisition unit 12 may also send an acquisition request to obtain the status value of the target register. To avoid conflicts, the processor chip 1 in this embodiment may further include: a status register access module (not shown in the figure) and an arbitration unit 15. The arbitration unit 15 is connected to the status register access module, the status value acquisition unit 12, and the target status register, respectively.

[0053] In this embodiment, the status register access module is used to send an access request; the status value acquisition unit 12 is specifically used to send an acquisition request to the arbitration unit 15; the arbitration unit 15 is used to receive the acquisition request and the access request sent by the status register access module, and determine the order in which the acquisition request and the access request are sent to the target status register according to a preset arbitration strategy; when the arbitration unit 15 sends an acquisition request to the target status register, the arbitration unit 15 acquires the status value in the target status register; and sends the status value to the status value acquisition unit 12; the status value acquisition unit 12 is specifically used to receive the status value sent by the arbitration unit 15.

[0054] like Figure 1 In the embodiment shown, the status register access module can be connected to the arbitration unit 15 through the register access interface 16.

[0055] When arbitration unit 15 receives both an acquisition request from status value acquisition unit 12 and an access request from status register access module, according to a preset arbitration strategy, it can first send an acquisition request to the target status register, and then send an access request to the target status register. To avoid affecting normal access to the target status register within processor chip 1, in some examples, upon receiving both an access request and an acquisition request, the access request is sent to the target status register first, followed by the acquisition request.

[0056] In this embodiment, normal register access has high priority, and a request can only access the target status register when the bus is idle. The register access bus can be flexibly customized according to the bus actually used by the status register, such as the APB bus or the AXI bus.

[0057] In this embodiment, the arbitration unit 15 serves both as an arbitration unit and as a function to forward the status value of the target register.

[0058] To facilitate subsequent tracing of the time when the state value stored in the first-in-first-out (FIFO) storage unit 14 was generated, in some examples, the arbitration unit 15 is also used to associate the state value with the timestamp of the acquired state value; wherein, the comparison unit 13 is specifically used to send the associated state value and the timestamp to the FIFO storage unit 14; the FIFO storage unit 14 is specifically used to store the associated state value and the timestamp.

[0059] Understandably, associating the status value with the timestamp can also be performed by comparison unit 13.

[0060] In addition to determining whether to send the state value to the FIFO storage unit 14 based on the comparison mode, the comparison unit 13, in order to more flexibly determine whether to execute the above process, in some examples, before sequentially determining whether to send the state values ​​at multiple times to the FIFO storage unit 14 according to the comparison mode, for each received state value, the comparison unit 13 is also used to determine whether to execute the step of determining whether to send the state value to the FIFO storage unit 14 according to the comparison mode based on a preset comparison trigger condition and the state value. For example, if the state value meets the comparison trigger condition, the step of determining whether to send the state value to the FIFO storage unit 14 according to the comparison mode is executed.

[0061] In a specific example, the comparison unit 13 is specifically used to perform logical operations on the state value and the third mask to obtain a new state value, and compare the new state value with the second threshold. If the new state value is consistent with the second threshold, it is then determined whether to send the state value to the first-in-first-out storage unit 14 according to the comparison mode.

[0062] In some examples, if the new status value matches the second threshold, for each received status value, the comparison unit 13 is further configured to determine, based on a preset comparison termination condition and the status value, whether to send the status value to the first-in-first-out (FIFO) storage unit 14 according to the comparison mode. For example, if the status value does not meet the comparison termination condition, the step of determining whether to send the status value to the FIFO storage unit 14 according to the comparison mode is executed; if the status value meets the comparison termination condition, the step of determining whether to send the status value to the FIFO storage unit 14 according to the comparison mode is not executed, and the status value is directly written to the FIFO storage unit 14; the status value acquisition unit 12 is notified to end reading the status value of the target status register.

[0063] In a specific example, the comparison unit 13 is specifically used to perform logical operations on the state value and the fourth mask to obtain a new state value, and compare the new state value with the third threshold; if the new state value is inconsistent with the third threshold, then determine whether to send the state value to the first-in-first-out storage unit 14 according to the comparison mode.

[0064] For example, in the status register, the [1:0] bit value is 00, which indicates a normal state; 01 indicates an abnormal state; and 10 indicates another state. In this case, the second threshold can be 01, and the third threshold can be 10. That is, when the [1:0] bit is 01, the capture starts; when the [1:0] bit is 10, the capture ends.

[0065] In a specific implementation, the comparison unit 13 may include a first comparator, a second comparator, and a third comparator connected in series. The first comparator receives the state value sent by the state value acquisition unit 12, performs a logical operation on the state value and a third mask to obtain a new state value, and compares the new state value with a second threshold. If they match, the state value is sent to the second comparator, which performs a logical operation on the state value and a fourth mask to obtain a new state value, and compares the new state value with the third threshold. If they do not match, the state value is sent to the third comparator, which determines whether to send the state value to the first-in-first-out (FIFO) storage unit 14 based on the comparison mode. If they match, the state value is sent to the FIFO storage unit 14.

[0066] In some cases, the functionality of the first and second comparators can be disabled.

[0067] The second and third thresholds in the above embodiments can be configured in the control unit 11. The third and fourth masks can also be configured in the control unit 11, thus enabling more flexible configuration of the second threshold, third threshold, third mask, and fourth mask.

[0068] Specifically, two sets of registers can be set in the control unit 11 to store the data registers for the start and end of the comparison (trigger). The start and end comparison conditions can be disabled through register configuration. When disabled, the control unit, status value acquisition unit, comparison unit, and first-in-first-out storage unit module will all be in the working state.

[0069] Figure 2 This is a flowchart illustrating a method for obtaining register status values ​​according to an embodiment of this application, as shown below. Figure 2 As shown, the register status value acquisition method of this embodiment may include: S101. Configure the identifier and comparison mode of the target status register.

[0070] In this embodiment, the target status register can be a register in the processor chip. There can be one or more target status registers.

[0071] In order to obtain the status value of any status register, the identifier of the configured target status register can be modified, and the modified status value of the target status register can be stored.

[0072] S102. Based on the identifier of the target status register, sequentially obtain the status values ​​in the target status register at multiple times.

[0073] The identifier of the target status register can be the address of the target status register.

[0074] In some cases, an enable signal can also be configured. In response to this enable signal, the status value in the target status register is sequentially acquired at multiple times based on the identifier of the target status register.

[0075] S103. Based on the comparison mode, determine in turn whether to send the status values ​​at multiple times to the first-in-first-out storage unit.

[0076] Based on the comparison mode, determine which state values ​​from multiple time points are sent to the first-in-first-out (FIFO) memory unit and which state values ​​do not need to be sent to the FIFO memory unit.

[0077] The state value that is stored (added) first in the first-in, first-out (FIFO) storage unit will also be retrieved (removed) first.

[0078] In one embodiment, a read time interval can be configured to retrieve status values ​​from the target status register at this interval. Alternatively, a status value retrieval request can be issued at this time interval.

[0079] S104. If it is determined that the status value will be sent to the first-in-first-out (FIFO) storage unit, the FIFO storage unit stores the status value.

[0080] The state values ​​in the first-in-first-out (FIFO) storage unit can be sent to memory to be stored in memory, or sent to other external interfaces of the processor chip, such as Universal Asynchronous Receiver / Transmitter (UART) or Serial Peripheral Interface (SPI), thus facilitating the transmission of state values ​​outside the processor chip.

[0081] After a processor chip system malfunctions, the changes in the processor chip system before, during, and after the problem can be analyzed based on the state values ​​in the first-in-first-out (FIFO) memory or the state values ​​stored in memory.

[0082] In this embodiment, based on the identifier of the configured target status register, the status values ​​in the target status register are sequentially acquired at multiple times. Then, based on the comparison mode, it is determined whether to send the status values ​​at multiple times to the first-in-first-out (FIFO) memory unit. If it is determined that the status values ​​will be sent to the FIFO memory unit, the FIFO memory unit stores the status values. In this way, based on the status values ​​in the FIFO memory unit, it is convenient to analyze the changes in the processor chip system before, during, and after the problem occurs when the processor chip system has problems. Based on the analysis, the processor chip design can be optimized and the performance of the processor chip can be improved.

[0083] The comparison mode used to determine whether to send the state values ​​at multiple times to the first-in-first-out (FIFO) storage unit can include various modes in a specific implementation. For example, each acquired state value can be compared with a threshold, or the acquired state value can be compared with adjacent state values. As an optional implementation, the state values ​​at multiple times include a first state value.

[0084] In this embodiment, determining whether to send the state values ​​at multiple times to the first-in-first-out storage unit according to the comparison mode (S103) may include: S103a. Based on the first state value and the first threshold, determine whether to send the first state value to the first-in-first-out storage unit.

[0085] The first state value can be any of the state values ​​at multiple times.

[0086] The first threshold in this embodiment can be obtained through configuration; that is, before this step, the first threshold is configured.

[0087] S103b If yes, then determine to send the first state value to the first-in-first-out storage unit.

[0088] When determining whether to send the first state value to the first-in-first-out (FIFO) storage unit based on the first state value and the first threshold, the first state value and the first threshold can be compared. If they are not equal, the first state value is sent to the FIFO storage unit; if they are equal, the first state value is not sent to the FIFO storage unit, that is, the first state value is not stored.

[0089] The status value of the target register contains some bits that are 0 or 1, and the changes in these bits do not necessarily indicate the status of the processor chip system. Therefore, this application does not require concern about the values ​​of these status bits or their changes. To reduce the number of bits compared each time, in one embodiment, the method may further include: S105, Configure the first mask.

[0090] The first mask can be set for bits that are not important or need to be masked. For example, if bit mask = 0xFF, then the value changes of bits [7:0] will be ignored, and even if the value of [7:0] changes, the first state value will not be written to the first-in-first-out storage unit.

[0091] The step of determining whether to send the first state value to the first-in-first-out memory unit based on the first state value and the first threshold (S103a) may include: A1. Perform a logical operation between the first state value and the first mask to obtain a new first state value.

[0092] Through logical operations, it is possible to mask specific bits in the first state value.

[0093] A2. Compare the new first state value with the first threshold.

[0094] A3. If the new first state value is not equal to the first threshold, then determine to send the first state value to the first-in-first-out storage unit.

[0095] As an alternative implementation, the state values ​​at multiple times include a first state value.

[0096] In this embodiment, determining whether to send the state values ​​at multiple times to the first-in-first-out storage unit according to the comparison mode (S103) may include: S103c: Based on the first state value and the second state value, determine whether to send the first state value to the first-in-first-out storage unit.

[0097] The second state value is the state value that is adjacent to the first state value and precedes the first state value among the state values ​​at different times.

[0098] When determining whether to send the first state value to the first-in-first-out (FIFO) storage unit based on the first state value and the second state value, the first state value and the second state value can be compared. If they are not equal, the first state value is sent to the FIFO storage unit; if they are equal, the first state value is not sent to the FIFO storage unit, that is, the first state value is not stored.

[0099] S103d If yes, then determine to send the first state value to the first-in-first-out storage unit.

[0100] Similar to the foregoing embodiments, specified bits in the status value of the target register can be masked, thereby reducing the number of bits compared each time. In one embodiment, the method may further include: S106, Configure the second mask.

[0101] The second mask can be the same as the first mask, or it can be different from the first mask.

[0102] The step of determining whether to send the first state value to the first-in-first-out memory unit based on the first state value and the second state value (S103c) may include: B1. Perform a logical operation between the first state value and the second mask to obtain a new first state value.

[0103] Through logical operations, a specified bit in the first state value can be masked to obtain a new first state value and a new second state value.

[0104] B2. Perform a logical operation between the second state value and the second mask to obtain a new second state value.

[0105] By performing logical operations, a specified bit in the second state value can be masked to obtain a new second state value.

[0106] B3. Compare the new first state value with the new second state value.

[0107] B4. If the new first state value is not equal to the new second state value, then the first state value is determined to be sent to the first-in-first-out storage unit.

[0108] If the new first state value and the new second state value are not equal, it means that the state value has changed, and the first state value can be sent to the first-in-first-out storage unit.

[0109] In some examples, during the operation of the processor chip, the core or other IP modules in the processor chip access the target status register, and the status value acquisition unit also sends an acquisition request to obtain the status value of the target register. To avoid conflicts, in some embodiments, the status value in the target status register is acquired sequentially at multiple times according to the identifier of the target status register (S102), which may include: S102a, Receive an acquisition request and an access request; wherein, the acquisition request includes the identifier of the target status register.

[0110] S102b: Determine the order in which to send the acquisition request and access request to the target status register according to the preset arbitration strategy.

[0111] When both a status value acquisition unit and a status register access module are received, according to the preset arbitration strategy, a acquisition request can be sent to the target status register first, followed by an access request.

[0112] To avoid affecting the processor chip's normal access to the target status register, in some examples, the order of sending the acquisition request and access request to the target status register is determined according to a preset arbitration strategy (S102b), which may include: C1. First, send an access request to the target status register, then send an acquisition request to the target status register.

[0113] In this embodiment, normal register access has high priority, and a request can only access the target status register when the bus is idle. The register access bus can be flexibly customized according to the bus actually used by the status register, such as the APB bus or the AXI bus.

[0114] S102c: When a request to acquire is sent to the target status register, acquire the status value in the target status register.

[0115] To facilitate subsequent tracing of the time when the state value stored in the first-in-first-out (FIFO) memory unit was generated, in some examples, the state values ​​at multiple times include a third state value; after sequentially acquiring the state values ​​in the target state register at multiple times (S102), the method of this embodiment may further include: S107. Associate the third state value with the timestamp of the third state value acquisition.

[0116] Wherein, when it is determined that the state value will be sent to the first-in-first-out (FIFO) storage unit, the FIFO storage unit stores the state value (S104), which may include: S104a. If it is determined that the third state value will be sent to the first-in-first-out (FIFO) storage unit, the FIFO storage unit stores the associated third state value and timestamp.

[0117] In some examples, the state values ​​at multiple time points include a fourth state value; the method further includes, before determining sequentially whether to send the state values ​​at multiple time points to the first-in-first-out memory unit according to the comparison mode: Based on the preset comparison trigger conditions and the fourth state value, determine whether to execute the step of determining whether to send the state value to the first-in-first-out memory unit according to the comparison mode.

[0118] If the fourth state value meets the comparison trigger condition, then the step of determining whether to send the state value to the first-in-first-out (FIFO) memory unit based on the comparison mode is executed; otherwise, the step of determining whether to send the state value to the FIFO memory unit based on the comparison mode is not executed.

[0119] In a specific example, determining whether to execute the step of deciding whether to send the state value to the first-in-first-out memory unit based on the preset comparison trigger condition and the fourth state value includes: Perform a logical operation between the fourth state value and the third mask to obtain a new state value; Compare the new state value with the second threshold; If the new state value matches the second threshold, then the step of determining whether to send the state value to the first-in-first-out memory unit is executed based on the comparison mode.

[0120] If the new state value is inconsistent with the second threshold, the step of determining whether to send the state value to the first-in-first-out memory unit based on the comparison mode is not performed.

[0121] In some examples, if the new state value matches the second threshold, the step of determining whether to send the state value to the first-in-first-out memory unit based on the comparison mode is performed, including: If the new state value matches the second threshold, then based on the preset comparison termination condition and the state value, it is determined whether to execute the step of determining whether to send the state value to the first-in-first-out storage unit according to the comparison mode.

[0122] If the status value does not meet the comparison termination condition, the step of determining whether to send the status value to the first-in-first-out (FIFO) memory unit based on the comparison mode is executed; if the status value meets the comparison termination condition, the step of determining whether to send the status value to the FIFO memory unit based on the comparison mode is not executed, and the status value is directly written to the FIFO memory unit.

[0123] In a specific example, if the new state value matches the second threshold, then based on a preset comparison termination condition and the state value, it is determined whether to execute the step of determining whether to send the state value to the first-in-first-out (FIFO) memory unit according to the comparison mode, including: Perform a logical operation between the state value and the fourth mask to obtain a new state value; Compare the new state value with the third threshold; If the new state value is inconsistent with the third threshold, then the step of determining whether to send the state value to the first-in-first-out memory unit is executed according to the comparison mode.

[0124] If the new state value matches the third threshold, the state value is sent to the first-in-first-out (FIFO) storage unit.

[0125] The second threshold, third threshold, third mask, and fourth mask in the above embodiments can be obtained through configuration, that is, the method further includes configuring the second threshold, third threshold, third mask, and fourth mask.

[0126] See Figure 1 and Figure 3 The technical solution of this application will be described below by way of a specific embodiment.

[0127] Step 1: Configure the target status register address, start comparison condition, end comparison condition, first threshold, third mask, and fourth mask.

[0128] The start comparison condition can be setting a second threshold in register a of control unit 11, and the end comparison condition can be setting a third threshold in register b of control unit 11.

[0129] Step 2: Obtain the status value.

[0130] The control unit 11 notifies the status value acquisition unit 12 to send an acquisition request. After acquiring the status, the status value acquisition unit 12 sends the status value to the comparison unit 13.

[0131] Step 3: Determine if there are any conditions for starting the comparison.

[0132] Determine whether a start comparison condition is configured in control unit 11; specifically, determine whether a second threshold is stored in register a.

[0133] This step can be performed by the first comparator of the comparison unit 13.

[0134] Step 4: Determine whether the conditions for starting the comparison are met.

[0135] Perform a logical operation between the state value and the third mask to obtain a new state value. Compare the new state value with the second threshold. If they are equal, proceed to step 5; otherwise, return to step 2.

[0136] This step can be performed by the first comparator of the comparison unit 13.

[0137] Step 5: Determine if there is a termination comparison condition.

[0138] Determine whether an end comparison condition is configured in control unit 11; specifically, determine whether a third threshold is stored in register b.

[0139] This step can be performed by the second comparator of the comparison unit 13.

[0140] Step 6: Determine whether the end comparison condition is met.

[0141] Perform a logical operation between the state value and the fourth mask to obtain a new state value. Compare the new state value with the third threshold. If they are equal, stop working; otherwise, return to step 7.

[0142] This step can be performed by the second comparator of the comparison unit 13.

[0143] Step 7: Determine whether the status value needs to be sent to the FIFO.

[0144] If a status value needs to be sent to the FIFO, then send the status value to the FIFO; otherwise, return to step 2.

[0145] This step can be performed by the third comparator of comparison unit 13.

[0146] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0147] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0148] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A processor chip, characterized in that, include: Status register; A control unit, which is used to configure the identifier and comparison mode of the target status register; A status value acquisition unit is connected to the control unit; the status value acquisition unit is used to sequentially acquire the status value in the target status register at multiple times according to the identifier of the target status register. A comparison unit, which is connected to the control unit and the status value acquisition unit respectively, is used to determine, according to the comparison mode, whether to send the status values ​​at multiple times to the first-in-first-out storage unit. The first-in-first-out storage unit is connected to the comparison unit and is used to receive the status value sent by the comparison unit and store the status value. The state values ​​at multiple times include a first state value; the comparison unit is specifically used for: Based on the first state value and the first threshold, determine whether to send the first state value to the first-in-first-out (FIFO) memory unit; if yes, determine whether to send the first state value to the FIFO memory unit; or, The comparison unit is specifically used to: determine whether to send the first state value to the first-in-first-out storage unit based on the first state value and the second state value; the second state value is the state value that is adjacent to the first state value and precedes the first state value among the state values ​​at different times; if so, determine to send the first state value to the first-in-first-out storage unit.

2. The processor chip according to claim 1, characterized in that, The control unit is also configured to configure the first mask; the comparison unit is specifically configured to: Perform a logical operation between the first state value and the first mask to obtain a new first state value; The new first state value is compared with the first threshold. If the new first state value is not equal to the first threshold, then it is determined that the first state value will be sent to the first-in-first-out storage unit; or, The control unit is also configured to configure a second mask; the comparison unit is specifically configured to: Perform a logical operation between the first state value and the second mask to obtain a new first state value; Perform a logical operation between the second state value and the second mask to obtain a new second state value; Compare the new first state value with the new second state value; If the new first state value is not equal to the new second state value, then the first state value is determined to be sent to the first-in-first-out storage unit.

3. The processor chip according to claim 1, characterized in that, Also includes: A status register access module, which is used to send access requests; An arbitration unit is connected to the status register access module, the status value acquisition unit, and the target status register, respectively. Specifically, the status value acquisition unit is used to send an acquisition request to the arbitration unit; The arbitration unit is used to receive the acquisition request and the access request sent by the status register access module, and to determine the order in which the acquisition request and the access request are sent to the target status register according to a preset arbitration strategy. When the arbitration unit sends the acquisition request to the target status register, the arbitration unit acquires the status value in the target status register and sends the status value to the status value acquisition unit. The status value acquisition unit is specifically used to receive the status value sent by the arbitration unit.

4. The processor chip according to claim 3, characterized in that, The arbitration unit is specifically used to, upon receiving the access request and the acquisition request, first send the access request to the target status register, and then send the acquisition request to the target status register.

5. The processor chip according to claim 3, characterized in that, The arbitration unit is also used to associate the status value with the timestamp of the status value being acquired. Specifically, the comparison unit is used to send the associated state value and the timestamp to the first-in-first-out storage unit; The first-in-first-out (FIFO) storage unit is specifically used to store the associated state value and the timestamp.

6. A method for obtaining register status values, characterized in that, include: Configure the identifier and comparison mode of the target status register; Based on the identifier of the target status register, the status values ​​in the target status register are sequentially acquired at multiple times. Based on the comparison mode, it is determined sequentially whether to send the state values ​​at multiple times to the first-in-first-out storage unit; If it is determined that the status value will be sent to the first-in-first-out (FIFO) storage unit, the FIFO storage unit stores the status value; The state values ​​at multiple times include a first state value; the step of determining whether to send the state values ​​at multiple times to the first-in-first-out (FIFO) storage unit according to the comparison mode includes: determining whether to send the first state value to the FIFO storage unit based on the first state value and a first threshold; if so, determining to send the first state value to the FIFO storage unit; or, The step of determining whether to send the state values ​​at multiple times to the first-in-first-out (FIFO) storage unit according to the comparison mode includes: determining whether to send the first state value to the FIFO storage unit based on the first state value and the second state value; the second state value is the state value that is adjacent to the first state value and precedes the first state value among the state values ​​at different times; if so, determining to send the first state value to the FIFO storage unit.

7. The method according to claim 6, characterized in that, The method further includes: Configure the first mask; The step of determining whether to send the first state value to the first-in-first-out storage unit based on the first state value and the first threshold includes: Perform a logical operation between the first state value and the first mask to obtain a new first state value; The new first state value is compared with the first threshold. If the new first state value is not equal to the first threshold, then it is determined that the first state value will be sent to the first-in-first-out storage unit; or, The method further includes: Configure a second mask; The step of determining whether to send the first state value to the first-in-first-out (FIFO) memory unit based on the first state value and the second state value includes: Perform a logical operation between the first state value and the second mask to obtain a new first state value; Perform a logical operation between the second state value and the second mask to obtain a new second state value; Compare the new first state value with the new second state value; If the new first state value is not equal to the new second state value, then the first state value is determined to be sent to the first-in-first-out storage unit.

8. The method according to claim 6, characterized in that, The step of sequentially acquiring the state value in the target state register at multiple times based on the identifier of the target state register includes: Receive an acquisition request and an access request; wherein the acquisition request includes the identifier of the target status register; According to the preset arbitration strategy, the order in which the acquisition request and the access request are sent to the target status register is determined. When the acquisition request is sent to the target status register, the status value in the target status register is acquired.

9. The method according to claim 8, characterized in that, Determining the order in which the acquisition request and the access request are sent to the target status register according to a preset arbitration strategy includes: First, send the access request to the target status register, and then send the acquisition request to the target status register.

10. The method according to claim 6, characterized in that, The state values ​​at multiple moments include a third state value; After sequentially acquiring the state values ​​in the target state register at multiple times, the method further includes: Associate the third state value with the timestamp at which the third state value was obtained; Wherein, when it is determined that the state value will be sent to the first-in-first-out (FIFO) storage unit, the FIFO storage unit stores the state value, including: If it is determined that the third state value will be sent to the first-in-first-out (FIFO) storage unit, the FIFO storage unit stores the associated third state value and the timestamp.

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