Multibus configurable DMA system, microcontroller and computer device

Abstract

The application discloses a multi-bus configurable DMA system, a microcontroller and computer equipment, and belongs to the technical field of semiconductors. The multi-bus configurable DMA system comprises a DMA module, at least two groups of bus matrices of different types and a peripheral subsystem; the at least two groups of bus matrices of different types comprise a first-type bus matrix and a second-type bus matrix; the peripheral subsystem is coupled with the second-type bus matrix; and the DMA module is coupled with the first-type bus matrix and the second-type bus matrix respectively. The application realizes direct data transmission between the DMA module and peripherals via the second-type bus matrix in a direct connection mode of the DMA module and the at least two groups of bus matrices of different types, that is, data transmission between the DMA module and the peripherals, and the conversion process from the first-type bus matrix to the second-type bus matrix is no longer needed, so that access path delay and control complexity are significantly reduced, and the real-time performance of the system is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a multi-bus configurable DMA system, a microcontroller, and a computer device. Background Technology

[0002] In microcontroller (MCU) design, a hierarchical bus architecture is typically used to interconnect modules. The global high-speed data path mainly uses the Advanced eXtensible Interface (AXI) bus, while peripherals are connected to the Advanced High-performance Bus (AHB) or the Advanced Peripheral Bus (APB) according to their performance differences.

[0003] In this architecture, data transfers initiated by the Direct Memory Access (DMA) module, regardless of whether the target is memory or a peripheral device, must pass through the AXI bus matrix. When accessing memory, the DMA module can directly complete the data transfer through the AXI bus matrix; when accessing peripheral devices, the data must first enter the AXI bus matrix, then be converted to the AHB or APB protocol step by step through the bus bridge, and finally complete the data transfer through the AHB or APB bus matrix. Although this path achieves interconnection unification, it increases the latency and complexity of peripheral access. In addition, the continuous data transfers initiated by the DMA module will continuously occupy the bandwidth of the AXI bus matrix, affecting the bus efficiency of the Central Processing Unit (CPU) and other master devices, thereby reducing the overall system performance. Summary of the Invention

[0004] This application provides a multi-bus configurable DMA system, a microcontroller, and a computer device. By directly connecting the DMA to multiple bus matrices, it achieves direct data transfer between the DMA and peripherals via a second-type bus matrix. That is, data transfer between the DMA and peripherals no longer requires a conversion process from a first-type bus matrix to a second-type bus matrix, thus significantly reducing access path latency and control complexity. The technical solution is as follows: Firstly, a multi-bus configurable DMA system is provided, including: Direct Memory Access (DMA) module, at least two different types of bus matrices, and peripheral subsystems; The at least two sets of bus matrices of different types include: The first type of bus matrix is ​​configured for system-oriented transmission; The second type of bus matrix is ​​configured to be accessed from peripherals. The peripheral subsystem is coupled to the second type of bus matrix; The DMA module is coupled to the first type of bus matrix and the second type of bus matrix respectively; The DMA module is configured to: select the first type of bus matrix to perform the system transfer, or select the second type of bus matrix to access the peripheral subsystem, depending on the type of bus matrix required during data access.

[0005] In one possible implementation, the DMA module includes a channel configuration register, a DMA control unit, a first cache unit, and at least two sets of different types of bus interfaces, wherein the at least two sets of different types of bus interfaces correspond one-to-one with the at least two sets of different types of bus matrices. The channel configuration register is configured to configure the type of bus matrix required during data access. The channel configuration register is coupled to the DMA control unit and the first cache unit respectively. The DMA control unit, the channel configuration register, and the first cache unit are coupled to the at least two sets of different types of bus interfaces respectively. The at least two sets of different types of bus interfaces are coupled to the corresponding bus matrix respectively. The DMA control unit is configured to: in conjunction with the first cache unit, select the first type of bus matrix to perform the system transmission, or select the second type of bus matrix to access the peripheral subsystem, based on the type of bus matrix configured in the channel configuration register.

[0006] In one possible implementation, the first cache unit is a cache unit whose write clock and read clock are the same clock, the clock of the second type of bus interface is different from the main clock of the DMA module, and the second type of bus interface is the bus interface corresponding to the second type of bus matrix. The second type of bus interface includes a second cache unit and a conversion control unit. The second cache unit is coupled to the first cache unit and the conversion control unit, respectively. The conversion control unit is also coupled to the channel configuration register and the DMA control unit, respectively.

[0007] In one possible implementation, the channel configuration register is coupled to the second type of bus matrix.

[0008] In one possible implementation, the first type of bus matrix includes an Advanced Extensible Interface (AXI) bus matrix, and the second type of bus matrix includes a first peripheral bus and a second peripheral bus, wherein the peripheral accessed by the first peripheral bus has a higher rate than the peripheral accessed by the second peripheral bus.

[0009] In one possible implementation, the first peripheral bus is an Advanced High Performance Bus (AHB) bus matrix, and the second peripheral bus is an Advanced Peripheral Bus (APB) bus matrix.

[0010] In a second aspect, a microcontroller is provided, the microcontroller including a multi-bus configurable DMA system.

[0011] In one possible implementation, the microcontroller further includes a processor interface coupled to the first type of bus matrix.

[0012] In one possible implementation, the microcontroller further includes a memory coupled to the first type of bus matrix.

[0013] Thirdly, a computer device is provided, the computer device including the microcontroller provided in the second aspect.

[0014] The multi-bus configurable DMA system provided in this application includes a DMA module, at least two sets of bus matrices of different types, and a peripheral subsystem. The at least two sets of bus matrices of different types include a first type of bus matrix and a second type of bus matrix. The DMA module is directly connected to each of the at least two sets of bus matrices of different types, meaning the DMA module can directly access peripherals through the second type of bus matrix. In other words, when accessing peripherals, the DMA module no longer needs to go through the conversion process from the first type of bus matrix to the second type of bus matrix, thereby significantly reducing access path latency and control complexity. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a microcontroller provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a DMA module provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a second type of bus interface provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an AHB bus interface provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an APB bus interface provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0018] In MCU design, a hierarchical bus architecture is typically used to achieve efficient interconnection between the processor, memory, and various peripherals. This architecture divides the system bus into different levels based on module performance, data throughput, and access frequency, and defines corresponding protocol types for each level. The global high-speed data path primarily uses an AXI bus matrix to carry high-bandwidth, low-latency transmission between the processor, DMA modules, and memory. Peripherals are connected to different bus matrices based on their performance differences. For example, peripherals with high bandwidth and real-time requirements are connected to the AHB bus matrix, while many low-speed configuration peripherals are connected to the APB bus matrix. The AXI, AHB, and APB bus matrices achieve protocol conversion and rate matching through hierarchical bus bridges, forming a clearly hierarchical and responsibility-separated on-chip communication network.

[0019] In the aforementioned hierarchical bus architecture, the DMA module, as a typical high-priority master device of the AXI bus matrix, must use the AXI bus matrix as a unified entry point for all data transmission operations it initiates, completing routing and forwarding through the AXI bus matrix. When the DMA module performs memory-to-memory data transmission, it can directly establish a high-speed path between the source and destination addresses through the AXI bus matrix without processor intervention. This fully leverages the high bandwidth and low latency advantages of the AXI protocol, meeting the performance requirements for continuous transmission of large data blocks.

[0020] When the target of the data transfer performed by the DMA module is a peripheral device, the data path needs to undergo a more complex protocol conversion process. Specifically, the transfer request is first sent by the DMA module to the AXI bus matrix, and then the protocol conversion, timing synchronization and handshake logic adaptation are completed in sequence through the AXI-to-AHB and AHB-to-APB bus bridges, and mapped down to the bus level to which the corresponding peripheral belongs.

[0021] While this unified entry point design simplifies system interconnection planning and verification convergence, and improves the scalability and compatibility of the architecture, it inevitably increases the path latency and control complexity of peripheral access, which has a particularly significant impact on peripherals with low latency and high real-time requirements.

[0022] Furthermore, in scenarios with concurrent access from multiple master devices, the above architecture also suffers from bus resource contention issues. When the DMA module initiates intensive or continuous large data stream transmissions, it will occupy the channel and bandwidth resources of the AXI bus matrix for an extended period, causing access blockages and prolonged waiting cycles for other master devices such as processors and high-speed interfaces, thereby reducing the system's real-time performance and overall throughput.

[0023] Based on this, embodiments of this application provide a multi-bus configurable DMA system, which includes a DMA module, at least two sets of bus matrices of different types, and a peripheral subsystem. The at least two sets of bus matrices of different types include a first type of bus matrix and a second type of bus matrix. The peripheral subsystem is coupled to the second type of bus matrix, and the DMA module is coupled to both the first and second type of bus matrices. Thus, by directly connecting the DMA module to the at least two sets of bus matrices of different types, the DMA module can directly access peripherals through the second type of bus matrix. In other words, when accessing peripherals, the DMA module no longer needs to go through the conversion process from the first type of bus matrix to the second type of bus matrix, thereby significantly reducing path latency and control complexity when accessing peripherals. Simultaneously, because this method reduces the occupancy rate of the first type of bus matrix, it improves the system's real-time performance and overall data throughput.

[0024] The multi-bus configurable DMA system provided in the embodiments of this application will now be explained in detail.

[0025] Figure 1 This is a schematic diagram of the structure of a multi-bus configurable DMA system provided in an embodiment of this application, as shown below. Figure 1 As shown, the multi-bus configurable DMA system includes a DMA module, at least two sets of bus matrices of different types, and a peripheral subsystem. The at least two sets of bus matrices of different types include: a first type of bus matrix configured for system transfer; and a second type of bus matrix configured for peripheral access. The peripheral subsystem is coupled to the second type of bus matrix. The DMA module is coupled to both the first type of bus matrix and the second type of bus matrix. The DMA module is configured to select the first type of bus matrix to perform system transfer or select the second type of bus matrix to access the peripheral subsystem, depending on the type of bus matrix required during data access.

[0026] In some embodiments, the first type of bus matrix is ​​used for system-oriented transmission, responsible for data communication between the internal main control unit, arithmetic units, and various core functional modules, completing internal global data scheduling and core business flow, and serving as the backbone for internal core data transmission. The second type of bus matrix is ​​used for peripheral access, primarily interfacing with various peripherals, responsible for reading and writing control of peripherals, issuing commands, and other operations. This type of bus matrix only implements data access and interaction with peripherals and does not participate in internal data transmission.

[0027] In some embodiments, the first type of bus matrix includes an AXI bus matrix; please refer to [reference needed]. Figure 1 The second type of bus matrix includes a first peripheral bus matrix and a second peripheral bus matrix. The peripherals accessed by the first peripheral bus matrix have a higher speed than the peripherals accessed by the second peripheral bus matrix.

[0028] AXI bus matrix is ​​used to support high-bandwidth, high-efficiency data transmission, and also has the capability for batch burst transmission. It can meet the system-level requirements for high-volume, high-real-time data interaction and is suitable for interconnection scenarios between the main controller and on-chip high-speed modules. Therefore, the AXI bus matrix can be used as the first type of bus matrix to realize high-speed transmission functions for the system.

[0029] Based on the above description, the second type of bus matrix is ​​typically used for peripheral access scenarios. Peripherals connected to this type of bus matrix can include both high-speed and low-speed peripherals. High-speed peripherals are also called high-speed peripherals, and low-speed peripherals are called low-speed peripherals. If a single bus matrix is ​​used to connect to both types of peripherals with different speeds simultaneously, it is highly likely to result in insufficient access performance and low bus resource utilization. Therefore, the second type of bus matrix can be further divided into a first peripheral bus matrix and a second peripheral bus matrix. The first peripheral bus matrix is ​​used to adapt to high-speed peripherals, and the second peripheral bus matrix is ​​used to adapt to low-speed peripherals. In this way, high-speed peripherals can be accessed through the first peripheral bus matrix, and low-speed peripherals can be accessed through the second peripheral bus matrix, thus balancing peripheral access speed requirements and effectively avoiding performance insufficiency and resource idleness.

[0030] In some embodiments, the first peripheral bus matrix is ​​an AHB bus matrix, and the second peripheral bus matrix is ​​an APB bus matrix. The AHB bus matrix is ​​used to implement data interaction and address allocation between medium- and high-speed peripherals, meeting the high-bandwidth and high-speed access requirements of high-speed peripherals; therefore, the AHB bus matrix can be used as the first peripheral bus matrix. The APB bus matrix is ​​used to connect low-speed peripherals, enabling unified management of low-power, simple control interfaces and adapting to the operation and transmission needs of low-speed peripherals; therefore, the APB bus matrix can be used as the second peripheral bus matrix. This ensures high-speed data transmission efficiency while reducing the power consumption and resource consumption of the low-speed peripheral bus.

[0031] Based on the above description, different types of bus matrices are adapted to peripherals and master devices with different speeds, bandwidths, and access characteristics. By employing multiple different types of bus matrices working together, the system can achieve hierarchical interconnection based on the performance, data throughput, and access timing requirements of each functional module. This improves bus resource utilization while reducing transmission interference between modules with different speeds, thereby enhancing the overall stability and scalability of the system.

[0032] It should be noted that the term "bus matrix" broadly refers to a bus switching structure capable of connecting at least one master device and at least one slave device, and supporting multiple access paths. This structure can be a crossbar switch matrix supporting fully concurrent paths (such as an AXI bus matrix), a shared bus structure supporting time-division multiplexing (such as a multi-master AHB bus), or a peripheral-mounted bus with a single master controller (such as an APB bus). Those skilled in the art will understand that different implementations of bus matrices differ in complexity, concurrency capabilities, and application scenarios, but all fall within the scope of the bus matrix described in the embodiments of this application.

[0033] Peripheral subsystems are typically functional modules coupled to a bus matrix to implement specific functions. Based on transmission characteristics, they can be divided into three categories: high-speed peripherals connected to an AXI bus matrix, suitable for high-bandwidth, high-throughput data interaction scenarios; medium-to-high-speed peripherals connected to an AHB bus matrix, suitable for medium-speed data transmission; and low-speed peripherals connected to an APB bus matrix, suitable for simple control and configuration access scenarios.

[0034] In some embodiments, the peripheral subsystem includes a first peripheral and a second peripheral. The first peripheral is coupled to a first peripheral bus matrix, and the second peripheral is coupled to a second peripheral bus matrix. When the first peripheral bus matrix is ​​an AHB bus matrix, the first peripheral is coupled to the AHB bus matrix; therefore, the first peripheral can be a medium-to-high-speed peripheral. For example, the first peripheral can be a functional module suitable for medium-speed data transmission, such as an Ethernet controller, a Universal Serial Bus (USB) controller, a Secure Digital Input and Output (SDIO) controller, a liquid crystal display controller, a general-purpose DMA module, or an interrupt controller.

[0035] When the second peripheral bus matrix is ​​an APB bus matrix, the second peripheral is coupled to the APB bus matrix, so the second peripheral can be a low-speed peripheral. For example, the second peripheral can be a general-purpose input / output port (GPIO), a universal asynchronous receiver / transmitter (UART), a serial peripheral interface (SPI), an inter-integrated circuit (I2C) bus, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a watchdog timer, etc., which are mainly used for control, configuration, and low-speed data interaction.

[0036] Because the peripheral subsystem is coupled to the second type of bus matrix, and the memory is typically coupled to the first type of bus matrix, the DMA module is coupled to both the first and second type of bus matrices. Therefore, the DMA module can directly access the memory through the first type of bus matrix to complete system-level data transfer; and directly access the peripheral subsystem through the second type of bus matrix, eliminating the need for a conversion process from the first to the second type of bus matrix. This significantly reduces path latency and control complexity when accessing peripherals. Simultaneously, it achieves physical isolation between the DMA module's peripheral access path and the system-level transmission path, thereby reducing mutual interference and improving system concurrency performance. Furthermore, because this approach reduces the occupancy rate of the first type of bus matrix, it improves the system's real-time performance and overall data throughput.

[0037] Based on the above description, the DMA module is directly coupled to the second type of bus matrix, and the peripheral subsystem is also coupled to the second type of bus matrix. The second type of bus matrix includes a first peripheral bus matrix and a second peripheral bus matrix. The peripheral subsystem includes a first peripheral and a second peripheral. The first peripheral is coupled to the first peripheral bus matrix, and the second peripheral is coupled to the second peripheral bus matrix. Therefore, when the DMA module accesses the peripheral subsystem through the second type of bus matrix, there are two possible scenarios.

[0038] In the first scenario, the DMA module accesses the first peripheral. In this case, the DMA module can directly access the first peripheral through the first peripheral bus matrix, eliminating the need for a conversion process from the first type of bus matrix to the first peripheral bus matrix. This significantly reduces path latency and control complexity when accessing the peripheral. Simultaneously, because this method reduces the occupancy rate of the first type of bus matrix, it improves the system's real-time performance and overall data throughput.

[0039] In the second scenario, the DMA module accesses the second peripheral. Similarly, the DMA module can directly access the second peripheral through the second peripheral bus matrix, eliminating the need for the conversion process from the first type of bus matrix to the second peripheral bus matrix. This significantly reduces path latency and control complexity when accessing peripherals.

[0040] Please refer to Figure 2 The DMA module includes a channel configuration register, a DMA control unit, a first buffer unit, and at least two sets of different types of bus interfaces, each corresponding to a different type of bus matrix. The channel configuration register is configured to configure the type of bus matrix required for data access. The channel configuration register is coupled to the DMA control unit and the first buffer unit, respectively. The DMA control unit, the channel configuration register, and the first buffer unit are coupled to the at least two sets of different types of bus interfaces, respectively. Each of the at least two sets of different types of bus interfaces is coupled to a corresponding bus matrix. The DMA control unit is configured to, in conjunction with the first buffer unit, select a first type of bus matrix to perform system transmission, or select a second type of bus matrix to access the peripheral subsystem, based on the type of bus matrix configured in the channel configuration register.

[0041] In some embodiments, the channel configuration register is used to receive configuration information sent by the host, including bus interface selection information, the size of the data to be accessed, and the address to be accessed. The channel configuration register may include multiple registers for storing the configuration information.

[0042] For example, the channel configuration register may include a first register for storing bus interface selection information, which indicates the bus interface to be used during the current data access. This bus interface selection information can be at least one of a first value, a second value, and a third value. The first value indicates that the AXI bus interface is required during the current data access, the second value indicates that the AHB bus interface is required, and the third value indicates that the APB bus interface is required. In this way, by configuring the first register, the bus interface used during the current data access can be dynamically and flexibly controlled. That is, the DMA module can dynamically switch bus interfaces as needed, offering high flexibility.

[0043] In some embodiments, the channel configuration register may further include a second register for storing the size of the data block to be accessed and the address to be accessed. The address to be accessed typically refers to the starting address of the storage area occupied by the data block to be accessed. This address includes the read address and / or write address of the data block to be accessed. The size of the data block to be accessed refers to the total length of the data transmitted in this transfer.

[0044] In some embodiments, the aforementioned channel configuration register is coupled to a second type of bus matrix.

[0045] Based on the above description, the second type of bus matrix includes a first peripheral bus matrix and a second peripheral bus matrix. The first peripheral bus matrix is ​​an AHB bus matrix, and the second peripheral bus matrix is ​​an APB bus matrix. That is, the host can send configuration information to the DMA module through either the AHB bus matrix or the APB bus matrix.

[0046] In some embodiments, the APB bus matrix is ​​typically used for simple control and configuration-related access scenarios. Therefore, the aforementioned channel configuration register is typically coupled to a second peripheral bus matrix.

[0047] The DMA control unit receives configuration information output from the channel configuration register and initiates data transfer tasks based on this information. It supports direct data interaction without processor intervention, thus freeing up processor computing power and significantly improving system efficiency. For example, taking reading data from a peripheral device as an example, after receiving the configuration information from the channel configuration register, the DMA control unit determines the target peripheral device according to the read address of the data block to be accessed, and drives the corresponding bus interface to read data from the target peripheral device based on the bus interface selection information and the size of the data block to be accessed.

[0048] The first buffer unit is used to receive configuration information output from the channel configuration register and to implement data buffering among functional modules within the same clock domain. The read clock and write clock within the same clock domain can typically be the same clock; that is, the read clock and write clock of the first buffer unit can be the same clock. For example, the first buffer unit can be a synchronous first-in-first-out (FIFO), where the read clock and write clock of the synchronous FIFO are the same clock.

[0049] In some embodiments, the depth of the first cache unit can be flexibly configured according to needs, that is, the user can configure the number of data that the first cache unit can cache according to needs. For example, the first cache unit is a FIFO, and the depth of the FIFO can be configured to 8 or 16, that is, the first cache unit can cache a maximum of 8 or 16 data.

[0050] In some embodiments, the at least two sets of different types of bus interfaces include a first type of bus interface and a second type of bus interface. The first type of bus interface includes an AXI bus interface, and the second type of bus interface includes an AHB bus interface and an APB bus interface.

[0051] The AXI bus interface is coupled to the AXI bus matrix, the AHB bus interface to the AHB bus matrix, and the APB bus interface to the APB bus matrix. This allows the DMA module to directly access medium-to-high-speed peripherals connected to the AHB bus matrix via the AHB bus interface, eliminating the need for a conversion process from the AXI bus matrix to the AHB bus matrix. This significantly reduces path latency and control complexity. For example, if the DMA module needs to read data from a USB drive, it can directly read the data from the USB drive via the AHB bus interface and then the AHB bus matrix.

[0052] Similarly, when the DMA module accesses low-speed peripherals connected to the APB bus matrix, it can directly access the corresponding peripherals through the APB bus interface and then through the APB bus matrix, eliminating the need for the conversion process from the AXI bus matrix to the AHB bus matrix and then back to the APB bus matrix. For example, if the DMA needs to read data from the UART, it can directly read the data from the UART through the APB bus interface and then through the APB bus matrix.

[0053] Please refer to Figure 2 and Figure 3 The first cache unit is a cache unit whose write clock and read clock are the same. The clock of the second type of bus interface is different from the main clock of the DMA module. The second type of bus interface is the bus interface corresponding to the second type of bus matrix. The second type of bus interface includes a second cache unit and a conversion control unit. The second cache unit is coupled to the first cache unit and the conversion control unit respectively. The conversion control unit is also coupled to the channel configuration register and the DMA control unit respectively.

[0054] Based on the above description, since the first cache unit is used for data caching among functional modules within the same clock domain, the write clock and read clock of the first cache unit can be the same clock. In some embodiments, the first cache unit and the DMA control unit operate in the same clock domain, therefore the master clock of the first cache unit and the DMA module is the same, wherein the master clock of the DMA module is the operating clock of the DMA control unit.

[0055] In some embodiments, the clock of the second type bus interface is different from the master clock of the DMA module. That is, the process of the DMA module reading or writing data through the second type bus interface involves cross-clock domain transmission. This transmission process may cause metastability propagation, which may lead to logic errors. Therefore, the second type bus interface may include a second buffer unit to perform data synchronization processing.

[0056] Based on the above description, the second type of bus interface includes the AHB bus interface and the APB bus interface.

[0057] Please refer to Figure 4 When the second type of bus interface is the AHB bus interface, the second buffer unit is also called the AHB buffer unit, and the conversion control unit is also called the AHB conversion control unit.

[0058] In some embodiments, the AHB buffer unit is used to implement reliable data transmission between different clock domains. It allows data to be written in one clock domain (e.g., a write clock domain) and read out in another completely independent clock domain (e.g., a read clock domain), thereby ensuring that data can be transmitted completely, correctly, and in an orderly manner between different clock domains. That is, when the clock of the second type bus interface is different from the master clock of the DMA module, and the master clock of the first buffer unit is the same as that of the DMA module, the AHB buffer unit can transmit data across clock domains, so that the data transmitted by the second type bus interface is in its own clock domain and isolated from the clock domain of the first buffer unit.

[0059] For example, the AHB cache unit can be an asynchronous FIFO, with different clocks for reading and writing. In some embodiments, the depth of the AHB cache unit can be flexibly configured as needed. For example, the depth of the AHB cache unit can be configured to 2.

[0060] The AHB conversion control unit receives data from the AHB buffer unit after cross-clock domain processing, and determines the target bus interface to be used by the DMA module for data transfer based on the bus interface selection information output by the channel configuration register. It then sends the received data out according to the protocol format corresponding to the target bus interface. For example, if the DMA module needs to write data to a peripheral coupled to the AHB bus matrix, the AHB conversion control unit receives the data output by the AHB buffer unit and sends the data out in a format conforming to the AHB protocol.

[0061] In some embodiments, the AHB conversion control unit is further configured to receive data conforming to the AHB bus protocol format and store the data in the AHB cache unit. For example, if the DMA module needs to read data from a peripheral coupled to the AHB bus matrix, the AHB conversion control unit receives data conforming to the AHB bus protocol format and stores the data in the AHB cache unit.

[0062] The above explanation uses the example of the DMA module writing data to or reading data from the first peripheral device. In some embodiments, the DMA module may also read data from memory and write the read data to the first peripheral device, or the DMA module may also read data from the first peripheral device and write the read data to memory, or the DMA module may also read data from the first peripheral device and write the read data to another first peripheral device.

[0063] Please refer to Figure 1 and Figure 2 The following example illustrates how a DMA module reads data from memory and writes it to a first peripheral device. During the data reading phase, after receiving configuration information, the DMA module drives the first type of bus interface to read data from memory according to the read address of the data block to be accessed, based on the bus interface selection information and the size of the data block, and stores the read data in the first cache unit. During the data writing phase, the DMA module determines the target first peripheral device according to the write address, drives the AHB bus interface to receive data from the first cache unit according to the bus interface selection information, performs cross-clock domain processing on the data, and sends the processed data to the AHB bus matrix according to the protocol format corresponding to the AHB bus interface. The data is then written to the target first peripheral device via the AHB bus matrix. For example, the DMA module reads data from memory and writes it to a USB drive. In this case, the DMA module reads data from memory via the AXI bus interface and then via the AXI bus matrix, and writes the read data to the USB drive via the AHB bus interface and then via the AHB bus matrix.

[0064] Please refer to Figure 5 When the second type of bus interface is the APB bus interface, the second buffer unit is also called the APB buffer unit, and the conversion control unit is also called the APB conversion control unit.

[0065] In some embodiments, the APB buffer unit is used to implement reliable data transmission between different clock domains. It allows data to be written in one clock domain (e.g., the write clock domain) and read out in another completely independent clock domain (e.g., the read clock domain), thereby ensuring that data can be transmitted completely, correctly, and in an orderly manner between different clock domains. That is, when the clock of the second type bus interface is different from the master clock of the DMA module, and the master clock of the first buffer unit is the same as that of the DMA module, the APB buffer unit can transmit data across clock domains, so that the data transmitted by the APB bus interface is in its own clock domain and isolated from the clock domain of the first buffer unit.

[0066] For example, the APB cache unit can be an asynchronous FIFO, with different clocks for reading and writing. In some embodiments, the depth of the APB cache unit can be flexibly configured as needed. For example, the depth of the APB cache unit can be configured to 2.

[0067] The APB conversion control unit receives the cross-clock domain processed data output from the APB buffer unit and, based on the bus interface selection information output from the channel configuration register, determines the target bus interface required by the DMA module for data transfer. It then sends the received data out according to the protocol format corresponding to the target bus interface. For example, if the DMA module needs to write data to a peripheral coupled to the APB bus matrix, the APB conversion control unit receives the data output from the APB buffer unit and sends the data out in a format conforming to the APB protocol.

[0068] In some embodiments, the APB conversion control unit is further configured to receive data conforming to the APB bus protocol format and store the data in the APB cache unit. For example, if the DMA module needs to read data from a peripheral coupled to the APB bus matrix, the APB conversion control unit receives data conforming to the APB bus protocol format and stores the data in the APB cache unit.

[0069] The above explanation uses the example of the DMA module writing data to or reading data from a second peripheral device. In some embodiments, the DMA module may also read data from memory and write the read data to the second peripheral device, or the DMA module may also read data from the second peripheral device and write the read data to memory, or the DMA module may also read data from the second peripheral device and write the read data to another second peripheral device.

[0070] Please refer to Figure 1 and Figure 2The following example illustrates how a DMA module reads data from memory and writes it to a second peripheral. During the data reading phase, after receiving configuration information, the DMA module drives the first type of bus interface to read data from memory according to the read address of the data block to be accessed, based on the bus interface selection information and the size of the data block. The read data is then stored in the first cache unit. During the data writing phase, the DMA module determines the target second peripheral according to the write address, drives the APB bus interface to receive data from the first cache unit according to the bus interface selection information, performs cross-clock domain processing on the data, and sends the processed data to the APB bus matrix according to the protocol format corresponding to the APB bus interface. The data is then written to the target second peripheral via the APB bus matrix. For example, the DMA module reads data from memory and writes it to the UART. In this case, the DMA module reads data from memory via the AXI bus interface and then via the AXI bus matrix, and writes the read data to the UART via the APB bus interface and then via the APB bus matrix.

[0071] The multi-bus configurable DMA system provided in this application includes a DMA module, at least two sets of bus matrices of different types, and a peripheral subsystem. By directly connecting the DMA module to the at least two sets of bus matrices of different types, the DMA module can directly access peripherals through the second type of bus matrix. That is, when accessing peripherals, the DMA module no longer needs to go through the conversion process from the first type of bus matrix to the second type of bus matrix, thus significantly reducing path latency and control complexity when accessing peripherals. Simultaneously, because the DMA module is directly connected to the at least two sets of bus matrices of different types—meaning the DMA module can access memory through the first type of bus matrix and access peripherals through the second type of bus matrix—the DMA module's peripheral access path and memory access path are physically separated, thus achieving physical isolation of the access paths, reducing mutual interference, and improving system concurrency performance. Furthermore, because this method effectively reduces the occupancy rate of the first type of bus matrix, it improves the system's real-time performance and overall data throughput. In addition, the embodiments of this application also retain the path between the first type of bus matrix and the second type of bus matrix to support some peripherals and memory mapping areas that still need to be accessed through the first type of bus matrix, thereby improving system compatibility and platform migration efficiency.

[0072] This application also provides a microcontroller configured with the multi-bus configurable DMA system described in the above embodiments.

[0073] In some embodiments, the microcontroller further includes a processor interface coupled to a first type of bus matrix.

[0074] In some embodiments, the microcontroller further includes a memory coupled to a first type of bus matrix.

[0075] This application also provides a computer device that includes the microcontroller described above.

[0076] It should be noted that the multi-bus configurable DMA system provided in the above embodiments is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0077] It should be understood that "at least one" as mentioned herein refers to one or more, and "multiple" refers to two or more. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. In addition, in order to clearly describe the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and the terms "first," "second," etc., are not necessarily different.

[0078] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in the embodiments of this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0079] The above descriptions are embodiments provided in this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A multi-bus configurable DMA system, characterized in that, include: Direct Memory Access (DMA) module, at least two different types of bus matrices, and peripheral subsystems; The at least two sets of bus matrices of different types include: The first type of bus matrix is ​​configured for system-oriented transmission; The second type of bus matrix is ​​configured to be accessed from peripherals. The peripheral subsystem is coupled to the second type of bus matrix; The DMA module is coupled to the first type of bus matrix and the second type of bus matrix respectively; The DMA module is configured to: select the first type of bus matrix to perform the system transfer, or select the second type of bus matrix to access the peripheral subsystem, depending on the type of bus matrix required during data access.

2. The multi-bus configurable DMA system as described in claim 1, characterized in that, The DMA module includes a channel configuration register, a DMA control unit, a first cache unit, and at least two sets of different types of bus interfaces, wherein the at least two sets of different types of bus interfaces correspond one-to-one with the at least two sets of different types of bus matrices. The channel configuration register is configured to configure the type of bus matrix required during data access. The channel configuration register is coupled to the DMA control unit and the first cache unit respectively. The DMA control unit, the channel configuration register, and the first cache unit are coupled to the at least two sets of different types of bus interfaces respectively. The at least two sets of different types of bus interfaces are coupled to the corresponding bus matrix respectively. The DMA control unit is configured to: in conjunction with the first cache unit, select the first type of bus matrix to perform the system transmission, or select the second type of bus matrix to access the peripheral subsystem, based on the type of bus matrix configured in the channel configuration register.

3. The multi-bus configurable DMA system as described in claim 2, characterized in that, The first cache unit is a cache unit whose write clock and read clock are the same clock. The clock of the second type of bus interface is different from the main clock of the DMA module. The second type of bus interface is the bus interface corresponding to the second type of bus matrix. The second type of bus interface includes a second cache unit and a conversion control unit. The second cache unit is coupled to the first cache unit and the conversion control unit, respectively. The conversion control unit is also coupled to the channel configuration register and the DMA control unit, respectively.

4. The multi-bus configurable DMA system as described in claim 2 or 3, characterized in that, The channel configuration register is coupled to the second type of bus matrix.

5. The multi-bus configurable DMA system as described in any one of claims 1-4, characterized in that, The first type of bus matrix includes an Advanced Extensible Interface (AXI) bus matrix, and the second type of bus matrix includes a first peripheral bus matrix and a second peripheral bus matrix. The peripherals accessed by the first peripheral bus matrix have a higher speed than the peripherals accessed by the second peripheral bus matrix.

6. The multi-bus configurable DMA system as described in claim 5, characterized in that, The first peripheral bus matrix is ​​an Advanced High Performance Bus (AHB) bus matrix, and the second peripheral bus matrix is ​​an Advanced Peripheral Bus (APB) bus matrix.

7. A microcontroller, characterized in that, The microcontroller includes the multi-bus configurable DMA system as described in any one of claims 1-6.

8. The microcontroller as described in claim 7, characterized in that, The microcontroller also includes a processor interface, which is coupled to the first type of bus matrix.

9. The microcontroller as described in claim 7 or 8, characterized in that, The microcontroller also includes a memory coupled to the first type of bus matrix.

10. A computer device, characterized in that, The computer device includes the microcontroller according to any one of claims 7-9.

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