A bare machine multi-sensor high-frequency acquisition transmission method

Abstract

The application belongs to the technical field of sensors, and provides a bare machine multi-sensor high-frequency acquisition transmission method, which comprises the following steps: independently configuring a hardware timer for each sensor, setting a sampling period and an overflow time, configuring an acquisition DMA channel and a sending DMA channel; constructing a ring-shaped FIFO buffer zone for each sensor, and setting a trigger depth threshold of the sensor internal FIFO; triggering sampling when the hardware timer corresponding to each sensor overflows, transmitting the data in the sensor data register to the address pointed to by the memory FIFO buffer zone write pointer corresponding to the sensor by the acquisition DMA; reading the cached data from the address pointed to by the memory FIFO buffer zone read pointer, and performing data validity determination; organizing the data determined as valid into a data frame according to a preset sending sequence, and transmitting the data frame to the serial port data register by starting the sending DMA. The application realizes multi-sensor high-frequency acquisition transmission in a bare machine environment.

Description

Technical Field

[0001] This invention belongs to the field of sensor technology, specifically a bare-metal multi-sensor high-frequency acquisition and transmission method. Background Technology

[0002] In embedded system development, microcontrollers (MCUs) execute programs sequentially in a bare-metal environment. When a program takes a long time to run, sensors operating at a fixed sampling rate via timers may fail to sample data in a timely manner, leading to uncontrolled sensor sampling rates. This, in turn, affects subsequent data processing results, such as the accuracy of Fast Fourier Transform (FFT) operations. In applications requiring high-frequency sampling from multiple different types of sensors, program design becomes particularly challenging, requiring the simultaneous maintenance of sampling timing for each sensor and the real-time performance of data processing.

[0003] Currently, two main technical solutions are used in this field. One is to introduce a real-time operating system (RTOS) to ensure the timing accuracy of multi-sensor sampling and the real-time performance of data processing through task scheduling mechanisms. However, the RTOS solution has high hardware performance requirements and significantly increases software development complexity, inevitably prolonging the software and hardware development cycle and increasing development costs. Furthermore, improper handling may still lead to sampling rate runaway issues. The other solution is to reduce the sampling rate to alleviate system load, but this approach sacrifices product performance, weakening the product's market competitiveness.

[0004] Therefore, the present invention provides a bare-metal multi-sensor high-frequency acquisition and transmission method. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, at least one technical problem raised in the background art is solved.

[0006] The technical solution adopted by this invention to solve its technical problem is: a bare-metal multi-sensor high-frequency acquisition and transmission method, comprising the following steps:

[0007] Step S10: Configure an independent hardware timer for each sensor, independently set the sampling period and overflow time of each sensor, and configure the acquisition DMA channel and the transmission DMA channel.

[0008] Specifically, the source address of the acquisition DMA channel is set to the sensor data register, and the destination address is set to the start address of the memory FIFO buffer. The source address of the transmission DMA channel is set to the start address of the memory FIFO buffer, and the destination address is set to the serial port data register.

[0009] Step S20: Construct a circular FIFO buffer for each sensor, define the buffer's start address, end address, read pointer, and write pointer, and set the trigger depth threshold for the sensor's internal FIFO;

[0010] Step S30: When the hardware timer corresponding to each sensor overflows, sampling is triggered. The acquisition DMA transfers the data in the sensor data register to the address pointed to by the write pointer of the corresponding sensor's memory FIFO buffer according to the configuration.

[0011] Step S40: Read the cached data of each sensor from the address pointed to by the read pointer in the memory FIFO buffer, and determine the validity of the data;

[0012] In step S50, the data determined to be valid by each sensor are organized into data frames according to a preset transmission order, and the transmission DMA is started to transmit the data frames to the serial port data register.

[0013] As a further aspect of the present invention: In step S10, the specific process of configuring an independent hardware timer for each sensor is as follows:

[0014] The MCU integrates multiple hardware timer modules, binds each timer to a sensor, enables each timer module through the timer configuration register, sets the working mode to periodic overflow mode, and enables the overflow interrupt bit.

[0015] The specific process for setting the sampling period and overflow time is as follows: the prescaler register and the auto-reload register are used for setting. The prescaler coefficient determines the timer counting clock frequency, and the auto-reload value determines when the count value reaches the value to generate an overflow event. The overflow time is equal to the product of the prescaler coefficient and the auto-reload value divided by the timer input clock frequency.

[0016] As a further aspect of the present invention: In step S10, the specific process of configuring the acquisition DMA channel and the transmission DMA channel is as follows: the acquisition DMA channel is allocated according to the number of sensors, with each sensor occupying one acquisition DMA channel and one transmission DMA channel allocated at the same time.

[0017] When configuring the acquisition DMA channel, set the channel priority to high, the transmission direction to peripheral to memory, the source address to the sensor data register and not increment, the destination address to the starting address of the memory FIFO buffer and increment, the data transmission width to 16 bits or 32 bits, and generate an interrupt when the transmission is completed.

[0018] When configuring the DMA channel, set the channel priority to medium, the transmission direction to memory to peripheral, the source address to the starting address of the memory FIFO buffer and increment it, the destination address to the serial port data register and not increment it, the data transmission width to 8 bits, and generate an interrupt when the transmission is completed.

[0019] As a further aspect of the present invention: In step S20, the process of constructing a circular FIFO buffer for each sensor is as follows:

[0020] In the MCU memory, a continuous storage space is allocated for each sensor as a circular FIFO buffer. The buffer capacity is at least f×b×t bytes, where f is the sampling frequency, b is the number of data bytes sampled each time, and t is the maximum response delay allowed by the system.

[0021] Define the starting address as the first address of the buffer, and the ending address as the starting address plus the total length of the buffer minus one. The read pointer and write pointer initially point to the starting address. Each time data is written or read, the corresponding pointer is incremented. When the ending address is reached, the pointer wraps back to the starting address.

[0022] As a further aspect of the present invention: In step S20, the process of setting the trigger depth threshold of the FIFO inside the sensor is as follows:

[0023] The trigger depth threshold is determined by combining the sensor sampling frequency f, the MCU interrupt response delay T_response, and the DMA transfer time T_dma. The time interval between two adjacent samples is T_sample=1 / f. The total delay from when the FIFO data reaches the threshold to when the data is completely read is T_response+T_dma. The trigger depth threshold N satisfies N≥(T_response+T_dma) / T_sample.

[0024] As a further aspect of the present invention: in step S30, the sampling process triggered when the hardware timer corresponding to each sensor overflows is as follows:

[0025] The timer runs independently according to the set sampling period. When the count value reaches the automatic reload value, an overflow event is generated. The overflow event is configured to trigger a DMA request, and the timer sends a request signal to the DMA controller.

[0026] The DMA transfers data from the sensor data register to the address pointed to by the write pointer in the memory FIFO buffer. The write pointer is automatically incremented after each DMA transfer and wraps back to the start address when it reaches the end address.

[0027] As a further aspect of the present invention: In step S40, the process of reading the cached data of each sensor from the address pointed to by the read pointer in the memory FIFO buffer is as follows:

[0028] The data read operation is triggered by the completion of the DMA transfer in step S30. The MCU reads data from the address currently pointed to by the read pointer. After each read is completed, the read pointer is incremented by a step size equal to the data width. When the read pointer is incremented to the end address of the buffer, it wraps back to the start address. The read operation continues until the preset number of reads is reached or the buffer is empty.

[0029] As a further aspect of the present invention: in step S40, the process of determining data validity is as follows:

[0030] The preset judgment conditions include multiple types such as data range judgment, data change rate judgment, sensor status judgment, and data continuity judgment;

[0031] The data range is determined by setting a valid numerical range based on the sensor's measurement range; data outside this range is considered invalid.

[0032] The rate of change of data is determined when the absolute value of the difference between two adjacent samples exceeds the maximum allowable value, at which point the data is deemed invalid.

[0033] Sensor status is determined by reading the sensor status register; if the status is abnormal, it is considered invalid.

[0034] Data continuity is determined by identifying discontinuous data sequences as invalid; data is considered invalid if any determination fails.

[0035] As a further aspect of the present invention: In step S50, the preset transmission order is calculated and determined based on the sampling frequency of each sensor and the current amount of data to be transmitted. Let the sampling frequency of sensor i be f_i and the amount of data to be transmitted in the current memory FIFO buffer be Q_i. Then the transmission priority score P_i = f_i × Q_i. The P_i values ​​of each sensor are calculated and sorted from largest to smallest. The sensor with the highest score obtains the highest transmission priority.

[0036] As a further aspect of the present invention: In step S50, the specific process of organizing the data determined to be valid by each sensor into data frames according to a preset transmission order, and starting the transmission DMA to transmit the data frames to the serial port data register is as follows:

[0037] Starting with the highest priority sensor, data deemed valid is read from its memory FIFO buffer and organized into data frames according to a preset frame format. The frame format includes, in order, a frame header, sensor identifier, timestamp, data length, data payload, and checksum.

[0038] After organizing a frame of data, configure the DMA channel to set the source address to the start address of the data frame, the destination address to the serial port data register address, and the transmission length to the total number of bytes in the data frame, and enable automatic transmission of the DMA channel; when an interrupt is generated after a frame of data transmission is completed, organize the next frame of data according to priority order and start transmission, until all valid data from all sensors have been transmitted.

[0039] The beneficial effects of this invention are as follows:

[0040] By configuring independent hardware timers for each sensor, precise separation of different sampling frequency requirements is achieved, avoiding the problem of mutual interference between sensor sampling timings in a single timer mode. Timer overflow events directly trigger DMA requests, and sampling triggering and data transmission are linked at the hardware level, avoiding sampling loss caused by code blocking in the bare-metal program and ensuring that each sensor operates stably according to the set sampling frequency. By configuring acquisition DMA channels and transmission DMA channels, the entire data transfer from sensor to memory and from memory to serial port is handled by the DMA controller. The CPU only updates the buffer pointer through an interrupt after the transfer is completed, significantly reducing the CPU load. By constructing a ring FIFO buffer for each sensor, the problem of mismatch between data acquisition speed and data processing speed under high-frequency sampling is solved. With the setting of the trigger depth threshold of the sensor's internal FIFO, multiple sets of data are buffered and triggered at once, significantly reducing the number of MCU interrupt responses. By performing multi-dimensional validity judgment on the buffered data, invalid data is filtered out, avoiding the occupation of limited serial bus bandwidth. The transmission priority is calculated by sampling frequency and the amount of data to be transmitted, so that data from high-load sensors is sent first, effectively preventing data accumulation and buffer overflow. The unified frame format design and time-division transmission mechanism ensure the stability and reliability of data transmission. This invention enables high-frequency data acquisition and transmission from multiple sensors in a bare-metal environment without the need for a real-time operating system. This reduces the performance requirements of the MCU hardware and avoids the software development complexity and extended development cycle issues associated with RTOS solutions. It reduces system costs and enhances product competitiveness while ensuring product performance. Attached Figure Description

[0041] The invention will now be further described with reference to the accompanying drawings.

[0042] Figure 1 This is a flowchart illustrating the steps of a bare-metal multi-sensor high-frequency acquisition and transmission method according to an embodiment of the present invention;

[0043] Figure 2 This is a logic judgment diagram of a bare-metal multi-sensor high-frequency acquisition and transmission method according to an embodiment of the present invention. Detailed Implementation

[0044] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0045] For examples, please refer to Figures 1-2 As shown in the embodiment of the present invention, a bare-metal multi-sensor high-frequency acquisition and transmission method includes the following steps:

[0046] Step S10: Configure an independent hardware timer for each sensor, independently set the sampling period and overflow time of each sensor, and configure the acquisition DMA (memory access) channel and the transmission DMA channel.

[0047] Specifically, the source address of the acquisition DMA channel is set to the sensor data register, and the destination address is set to the starting address of the memory FIFO (first-in-first-out) buffer. The source address of the transmission DMA channel is set to the starting address of the memory FIFO buffer, and the destination address is set to the serial port data register.

[0048] In step S10, the sensors include, but are not limited to: accelerometer, gyroscope, microphone, temperature, humidity, pressure, magnetometer, and light intensity sensor. Each sensor is selected according to the application requirements, with the accelerometer preferably being a model with built-in FIFO buffering.

[0049] In step S10, the specific process of configuring independent hardware timers for each sensor is as follows: The MCU (microcontroller) integrates multiple hardware timer modules, such as Timer 1, Timer 2, Timer 3, etc. Each timer is bound to a sensor. Through the MCU's timer configuration register, each timer module is enabled, the timer's working mode is set to periodic overflow mode, and the overflow interrupt enable bit of each timer is enabled.

[0050] In step S10, the specific process of setting the sampling period and overflow time of each sensor is as follows:

[0051] Based on the sampling frequency requirements of each sensor, the corresponding timer overflow time is calculated. When the sampling frequency is 1000Hz, the overflow time is set to 1 millisecond; when the sampling frequency is 500Hz, the overflow time is set to 2 milliseconds. This is set through the MCU's timer prescaler register and auto-reload register. First, the prescaler coefficient is set to determine the timer counting clock frequency. Then, the auto-reload value is set to determine when the count value reaches this value and an overflow event is generated. The overflow time is equal to the product of the prescaler coefficient and the auto-reload value divided by the timer input clock frequency.

[0052] For example, the specific process of setting the sampling period and overflow time for each sensor is explained:

[0053] Based on the sampling frequency requirements of each sensor, the corresponding timer overflow time is calculated. When the sampling frequency is 1000Hz, the overflow time is set to 1 millisecond; when the sampling frequency is 500Hz, the overflow time is set to 2 milliseconds.

[0054] The timer clock frequency is set via the MCU's timer prescaler register and auto-reload register. The input clock frequency of the MCU timer is usually the system clock frequency, such as 72MHz. First, set the prescaler register to divide the input clock frequency and use it as the timer's counting clock. The formula for calculating the prescaler is: Counting clock frequency = Timer input clock frequency / (Prescaler + 1). For example, if the required counting clock frequency is 72kHz, the prescaler is set to 999, then 72MHz / (999 + 1) = 72kHz, and the counting period is approximately 13.89 microseconds.

[0055] Then, configure the auto-reload register to determine the maximum value of the timer count. The timer starts counting from 0 and increments by 1 after each counting cycle. When the count reaches the auto-reload value, the timer generates an overflow event and resets to zero to start counting again. The overflow time is calculated as: Overflow time = (Auto-reload value + 1) × Counting cycle. For example, if the required overflow time is 1 millisecond and the counting cycle is 13.89 microseconds, then the auto-reload value is set to 71, i.e., (71 + 1) × 13.89 microseconds = 1 millisecond.

[0056] It should be noted that in actual configuration, for sensors with a sampling frequency of 1000Hz, the prescaler coefficient is first calculated based on the system's main frequency to ensure the counting period meets accuracy requirements, and then the automatic reload value is calculated to ensure the overflow time is 1 millisecond. For sensors with a sampling frequency of 500Hz, the same counting period is maintained, and the automatic reload value is doubled to ensure the overflow time is 2 milliseconds. Through these two steps, the calculated values ​​are written to the prescaler register and automatic reload register of each sensor, completing the independent setting of the sampling period.

[0057] In step S10, the specific process of configuring the acquisition DMA channel and the transmission DMA channel is as follows:

[0058] The MCU integrates multiple DMA controller channels, each of which can be configured independently. Acquisition DMA channels are allocated based on the number of sensors, with each sensor occupying one acquisition DMA channel and simultaneously allocated one transmit DMA channel for serial data transmission.

[0059] When configuring the acquisition DMA channel, first set the channel priority. The MCU's DMA controller supports multiple priority levels, usually divided into four levels: very high, high, medium, and low. When multiple DMA channels request transmission at the same time, the channel with higher priority is executed first. Since sensor data acquisition has real-time requirements, set the priority of the acquisition DMA channel of each sensor to high to ensure timely data transfer.

[0060] The transmission direction is set to peripheral to memory, meaning data is read from the sensor data register and written to the memory FIFO buffer. The source address is set to the address of the corresponding sensor's data register, and the address does not increment because data is read from the same register address each time. The destination address is set to the starting address of the corresponding sensor's memory FIFO buffer, and the address increments because data needs to be stored in the next location of the buffer after each transmission. The data transmission width is set to 32 bits or 16 bits, depending on the sensor's data bit width; accelerometers are typically 16 bits, and microphone sensors are 32 bits. An interrupt is generated upon completion of the transmission to update the FIFO write pointer.

[0061] When configuring the transmit DMA channel, first set the channel priority. The transmit DMA channel is used for serial port data transmission. Set its priority to medium, lower than the acquisition DMA channel, to ensure that data acquisition is completed first.

[0062] The transmission direction is set to memory to peripheral, meaning data is read from the memory FIFO buffer and written to the serial port data register. The source address is set to the starting address of the memory FIFO buffer and incremented, because each transmission requires reading data from the next position in the buffer. The destination address is set to the address of the serial port data register and does not increment, because each transmission writes to the same register address. The data transmission width is set to 8 bits, because serial ports typically send data in bytes. An interrupt is generated upon completion of the transmission to update the FIFO read pointer and initiate the next transmission.

[0063] The significance of step S10 is understandable: by configuring hardware timers independently for each sensor, precise separation of different sampling frequency requirements is achieved, avoiding the problem of mutual interference between the sampling timings of different sensors in a single timer mode. By configuring the acquisition DMA and transmission DMA channels, the data transfer work is transferred from the CPU to the DMA controller, freeing the CPU from frequent data transfer tasks and allowing it to focus on logical judgment and system management. The collaborative work of the timer and DMA ensures the accuracy of the sampling trigger timing and significantly reduces the CPU load, laying the hardware foundation for high-frequency acquisition of multiple sensors in a bare-metal environment, and avoiding the increased hardware costs and extended development cycle caused by introducing a real-time operating system.

[0064] Step S20: Construct a circular FIFO buffer for each sensor, define the buffer's start address, end address, read pointer, and write pointer, and set the trigger depth threshold for the sensor's internal FIFO;

[0065] In step S20, the process of constructing a circular FIFO buffer for each sensor is as follows:

[0066] Within the MCU's internal random access memory, a contiguous storage space is allocated for each sensor as a dedicated circular FIFO buffer. The size of the buffer is determined based on the sensor's sampling frequency, data width, and the system's maximum allowable response delay. If a sensor's sampling frequency is f (Hz), the number of data bytes generated per sample is b (bytes), and the system's maximum allowable response delay is t (seconds), then the sensor's buffer capacity must be at least f × b × t bytes.

[0067] In step S20, the process of defining the buffer's start address, end address, read pointer, and write pointer is as follows:

[0068] Four key parameters are defined for each sensor's buffer: the start address is the first address of the buffer, i.e., the address of the first element of the array, obtained using the address-of operator; the end address is the last address of the buffer, i.e., the start address plus the total buffer length minus one; the read pointer indicates the position for the next data read, initially pointing to the start address; the write pointer indicates the position for the next data write, initially pointing to the start address; both the read and write pointers are stored in pointer variables. During data transmission, the write pointer increments for each piece of data written, and the read pointer increments for each piece of data read; when either the read or write pointer reaches the end address, it automatically wraps back to the start address, forming a circular structure.

[0069] In step S20, the process of setting the trigger depth threshold of the sensor's internal FIFO is as follows:

[0070] The trigger depth threshold is determined by a combination of the sensor's sampling frequency, the MCU's interrupt response delay, and the DMA transfer time. Let the sensor sampling frequency be f (in Hz), then the time interval between two adjacent samples is T_sample = 1 / f (in seconds). Let the MCU's response delay from triggering the sensor interrupt pin to starting DMA transfer be T_response (in seconds), and the DMA's transfer time to complete one FIFO data read be T_dma (in seconds). Then the total delay from when the FIFO data reaches the threshold to when the data is completely read is T_response + T_dma. To ensure that the FIFO does not overflow during the total delay, the trigger depth threshold N should satisfy: N ≥ (T_response + T_dma) / T_sample.

[0071] Understandably, the significance of step S20 lies in the following: By constructing a circular FIFO buffer for each sensor, an independent data temporary storage space is established in memory, solving the problem of the mismatch between data acquisition speed and data processing speed under high-frequency sampling. The circular structure achieves cyclic data coverage, avoiding data loss caused by buffer overflow. By defining read and write pointers, ordered data writing and reading are achieved, ensuring data integrity. Setting the trigger depth threshold of the sensor's internal FIFO allows multiple sets of data from the sensor to be cached and then triggered to interrupt at once, significantly reducing the number of interrupt responses from the MCU, further reducing system overhead, and enabling the bare-metal system to easily handle the high-frequency sampling data flow.

[0072] Step S30: When the hardware timer corresponding to each sensor overflows, sampling is triggered. The acquisition DMA transfers the data in the sensor data register to the address pointed to by the write pointer of the corresponding sensor's memory FIFO buffer according to the configuration.

[0073] In step S30, the sampling process is triggered when the hardware timer corresponding to the sensor overflows as follows:

[0074] Each sensor's corresponding hardware timer runs independently according to the sampling period set in step S10. The timer increments from 0. When the count value reaches the value set in the automatic reload register, the timer generates an overflow event. When an overflow event occurs, the corresponding overflow flag in the timer's status register is set to 1 by the hardware. At the same time, according to the configuration of the timer control register, a DMA request is generated. In this implementation, the timer overflow event is configured to trigger a DMA request instead of generating an interrupt. Specifically, the DMA request output is enabled in the timer's DMA control register, and the DMA request source is set to the timer overflow event. When the timer overflows, the timer sends a request signal to the DMA to inform the DMA sensor that there is new sampled data that needs to be transmitted.

[0075] In step S30, the process of the acquisition DMA transferring data from the sensor data register to the address pointed to by the write pointer of the corresponding sensor's memory FIFO buffer according to the configuration is as follows:

[0076] After receiving the DMA request from the timer, the DMA controller performs data transmission according to the acquisition DMA channel parameters configured in step S10. First, it checks the priority of the DMA channel. If there is no higher priority DMA request being processed, it responds to the request. The DMA controller reads data from the configured source address, which is the address of the sensor data register. The data width is 32 bits or 16 bits set in step S10. The sensor completes a sampling at the moment the timer is triggered and stores the sampling result in its data register. When the DMA controller reads the register, it obtains the latest sampling data.

[0077] After the DMA controller reads the data, it writes the data to the configured destination address, which is the address currently pointed to by the write pointer of the corresponding sensor's memory FIFO buffer. The value of the write pointer is automatically incremented by the DMA controller after each DMA transfer, and the increment step is equal to the data width. While transferring data, the DMA controller updates the value of the write pointer to the current write address plus the data width. When the write pointer reaches the end address of the buffer, according to the circular buffer rule set in step S20, the DMA controller wraps the write pointer back to the start address of the buffer.

[0078] It should be noted that the above process is executed independently and in parallel for each sensor. The hardware timer corresponding to each sensor independently generates an overflow event according to its own sampling frequency, and the DMA channel corresponding to each sensor independently responds to its own DMA request. When multiple sensors trigger sampling simultaneously, the DMA controller arbitrates according to the channel priority set in step S10, prioritizing the response to the DMA channel with higher priority. For example, the DMA channel corresponding to a sensor with a higher sampling frequency is set to a higher priority to ensure its data is transmitted first. The DMA controller completes the data transmission of each channel sequentially according to priority. Since the DMA transmission speed is much higher than the sampling frequency, parallel acquisition of multiple channels will not cause data loss or conflicts.

[0079] The significance of step S30 is understandable: it directly triggers the DMA request through a hardware timer overflow event, achieving hardware-level linkage between sampling triggering and data transmission. This allows data transfer from the sensor data register to the memory FIFO buffer without CPU intervention. Each sensor's timer runs independently, and the DMA channels operate in parallel, enabling simultaneous acquisition of data from multiple channels. The DMA controller arbitrates based on preset channel priorities, ensuring priority transmission of data from sensors with higher sampling frequencies. The entire process is fully automated by hardware; the CPU only updates the write pointer via an interrupt after the DMA transfer is complete, minimizing CPU intervention and ensuring the real-time performance and reliability of data acquisition at high sampling frequencies.

[0080] Step S40: Read the cached data of each sensor from the address pointed to by the read pointer in the memory FIFO buffer, and determine the validity of the data;

[0081] In step S40, the process of reading the buffered data of each sensor from the address pointed to by the read pointer in the memory FIFO buffer is as follows:

[0082] When reading data, the MCU starts reading data from the address currently pointed to by the read pointer. The address pointed to by the read pointer is the starting address of the buffer defined in step S20 plus the offset of the already read data. The MCU reads data according to the data width configured in step S10, which is 16 bits or 32 bits. After each read is completed, the read pointer is incremented by a step size equal to the data width. When the read pointer increments to the end address of the buffer, according to the circular buffer rule set in step S20, the read pointer wraps back to the starting address of the buffer. The reading operation continues until the preset number of reads is reached or the buffer is empty.

[0083] It should be noted that the data read operation is triggered by the completion of the DMA transfer in step S30;

[0084] In step S40, the process of determining data validity is as follows:

[0085] Data validity is determined based on preset criteria, which are set according to the physical characteristics of each sensor and the application scenario. The preset criteria include the following:

[0086] Data range determination: The effective value range is set according to the measurement range of the sensor. For example, when the measurement range of the accelerometer is ±2g, the effective value range is -2g to +2g. Data outside this range is determined to be invalid.

[0087] Data change rate determination: Based on the physical characteristics of the sensor output signal, a maximum allowable value for the change rate of two adjacent sampled data is set. When the absolute value of the difference between two adjacent sampled data exceeds the maximum allowable value, the data is determined to be invalid.

[0088] The maximum allowable value Δ_max is determined by calculating the maximum possible rate of change of the sensor under physical limit conditions. For example, for an accelerometer at its maximum rate of acceleration change, the maximum amplitude of data change within two adjacent sampling intervals is Δ_max. For an accelerometer with a sampling frequency of 1000Hz, if its physical limit rate of change is 100g per second, then the maximum change within one millisecond is 0.1g, and Δ_max is set to the digital value corresponding to 0.1g.

[0089] Sensor status determination: Sensors typically provide a status register to indicate whether the sensor is in normal working condition, whether an overload has occurred, or whether a self-test has failed. When the status register indicates an abnormality, the corresponding sampled data is determined to be invalid.

[0090] Data continuity determination: Based on the sampling period, determine whether data loss has occurred. When a data sequence discontinuity is detected, the corresponding data is determined to be invalid.

[0091] The read data is compared with the preset judgment conditions one by one. If the data range judgment, data change rate judgment, sensor status judgment and data continuity judgment all pass, the data is considered valid. Otherwise, if any judgment fails, the data is invalid.

[0092] Understandably, the significance of step S40 lies in: by performing multi-dimensional validity checks on the cached data, including data range, rate of change, sensor status, and data continuity, it effectively filters out invalid data generated by sensor malfunctions, external interference, or sampling anomalies. Invalid data is discarded before transmission, avoiding the occupation of limited serial bus bandwidth and improving data transmission efficiency. Simultaneously, by monitoring data quality in real time, abnormal sensor states can be detected promptly, providing a basis for system fault diagnosis. Data validity determination, as a crucial link between acquisition and transmission, ensures the quality of data entering the transmission process, providing a reliable data foundation for subsequent data processing and decision-making.

[0093] Step S50: Organize the data determined to be valid by each sensor into data frames according to the preset transmission order, and start the transmission DMA to transmit the data frames to the serial port data register.

[0094] In step S50, the preset transmission order is calculated and determined based on the sampling frequency of each sensor and the current amount of data to be transmitted. Let the sampling frequency of sensor i be f_i, and the amount of data to be transmitted in the current memory FIFO buffer be Q_i. Then the transmission priority score P_i = f_i × Q_i. The P_i value of each sensor is calculated and sorted from largest to smallest. The sensor with the highest score gets the highest transmission priority. When multiple sensors have the same P_i value, the sensor with the higher sampling frequency is sent first.

[0095] In step S50, the data frame is composed as follows:

[0096] According to priority order, starting with the highest priority sensor, valid data is read from its memory FIFO buffer. The read data is organized into data frames according to a preset frame format, which includes, in order: frame header, sensor identifier, timestamp, data length, data payload, and checksum.

[0097] The frame header is a fixed byte sequence used by the receiving end to identify the start position of the data frame, and is set to a fixed value of 0xAA55 for two bytes.

[0098] The sensor identifier is a single-byte field used to identify the sensor type from which the data originates. The accelerometer sensor identifier is set to 0x01, the microphone sensor identifier is set to 0x02, and the temperature sensor identifier is set to 0x03.

[0099] The timestamp is a four-byte field that records the time of data acquisition. It is represented by the system tick counter value of the MCU and is used by the receiving end for data timing analysis and multi-sensor data fusion.

[0100] The data length field is two bytes, indicating the number of bytes in the data payload;

[0101] The data payload is the raw byte sequence of valid data, arranged in chronological order of collection time. When multiple sets of data are sent simultaneously, the data payload contains multiple sets of sampled data.

[0102] The checksum is a single-byte field, calculated using an XOR check or cyclic redundancy check algorithm on the frame header, sensor identifier, timestamp, data length, and data payload. It is used by the receiving end to verify the correctness of data transmission.

[0103] In step S50, the process of initiating the transmit DMA to transfer the data frame to the serial port data register is as follows:

[0104] After organizing a data frame, the MCU configures the DMA transmission channel: setting the source address to the data frame start address, the destination address to the serial port data register address, and the transmission length to the total number of bytes in the data frame. Enabling the DMA transmission channel, the DMA controller automatically transmits the data frame to the serial port data register. During DMA transmission, the MCU does not participate in the data transmission process. When a data frame transmission is complete, the DMA controller generates a transmission completion interrupt. Upon responding to the interrupt, the MCU organizes the next data frame according to priority and starts transmission until all valid data from all sensors has been transmitted. If multiple sensors have data to be transmitted simultaneously, the data frames from each sensor are transmitted in a time-division multiplexing manner on the bus, with the start position of each frame distinguished by the frame header.

[0105] The significance of step S50 is understandable: by calculating the transmission priority based on the sampling frequency and the amount of data to be transmitted, data from high-load sensors is transmitted first, effectively preventing data backlog and buffer overflow. The unified frame format design, including frame headers, sensor identifiers, timestamps, checksums, and other information, provides the receiving end with complete data parsing information, supporting accurate differentiation and timing reconstruction of multi-sensor data. The introduction of transmit DMA eliminates CPU involvement in the data transmission process, forming a complete data path with the acquisition DMA. The time-division multiplexing mechanism avoids conflicts between multi-sensor data on the bus, ensuring the stability and reliability of data transmission and enabling effective output of high-frequency multi-sensor data in a bare-metal environment.

[0106] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A bare-metal multi-sensor high-frequency data acquisition and transmission method, characterized in that: Includes the following steps: Step S10: Configure an independent hardware timer for each sensor, independently set the sampling period and overflow time of each sensor, and configure the acquisition DMA channel and the transmission DMA channel. Specifically, the source address of the acquisition DMA channel is set to the sensor data register, and the destination address is set to the start address of the memory FIFO buffer. The source address of the transmission DMA channel is set to the start address of the memory FIFO buffer, and the destination address is set to the serial port data register. In step S10, the specific process of configuring an independent hardware timer for each sensor is as follows: The MCU integrates multiple hardware timer modules, binds each timer to a sensor, enables each timer module through the timer configuration register, sets the working mode to periodic overflow mode, and enables the overflow interrupt bit. The specific process for setting the sampling period and overflow time is as follows: the prescaler register and the auto-reload register are used for setting. The prescaler coefficient determines the timer counting clock frequency. When the count value reaches the auto-reload value, an overflow event is generated. The overflow time is equal to the product of the prescaler coefficient and the auto-reload value divided by the timer input clock frequency. In step S10, the specific process of configuring the acquisition DMA channel and the transmission DMA channel is as follows: allocate acquisition DMA channels according to the number of sensors, with each sensor occupying one acquisition DMA channel and one transmission DMA channel allocated at the same time. When configuring the acquisition DMA channel, set the channel priority to high, the transmission direction to peripheral to memory, the source address to the sensor data register and not increment, the destination address to the starting address of the memory FIFO buffer and increment, the data transmission width to 16 bits or 32 bits, and generate an interrupt when the transmission is completed. When configuring the DMA channel, set the channel priority to medium, the transmission direction to memory to peripheral, the source address to the starting address of the memory FIFO buffer and increment it, the destination address to the serial port data register and not increment it, the data transmission width to 8 bits, and generate an interrupt when the transmission is completed. Step S20: Construct a circular FIFO buffer for each sensor, define the buffer's start address, end address, read pointer, and write pointer, and set the trigger depth threshold for the sensor's internal FIFO; Step S30: When the hardware timer corresponding to each sensor overflows, sampling is triggered. The acquisition DMA transfers the data in the sensor data register to the address pointed to by the write pointer of the corresponding sensor's memory FIFO buffer according to the configuration. In step S30, the sampling process is triggered when the hardware timer corresponding to each sensor overflows: The timer runs independently according to the set sampling period. When the count value reaches the automatic reload value, an overflow event is generated. The overflow event is configured to trigger a DMA request, and the timer sends a request signal to the DMA controller. The DMA transfers data from the sensor data register to the address pointed to by the write pointer in the memory FIFO buffer. The write pointer is automatically incremented after each DMA transfer is completed, and wraps back to the start address when it reaches the end address. Step S40: Read the cached data of each sensor from the address pointed to by the read pointer in the memory FIFO buffer, and determine the validity of the data; In step S50, the data determined to be valid by each sensor are organized into data frames according to a preset transmission order, and the transmission DMA is started to transmit the data frames to the serial port data register.

2. The bare-metal multi-sensor high-frequency acquisition and transmission method according to claim 1, characterized in that: In step S20, the process of constructing a circular FIFO buffer for each sensor is as follows: In the MCU memory, a continuous storage space is allocated for each sensor as a circular FIFO buffer. The buffer capacity is at least f×b×t bytes, where f is the sampling frequency, b is the number of data bytes sampled each time, and t is the maximum response delay allowed by the system. Define the starting address as the first address of the buffer, and the ending address as the starting address plus the total length of the buffer minus one. The read pointer and write pointer initially point to the starting address. Each time data is written or read, the corresponding pointer is incremented. When the ending address is reached, the pointer wraps back to the starting address.

3. The bare-metal multi-sensor high-frequency acquisition and transmission method according to claim 2, characterized in that: In step S20, the process of setting the trigger depth threshold of the sensor's internal FIFO is as follows: The trigger depth threshold is determined by combining the sensor sampling frequency f, the MCU interrupt response delay T_response, and the DMA transfer time T_dma. The time interval between two adjacent samples is T_sample=1 / f. The total delay from when the FIFO data reaches the threshold to when the data is completely read is T_response+T_dma. The trigger depth threshold N satisfies N≥(T_response+T_dma) / T_sample.

4. The bare-metal multi-sensor high-frequency acquisition and transmission method according to claim 1, characterized in that: In step S40, the process of reading the cached data of each sensor from the address pointed to by the read pointer in the memory FIFO buffer is as follows: The data read operation is triggered by the completion of the DMA transfer in step S30. The MCU reads data from the address currently pointed to by the read pointer. After each read is completed, the read pointer is incremented by a step size equal to the data width. When the read pointer is incremented to the end address of the buffer, it wraps back to the start address. The read operation continues until the preset number of reads is reached or the buffer is empty.

5. The bare-metal multi-sensor high-frequency acquisition and transmission method according to claim 4, characterized in that: In step S40, the process of determining data validity is as follows: The preset judgment conditions include multiple types such as data range judgment, data change rate judgment, sensor status judgment, and data continuity judgment; The data range is determined by setting a valid numerical range based on the sensor's measurement range; data outside this range is considered invalid. The rate of change of data is determined when the absolute value of the difference between two adjacent samples exceeds the maximum allowable value, at which point the data is deemed invalid. Sensor status is determined by reading the sensor status register; if the status is abnormal, it is considered invalid. Data continuity is determined by identifying discontinuous data sequences as invalid; data is considered invalid if any determination fails.

6. The bare-metal multi-sensor high-frequency acquisition and transmission method according to claim 1, characterized in that: In step S50, the preset transmission order is calculated and determined based on the sampling frequency of each sensor and the current amount of data to be transmitted. Let the sampling frequency of sensor i be f_i and the amount of data to be transmitted in the current memory FIFO buffer be Q_i. Then the transmission priority score P_i = f_i × Q_i. The P_i values ​​of each sensor are calculated and sorted from largest to smallest. The sensor with the highest score gets the highest transmission priority.

7. The bare-metal multi-sensor high-frequency acquisition and transmission method according to claim 1, characterized in that: In step S50, the specific process of organizing the data determined to be valid by each sensor into data frames according to a preset transmission order, and starting the transmission DMA to transmit the data frames to the serial port data register is as follows: Starting with the highest priority sensor, data deemed valid is read from its memory FIFO buffer and organized into data frames according to a preset frame format. The frame format includes, in order, a frame header, sensor identifier, timestamp, data length, data payload, and checksum. After organizing a frame of data, configure the DMA channel to set the source address to the start address of the data frame, the destination address to the serial port data register address, and the transmission length to the total number of bytes in the data frame, and enable automatic transmission of the DMA channel; when an interrupt is generated after a frame of data transmission is completed, organize the next frame of data according to priority order and start transmission, until all valid data from all sensors have been transmitted.

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