Chip packaging structure modeling method and device, storage medium and computer equipment

Abstract

The application discloses a kind of modeling method and device of chip packaging structure, storage medium, computer equipment, it is related to chip three-dimensional structure simulation analysis technical field, mainly in solving the low reusability and long time-consuming of existing manual modeling method when processing the geometric modeling of small core particles of heterogeneous packaging appear Simulation efficiency low problem caused by, including obtaining the structure distribution characteristics of chip packaging structure to be modeled;Corresponding modeling scheme of the chip packaging structure to be modeled is generated based on pre-set modeling rule and the structure distribution characteristics;The structure parameter characteristics of the chip packaging structure to be modeled are acquired;And the chip packaging structure to be modeled is modeled based on the modeling scheme and the structure parameter characteristics processing, obtains target chip packaging structure model.

Description

Technical Field

[0001] This invention relates to the field of chip three-dimensional structure simulation and analysis technology, and in particular to a chip packaging structure modeling method and apparatus, storage medium, and computer equipment. Background Technology

[0002] During the chip design phase, structural simulation of the packaged chip is necessary to analyze its performance and ensure that the design meets performance requirements. Chip structural simulation typically includes steps such as geometric modeling and load application.

[0003] Currently, manual modeling is commonly used in simulation software during the geometric modeling stage of chips. However, this method is more useful for models with simple structures and small size differences. For small chips with complex structures and heterogeneous packages, the reusability of the model is very low, and manual modeling is time-consuming, seriously affecting simulation efficiency. Summary of the Invention

[0004] In view of this, the present invention provides a modeling method and apparatus for chip packaging structures, a storage medium, and a computer device. The main purpose is to solve the problems of low reusability and long simulation efficiency caused by the long time consumption when the existing manual modeling method is used to process the geometric modeling of small chips in heterogeneous packaging.

[0005] According to one aspect of the present invention, a method for modeling a chip package structure is provided, comprising:

[0006] Obtain the structural distribution characteristics of the chip packaging structure to be modeled; the structural distribution characteristics include component arrangement rules, component stacking methods, and component connection relationships.

[0007] A modeling scheme corresponding to the chip packaging structure to be modeled is generated based on preset modeling rules and the structural distribution features.

[0008] Obtain the structural parameter features of the chip package structure to be modeled; and perform modeling processing on the chip package structure to be modeled based on the modeling scheme and the structural parameter features to obtain the target chip package structure model.

[0009] Furthermore, the preset modeling rules include overall structure modeling rules, component modeling rules, and part modeling rules;

[0010] The step of generating a modeling scheme corresponding to the chip packaging structure to be modeled based on preset modeling rules and the structural distribution features includes:

[0011] The modeling order between components is determined based on the overall structural modeling rules and the component arrangement rules.

[0012] The internal modeling order of a component is determined based on the component modeling rules and the component stacking method;

[0013] The component modeling order is determined based on the component modeling rules and the component connection relationships;

[0014] The modeling order between the components, the modeling order within the components, and the modeling order of the parts are integrated to obtain the modeling scheme corresponding to the chip packaging structure to be modeled.

[0015] Furthermore, the component stacking method includes an array structure;

[0016] When the component stacking method is the array structure, the internal modeling order of the components is determined based on the component modeling rules and the component stacking method, including:

[0017] Establish a single component;

[0018] Based on the single component, an internal array model of the first component is established using the first array method;

[0019] The second component's internal array model is established based on the first component's internal array model using a second array method.

[0020] Furthermore, the component stacking method includes a layered structure;

[0021] When the component stacking method is the layered structure, the internal modeling order of the component is determined based on the component modeling rules and the component stacking method, including:

[0022] Establish an overall structural model for the components;

[0023] The overall structural model is segmented using a segmentation method to obtain the internal stacked model of the components.

[0024] Furthermore, the component connection relationship includes a component nesting structure;

[0025] When the component connection relationship is a nested structure, the component modeling order is determined based on the component modeling rules and the component connection relationship, including:

[0026] The components in the nested structure are modeled from the inside out to obtain a nested structure model carrying interference geometry.

[0027] The Boolean method is used to remove duplicates from the interference geometry in the nested structure model to obtain the target nested structure model.

[0028] Furthermore, the structural parameter features include component parameters, component orientation information, and component shape and size information;

[0029] The process of modeling the chip packaging structure to be modeled based on the modeling scheme and the structural parameter features includes:

[0030] Establish a three-dimensional coordinate system, and determine the corresponding component positions of each component structure in the three-dimensional coordinate system based on the component orientation information;

[0031] The chip packaging structure to be modeled is modeled according to the modeling sequence in the modeling scheme, combined with the component parameters, the shape and size information of the component, and the position of the component.

[0032] Furthermore, the method also includes filler glue modeling processing, including:

[0033] Determine the filler adhesive layer of the chip packaging structure to be modeled; and determine the main dimensions of the filler adhesive layer based on the upper structure dimensions of the filler adhesive layer.

[0034] A main model of the filler adhesive layer is established based on its main dimensions, and the Boolean method is used to remove interference geometry from the main model of the filler adhesive layer.

[0035] The overflow edge model of the filler glue is created by sweeping a triangle around the side of the main body model.

[0036] According to another aspect of the present invention, a modeling apparatus for a chip package structure is provided, comprising:

[0037] The acquisition module is used to acquire the structural distribution characteristics of the chip packaging structure to be modeled; the structural distribution characteristics include the component arrangement pattern, component stacking method, and component connection relationship.

[0038] The scheme generation module is used to generate a modeling scheme corresponding to the chip packaging structure to be modeled based on preset modeling rules and the structural distribution features.

[0039] The modeling processing module is used to obtain the structural parameter features of the chip package structure to be modeled; and to perform modeling processing on the chip package structure to be modeled based on the modeling scheme and the structural parameter features to obtain the target chip package structure model.

[0040] Furthermore, the preset modeling rules include overall structure modeling rules, component modeling rules, and part modeling rules; the scheme generation module is also used for:

[0041] The modeling order between components is determined based on the overall structural modeling rules and the component arrangement rules.

[0042] The internal modeling order of a component is determined based on the component modeling rules and the component stacking method;

[0043] The component modeling order is determined based on the component modeling rules and the component connection relationships;

[0044] The modeling order between the components, the modeling order within the components, and the modeling order of the parts are integrated to obtain the modeling scheme corresponding to the chip packaging structure to be modeled.

[0045] Furthermore, the component stacking method includes an array structure; when the component stacking method is the array structure, the scheme generation module is further configured to:

[0046] Establish a single component;

[0047] Based on the single component, an internal array model of the first component is established using the first array method;

[0048] The second component's internal array model is established based on the first component's internal array model using a second array method.

[0049] Furthermore, the component stacking method includes a layered structure; when the component stacking method is the layered structure, the solution generation module is further configured to:

[0050] Establish an overall structural model for the components;

[0051] The overall structural model is segmented using a segmentation method to obtain the internal stacked model of the components.

[0052] Furthermore, the component connection relationship includes a component nesting structure; when the component connection relationship is the component nesting structure, the solution generation module is further used to:

[0053] The components in the nested structure are modeled from the inside out to obtain a nested structure model carrying interference geometry.

[0054] The Boolean method is used to remove duplicates from the interference geometry in the nested structure model to obtain the target nested structure model.

[0055] Furthermore, the structural parameter features include component parameters, component orientation information, and component shape and size information; the modeling processing module is also used for:

[0056] Establish a three-dimensional coordinate system, and determine the corresponding component positions of each component structure in the three-dimensional coordinate system based on the component orientation information;

[0057] The chip packaging structure to be modeled is modeled according to the modeling sequence in the modeling scheme, combined with the component parameters, the shape and size information of the component, and the position of the component.

[0058] Furthermore, the modeling processing module also includes a filler glue processing unit, which is used for:

[0059] Determine the filler adhesive layer of the chip packaging structure to be modeled; and determine the main dimensions of the filler adhesive layer based on the upper structure dimensions of the filler adhesive layer.

[0060] A main model of the filler adhesive layer is established based on its main dimensions, and the Boolean method is used to remove interference geometry from the main model of the filler adhesive layer.

[0061] The overflow edge model of the filler glue is created by sweeping a triangle around the side of the main body model.

[0062] According to another aspect of the present invention, a storage medium is provided, wherein at least one executable instruction is stored therein, the executable instruction causing a processor to perform an operation corresponding to the modeling method of the chip package structure described above.

[0063] According to another aspect of the present invention, a computer device is provided, including a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus;

[0064] The memory is used to store at least one executable instruction, which causes the processor to perform operations corresponding to the modeling method of the chip package structure described above.

[0065] By employing the above-described technical solutions, the technical solutions provided by the embodiments of the present invention have at least the following advantages:

[0066] This invention provides a method and apparatus for modeling chip package structures, a storage medium, and a computer device. Compared with existing technologies, this invention obtains the structural distribution characteristics of the chip package structure to be modeled, generates a modeling scheme corresponding to the chip package structure based on preset modeling rules and the structural distribution characteristics, obtains the structural parameter characteristics of the chip package structure to be modeled, and performs modeling processing on the chip package structure to be modeled based on the modeling scheme and the structural parameter characteristics to obtain the target chip package structure model. This achieves automatic modeling processing of chip package structures and improves the modeling efficiency of chip package structures. Furthermore, the method of this invention is also applicable to modeling chip package structures in heterogeneous scenarios, no longer affected by the complexity of the chip package structure, ensuring the efficiency of subsequent simulation of the chip package structure.

[0067] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0068] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0069] Figure 1 A schematic flowchart of a chip packaging structure modeling method provided by an embodiment of the present invention is shown;

[0070] Figure 2 This diagram shows a cross-sectional view of a chip packaging structure to be modeled according to an embodiment of the present invention.

[0071] Figure 3 This figure shows a top view of a chip package structure to be modeled according to an embodiment of the present invention;

[0072] Figure 4 A flowchart illustrating another chip packaging structure modeling method provided by an embodiment of the present invention is shown;

[0073] Figure 5 A flowchart illustrating another chip packaging structure modeling method provided by an embodiment of the present invention is shown;

[0074] Figure 6 A flowchart illustrating another chip packaging structure modeling method provided in an embodiment of the present invention is shown;

[0075] Figure 7 A flowchart illustrating another chip packaging structure modeling method provided in an embodiment of the present invention is shown;

[0076] Figure 8 This is a schematic projection of a model of overflowing filler glue provided in an embodiment of the present invention;

[0077] Figure 9 This diagram illustrates a modeling apparatus for a chip packaging structure provided in an embodiment of the present invention.

[0078] Figure 10 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention is shown. Detailed Implementation

[0079] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0080] This invention provides a method for modeling chip packaging structures, such as... Figure 1 As shown, the method includes:

[0081] 101. Obtain the structural distribution characteristics of the chip packaging structure to be modeled; the structural distribution characteristics include the component arrangement pattern, component stacking method, and component connection relationship;

[0082] In this embodiment of the invention, the current execution terminal obtains the structural distribution features of the chip packaging structure to be modeled, in order to Figure 2 Taking the chip packaging structure to be modeled as an example, the component arrangement in the structural distribution features is as follows from bottom to top: printed circuit board assembly, solder ball assembly, substrate assembly, solder ball assembly, adapter board assembly, bump assembly, and chip assembly; the corresponding component stacking methods include array structure and layered structure. For example, the stacking method of the printed circuit board assembly, substrate assembly, and adapter board assembly all belong to the layered structure; the stacking method of the solder ball assembly, bump assembly, and chip assembly all belong to the array structure. This embodiment of the invention does not make specific limitations. Figure 2 As shown, the component connection relationships in the chip packaging structure to be modeled include: a nested relationship between the chip and the molding compound; a nested relationship between the chip and the adapter board connected by filler glue, with the bumps between the chip and the adapter board and the filler glue being nested; a nested relationship between the adapter board and the substrate connected by filler glue, with the solder balls between the adapter board and the substrate and the filler glue being nested; and a nested relationship between the substrate and the printed circuit board connected by filler glue, with the solder balls between the substrate and the printed circuit board and the filler glue being nested, etc. The embodiments of the present invention do not impose specific limitations.

[0083] 102. Generate a modeling scheme corresponding to the chip packaging structure to be modeled based on preset modeling rules and the structural distribution features;

[0084] In this embodiment of the invention, the current execution terminal generates a modeling scheme corresponding to the chip packaging structure to be modeled based on preset modeling rules and the structural distribution features obtained in step 101. The preset modeling rules can be set according to the modeling experience of relevant personnel, and are not specifically limited in this embodiment of the invention.

[0085] 103. Obtain the structural parameter features of the chip packaging structure to be modeled; and perform modeling processing on the chip packaging structure to be modeled based on the modeling scheme and the structural parameter features to obtain the target chip packaging structure model.

[0086] In this embodiment of the invention, the current execution terminal acquires the structural parameter features of the chip packaging structure to be modeled. These structural parameter features include component parameters, component orientation information, and component shape and size information, etc., which are not specifically limited in this embodiment. The structural parameter features can be stored in the form of multiple tables, as shown in Tables 1, 2, 3, 4, 5, and 6 below:

[0087] Table 1 Component Parameter Table

[0088] part shape Length (mm) Width (mm) Depth (mm) quantity molding compound cuboid 22 20 0.85 4 chip cuboid 5.6 5.3 0.37 144 Filler glue 1 + bump 1 cuboid 20 18 0.04 4 Adapter board cuboid 22 20 0.04 4 2 filler glues + 2 solder balls cuboid 22 20 0.12 4 substrate cuboid 24 22 0.08 4 3 filler glues + 3 solder balls cuboid 24 22 0.12 4 Printed Circuit Board cuboid 52 50 1.2 1

[0089] As can be seen from the component parameter table 1 above, the chip assembly consists of 144 small chip components. The chip dimensions are 5.6mm in length, 5.3mm in width, and 0.37mm in depth, etc. This embodiment of the invention does not impose specific limitations.

[0090] Table 2 Component Location Information

[0091] Component distance from origin x-direction (mm) y direction(mm) z-direction (mm) molding compound 1.2 1.2 1.56 chip 2.2 2.2 1.6 Filler glue 1 + bump 1 2.2 2.2 1.56 Adapter board 2 2 1.52 2 filler glues + 2 solder balls 1 1 1.4 substrate 0 0 1.32 3 filler glues + 3 solder balls 1 1 1.2 Printed Circuit Board 0 0 0

[0092] As shown in Table 2 above, the distances of the chips from the origin of the coordinate system are 2.2 mm in the x-direction, 2.2 mm in the y-direction, and 1.6 mm in the z-direction. Furthermore, the spacing between chips is 0.75 mm in the x-direction and 0.8 mm in the y-direction, etc., but this embodiment of the invention does not impose specific limitations.

[0093] Table 3. Array parameters of the 36 chips in each chip group.

[0094]

[0095] Table 4 Array Parameters of the Four Chip Groups

[0096]

[0097] Table 5. Array parameters for bumps and solder balls.

[0098]

[0099] Table 6. Array parameters for four groups of bumps and solder balls.

[0100]

[0101]

[0102] Next, the current execution end performs modeling processing on the chip package structure to be modeled based on the modeling scheme generated in step 102 and the aforementioned structural parameter features, to obtain the target chip package structure model. The specific modeling process includes:

[0103] (1) Establish a three-dimensional coordinate system and determine the corresponding component position of each component structure in the three-dimensional coordinate system based on the component orientation information; for example, the distance of the chip component from the origin of the coordinate system is 2.2mm in the x direction, 2.2mm in the y direction, and 1.6mm in the z direction, etc. The embodiments of the present invention do not make specific limitations.

[0104] (2) Following the modeling order in the modeling scheme, the chip packaging structure to be modeled is modeled by combining the component parameters, the shape and size information of the component and the position of the component, so as to obtain the target chip packaging structure model.

[0105] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, to further clarify the process of determining the modeling scheme, another modeling method for chip packaging structures is provided. This method includes preset modeling rules such as overall structure modeling rules, component modeling rules, and part modeling rules; for example... Figure 4 As shown, the steps involve generating a modeling scheme corresponding to the chip packaging structure to be modeled based on preset modeling rules and the structural distribution features, including:

[0106] 201. Determine the modeling order between components based on the overall structure modeling rules and the component arrangement rules;

[0107] In this embodiment of the invention, the current execution terminal obtains the overall structure modeling rule from the preset modeling rules. The overall structure modeling rule represents a preset rule for the overall modeling order of the chip package structure, such as a bottom-up overall structure modeling rule, a left-to-right overall structure modeling rule, a right-to-left overall structure modeling rule, etc., which are not specifically limited in this embodiment. After obtaining the overall structure modeling rule, the current execution terminal determines the modeling order between components based on the overall structure modeling rule and the component arrangement rules. For example, when the overall structure modeling rule is bottom-up, the modeling order between the components of the chip package structure to be modeled, as shown in Figure 2, is as follows: printed circuit board assembly, solder ball assembly, substrate assembly, solder ball assembly, adapter board assembly, bump assembly, and chip assembly. This is not specifically limited in this embodiment.

[0108] 202. Determine the internal modeling order of the components based on the component modeling rules and the component stacking method;

[0109] In this embodiment of the invention, the current execution terminal obtains component modeling rules from preset modeling rules. These component modeling rules include preset rules for the modeling order of different types of components. For example, for components arranged in a horizontal pattern, a preset modeling method combining single-part modeling with array and rotation / mirroring is used; for stacked structures with regular shapes, a preset rule using single large geometric modeling and multiple segmentation is used, etc. This embodiment of the invention does not impose specific limitations. After obtaining the component modeling rules, the current execution terminal determines the internal modeling order of the component based on the component modeling rules and the component stacking method. The internal modeling order of the component represents the modeling order of each part within the corresponding component, such as... Figure 2 As shown, the chip assembly includes 144 small chips. The modeling order within the assembly determines the modeling order of the 144 small chips within the chip assembly, etc., and this embodiment of the invention does not impose specific limitations.

[0110] 203. Determine the component modeling order based on the component modeling rules and the component connection relationships;

[0111] In this embodiment of the invention, the current execution terminal obtains component modeling rules from the preset modeling rules. Component modeling rules represent preset rules for the modeling order of components other than those involved in the aforementioned components. For example, for irregularly shaped components, a component segmentation approach may be adopted, establishing preset rules for segmented components in multiple stages. This embodiment of the invention does not impose specific limitations. Components other than those involved in the aforementioned components include... Figure 2 The molding compound, filler, etc., used in this embodiment are not specifically limited. After obtaining the component modeling rules, the current execution end determines the component modeling order based on the component modeling rules and component connection relationships; this embodiment is not specifically limited.

[0112] 204. Integrate the modeling order between the components, the modeling order within the components, and the modeling order of the parts to obtain the modeling scheme corresponding to the chip packaging structure to be modeled.

[0113] In this embodiment of the invention, the current execution end integrates the modeling order between components, the modeling order within components, and the modeling order of parts obtained in steps 201 to 203 to obtain a modeling scheme corresponding to the chip packaging structure to be modeled.

[0114] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to improve modeling efficiency, another modeling method for chip packaging structures is provided, in which the component stacking method includes an array structure; such as Figure 5 As shown, when the component stacking method is the array structure, the step of determining the internal modeling order of the components based on the component modeling rules and the component stacking method includes:

[0115] 301. Establish a single component;

[0116] For example Figure 3 The chip package structure shown contains 144 small chips. If each small chip is modeled sequentially based on its distance from the origin and its size, a significant amount of modeling time would be required. Figure 3 As can be seen, the 144 small chips in the chip assembly are divided into 4 groups, and each group contains 6*6=36 small chip components. These 36 small chip components are arranged horizontally in a regular pattern, and their spacing is shown in Table 3.

[0117] In this embodiment of the invention, the current execution end can first use the spaceclaim command `BlockBody.Create()` to create a single chip. The specific command is as follows:

[0118] DIE=BlockBody.Create(Point.Create(NM(2.2),NM(2.2),

[0119] NM(1.6)),Point.Create(NM(2.2+5.6),NM(2.2+5.3),

[0120] NM(1.6+0.37)),extrudeMode=ExtrudeType.ForceIndependent)

[0121] 302. Based on the single component, an internal array model of the first component is established using a first array method;

[0122] In this embodiment of the invention, the current execution end further establishes an internal array model of the first component based on a single component using a first array method. For example, the command to establish 36 chips using Python array commands is as follows:

[0123]

[0124] The array command for 36 chips is as follows:

[0125] DIEs_CName = ["DIE"]

[0126] DIEs_X=[MM(6.15),MM(6.15),MM(6.15),MM(6.15),MM(6.15)]

[0127] DIEs_Y=[MM(5.74),MM(5.74),MM(5.74),MM(5.74),MM(5.74)]

[0128] for name in DIEs_CName:

[0129] ComponentArray(name,XOffset=DIEs_X,YOffset=DIEs_Y)

[0130] 303. Based on the internal array model of the first component, a second array method is used to establish the internal array model of the second component.

[0131] In this embodiment of the invention, the current execution terminal establishes a second component internal array model based on the aforementioned first component internal array model using a second array method. For example, using the second array method, 36*4=144 chips are established. The specific array command for 144 chips is as follows:

[0132] DIEs_CName = ["DIE"]

[0133] DIEs_X=[MM(26)]

[0134] DIEs_Y = [MM(25)]

[0135] for name in DIEs_CName:

[0136] ComponentArray(name,XOffset=DIEs_X,YOffset=DIEs_Y)

[0137] The above describes the modeling method for chip components. The modeling of other array structures is similar to that of chip components, such as solder ball components and bump components. The embodiments of the present invention do not impose specific limitations.

[0138] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to improve modeling efficiency, another modeling method for chip packaging structures is provided, in which the component stacking method includes a layered structure; such as Figure 6 As shown, when the component stacking method is the layered structure, the step of determining the internal modeling order of the component based on the component modeling rules and the component stacking method includes:

[0139] 401. Establish the overall structural model of the components;

[0140] Modeling a multilayer structure can be time-consuming if each layer is modeled sequentially based on its distance from the origin and its dimensions. For example, a transition board assembly may contain multiple internal metal and dielectric layers. Modeling each layer individually would reduce efficiency.

[0141] In this embodiment of the invention, the current execution end first establishes an overall component structure model. Taking an adapter board as an example, a cuboid naming flow is first created using spaceclaim to automatically establish the overall component structure model of the adapter board component. The specific commands are as follows:

[0142] Interposer=BlockBody.Create(Point.Create(NM(2),NM(2),

[0143] NM(1.52)),Point.Create(NM(2+22),NM(2+20),

[0144] NM(1.52+0.04)),extrudeMode=ExtrudeType.ForceIndependent)

[0145] 402. The overall structural model is segmented using a segmentation method to obtain the internal stacked model of the component.

[0146] In this embodiment of the invention, the current execution end uses a segmentation method to segment the overall structural model to obtain the internal stack-up model of the component. For example, the overall structural model of the adapter board component obtained in step 401 is cut multiple times along the depth z direction to segment the overall structural model of the adapter board component into dielectric layers, metal layers, etc., with the cutting size set to 0.01mm. The specific cutting command is as follows:

[0147]

[0148] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to further improve the efficiency of modeling, another modeling method for chip packaging structures is provided, in which the component connection relationship includes a component nesting structure; such as Figure 7 As shown, when the component connection relationship is a nested structure, the steps for determining the component modeling order based on the component modeling rules and the component connection relationship include:

[0149] 501. Model each component in the nested structure from the inside out to obtain a nested structure model carrying interference geometry;

[0150] In this embodiment of the invention, the current execution end performs component modeling processing on each component in the component nesting structure in an order from the inside out, such as... Figure 2 As shown, for the nested structure of chip and molding compound, the chip assembly model is first established according to the method of steps 301 to 303, and then the molding compound model is established outside the chip assembly model to obtain the nested structure model carrying interference geometry. This embodiment of the invention does not make specific limitations.

[0151] 502. Use the Boolean method to remove duplicates from the interference geometry in the nested structure model to obtain the target nested structure model.

[0152] In this embodiment of the invention, the current execution end can use Boolean algorithm to remove duplicate interference geometry from the nested structure model containing interference geometry, thereby obtaining a target nested structure model without interference geometry. For example, for interference geometry in the nested structure of chip and molding compound, multiple Boolean operations are used to remove overlapping parts in the nested structure model. Specifically, the `spaceclaim.result = Combine.Intersect(targets,tools,options)` command is used to remove interference geometry, as follows:

[0153]

[0154]

[0155] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to further clarify the modeling sequence of irregularly shaped structures and improve modeling efficiency, another modeling method for chip packaging structures is provided. This method further includes filler modeling processing, including:

[0156] Determine the filler adhesive layer of the chip packaging structure to be modeled; and determine the main dimensions of the filler adhesive layer based on the upper structure dimensions of the filler adhesive layer.

[0157] In this embodiment of the invention, the current execution end determines the filler layer in the chip packaging structure to be modeled based on structural distribution characteristics, obtains the upper structure dimensions of the filler layer, and determines the main body dimensions of the current filler layer based on the upper structure dimensions. For example... Figure 2 As shown, the upper structure of the filler adhesive 2 is the adapter plate 1. The main body size of the filler adhesive 2 is determined by the size of the adapter plate 1. Referring to Table 1, the length of the filler adhesive 2 is equal to the length of the adapter plate, which is 22mm, and the width of the filler adhesive 2 is equal to the width of the adapter plate, which is 20mm, etc. The embodiments of the present invention do not make specific limitations.

[0158] A main model of the filler adhesive layer is established based on its main dimensions, and the Boolean method is used to remove interference geometry from the main model of the filler adhesive layer.

[0159] In this embodiment of the invention, the current execution end establishes a main body model of the filler adhesive based on the main body size and thickness of the filler adhesive. The specific steps are the same as those in step 401 for establishing the cuboid structure, and this embodiment of the invention does not impose specific limitations. Since there are interference geometries between the filler adhesive layer and the bump assembly or solder ball assembly, in this embodiment of the invention, the current execution end also needs to use the same method as in steps 501 to 502, that is, to use multiple Boolean methods to remove the interference geometries in the main body model of the filler adhesive.

[0160] The overflow edge model of the filler glue is created by sweeping a triangle around the side of the main body model.

[0161] In this embodiment of the invention, the current execution end constructs triangles on the sides of the filler glue main body model, i.e., on the xoz plane in the three-dimensional coordinate system. Then, it uses a triangle sweeping method to construct the filler glue overflow edge model around the four sides of the filler glue main body model. Figure 2 Taking filler glue 3 as an example, the projection of the filler glue overflow edge model is as follows: Figure 8 As shown.

[0162] This invention provides a method for modeling chip package structures. Compared with existing technologies, this invention obtains the structural distribution characteristics of the chip package structure to be modeled, generates a modeling scheme corresponding to the chip package structure based on preset modeling rules and the structural distribution characteristics, obtains the structural parameter characteristics of the chip package structure to be modeled, and performs modeling processing on the chip package structure to be modeled based on the modeling scheme and the structural parameter characteristics to obtain the target chip package structure model. This achieves automatic modeling processing of chip package structures and improves the modeling efficiency of chip package structures. Furthermore, the method of this invention is also applicable to modeling chip package structures in heterogeneous scenarios, no longer affected by the complexity of the chip package structure, ensuring the efficiency of subsequent simulation of the chip package structure.

[0163] As a response to the above Figure 1 The implementation of the method shown in this invention provides a modeling device for chip packaging structures, such as... Figure 9 As shown, the device includes:

[0164] The acquisition module 61 is used to acquire the structural distribution features of the chip packaging structure to be modeled; the structural distribution features include the component arrangement pattern, component stacking method, and component connection relationship.

[0165] The scheme generation module 62 is used to generate a modeling scheme corresponding to the chip packaging structure to be modeled based on preset modeling rules and the structural distribution features.

[0166] The modeling processing module 63 is used to obtain the structural parameter features of the chip packaging structure to be modeled; and to perform modeling processing on the chip packaging structure to be modeled based on the modeling scheme and the structural parameter features to obtain the target chip packaging structure model.

[0167] Furthermore, the preset modeling rules include overall structure modeling rules, component modeling rules, and part modeling rules; the scheme generation module 62 is also used for:

[0168] The modeling order between components is determined based on the overall structural modeling rules and the component arrangement rules.

[0169] The internal modeling order of a component is determined based on the component modeling rules and the component stacking method;

[0170] The component modeling order is determined based on the component modeling rules and the component connection relationships;

[0171] The modeling order between the components, the modeling order within the components, and the modeling order of the parts are integrated to obtain the modeling scheme corresponding to the chip packaging structure to be modeled.

[0172] Furthermore, the component stacking method includes an array structure; when the component stacking method is the array structure, the scheme generation module 62 is further configured to:

[0173] Establish a single component;

[0174] Based on the single component, an internal array model of the first component is established using the first array method;

[0175] The second component's internal array model is established based on the first component's internal array model using a second array method.

[0176] Furthermore, the component stacking method includes a layered structure; when the component stacking method is the layered structure, the scheme generation module 62 is further configured to:

[0177] Establish an overall structural model for the components;

[0178] The overall structural model is segmented using a segmentation method to obtain the internal stacked model of the components.

[0179] Furthermore, the component connection relationship includes a component nesting structure; when the component connection relationship is the component nesting structure, the scheme generation module 62 is further configured to:

[0180] The components in the nested structure are modeled from the inside out to obtain a nested structure model carrying interference geometry.

[0181] The Boolean method is used to remove duplicates from the interference geometry in the nested structure model to obtain the target nested structure model.

[0182] Furthermore, the structural parameter features include component parameters, component orientation information, and component shape and size information; the modeling processing module 63 is also used for:

[0183] Establish a three-dimensional coordinate system, and determine the corresponding component positions of each component structure in the three-dimensional coordinate system based on the component orientation information;

[0184] The chip packaging structure to be modeled is modeled according to the modeling sequence in the modeling scheme, combined with the component parameters, the shape and size information of the component, and the position of the component.

[0185] Furthermore, the modeling processing module 63 also includes a filler glue processing unit, which is used for:

[0186] Determine the filler adhesive layer of the chip packaging structure to be modeled; and determine the main dimensions of the filler adhesive layer based on the upper structure dimensions of the filler adhesive layer.

[0187] A main model of the filler adhesive layer is established based on its main dimensions, and the Boolean method is used to remove interference geometry from the main model of the filler adhesive layer.

[0188] The overflow edge model of the filler glue is created by sweeping a triangle around the side of the main body model.

[0189] This invention provides a modeling device for chip packaging structures. Compared with existing technologies, this invention obtains the structural distribution characteristics of the chip packaging structure to be modeled, generates a modeling scheme corresponding to the chip packaging structure based on preset modeling rules and the structural distribution characteristics, obtains the structural parameter characteristics of the chip packaging structure to be modeled, and performs modeling processing on the chip packaging structure to be modeled based on the modeling scheme and the structural parameter characteristics to obtain a target chip packaging structure model. This achieves automatic modeling processing of chip packaging structures and improves the modeling efficiency of chip packaging structures. Furthermore, the method of this invention is also applicable to modeling chip packaging structures in heterogeneous scenarios, no longer affected by the complexity of the chip packaging structure, ensuring the efficiency of subsequent simulation of the chip packaging structure.

[0190] According to one embodiment of the present invention, a storage medium is provided, the storage medium storing at least one executable instruction, the computer executable instruction being able to execute the chip packaging structure modeling method in any of the above method embodiments.

[0191] Figure 10The diagram illustrates a structural schematic of a computer device according to an embodiment of the present invention. The specific embodiments of the present invention do not limit the specific implementation of the computer device.

[0192] like Figure 10 As shown, the computer device may include: a processor 702, a communications interface 704, a memory 706, and a communications bus 708.

[0193] The processor 702, communication interface 704, and memory 706 communicate with each other via communication bus 708.

[0194] The communication interface 704 is used to communicate with other network elements such as clients or other servers.

[0195] The processor 702 is used to execute program 710, which can specifically perform the relevant steps of the modeling method for the chip package structure described above.

[0196] Specifically, program 710 may include program code that includes computer operation instructions.

[0197] Processor 702 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. The computer device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or they may be processors of different types, such as one or more CPUs and one or more ASICs.

[0198] Memory 706 is used to store program 710. Memory 706 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0199] Specifically, program 710 can be used to cause processor 702 to perform the following operations:

[0200] Obtain the structural distribution characteristics of the chip packaging structure to be modeled; the structural distribution characteristics include component arrangement rules, component stacking methods, and component connection relationships.

[0201] A modeling scheme corresponding to the chip packaging structure to be modeled is generated based on preset modeling rules and the structural distribution features.

[0202] Obtain the structural parameter features of the chip package structure to be modeled; and perform modeling processing on the chip package structure to be modeled based on the modeling scheme and the structural parameter features to obtain the target chip package structure model.

[0203] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0204] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for modeling a chip packaging structure, characterized in that, include: Obtain the structural distribution characteristics of the chip packaging structure to be modeled; The structural distribution characteristics include the component arrangement pattern, component stacking method, and component connection relationship; A modeling scheme corresponding to the chip packaging structure to be modeled is generated based on preset modeling rules and the structural distribution features. Obtain the structural parameter features of the chip packaging structure to be modeled; Based on the modeling scheme and the structural parameter features, the chip packaging structure to be modeled is modeled to obtain the target chip packaging structure model.

2. The method according to claim 1, characterized in that, The preset modeling rules include overall structure modeling rules, component modeling rules, and part modeling rules; The step of generating a modeling scheme corresponding to the chip packaging structure to be modeled based on preset modeling rules and the structural distribution features includes: The modeling order between components is determined based on the overall structural modeling rules and the component arrangement rules. The internal modeling order of a component is determined based on the component modeling rules and the component stacking method. The component modeling order is determined based on the component modeling rules and the component connection relationships; The modeling order between the components, the modeling order within the components, and the modeling order of the parts are integrated to obtain the modeling scheme corresponding to the chip packaging structure to be modeled.

3. The method according to claim 2, characterized in that, The component stacking method includes an array structure; When the component stacking method is the array structure, the internal modeling order of the components is determined based on the component modeling rules and the component stacking method, including: Establish a single component; Based on the single component, an internal array model of the first component is established using the first array method; The second component's internal array model is established based on the first component's internal array model using a second array method.

4. The method according to claim 2, characterized in that, The component stacking method includes a layered structure; When the component stacking method is the layered structure, the internal modeling order of the component is determined based on the component modeling rules and the component stacking method, including: Establish an overall structural model for the components; The overall structural model is segmented using a segmentation method to obtain the internal stacked model of the components.

5. The method according to claim 2, characterized in that, The component connection relationship includes a component nesting structure; When the component connection relationship is a nested structure, the component modeling order is determined based on the component modeling rules and the component connection relationship, including: The components in the nested structure are modeled from the inside out to obtain a nested structure model carrying interference geometry. The Boolean method is used to remove duplicates from the interference geometry in the nested structure model to obtain the target nested structure model.

6. The method according to claim 1, characterized in that, The structural parameter features include component parameters, component orientation information, and component shape and size information; The process of modeling the chip packaging structure to be modeled based on the modeling scheme and the structural parameter features includes: Establish a three-dimensional coordinate system, and determine the corresponding component positions of each component structure in the three-dimensional coordinate system based on the component orientation information; The chip packaging structure to be modeled is modeled according to the modeling sequence in the modeling scheme, combined with the component parameters, the shape and size information of the component, and the position of the component.

7. The method according to any one of claims 1 to 6, characterized in that, The method also includes filler glue modeling processing, including: Determine the filler adhesive layer of the chip packaging structure to be modeled; and determine the main dimensions of the filler adhesive layer based on the upper structure dimensions of the filler adhesive layer. A main model of the filler adhesive layer is established based on its main dimensions, and the Boolean method is used to remove interference geometry from the main model of the filler adhesive layer. The overflow edge model of the filler glue is created by sweeping a triangle around the side of the main body model.

8. A modeling device for chip packaging structures, characterized in that, include: The acquisition module is used to acquire the structural distribution characteristics of the chip packaging structure to be modeled. The structural distribution characteristics include the component arrangement pattern, component stacking method, and component connection relationship; The scheme generation module is used to generate a modeling scheme corresponding to the chip packaging structure to be modeled based on preset modeling rules and the structural distribution features. The modeling processing module is used to obtain the structural parameter features of the chip packaging structure to be modeled. Based on the modeling scheme and the structural parameter features, the chip packaging structure to be modeled is modeled to obtain the target chip packaging structure model.

9. A storage medium storing at least one executable instruction that performs an operation corresponding to the chip package structure modeling method as described in any one of claims 1-7.

10. A computer device, comprising a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the chip package structure modeling method as described in any one of claims 1-7.

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