Chip interface automatic inspection method, electronic device and medium
By constructing a chip interface inspection data structure and generating assertion code, automated chip interface inspection is achieved, solving the problem of low efficiency in chip interface inspection and improving the efficiency and accuracy of chip development.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-14
AI Technical Summary
In existing technologies, chip interface inspection is inefficient and prone to errors, which reduces chip development efficiency and accuracy. In particular, it is difficult to bind verification components and write attribute information for each chip interface individually in system-on-a-chip.
The chip interface inspection data structure IFC is constructed, attribute information is inserted into the chip code, and assertion code is generated to perform X-state, Z-state and bus protocol checks to achieve automated inspection.
This improves the efficiency and accuracy of chip interface inspection, thereby enhancing the efficiency and accuracy of chip development.
Smart Images
Figure CN122389764A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to an automatic chip interface inspection method, electronic device, and medium. Background Technology
[0002] During chip development, chip interfaces need to be inspected for debugging. For complex System-on-Chips (SoCs), it's difficult to bind a verification component to each chip interface for inspection. Furthermore, inspecting chip interfaces typically requires setting corresponding attribute information, which becomes increasingly complex as the number of chip interfaces grows. Current technologies require writing code for each individual chip interface to set its attributes. This process involves a large amount of repetitive coding, is inefficient, and prone to errors, reducing the efficiency and accuracy of chip interface inspection and consequently impacting chip development efficiency and accuracy. Therefore, improving the efficiency and accuracy of chip interface inspection is a pressing technical problem that needs to be addressed. Summary of the Invention
[0003] The purpose of this invention is to provide an automatic chip interface inspection method, electronic device, and medium, which improves the efficiency and accuracy of chip interface inspection.
[0004] According to a first aspect of the present invention, an automatic chip interface inspection method is provided, comprising: Step S1: Construct the chip interface check data structure IFC={B1,B2,B3,B4,B5}, where B1 is the chip interface clock information, B2 is the chip interface reset information, B3 is the chip interface root clock information, B4 is the chip interface root reset information, and B5 is the chip interface bus protocol information. Step S2: Based on the chip interface inspection structure, insert chip interface attribute information into the chip code; Step S3: Parse the chip code after inserting the chip interface attribute information, and generate assertion code for each chip interface in the chip code, which includes chip interface X-state check, Z-state check and bus protocol check; Step S4: Run the chip code and perform X-state checks, Z-state checks, and bus protocol checks on the chip interface based on the assertion code.
[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.
[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.
[0007] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the chip interface automatic inspection method, electronic device, and medium provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects: This invention improves the efficiency and accuracy of chip interface checks by inserting chip interface attribute information generated based on a chip interface inspection data structure into the chip code, parsing the chip code after inserting the chip interface attribute information, generating assertion code for each chip interface in the chip code, including chip interface X-state checks, Z-state checks, and bus protocol checks, and finally automatically performing X-state checks, Z-state checks, and bus protocol checks on the chip interface by running the chip code and based on the assertion code. This improves the efficiency and accuracy of chip interface checks, thereby improving chip development efficiency and accuracy. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 A flowchart of an automatic chip interface inspection method provided in an embodiment of the present invention. Detailed Implementation
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] This invention provides an automatic chip interface inspection method, such as... Figure 1 As shown, it includes: Step S1: Construct the chip interface check data structure IFC={B1,B2,B3,B4,B5}, where B1 is the chip interface clock information, B2 is the chip interface reset information, B3 is the chip interface root clock information, B4 is the chip interface root reset information, and B5 is the chip interface bus protocol information.
[0012] As an example, the chip may specifically be a Graphics Processing Unit (GPU) chip. It should be noted that the chip interface root clock information is the source clock information that can affect the chip interface clock, the chip interface clock information is the current clock information of the chip interface, the chip interface root reset information is the source reset information that can affect the chip reset information, and the chip interface reset information is the current reset information of the chip interface.
[0013] Step S2: Insert chip interface attribute information into the chip code based on the chip interface inspection structure.
[0014] As an example, the chip code is generated based on a JSON schema, which includes multiple sets of key-value pairs. These key-value pairs can be nested, for example, the value corresponding to a certain key may contain a key-value pair.
[0015] Step S3: Parse the chip code after inserting the chip interface attribute information, and generate assertion code for each chip interface in the chip code, which includes chip interface X-state check, Z-state check and bus protocol check.
[0016] Among them, assertion code is a hardware-level, real-time, synthesizable logic checking method in chip design. It can be directly embedded in RTL (Register Transfer Level) code to monitor whether signal behavior conforms to design rules in real time.
[0017] Step S4: Run the chip code and perform X-state checks, Z-state checks, and bus protocol checks on the chip interface based on the assertion code.
[0018] Among them, the X state is an unknown state, and the Z state is a high-resistivity state.
[0019] As one embodiment, step S2 includes: Step S21: Obtain the chip code, wherein the chip code includes {A1,A2,...,A...} m ,...,A M}, A m Let A be the m-th chip interface code, where m ranges from 1 to M, and M is the total number of chip interface code groups. m ={A1 m A2 m},A1 m For A m The corresponding key code is A2. m For A m The corresponding value code is A1 m Includes A m Corresponding key K m A2m ={V1 m V2 m ,...,V i m ,...,V f(m) m}, V i m A2 m The corresponding i-th value code, V i m Includes A m The corresponding i-th chip interface P mi The value of i ranges from 1 to f(m), where f(m) is A. m The total number of corresponding chip interfaces.
[0020] Step S22, in A1 m Insert A based on IFC generation m Corresponding chip interface attribute information F m .
[0021] It is understandable that the chip interface attribute information F m Specifically, this includes chip interface clock information, chip interface reset information, chip interface root clock information, chip interface root reset information, and chip interface bus protocol information.
[0022] Step S23, in V i m Insert the corresponding inheritance type parameters and chip interface inheritance attribute information.
[0023] It should be noted that by using steps S21-S23, the attribute information of chip interfaces can be processed in batches without having to write corresponding attribute information code for each chip interface separately.
[0024] As one embodiment, step S3 includes: Step S31: Obtain the interface P of each chip. mi Corresponding A m The corresponding chip interface attribute information F m As P mi The corresponding interface attribute information of the chip to be processed.
[0025] Step S32: Obtain the interface P of each chip. mi The corresponding inheritance type parameters and chip interface inheritance attribute information.
[0026] Step S33: Based on each chip interface P mi The corresponding chip interface attribute information, inheritance type parameters, and chip interface inheritance attribute information are used to generate P. miThe corresponding chip interface attribute information.
[0027] The inheritance type parameter includes inheritance, overriding, and ignoring. The chip interface inheritance attribute information includes one or more of the following: chip interface clock information, chip interface reset information, chip interface root clock information, chip interface root reset information, and chip interface bus protocol information.
[0028] Step S34, P mi The corresponding chip interface attribute information is bound to P. mi And set the corresponding X-state check logic, Z-state check logic and bus protocol check logic.
[0029] Among them, P mi The corresponding chip interface attribute information is bound to P. mi It also sets the corresponding X-state check logic, Z-state check logic, and bus protocol check logic. Since the attribute information includes the chip interface root clock information and the chip interface root reset information, the chip interface can be accurately checked at both the logic layer and the physical layer.
[0030] The X-state check logic includes that the input signal cannot be in the X-state and the output signal cannot be in the X-state; the Z-state check logic includes that the input signal cannot be in the Z-state and the output signal can be in the Z-state; the bus protocol check logic includes that the bus protocol corresponding to the chip interface must follow a preset bus protocol.
[0031] Step S35, based on P mi The bound chip interface attribute information and the corresponding X-state check, Z-state check and bus protocol check logic generate assertion code containing chip interface X-state check, Z-state check and bus protocol check.
[0032] It should be noted that, through steps S31-S35, the interface P of each chip is first obtained. mi Corresponding A m The corresponding chip interface attribute information F m Then, based on the inheritance type parameters and chip interface inheritance attribute information, A is... m The corresponding chip interface attribute information can be inherited, partially overridden, or ignored. It's understandable that for chip interfaces with identical interface attribute information, the corresponding A can be directly inherited. m The corresponding chip interface attribute information, for interfaces that only need to modify local attribute information, can be found in A. mThe chip interface attribute information is obtained by partially modifying the corresponding chip interface attribute information. For chip interfaces that do not need to be checked, the inheritance type parameter can be directly set to ignore, and no check is performed on chip interfaces that do not need to be checked. The processing steps S31-S35 improve the accuracy and efficiency of chip interface attribute information generation, thereby improving the accuracy and efficiency of chip interface checking.
[0033] As one embodiment, step S33 includes: Step S331, if P mi If the corresponding inheritance type is inheritance, then execute step S332; if it is overriding, then execute step S333; if it is ignoring, then execute step S334.
[0034] Step S332, P mi The corresponding interface attribute information of the chip to be processed is determined to be P. mi The corresponding chip interface attribute information is used to execute step S335.
[0035] It is understandable that if P mi If the corresponding inheritance type is inheritance, then P is directly inherited. mi The corresponding interface attribute information of the chip to be processed.
[0036] Step S333: Place P mi The corresponding chip interface inherited attribute information is used as the attribute information to be replaced, and P is used as the attribute information to be replaced. mi Replace the information corresponding to the attribute to be replaced in the corresponding chip interface attribute information with the attribute information to be replaced, and then replace the P with the attribute information to be replaced. mi The corresponding attribute information to be processed is determined to be P. mi The corresponding chip interface attribute information is used to execute step S335.
[0037] It is understandable that the chip interface inherited attribute information consists of one or more of the corresponding attribute information in the chip interface inspection data structure. The attribute to be replaced is the attribute corresponding to the attribute information to be replaced.
[0038] Step S344, P mi The corresponding chip interface inheritance attribute information is set to empty, and this P is not... mi Perform subsequent inspection operations, proceeding to step S335.
[0039] It should be noted that this P is not... mi Performing follow-up checks refers to not performing checks on the P. mi Perform all subsequent inspection-related operations, including steps S34-S35 and all operations in step S4.
[0040] Step S335: If all chip interfaces have generated corresponding chip interface attribute information, then proceed to step S34; otherwise, return to step S331.
[0041] It should be noted that steps S331-S335 can achieve rapid and accurate automated generation of chip interface attribute information without the need to manually write code for each chip interface.
[0042] As one embodiment, step S4 includes: Step S41: Run the chip code and obtain the attribute information corresponding to the chip interface based on the assertion code.
[0043] It should be noted that in step S3, corresponding attribute information has been bound to each chip interface. Therefore, when running the chip code, the attribute information corresponding to the chip interface can be obtained based on the assertion code.
[0044] Step S42: Based on the attribute information corresponding to the chip interface, determine whether it conforms to the X-state check logic, Z-state check logic, and bus protocol check logic, and generate the corresponding interface check data to the preset database.
[0045] It is understandable that when the X-state check logic, Z-state check logic, and bus protocol check logic do not meet the requirements, the corresponding interface check data can be the corresponding error data, and the corresponding error data can be stored in a preset database for subsequent debugging and analysis.
[0046] This invention improves the efficiency and accuracy of chip interface checks by inserting chip interface attribute information generated based on a chip interface inspection data structure into the chip code, parsing the chip code after inserting the chip interface attribute information, generating assertion code for each chip interface in the chip code, including chip interface X-state checks, Z-state checks, and bus protocol checks, and finally automatically performing X-state checks, Z-state checks, and bus protocol checks on the chip interface by running the chip code and based on the assertion code. This improves the efficiency and accuracy of chip interface checks, thereby improving chip development efficiency and accuracy.
[0047] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.
[0048] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.
[0049] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.
[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. An automatic chip interface inspection method, characterized in that, include: Step S1: Construct the chip interface check data structure IFC={B1,B2,B3,B4,B5}, where B1 is the chip interface clock information, B2 is the chip interface reset information, B3 is the chip interface root clock information, B4 is the chip interface root reset information, and B5 is the chip interface bus protocol information. Step S2: Based on the chip interface inspection structure, insert chip interface attribute information into the chip code; Step S3: Parse the chip code after inserting the chip interface attribute information, and generate assertion code for each chip interface in the chip code, which includes chip interface X-state check, Z-state check and bus protocol check; Step S4: Run the chip code and perform X-state checks, Z-state checks, and bus protocol checks on the chip interface based on the assertion code.
2. The method according to claim 1, characterized in that, Step S2 includes: Step S21: Obtain the chip code, wherein the chip code includes {A1,A2,...,A...} m ,...,A M }, A m Let A be the m-th chip interface code, where m ranges from 1 to M, and M is the total number of chip interface code groups. m ={A1 m A2 m },A1 m For A m The corresponding key code is A2. m For A m The corresponding value code is A1 m Includes A m Corresponding key K m A2 m ={V1 m V2 m ,...,V i m ,...,V f(m) m }, V i m A2 m The corresponding i-th value code, V i m Includes A m The corresponding i-th chip interface P mi The value of i ranges from 1 to f(m), where f(m) is A. m The corresponding total number of chip interfaces; Step S22, in A1 m Insert A based on IFC generation m Corresponding chip interface attribute information F m ; Step S23, in V i m Insert the corresponding inheritance type parameters and chip interface inheritance attribute information.
3. The method according to claim 2, characterized in that, Step S3 includes: Step S31: Obtain the interface P of each chip. mi Corresponding A m The corresponding chip interface attribute information F m As P mi The corresponding interface attribute information of the chip to be processed; Step S32: Obtain the interface P of each chip. mi The corresponding inheritance type parameters and chip interface inheritance attribute information; Step S33: Based on each chip interface P mi The corresponding chip interface attribute information, inheritance type parameters, and chip interface inheritance attribute information are used to generate P. mi Corresponding chip interface attribute information; Step S34, P mi The corresponding chip interface attribute information is bound to P. mi And set the corresponding X-state check logic, Z-state check logic and bus protocol check logic; Step S35, based on P mi The bound chip interface attribute information and the corresponding X-state check, Z-state check and bus protocol check logic generate assertion code containing chip interface X-state check, Z-state check and bus protocol check.
4. The method according to claim 3, characterized in that, The inheritance type parameter includes inheritance, overriding, and ignoring. The chip interface inheritance attribute information includes one or more of the following: chip interface clock information, chip interface reset information, chip interface root clock information, chip interface root reset information, and chip interface bus protocol information.
5. The method according to claim 4, characterized in that, Step S33 includes: Step S331, if P mi If the corresponding inheritance type is inheritance, then execute step S332; if it is overriding, then execute step S333; if it is ignoring, then execute step S334. Step S332, P mi The corresponding chip interface attribute information to be processed is determined to be P. mi Execute step S335 based on the corresponding chip interface attribute information; Step S333: Place P mi The corresponding chip interface inherited attribute information is used as the attribute information to be replaced, and P is used as the attribute information to be replaced. mi Replace the information corresponding to the attribute to be replaced in the corresponding chip interface attribute information with the attribute information to be replaced, and then replace the P with the attribute information to be replaced. mi The corresponding attribute information to be processed is determined to be P. mi Execute step S335 based on the corresponding chip interface attribute information; Step S344, P mi The corresponding chip interface inheritance attribute information is set to empty, and this P is not... mi Perform subsequent inspection operations, proceeding to step S335; Step S335: If all chip interfaces have generated corresponding chip interface attribute information, then proceed to step S34; otherwise, return to step S331.
6. The method according to claim 3, characterized in that, The X-state check logic includes the following: the input signal cannot be in the X-state, and the output signal cannot be in the X-state. The Z-state checking logic includes the condition that the input signal cannot be in the Z-state and the output signal can be in the Z-state. The bus protocol check logic includes ensuring that the bus protocol corresponding to the chip interface follows a preset bus protocol.
7. The method according to claim 3, characterized in that, Step S4 includes: Step S41: Run the chip code and obtain the attribute information corresponding to the chip interface based on the assertion code; Step S42: Based on the attribute information corresponding to the chip interface, determine whether it conforms to the X-state check logic, Z-state check logic, and bus protocol check logic, and generate the corresponding interface check data to the preset database.
8. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-7.
9. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-7.