Cross-clock domain synchronization validity checking method, electronic device, and storage medium

Abstract

The application relates to the field of integrated circuit design, and discloses a cross-clock domain synchronization validity checking method, an electronic device and a storage medium, the method comprises the following steps: identifying an output node of a logic operation device receiving a source signal and a synchronized control signal as an input as a first logic node in a data path, and determining the first logic node as a starting node of the data path detection range; starting from the starting node, identifying output nodes of other logic operation devices in the data path as to-be-detected nodes in a data propagation direction, and determining the starting node and each to-be-detected node identified to be a to-be-detected node set in the data path detection range, a data path synchronization validity problem which is originally difficult to directly judge is checked, and a label reflecting a cross-clock domain synchronization state is identified for each to-be-detected node in the data path, so that the accuracy and traceability of the cross-clock domain synchronization validity checking are improved.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit design technology, and in particular relates to a method for checking the effectiveness of cross-clock domain synchronization, an electronic device, and a storage medium. Background Technology

[0002] In digital integrated circuits, a circuit system typically includes multiple clock domains, with different parts driven by different clock signals. When a signal from one clock domain needs to be propagated to and used in another clock domain, a clock domain crossing (CDC) problem occurs. Because there is no fixed timing relationship between different clock domains, when a signal from the source clock domain propagates to the destination clock domain, the registers in the destination clock domain may be sampling during that signal change, resulting in an unstable state, or metastability. Metastability can further lead to logical errors, functional abnormalities, and circuit instability.

[0003] In practical analysis, the cross-domain transmission relationship of a source signal in the source clock domain, propagating through combinational or sequential logic and ultimately captured by the destination node in the destination clock domain, is typically abstracted as a cross-clock domain path pair (CDC pair). By abstracting the cross-clock domain problem into cross-clock domain path pairs, the CDC analysis object in complex circuits can be focused on the specific relationship between the source node, propagation path, and destination node. For example, in a digital circuit, the output signal sig_a of register FF1 under the source clock domain clk_a is propagated through combinational logic and sampled by register FF2 under the destination clock domain clk_b. The cross-domain transmission relationship consisting of the output of FF1, the propagation path corresponding to sig_a, and the input of FF2 can be abstracted as a CDC path pair. Here, the output of FF1 corresponds to the source node, the input of FF2 corresponds to the destination node, and the entire logical path of sig_a propagating from the source node to the destination node is the propagation path corresponding to this CDC path pair.

[0004] Depending on the synchronization protection method, the aforementioned cross-clock domain paths can generally be divided into two types: control paths and data paths. The control path refers to the cross-clock domain control signal propagation path used to generate the synchronized control signal, while the data path refers to the source signal propagation path constrained by the synchronized control signal. In the control path, the cross-clock domain control signal is synchronized step-by-step through a register chain structure, and the output of the final register in the register chain structure is the synchronized control signal. Correspondingly, in the data path, the synchronized control signal is used to block or allow the propagation of the source signal.

[0005] To mitigate the risks associated with unstable sampling of cross-clock domain signals, existing technologies typically incorporate synchronization protection structures, such as synchronizers, into cross-clock domain path pairs. Synchronizers generally consist of multiple cascaded registers. By performing step-by-step sampling of the cross-domain signal in the destination clock domain, they increase the probability of stable signal acquisition, thereby reducing the risk of metastability propagation. For control paths, since the cross-domain signal usually enters directly into the synchronizer structure composed of multiple registers and is sampled sequentially through the first-stage register, the second-stage register, and subsequent stages, the potential risk of metastability propagation gradually diminishes during continuous sampling until it stabilizes at the output of the final-stage register. Therefore, control paths typically exhibit a well-defined multi-stage register chain structure. Existing technologies often determine whether a path possesses synchronization protection by identifying this multi-stage register synchronization structure. In such paths, the final-stage register performing the final stable acquisition function acts as a limiter, and its output can generally be considered as having achieved cross-clock domain synchronization.

[0006] However, the aforementioned synchronizer-based identification techniques are primarily applicable to control paths and not directly suitable for data paths. This is because data paths typically do not perform step-by-step synchronization of the data itself, but rather rely on the control signals output by limiters to block or allow the propagation of source signals. In other words, even if the presence of a synchronizer is detected, it only indicates that a certain control signal has been synchronized, and does not directly imply that the source signals in the data path are securely protected. For data paths, the key is not the presence of synchronizers or limiters, but whether the control signals output by the limiters can effectively block the source signals at the corresponding logic nodes, thereby preventing the unstable source signals from being directly sampled by the destination clock domain. Furthermore, the subsequent logic of the data path may include combinational logic such as AND gates, OR gates, and selectors, and may involve the combined action of multiple source signals, multiple limiters, and multiple destination nodes. There may even be situations where a single limiter is insufficient to achieve blocking, and multiple limiters must work together to achieve effective blocking.

[0007] Therefore, there is an urgent need for a method to accurately analyze the relationship between the limiter, the source signal, and the destination node for cross-clock domain path pairs corresponding to the data path, and to determine whether the limiter effectively blocks the source signal, thereby accurately determining the cross-clock domain path pair synchronization validity check method. Summary of the Invention

[0008] This application provides a method, electronic device, and storage medium for checking the synchronization validity across clock domains, aiming to provide a method for accurately determining the synchronization status of cross-clock domain path pairs in a data path.

[0009] On the one hand, this application provides a method for checking the validity of cross-clock domain synchronization, including the following steps: The output node of the logic operation device that receives the source signal and the synchronized control signal as input in the data path is identified as the first logic node, and the first logic node is determined as the starting node of the data path detection range. Starting from the starting node, the output nodes of other logic operation devices in the data path are identified as nodes to be detected along the data propagation direction, and the starting node and the identified nodes to be detected are determined as the set of nodes to be detected within the data path detection range. Logical calculations are performed on each node in the set of nodes to be detected to determine whether the source signal in the logical result corresponding to each node to be detected is blocked by the synchronized control signal, and a state flag is established based on the determination result to characterize the cross-clock domain state of each node to be detected. Based on the status flags corresponding to each node in the set of nodes to be detected, the blocking status of the synchronized control signal to the source signal in the data path is determined, and a synchronization effectiveness detection result for at least one node in the set of nodes to be detected is output, wherein the synchronization effectiveness detection result includes the status flags of the corresponding node to be detected.

[0010] On the other hand, embodiments of this application provide an electronic device, including: processor; A memory for storing processor-executable instructions, wherein the processor-executable instructions perform the aforementioned cross-clock domain synchronization validity check method when executed by the processor.

[0011] In another aspect, embodiments of this application provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by the processor of an electronic device, enables the electronic device to perform the aforementioned cross-clock domain synchronization validity check method.

[0012] This application embodiment, through the aforementioned cross-clock domain synchronization validity check method, identifies the output node of the logic operation device that receives the source signal and the synchronized control signal as input in the data path as the first logic node, and determines the first logic node as the starting node of the data path detection range; starting from the starting node, identifies the output nodes of other logic operation devices in the data path as nodes to be detected along the data propagation direction, and determines the starting node and the identified nodes to be detected as the set of nodes to be detected within the data path detection range; performs logic calculations on each node to be detected in the set of nodes to be detected one by one, determines whether the source signal in the logic result corresponding to each node to be detected is blocked by the synchronized control signal, and establishes a state label to characterize the cross-clock domain state at each node to be detected based on the determination result. This transforms the originally difficult-to-determine data path synchronization validity problem into a point-by-point analysis process of whether the source signal at a specific node to be detected is blocked, and identifies each node to be detected in the data path with a label reflecting the cross-clock domain synchronization state, thereby improving the accuracy and traceability of the cross-clock domain synchronization validity check. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart illustrating the cross-clock domain synchronization validity check method of this application; Figure 2 This is a circuit example diagram of the cross-clock domain synchronization validity check method of this application; Figure 3 This is another circuit example diagram of the cross-clock domain synchronization validity check method of this application; Figure 4 This is a schematic diagram of the electronic device used in the cross-clock domain synchronization validity check method of this application. Detailed Implementation

[0015] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0016] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0017] As an optional implementation, the cross-clock domain synchronization validity check method in this embodiment includes the following steps: S100, identify the output node of the logic operation device that receives the source signal and the synchronized control signal as input in the data path as the first logic node, and determine the first logic node as the starting node of the data path detection range; S200: Starting from the starting node, identify the output nodes of other logic operation devices in the data path along the data propagation direction as nodes to be detected, and determine the starting node and each identified node to be detected as the set of nodes to be detected within the data path detection range; S300: Perform logical calculations on each node to be detected in the set of nodes to be detected, determine whether the source signal in the logical result corresponding to each node to be detected is blocked by the synchronization control signal, and establish a state flag to characterize the cross-clock domain state of each node to be detected based on the determination result. S400, based on the status flags corresponding to each node in the set of nodes to be detected, determines the blocking status of the control signal after synchronization to the source signal in the data path, and outputs the synchronization validity detection result for at least one node in the set of nodes to be detected, wherein the synchronization validity detection result includes the status flags of the corresponding node to be detected.

[0018] Specifically, this embodiment mainly checks the synchronization effectiveness of the data path, that is, whether there is a risk of desynchronization in the data path. Depending on the synchronization protection method, cross-clock domain paths can generally be divided into two types: control paths and data paths. The control path refers to the cross-clock domain control signal propagation path used to generate the synchronized control signal, while the data path refers to the source signal propagation path constrained by the synchronized control signal. In the control path, the cross-clock domain control signal is synchronized step-by-step through a register chain structure, and the output of the last register in the register chain structure is the synchronized control signal. In the data path, the synchronized control signal is used to block or allow the propagation of the source signal. Therefore, the focus of this embodiment is not to determine whether a step-by-step blocking structure exists inside the synchronizer, but rather to further examine whether the synchronized control signal in the logic following the synchronizer truly effectively blocks the source signal.

[0019] In the step of identifying the output node of a logic device that receives both the source signal and the post-synchronization control signal as input in the data path as the first logic node, and determining the first logic node as the starting node of the data path detection range, the source signal refers to a signal located in the source clock domain, propagating along the data path, and requiring a determination of whether it is blocked by the post-synchronization control signal; the post-synchronization control signal refers to the control signal output by the synchronizer in the control path after completing step-by-step synchronization. In this embodiment, based on the post-synchronization control signal in the circuit under test, the connection relationship after the synchronizer can be analyzed to identify the logic device in the data path that simultaneously receives both the source signal and the post-synchronization control signal as input and participates in subsequent logic operations, and the output node of this logic device is identified as the first logic node. As an example, the logic device can be an AND gate, an OR gate, a selector, a multiplexer, or other devices used to carry the logical relationship between the post-synchronization control signal and the source signal. Since the first logic node corresponds to the first output node after the synchronizer that actually carries the constraint relationship between the propagation of the source signal and the post-synchronization control signal, after determining the first logic node as the starting node of the data path detection range, subsequent data path detection can begin from the logic position after the synchronizer that is truly related to the data propagation constraint. Therefore, the control path identification result can be accurately linked with the data path detection starting point, so that the analysis boundary is located at the logical position after the synchronizer output and is truly affected by the synchronized control signal, thereby avoiding the repeated inclusion of the synchronizer's internal register chain into the data path analysis object.

[0020] like Figure 2As shown, the input signal di_0 is connected to the input pin d of instance begin, and the clock signal clk[0] is connected to the clock input terminal clk of instance begin; the input signal d0 is connected to the input pin d of instance q0. The output pin q of instance q0 is connected to the input pin d of instance q1_1, the output pin q of instance q1_1 is connected to the input pin d of instance q1_2, and the output pin q of instance q1_2 is connected to the input pin d of instance q1. The clock signal clk[1] is connected to the clock input terminals clk of instances q1_1, q1_2, and q1 respectively, and is connected to the control terminal gate of instance latch1 and the clock input terminal clk of instance end. The output pin q of instance q1 is connected to the input pin d of instance latch1, the output pin q of instance latch1 is connected to the control input terminal c of instance i18, the output pin q of instance begin is connected to the input terminal a1 of instance i18, the output pin o of instance i18 is connected to the input pin d of instance end, and the output pin q of instance end can be used as the output signal of the subsequent stage. In this embodiment, instances q0, q1_1, q1_2, and q1 are first identified as a sequentially cascaded register chain structure, and this register chain structure is determined as the synchronizer in the control path. Instance q1 can be considered the final register in the register chain structure, and its output pin q can be used as the output location of the synchronized control signal. Continuing the analysis along the subsequent connections of the output pin q of instance q1, a logic device that simultaneously receives both the source signal and the synchronized control signal as input can be identified. For example, instance i18 in the figure is a selector. The control input terminal c of instance i18 can receive the synchronized control signal from the output pin q of instance q1, and its data input terminal a1 corresponds to the source signal propagation path. Therefore, the output pin o of instance i18 can be identified as the first logic node, and this output pin o is determined as the starting node of the data path detection range. Accordingly, by continuing the analysis along the subsequent connection relationship of the output pin o of instance i18, the target register instance end can be identified as the one used to receive the output signal and sample it in the target clock domain. Since the input pin d of instance end is connected to the output pin o of instance i18, and the clock input terminal clk of instance end receives the clock signal clk[1], the input pin d of instance end can be determined as the target destination node and used as the termination node of the data path detection range.

[0021] Since the first logical node corresponds to the output node that actually carries the relationship between the propagation of the source signal and the constraint relationship of the synchronized control signal after synchronization, once the first logical node is determined as the starting node of the data path detection range, subsequent data path detection can be carried out from the logical position after the synchronizer that is truly related to the data propagation constraint. Therefore, the control path identification result can be accurately connected with the starting point of the data path detection, so that the analysis boundary is located at the logical position after the synchronizer output that is truly affected by the synchronized control signal, thereby avoiding repeatedly including the synchronizer's internal register chain in the data path analysis object.

[0022] In the step of identifying the nodes to be detected corresponding to other logic devices along the data propagation direction starting from the starting node, and determining the starting node and the identified nodes to be detected as the set of nodes to be detected within the detection range of the data path, after the first logic node is determined as the starting node, the logic devices subsequently connected to the first logic node can be analyzed along the data propagation direction, and the nodes to be detected corresponding to these logic devices can be identified as other nodes to be detected. Subsequently, the nodes to be detected corresponding to the starting node and other logic devices are jointly determined as the set of nodes to be detected. That is, multiple nodes to be detected that can be reached along the data propagation direction from the starting node can be gathered together to form a set of nodes to be detected. The set of nodes to be detected thus formed is used to characterize the logic detection range after the synchronizer and related to the source signal propagation and the control signal constraints after synchronization. By limiting the subsequent analysis to the set of nodes to be detected, the subsequent logic calculation can focus on the set of nodes directly related to the data propagation constraints, thereby providing a clear scope of analysis objects for point-by-point state identification.

[0023] For example, after identifying the output pin o of instance i18 as the starting node, the subsequent connection relationships of the output pin o can be analyzed along the data propagation direction. For example, the output pin o of instance i18 in the figure can continue to be connected to the input pin d of the subsequent unit end. If there are other logic operation devices after the output pin o, the output nodes corresponding to these subsequent logic operation devices can be further identified as other nodes to be detected, and included in the set of nodes to be detected together with the starting node. Thus, the set of nodes to be detected can specifically cover the relevant logic detection range starting from the output pin o of instance i18 and extending along the subsequent data propagation direction.

[0024] In the steps of performing logical calculations on each node in the set of nodes to be tested, determining whether the source signal in the logical result corresponding to each node is blocked by the synchronized control signal, and establishing a state marker to characterize the cross-clock domain state of each node based on the determined result, logical calculations can be performed on each node in the set of nodes to be tested, based on the data propagation relationship of the current node. Here, the logical calculation is not only used to obtain the logical output value of the current node to be tested, but also to determine whether the source signal still exists in the logical result corresponding to the current node to be tested. Specifically, it can be determined whether the source signal still exists in the logical result corresponding to the current node to be tested by analyzing whether the source signal changes with the source signal. If the logical calculation result shows that the source signal no longer exists in the logical result corresponding to the current node to be tested, it means that the synchronized control signal has effectively blocked the source signal before reaching the current node to be tested; if the logical calculation result shows that the source signal still exists in the logical result corresponding to the current node to be tested, it means that the synchronized control signal has not yet effectively blocked the source signal before reaching that node. After completing the above logical calculations, corresponding state markers can be established at each node to be detected based on the corresponding judgment results. These markers characterize the cross-clock domain state of the node to be detected. In one implementation, the state markers can be used to characterize the synchronization-maintained state, the unblocked state, or the blocked state. By establishing state markers at each node to be detected, the synchronization validity analysis results can be refined to the specific node to be detected, thereby generating corresponding synchronization validity information for each node to be detected in the data path.

[0025] For example, in Figure 2 In the demonstrated example, logical calculations can be performed on the logical relationship corresponding to the output pin o of instance i18. For example, the logical expression of instance i18 is c&a1|!c&a0, where input c can correspond to the synchronized control signal output by the output pin q of instance q1, and input a1 can correspond to the input path that introduces the source signal. In addition, it is assumed that instance i18 also has an input a0 that can correspond to another input path that does not introduce the source signal. Therefore, when the value of the synchronized control signal causes the output pin o of instance i18 to select the a0 path, it can be determined that there is no source signal in the logical result corresponding to the output pin o, and a state flag representing the blocked state is established at the output pin o. When the value of the synchronized control signal causes the output pin o of instance i18 to select the a1 path, it can be determined that there is still a source signal in the logical result corresponding to the output pin o, and a state flag representing the unblocked state is established at the output pin o.

[0026] Furthermore, the output pin q of instance latch1 is connected to instance i18. When the control input c of instance i18 selects the a1 path for output, the logic result corresponding to the output pin o of instance i18 still contains the source signal from the output path of instance latch1; when the control input c of instance i18 selects the a0 path for output, the logic result corresponding to the output pin o of instance i18 no longer contains the source signal. This demonstrates that after synchronization, the control signal, by controlling the gating relationship of instance i18, blocks or allows the propagation of the source signal.

[0027] In the step of determining the blocking status of the control signal to the source signal in the data path after synchronization based on the state flags corresponding to each node in the set of nodes to be detected, and outputting the synchronization effectiveness detection result for at least one node in the set of nodes to be detected, wherein the synchronization effectiveness detection result includes the state flags of the corresponding node, after the state flags of each node to be detected are established, the state flags corresponding to each node to be detected can be read or summarized first, and then the synchronization effectiveness detection result for the corresponding node to be detected can be determined based on the state flags. Specifically, if the state flag of the corresponding node to be detected indicates that the source signal is no longer present in the logical result corresponding to the current node to be detected, then it can be determined that there is no synchronization effectiveness risk for the corresponding node to be detected; if the state flag of the corresponding node to be detected indicates that the source signal is still present in the logical result corresponding to the current node to be detected, then it can be determined that there is synchronization effectiveness risk for the corresponding node to be detected. Subsequently, the synchronization effectiveness detection result for at least one node in the set of nodes to be detected can be output, wherein the synchronization effectiveness detection result includes the state flags of the corresponding node to be detected. Therefore, it can not only provide a judgment on whether there is a risk of asynchrony in the corresponding node to be detected, but also provide specific status information of the node to be detected, thereby supporting the further location of the decisive node to be detected, the effective position of the control signal after synchronization, and the node with potential risks.

[0028] As an example, if a control path exists in the circuit under test, and its cross-clock domain control signal is synchronized step-by-step through two levels of registers in the destination clock domain, with the synchronized control signal output by the final register, then an AND gate connected to the synchronized control signal and simultaneously receiving the source signal input can be identified after the synchronizer output. The output node of this AND gate is identified as the first logic node and determined as the starting node of the data path detection range. Subsequently, along the subsequent connection relationship of the AND gate output node, the corresponding nodes under test for other logic operation devices located on the subsequent data propagation path are identified, and the first logic node and these nodes under test are included in the set of nodes under test. When performing logical calculations on each node under test in the set of nodes under test, if the logical result corresponding to a certain node under test remains unchanged under different source signal conditions, it can be determined that the source signal no longer exists in the logical result corresponding to the node under test, and a state marker representing the blocked state is established at the node under test; if the logical result corresponding to a certain node under test still changes with the source signal, it can be determined that the source signal still exists in the logical result corresponding to the node under test, and a state marker representing the unblocked state is established at the node under test. Finally, based on the status flags corresponding to each node to be detected, the synchronization validity detection results of the corresponding node to be detected can be output.

[0029] For example, if the synchronized control signal is connected to a logic device such as a selector or multiplexer, the first logic node can correspond to the output node of that selector or multiplexer. In this case, the output node can be used as the starting node, and other logic devices can be identified along their output direction to determine the nodes to be tested. For any node to be tested, if the logic calculation result indicates that the synchronized control signal only allows input paths that do not introduce the source signal to propagate backward, then it can be determined that the source signal is no longer present in the logic result corresponding to that node; if the logic calculation result indicates that the synchronized control signal still allows input paths containing the source signal to propagate backward, then it can be determined that the source signal still exists in the logic result corresponding to that node. Therefore, corresponding status flags can be established for different types of logic devices, and the data path synchronization validity check can be performed accordingly.

[0030] The cross-clock domain synchronization validity check method provided in this embodiment can identify subsequent nodes to be tested step by step, forming a set of nodes to be tested, by using the output node of the logic device that receives the source signal and the synchronized control signal as input in the data path as the first logic node. Logical calculations are then performed on each node in this set to establish a state marker characterizing the cross-clock domain state. Based on the state marker, the blocking state of the synchronized control signal on the source signal in the data path can be further determined, and a synchronization validity check result for at least one node in the set of nodes to be tested can be output. Therefore, the data path synchronization validity problem can be transformed into a point-by-point analysis of whether the source signal still exists in the logical result corresponding to a specific node to be tested, thereby improving the accuracy and traceability of the cross-clock domain synchronization validity check.

[0031] As an optional implementation, the output node of the logic device that receives the source signal and the synchronized control signal as input in the data path is designated as the first logic node, and the first logic node is determined as the starting node of the data path detection range. This includes: identifying the register chain structure in the circuit under test that performs step-by-step synchronization of the cross-clock domain control signal, and determining the register chain structure as the synchronizer in the control path; determining the control signal output by the last register of the register chain structure as the synchronized control signal; and based on the synchronized control signal, identifying the output node of the logic device that receives the source signal and the synchronized control signal as input in the data path as the first logic node, and determining the first logic node as the starting node of the data path detection range.

[0032] Specifically, in this embodiment, the propagation relationship of cross-clock domain control signals in the circuit to be tested can be analyzed first to identify a register chain structure formed by multiple registers cascaded sequentially in the destination clock domain. The output of the previous register is connected to the input of the next register, and each register is driven by the same destination clock domain. Based on this, the register chain structure can be identified as the synchronizer in the control path that performs step-by-step synchronization of cross-clock domain control signals. Through the above steps, the control path responsible for synchronization can be identified from the circuit to be tested, allowing subsequent data path detection to be based on the identified control path. This eliminates the need to start the analysis from the entire circuit again, allowing it to continue from the logic position after the synchronizer output. For example, in... Figure 3 In the database, din_ff1, din_ff2, and din_ff3 can be identified as a sequentially cascaded register chain structure.

[0033] After identifying the register chain structure, the last register in the cascaded sequence can be further determined and identified as the final-stage register. Since the cross-clock domain control signals are synchronized step-by-step through the register chain structure, the relevant control signals at the output of the final-stage register can be considered as already synchronized. Based on this, the control signals output by the final-stage register can be identified as the synchronized control signals. Therefore, the starting point for subsequent data path detection analysis can be shifted from inside the synchronizer to the logic region after the synchronizer output, allowing subsequent data path detection to focus on the logical constraints after the synchronizer, rather than repeatedly analyzing the step-by-step synchronization process inside the synchronizer. For example, in Figure 3 In this process, din_ff3 is designated as the last register in the register chain structure, and the output pin q of din_ff3 is designated as the control signal after synchronization.

[0034] After the synchronization control signal is determined, the subsequent logic can be analyzed along the output connection relationship of the synchronization control signal to identify the logic operation device in the data path that receives the source signal and the synchronization control signal as inputs, and the output node of the logic operation device is identified as the first logic node. Here, receiving the source signal and the synchronization control signal as inputs can be understood as the synchronization control signal participating in the logic operation as the input signal of the logic operation device, thereby affecting the propagation result of the source signal in the data propagation path. In specific implementation, the logic operation device that is directly connected to the synchronization control signal, receives the source signal input, and is located in the data propagation direction can be identified, and its output node can be determined as the first logic node. Thus, the first logic node can be determined as the starting node of the data path detection range, so that the subsequent data path detection can start from the output node after the synchronizer that actually carries the constraint relationship between the source signal propagation and the synchronization control signal, thereby ensuring that the starting position of the data path detection range is consistent with the starting position of the subsequent logic constraint analysis.

[0035] For example, such as Figure 3As shown, instances din_ff1, din_ff2, and din_ff3 can first be identified as a sequentially cascaded register chain structure, and this register chain structure can be identified as the synchronizer in the control path. Specifically, the output pin q of instance din_ff1 is connected to the input pin d of instance din_ff2, and the output pin q of instance din_ff2 is connected to the input pin d of instance din_ff3. The clock input clk of each instance receives the corresponding clock signal. Further, instance din_ff3 can be identified as the last-stage register in the register chain structure, and its output pin q can be identified as the synchronized control signal. After identifying the output pin q of instance din_ff3 as the synchronized control signal, the multiplexer i25 can be identified along its subsequent connections. Instance i25 has inputs a0 and a1, a control terminal c, and an output terminal o. Since the control terminal c of instance i25 can receive the synchronized control signal transmitted from the output pin q of instance din_ff3, and at least one of its data input terminals a0 and a1 can receive the signal on the source signal propagation path, instance i25 can be identified as a logic device, and its output pin o can be identified as the first logic node, thus determining it as the starting node of the data path detection range. Furthermore, the output pin o of instance i25 can be connected to the input pin d of instance end, the clock input terminal clk of instance end receives the corresponding clock signal, and the output pin q of instance end can be used as the output position of the subsequent stage. Therefore, in Figure 3 In the circuit shown, din_ff1, din_ff2, and din_ff3 form a register chain structure. The output pin q of example din_ff3 constitutes the synchronization control signal, and the output pin o of example i25 constitutes the first logic node. Although the corresponding logic device in the figure is a multiplexer i25 rather than an AND gate, both belong to the logic devices that carry the logical relationship between the synchronization control signal and the source signal. Therefore, using the output pin o of example i25 as the starting node of the data path detection range can also reflect the correspondence between the control path identification result and the starting position of the data path detection.

[0036] In one specific implementation, if the circuit under test contains a cross-clock domain control signal output from the source clock domain, and this cross-clock domain control signal is sequentially input into the first-level register and the second-level register in the destination clock domain, forming a register chain structure, then this register chain structure can be identified as a register chain structure that performs step-by-step synchronization of the cross-clock domain control signal, and determined as a synchronizer in the control path. The second-level register can be identified as the final-level register, and the control signal output by the second-level register can be identified as the synchronized control signal. When analyzing the subsequent logic along the output connection relationship of the synchronized control signal, if an AND gate is located on the data propagation path and simultaneously receives the source signal and the synchronized control signal as inputs, then the output node of the AND gate can be identified as the first logic node, and further determined as the starting node of the data path detection range. In this example, the register chain structure undertakes the step-by-step synchronization function in the control path, and the output node of the AND gate begins to carry the correspondence between the source signal propagation and the logic constraints of the synchronized control signal. Therefore, using this output node as the starting node of the data path detection range can reflect the correspondence between the control path identification result and the starting position of the data path detection. exist Figure 3 In the circuit shown, din_ff1, din_ff2, and din_ff3 form a register chain structure. The output pin q of example din_ff3 constitutes the synchronization control signal, and the output pin o of example i25 constitutes the first logic node. Although the corresponding logic device in the figure is a multiplexer i25 rather than an AND gate, both belong to the logic devices that carry the logical relationship between the synchronization control signal and the source signal. Therefore, using the output pin o of example i25 as the starting node of the data path detection range can also reflect the correspondence between the control path identification result and the starting position of the data path detection.

[0037] Through the above steps, the register chain structure that synchronizes the control signals across clock domains in the circuit under test can be identified first, thus completing the identification of the synchronizer in the control path. Then, the control signal output by the last register in the register chain structure is determined as the synchronized control signal, thus positioning the analysis boundary at the synchronizer output. Subsequently, based on the synchronized control signal, the output node of the logic operation device that receives the source signal and the synchronized control signal as inputs in the data path is identified as the first logic node, and this first logic node is determined as the starting node of the data path detection range. This provides a clear, stable, and consistent starting point for subsequent determination of the set of nodes to be tested and for further execution of data path synchronization validity checks.

[0038] As an optional implementation, logical calculations are performed on each node in the set of nodes to be detected one by one to determine whether the source signal in the logical result corresponding to each node to be detected is blocked by the synchronization control signal, and a state marker is established based on the determination result to characterize the cross-clock domain state of each node to be detected. This includes: identifying one or more path sets that can reach each node to be detected, the path sets being used to characterize the propagation path range of the synchronization control signal along the data path and reaching the corresponding node to be detected; performing logical calculations on one or more path sets respectively, and establishing state markers characterizing the cross-clock domain state of the path sets at the corresponding nodes to be detected, the state markers being used to record the cross-clock domain state of different path sets at the corresponding nodes to be detected; and determining the cross-clock domain state corresponding to each node to be detected based on one or more state markers corresponding to each node to be detected.

[0039] Specifically, in this embodiment, logical calculations can first be performed on one or more sets of paths that can reach each node to be detected, and corresponding state flags can be established. Then, the cross-clock domain state of the corresponding node to be detected can be determined based on these state flags. In this way, the effects of different sets of paths at the same node to be detected can be distinguished, making the determination of the cross-clock domain state accurate to the specific node to be detected, and providing a node-level analysis basis for subsequent determination of synchronization effectiveness detection results based on state flags.

[0040] In the step of identifying one or more sets of paths that can reach each node to be detected, where each path set represents the range of propagation paths along the data path after synchronization that can reach the corresponding node to be detected, one or more sets of paths that can reach the corresponding node to be detected can be identified first. Since the same node to be detected may be located in multiple path sets simultaneously, when analyzing the node to be detected, all path sets are not mixed together, but each path set is analyzed separately. This allows for the differentiation of different propagation path ranges corresponding to the control signal propagating along the data path to the current node to be detected after synchronization, thus providing a basis for subsequent separate logical calculations.

[0041] In the step of performing logical calculations on one or more path sets and establishing state markers representing the cross-clock domain state of each path set at the corresponding node to be detected, these state markers record the cross-clock domain state of different path sets at the corresponding node to be detected. After identifying one or more path sets reaching the current node to be detected, the current node to be detected is used as the analysis object. Logical calculations are performed on each path set to determine whether the source signal in the logical result corresponding to the current node to be detected is blocked by the synchronization control signal under the conditions of the corresponding path set. After obtaining the corresponding logical calculation results, state markers can be established. In other words, for each path set reaching the current node to be detected, a corresponding state marker can be established at that node to record the cross-clock domain state of that path set at that node. Since the same node to be detected can correspond to one or more path sets, one or more state markers can also be established at the same node to be detected, with each state marker corresponding to a different path set. In this way, the cross-clock domain state of each path set at the current node to be detected can be recorded one by one, thereby achieving a one-to-one correspondence between the path sets and the state of the node to be detected.

[0042] In this embodiment, the same node to be detected can correspond to one or more path sets. That is, if multiple path sets can reach the same node to be detected, then the node to be detected is simultaneously within the propagation path range corresponding to multiple path sets. In this case, multiple corresponding state markers can be established at the node to be detected for each path set, and each state marker is used to characterize the cross-clock domain state of the corresponding path set at that node to be detected. This avoids mixing the different effects of multiple path sets at the same node to be detected, thereby distinguishing the states of each node to be detected in the data path and retaining the state of each path set at the current node to be detected, providing a basis for subsequent comprehensive judgment of the cross-clock domain state corresponding to the current node to be detected.

[0043] For example, in one specific implementation, if a node to be detected is simultaneously located in a first path set and a second path set, logical calculations can be performed on the first path set and the second path set respectively. If the logical calculation result indicates that the source signal has been effectively blocked when the first path set reaches the node to be detected, a first state flag corresponding to the first path set can be established for the node to be detected to record the cross-clock domain state of the node under the first path set condition. If the logical calculation result indicates that the source signal has not been blocked when the second path set reaches the node to be detected, a second state flag corresponding to the second path set can be established for the node to be detected to record the cross-clock domain state of the node under the second path set condition. Subsequently, based on the first and second state flags, the cross-clock domain state corresponding to the node to be detected is comprehensively determined. Thus, even if the same node to be detected corresponds to multiple path sets, the states of each path set at the node to be detected can be recorded and utilized separately, thereby avoiding the simple merging of the state results of different path sets into a single judgment conclusion.

[0044] For example, in one specific implementation, if both the first path set and the second path set can reach the node to be detected, then the node to be detected corresponds to both the first path set and the second path set, and state markers corresponding to the first path set and the second path set can be established at the node to be detected, respectively. Similarly, if the node to be detected is covered by the propagation path ranges corresponding to the third path set, the fourth path set, and the fifth path set, then multiple state markers corresponding to the third path set, the fourth path set, and the fifth path set can be established at the node to be detected. Thus, the state of the same node to be detected can be recorded separately across clock domains under multiple path sets.

[0045] In the step of determining the cross-clock domain state of each node to be detected based on one or more state flags corresponding to each node to be detected, after the aforementioned state flag establishment is completed, each node in the set of nodes to be detected has established one or more state flags matching its corresponding path set. At this point, for any node to be detected, the one or more state flags corresponding to that node can be summarized, and the cross-clock domain state corresponding to that node can be determined based on the state flags. In other words, the cross-clock domain state corresponding to the current node to be detected is not directly given by a single logical calculation result, but is reflected by one or more state flags corresponding to that node to be detected. Since the state flags have already characterized the cross-clock domain state of each path set at the current node to be detected, the analysis results at the path set level can be elevated to the state determination at the node to be detected level based on these state flags. In other words, the previous steps solved the problem of what cross-clock domain state each path set is in at the node to be detected, while this step solves the problem of what cross-clock domain state the current node to be detected as a whole corresponds to. This two-level processing method enables the judgment process of cross-clock domain state to have a clear hierarchy, that is, firstly, state labels are established for each path set, and then the state of the node to be detected as a whole is determined.

[0046] Through the above steps, this implementation first identifies one or more sets of paths that can reach each node to be detected, and performs logical calculations on each set of paths to establish a state marker representing the cross-clock domain state of the path set at the corresponding node to be detected. Then, based on the one or more state markers corresponding to each node to be detected, the cross-clock domain state of each node to be detected is determined. Thus, the original state judgment directly targeting the node to be detected can be refined into a two-level processing procedure: first, state markers are established for each set of paths, and then the state of the node to be detected as a whole is determined. This improves the accuracy of cross-clock domain state identification of each node to be detected in the data path and enhances the traceability of subsequent synchronization effectiveness detection results.

[0047] As an optional implementation, the aforementioned status marker includes: a path set identifier representing the path set to which the status marker belongs, a node identifier representing the node to be detected, status information representing the cross-clock domain status of the node to be detected, source clock domain information to which the path set belongs, destination clock domain information to which the path set belongs, and a destination node identifier that the node to be detected can reach.

[0048] Specifically, in this embodiment, the path set identifier in the status marker is used to represent the path set to which the current status marker belongs, the node to be detected identifier is used to represent the node to be detected corresponding to the current status marker, the status information is used to represent the cross-clock domain status of the corresponding path set at the corresponding node to be detected, the source clock domain information is used to represent the source clock domain to which the corresponding path set belongs, the destination clock domain information is used to represent the destination clock domain to which the corresponding path set belongs, and the destination node identifier is used to represent the destination node that the corresponding node to be detected can reach when it continues to propagate along the corresponding path set. Thus, the status marker can not only represent the status result at the corresponding node to be detected, but also the path set to which the status result belongs, the clock domain affiliation, and the corresponding destination node information.

[0049] In this embodiment, a correspondence is established between the path set identifier, the node to be detected identifier, and the status information. That is, for any status marker, its path set identifier determines which path set it belongs to, its node to be detected identifier determines which node it corresponds to, and its status information determines the cross-clock domain state of the path set at that node. This allows for a clear association between the status marker, the path set, and the node to be detected, avoiding the confusion of different path sets' effects based solely on the overall state of the node to be detected.

[0050] Furthermore, in this embodiment, the state marker also includes source clock domain information and destination clock domain information of the corresponding path set. Since cross-clock domain problems essentially involve the propagation of source signals from the source clock domain to logic in the destination clock domain, simply recording the state itself is insufficient to fully reflect the cross-clock domain context of the node being detected in data path detection. By further recording source and destination clock domain information in the state marker, the state of each path set at the node being detected can have a clearer clock domain background, thereby helping to distinguish the state differences formed by different cross-clock domain path pairs at the same node being detected.

[0051] Furthermore, in this embodiment, the state flag also includes the identifier of the destination node that the corresponding node to be detected can reach. That is, in addition to recording the current state of the node to be detected, the state flag can also record the destination node information that can be reached when propagating from the node to be detected along the corresponding path set. Therefore, the cross-clock domain state of the current node to be detected can be associated with the corresponding destination node, so that the state flag not only reflects the current state of the node to be detected, but also reflects which destination node that state ultimately corresponds to, thus providing a more complete information basis for the subsequent output of synchronization validity detection results.

[0052] In this embodiment, when the same node to be detected is located in multiple path sets simultaneously, different path sets may not only correspond to different cross-clock domain states at the node to be detected, but these path sets may also correspond to different source clock domain information, destination clock domain information, and different destination node identifiers. In this case, by recording the path set identifier, node to be detected identifier, state information, source clock domain information, destination clock domain information, and destination node identifier in each state marker, the distinction between path source and clock domain levels can be further preserved when reading the state markers subsequently. This enhances the expressive power of the state markers, enabling them to not only reflect what the state is, but also which path set the state belongs to, which node to be detected it is located at, which source clock domain / destination clock domain relationship it corresponds to, and which destination node it can reach.

[0053] For example, in one specific implementation, if a first state marker corresponding to a first path set and a second state marker corresponding to a second path set exist simultaneously at the node to be detected a, then the path set identifier in the first state marker is used to indicate that it belongs to the first path set, and the path set identifier in the second state marker is used to indicate that it belongs to the second path set; the node to be detected identifiers of both are used to indicate that they are established at the node to be detected a; their state information is used to indicate the cross-clock domain state of the first path set and the second path set at the node to be detected a, respectively; their source clock domain information and destination clock domain information are used to indicate the source clock domain and destination clock domain to which the corresponding path set belongs, respectively; their destination node identifiers are used to indicate the destination node that the node to be detected a can reach along its respective corresponding path set. Similarly, at the node to be detected c, multiple state markers corresponding to the third path set, the fourth path set, and the fifth path set can be established respectively, and the state information, source clock domain information, destination clock domain information, and corresponding destination node identifier of the corresponding path set at the node to be detected c can be recorded respectively. Therefore, the states of multiple path sets, their source information, and destination node information can be retained simultaneously at the same node to be detected, thus providing a more complete data foundation for subsequent cross-clock domain state analysis, blocking state determination, and synchronization effectiveness detection results output.

[0054] Through the above settings, the status markers can simultaneously possess the functions of path set representation, node location, status representation, clock domain affiliation representation, and destination node association. Therefore, in the subsequent data path synchronization validity detection process, not only can the cross-clock domain status of each node under test be determined based on the status markers, but also, by combining the path set, source clock domain, destination clock domain, and destination node information, the scope of the synchronized control signals and potential risk nodes in the data path can be more accurately located and analyzed.

[0055] As an optional implementation, the above-mentioned state information includes a synchronization-maintained state, an unblocked state, and a blocked state. The synchronization-maintained state is used to indicate that no source signal has been encountered on the propagation path from the corresponding synchronized control signal to the corresponding node to be detected. The unblocked state is used to indicate that, under the conditions of the corresponding path set, the source signal still exists in the logical result of the current node to be detected. The blocked state is used to indicate that, under the conditions of the corresponding path set, the source signal no longer exists in the logical result of the current node to be detected.

[0056] Specifically, in this embodiment, the state information in the state flag is used to subdivide the specific cross-clock domain state of the corresponding path set at the corresponding node to be detected. The synchronization hold state corresponds to the situation where no source signal has been encountered on the propagation path from the corresponding synchronized control signal to the corresponding node to be detected. In this case, the corresponding path set has propagated to the current node to be detected, but no source signal requiring a determination of whether it has been blocked has been introduced on the propagation path. Therefore, the synchronization hold state can be used to characterize this propagation stage.

[0057] The unblocked state corresponds to the situation where, under the conditions of the corresponding path set, the source signal still exists in the logical result of the current node to be detected. In other words, after performing logical calculations on the current node to be detected, if the source signal still exists in the logical result, it means that the synchronized control signal has not yet caused the source signal to disappear from the logical result of the current node to be detected under the conditions of that path set. Therefore, the state information of the current node to be detected corresponding to that path set can be determined as the unblocked state.

[0058] The blocked state corresponds to the situation where, under the conditions of the corresponding path set, the source signal is no longer present in the logical result of the current node to be detected. In other words, after performing logical calculations on the current node to be detected, if the source signal is no longer present in the logical result of the current node to be detected under the conditions of the path set, it means that the synchronized control signal has prevented the source signal from being reflected in the logical result of the current node to be detected. Therefore, the state information of the current node to be detected corresponding to this path set can be determined as the blocked state.

[0059] In this embodiment, the three states described above correspond to different scenarios in the data path analysis process. The "synchronization maintained" state indicates that no source signal has been encountered on the propagation path from the corresponding synchronized control signal to the corresponding node under test; the "unblocked" state indicates that, under the conditions of the corresponding path set, the source signal still exists in the logical result of the current node under test; and the "blocked" state indicates that, under the conditions of the corresponding path set, the source signal no longer exists in the logical result of the current node under test. By classifying the state information as described above, the state differences of different path sets at the same node under test can be recorded more accurately.

[0060] exist Figure 2 In the example shown, since the propagation path of the synchronized control signal output from the output pin q of instance q1 to these positions has not yet encountered the introduced source signal, the corresponding state information can be determined as a synchronized holding state, and can be marked in the circuit diagram as the identifier SYNC representing the synchronized holding state; similarly, since the synchronized control signal controls the gating relationship of instance i18, there is no source signal in the logic result corresponding to the output pin o of instance i18, the state information corresponding to the output pin o of instance i18 can be determined as a blocked state, and can be marked in the circuit diagram as the identifier GATED representing the blocked state; similarly, since the input pin d of the subsequent register end directly receives the output signal from instance i18, and there is no source signal in the output signal, the state information corresponding to the input pin d can also be determined as a blocked state, and can be marked in the circuit diagram as the identifier GATED representing the blocked state. Conversely, if the control signal after synchronization does not eliminate the source signal from the output result of instance i18, the source signal will still exist in the logic result corresponding to the output pin o of instance i18. In this case, the state information corresponding to the node to be detected can be determined as an unblocked state, and can be marked as the identifier UNGATED representing the unblocked state in the circuit diagram.

[0061] The above method allows multiple state markers at the same node to record the specific state differences of different path sets at that node, thus providing a basis for determining the cross-clock domain state of the node to be detected based on one or more state markers, and further judging the effectiveness of data path synchronization.

[0062] As an optional implementation, the above-mentioned logic calculation is performed on each node in the set of nodes to be detected, determining whether the source signal in the logic result corresponding to each node to be detected is blocked by the synchronization control signal, and establishing a state flag to characterize the cross-clock domain state of each node to be detected based on the determination result, including: assigning logic values ​​0 and 1 to the source signal respectively, and performing logic function calculation on each node to be detected from the source signal to the target node to determine the logic function expression corresponding to each node to be detected; based on the logic function expression corresponding to each node to be detected, determining whether the logic variable corresponding to the source signal still exists in the logic result corresponding to each node to be detected; establishing a corresponding state flag at each node to be detected; if the logic variable corresponding to the source signal no longer exists in the logic result corresponding to the current node to be detected, then it is determined that the source signal no longer exists in the logic result of the current node to be detected, and the state flag corresponding to the current node to be detected is determined to be in a blocked state; if the logic variable corresponding to the source signal still exists in the logic result corresponding to the current node to be detected, then it is determined that the source signal still exists in the logic result of the current node to be detected, and the state flag corresponding to the current node to be detected is determined to be in an unblocked state.

[0063] Specifically, in this embodiment, the logical function expression corresponding to each node to be detected can be determined by assigning logical values ​​0 and 1 to the source signal, and then performing logical function calculations point by point on each node to be detected from the source signal to the target node. Here, the target node is the destination node on the same data path as the source signal, used to define the analysis endpoint of the logical function calculation. That is, after assigning different logical values ​​to the source signal, the logical relationship corresponding to each node to be detected can be calculated point by point along the propagation path from the source signal to the target node, thereby determining the logical function expression corresponding to each node to be detected.

[0064] In the step of determining whether the logical result of each node still contains the logical variable corresponding to the source signal based on the logical function expression corresponding to each node to be detected, the logical function expression of the current node to be detected can be further analyzed to determine whether the logical result still contains the logical variable corresponding to the source signal. If the logical function expression of the current node to be detected indicates that the logical result still contains the logical variable corresponding to the source signal, it means that the logical result of the current node to be detected still depends on the source signal; if the logical function expression of the current node to be detected indicates that the logical result no longer contains the logical variable corresponding to the source signal, it means that the logical result of the current node to be detected no longer depends on the source signal.

[0065] In the step of establishing corresponding state markers at each node to be detected, after completing the aforementioned logical function expression analysis, corresponding state markers can be established at each node to be detected to record the cross-clock domain state of the current node to be detected. Subsequently, if the logical result corresponding to the source signal no longer exists in the logical result of the current node to be detected, it can be determined that the source signal no longer exists in the logical result of the current node to be detected, and the state marker corresponding to the current node to be detected is determined to be in a blocked state; if the logical result corresponding to the source signal still exists in the logical result of the current node to be detected, it can be determined that the source signal still exists in the logical result of the current node to be detected, and the state marker corresponding to the current node to be detected is determined to be in an unblocked state. Thus, the blocking effect of the synchronized control signal on the propagation of the source signal can be implemented at the specific node to be detected.

[0066] In one specific implementation, a simple logic device can be used as an example. Assuming the logic device is an AND gate, with one input receiving the source signal `src` and the other input receiving the synchronized control signal `q`, and the output signal denoted as `out`, the logic function expression corresponding to the current node to be detected can be expressed as: `out = src AND q`. If this AND gate is located on the propagation path from the source signal to the target node, the output node of this AND gate can be considered one of the current nodes to be detected. During the logic function calculation, the source signal `src` is assigned logic values ​​0 and 1 respectively, and the logic result of the current node to be detected is analyzed to determine whether the logic variable corresponding to the source signal still exists. If the synchronized control signal `q` takes the logic value 0 in the logic function expression of the current node to be detected, then regardless of whether the source signal `src` takes the logic value 0 or 1, the logic result corresponding to the current node to be detected is 0, i.e., `out = src AND 0 = 0`. Therefore, the logic result corresponding to the current node to be detected no longer contains the logic variable corresponding to the source signal, and the state flag of the current node to be detected can be determined as a blocked state. If, in the logic function expression corresponding to the current node to be detected, the synchronized control signal q takes the logic value 1, then the logic function expression corresponding to the current node to be detected is out=src AND 1=src. In this case, the logic result corresponding to the current node to be detected still contains the logic variable corresponding to the source signal, thus the state flag corresponding to the current node to be detected can be determined as an unblocked state.

[0067] For example, in Figure 2In the circuit structure shown, the output pin q of example q1 can be determined as the output position of the control signal after synchronization, and the output pin o of example i18 can be taken as one of the nodes to be detected. If the input terminal a0 of example i18 corresponds to the input path of the source signal, then the logic variable corresponding to the source signal can be the input signal variable input to the input terminal a0. When analyzing the logic function expression corresponding to the output pin o of example i18, the input signal variable can be assigned logic values ​​0 and 1 respectively. If the output logic result no longer contains the input signal variable, it can be determined that the source signal does not exist in the logic result corresponding to the output pin o of example i18, and the state flag corresponding to the node to be detected is determined to be in the blocked state; if the output logic result still contains the input signal variable, it can be determined that the source signal still exists in the logic result corresponding to the output pin o of example i18, and the state flag corresponding to the node to be detected is determined to be in the unblocked state.

[0068] Using the above method, for different types of logic devices, as long as the logic function expression corresponding to the current node under test can be determined, and it can be judged whether the logic variable corresponding to the source signal still exists in the logic result corresponding to the current node under test, the state flag corresponding to the current node under test can be determined accordingly. Therefore, the blocking effect of the synchronized control signal on the propagation of the source signal can be accurately applied to the specific node under test, improving the accuracy of cross-clock domain state identification and providing a basis for subsequent determination of the data path synchronization effectiveness detection results based on the state flag.

[0069] As an optional implementation, the above output of the synchronization validity detection result for at least one node in the set of nodes to be detected includes: in response to a query of a node in the set of nodes to be detected, outputting one or more status flags corresponding to the node to be detected; if one or more status flags are in an unblocked state, outputting a detection result indicating that the node to be detected has a risk of being out of sync; if one or more status flags are in a blocked state or a synchronized state, outputting a detection result indicating that the node to be detected does not have a risk of being out of sync.

[0070] Specifically, in response to a query for a node in the set of nodes to be detected, one or more status flags corresponding to the node to be detected are output. This can be achieved by receiving a query request for any node in the set of nodes to be detected and reading one or more status flags already established at that node. Since status flags are used to characterize the cross-clock domain state of the corresponding node to be detected, the state information of the node to be detected under the corresponding path set conditions can be directly obtained by outputting one or more status flags. If the same node to be detected corresponds to one or more status flags, then one or more status flags corresponding to that node can be output accordingly to reflect the state differences of different path sets at that node.

[0071] In the step of outputting a detection result indicating a risk of desynchronization in the node under test if one or more status flags show an unblocked state, if one or more of the retrieved status flags show an unblocked state, it indicates that under the corresponding path set conditions, the logical result of the current node under test still contains the source signal, meaning that the synchronized control signal has not yet effectively blocked the source signal before the node under test. In this case, a detection result indicating a risk of desynchronization in the node under test can be output.

[0072] In the step of outputting a detection result indicating that the node under test has no risk of desynchronization if one or more status flags are in a blocked state or a synchronization-maintained state, if one or more status flags obtained by the query are in a blocked state or a synchronization-maintained state, it indicates that there is no unblocked situation at the current node under test in the corresponding path set. Specifically, if the status flag is in a blocked state, it indicates that under the conditions of the corresponding path set, there is no source signal in the logical result of the current node under test, that is, the synchronized control signal has effectively blocked the source signal before reaching the node under test; if the status flag is in a synchronization-maintained state, it indicates that no introduced source signal has been encountered on the propagation path from the corresponding synchronized control signal to the node under test. Based on the above two situations, a detection result indicating that the node under test has no risk of desynchronization can be output.

[0073] This implementation establishes a direct mapping from the state of the node to be detected to risk conclusions by associating state markers with detection result output rules. Specifically, if one or more state markers indicate an unblocked state, the corresponding output is a detection result indicating a risk of asynchronous operation; conversely, if one or more state markers indicate a blocked state or a synchronized state, the corresponding output is a detection result indicating no risk of asynchronous operation. This approach, while maintaining the traceability of state markers, further provides clear conclusions for the detection result output, thereby improving the readability and usability of the detection results.

[0074] For example, in one specific implementation, if a query is performed on node a to be detected and one or more of its corresponding status markers are all in a blocked state, then the detection result that node a to be detected has no risk of desynchronization can be further output. If a query is performed on node b to be detected and one or more of its corresponding status markers are all in a synchronized state, then the detection result that node b to be detected has no risk of desynchronization can be further output. If a query is performed on node c to be detected and one or more of its corresponding status markers are in an unblocked state, then the detection result that node c to be detected has a risk of desynchronization can be further output. Thus, based on one or more status markers corresponding to different nodes to be detected, corresponding synchronization effectiveness detection results can be given respectively.

[0075] Through the above steps, after establishing the state markers, in response to queries from the set of nodes to be tested, one or more state markers corresponding to the node to be tested can be output, and the synchronization validity test result of the corresponding node to be tested can be output based on one or more state markers. This not only preserves the node-level information of the cross-clock domain state of each node to be tested, but also further transforms the state information into clear risk judgment results, thus providing a more intuitive output format for data path synchronization validity analysis.

[0076] As an optional implementation, if the output pin of the current node under test is directly connected to the input signal pin of the subsequent logic operation device, one or more status flags corresponding to the current node under test are assigned to the input signal pin so that the input signal pin has one or more status flags that are the same as those of the output pin of the current node under test.

[0077] Specifically, in this embodiment, the nodes to be detected in the set of nodes to be detected are mainly the analysis nodes in the aforementioned logic calculation and state flag establishment process. Based on this, if the output pin corresponding to a certain current node to be detected is directly connected to the input signal pin of the subsequent logic operation device, and there is no new logic operation relationship in the connection process, then it is not necessary to re-perform the logic calculation for the input signal pin. Instead, one or more state flags corresponding to the current node to be detected can be directly assigned to the input signal pin.

[0078] In other words, in this embodiment, although the input signal pin does not participate in the aforementioned point-by-point logic calculation as an independent node in the set of nodes to be detected, it can inherit one or more status flags corresponding to the previous stage output pin when there is only a direct connection between it and the previous stage output pin. This allows the status flags to propagate continuously along the direct connection relationship in the data path, thereby maintaining the consistency of the status flags during signal transmission. For example, if the current node to be detected corresponding to the first logic operation device has already established one or more status flags, and the output pin of the current node to be detected is directly connected to the input signal pin of the second logic operation device, then one or more status flags can be directly assigned to the input signal pin of the second logic operation device. At this time, the input signal pin has one or more status flags identical to those of the previous stage output pin. If it is necessary to continue performing logic calculations on the node to be detected corresponding to the second logic operation device, the status flags corresponding to the node to be detected can be further determined based on the one or more status flags already inherited by the input signal pin, combined with the logic relationship corresponding to the second logic operation device.

[0079] Combination Figure 2In the actual circuit structure, the output pin q of instance q1 can be directly connected to the input pin d of instance latch1, the output pin q of instance latch1 can be directly connected to the control input terminal c of instance i18, and the output pin o of instance i18 can be directly connected to the input pin d of the subsequent register end. For these direct connections, since there is no new logical operation relationship between the output pins of the preceding stage and the input signal pins of the following stage, one or more status flags corresponding to the output pins of the preceding stage can be directly assigned to the input signal pins of the following stage. Thus, the status flag at the output pin q of instance q1 can be passed to the input pin d of instance latch1, the status flag at the output pin q of instance latch1 can be passed to the control input terminal c of instance i18, and the status flag at the output pin o of instance i18 can be passed to the input pin d of the subsequent register end, thereby more specifically illustrating the continuous transmission process of status flags between the input and output nodes.

[0080] By using the above method, we can avoid repeatedly performing logic calculations between adjacent pins that only have a direct connection relationship. At the same time, we can enable the status flag to be continuously propagated from the output pin of the previous stage to the input signal pin of the subsequent stage, thereby improving the continuity and calculation efficiency of the status flag establishment process, and providing a consistent input status basis for the status judgment of the corresponding node to be detected by the subsequent logic operation device.

[0081] In a second aspect of an exemplary embodiment of the present invention, an electronic device is provided. The electronic device includes: a processor and a memory for storing processor-executable instructions, wherein the processor-executable instructions, when executed by the processor, perform a cross-clock domain synchronization validity check method according to an exemplary embodiment of the present invention.

[0082] Figure 4 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present invention. Figure 4 As shown, the electronic device 410 includes a processor 401 and a memory 402 for storing processor-executable instructions. The processor-executable instructions, when executed by the processor, perform a cross-clock domain synchronization validity check method according to an exemplary embodiment of the present invention.

[0083] As an example, electronic device 410 is not necessarily a single device, but can be a collection of any means or circuits capable of executing the aforementioned instructions (or instruction sets) individually or in combination. Electronic device 410 can also be part of an integrated control system or system manager, or can be configured to interface with a server locally or remotely (e.g., via wireless transmission).

[0084] In electronic device 410, processor 401 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, processor 401 may also include analog processors, digital processors, microprocessors, multi-core processors, processor arrays, network processors, etc.

[0085] The processor 401 can execute instructions or code stored in the memory 402, which can also store data. Instructions and data can also be sent and received via a network through a network interface device, which can employ any known transmission protocol.

[0086] The memory 402 may be integrated with the processor 401, for example, by arranging random access memory (RAM) or flash memory within an integrated circuit microprocessor. Alternatively, the memory 402 may comprise a separate device, such as an external disk drive, a storage array, or other storage device usable by a database system. The memory 402 and the processor 401 may be operatively coupled or communicate via input / output ports, network connections, etc., enabling the processor 401 to read files stored in the memory 402.

[0087] The communication interface 403 is used to enable data communication between the electronic device 410 and external devices. Specifically, the communication interface 403 may include a wired communication interface or a wireless communication interface for data interaction with external servers, database systems, or other electronic devices via a network. For example, the communication interface 403 may support Ethernet interfaces, wireless LAN interfaces, cellular communication interfaces, Bluetooth interfaces, or other network communication interfaces.

[0088] In addition, electronic device 410 may also include a video display (e.g., a liquid crystal display) and a user interaction interface (e.g., a keyboard, mouse, touch input device, etc.). The components in electronic device 410 can be interconnected via a bus or network.

[0089] In an exemplary embodiment, a computer-readable storage medium is also provided, which, when the instructions in the computer-readable storage medium are executed by the processor of an electronic device, enables the electronic device to perform the cross-clock domain synchronization validity check method as described in the exemplary embodiment above.

[0090] Computer-readable storage media can be memory that stores computer programs. For example, computer-readable storage media can include, but are not limited to: read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, DVD-ROM, Blu-ray disc, hard disk drive (HDD), solid-state drive (SSD), memory card (e.g., SD card or multimedia card), magnetic tape, floppy disk, magneto-optical storage device, and other storage media capable of storing computer programs in a non-transitory manner and allowing them to be executed by a processor.

[0091] Computer programs can be deployed and run on clients, hosts, servers, or other computer devices. In one embodiment, the computer program and related data can also be distributed across a networked computer system, enabling the computer program and related data to be stored, accessed, and executed in a distributed manner through one or more processors.

[0092] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0093] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0094] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for checking the validity of cross-clock domain synchronization, characterized in that, Includes the following steps: The output node of the logic operation device that receives the source signal and the synchronized control signal as input in the data path is identified as the first logic node, and the first logic node is determined as the starting node of the data path detection range. Starting from the starting node, the output nodes of other logic devices in the data path are identified as nodes to be detected along the data propagation direction, and the starting node and each identified node to be detected are determined as the set of nodes to be detected within the detection range of the data path. Logical calculations are performed on each node in the set of nodes to be detected to determine whether the source signal in the logical result corresponding to each node to be detected is blocked by the synchronized control signal, and a state flag is established based on the determination result to characterize the cross-clock domain state of each node to be detected. Based on the status flags corresponding to each node in the set of nodes to be detected, the blocking status of the synchronized control signal to the source signal in the data path is determined, and a synchronization effectiveness detection result for at least one node in the set of nodes to be detected is output, wherein the synchronization effectiveness detection result includes the status flags of the corresponding node to be detected.

2. The method for checking the validity of cross-clock domain synchronization according to claim 1, characterized in that, The output node of the logic processing device that receives the source signal and the synchronized control signal as input in the identification data path is designated as the first logic node, and the first logic node is determined as the starting node of the data path detection range, including: Identify the register chain structure in the circuit under test that performs step-by-step synchronization of control signals across clock domains, and determine the register chain structure as the synchronizer in the control path; The control signal output by the last-stage register of the register chain structure is determined as the synchronization control signal; Based on the synchronized control signal, the output node of the logic operation device that receives the source signal and the synchronized control signal as input in the data path is identified as the first logic node, and the first logic node is determined as the starting node of the data path detection range.

3. The method for checking the validity of cross-clock domain synchronization according to claim 1, characterized in that, The step involves performing logical calculations on each node in the set of nodes to be detected, determining whether the source signal in the logical result corresponding to each node is blocked by the synchronized control signal, and establishing a state flag to characterize the cross-clock domain state of each node based on the determination result, including: Identify one or more sets of paths that can reach each node to be detected. The set of paths is used to characterize the propagation path range of the control signal after synchronization along the data path and can reach the corresponding node to be detected. Perform logical calculations for the one or more sets of paths respectively, and establish a state flag characterizing the cross-clock domain state of the set of paths at the corresponding node to be detected. The state flag is used to record the cross-clock domain state of different sets of paths at the corresponding node to be detected. Based on one or more of the state flags corresponding to each node to be detected, the cross-clock domain state corresponding to each node to be detected is determined.

4. The method for checking the validity of cross-clock domain synchronization according to claim 1, characterized in that, The status marker includes: a path set identifier representing the path set to which the status marker belongs, a node identifier representing the node to be detected, status information representing the cross-clock domain status of the node to be detected, source clock domain information to which the path set belongs, destination clock domain information to which the path set belongs, and a destination node identifier that the node to be detected can reach.

5. The method for checking the validity of cross-clock domain synchronization according to claim 4, characterized in that: The state information includes a synchronization-maintained state, an unblocked state, and a blocked state. The synchronization-maintained state indicates that no source signal has been encountered on the propagation path from the corresponding synchronized control signal to the corresponding node to be detected. The unblocked state indicates that, under the conditions of the corresponding path set, the source signal still exists in the logical result of the current node to be detected. The blocked state indicates that, under the conditions of the corresponding path set, the source signal no longer exists in the logical result of the current node to be detected.

6. The method for checking the validity of cross-clock domain synchronization according to claim 1, characterized in that, The step involves performing logical calculations on each node in the set of nodes to be detected, determining whether the source signal in the logical result corresponding to each node is blocked by the synchronized control signal, and establishing a state flag to characterize the cross-clock domain state of each node based on the determination result, including: The source signal is assigned logic values ​​0 and 1 respectively, and logic function calculations are performed point by point on each node to be detected from the source signal to the target node to determine the logic function expression corresponding to each node to be detected. Based on the logical function expression corresponding to each node to be detected, determine whether the logical variable corresponding to the source signal still exists in the logical result corresponding to each node to be detected. Establish corresponding status markers at each node to be detected; If the logical result corresponding to the source signal does not exist in the logical result of the current node to be detected, then it is determined that the source signal does not exist in the logical result of the current node to be detected, and the state flag corresponding to the current node to be detected is determined to be blocked. If the logical result corresponding to the source signal still exists in the logical result of the current node to be detected, then it is determined that the source signal still exists in the logical result of the current node to be detected, and the state flag corresponding to the current node to be detected is determined to be in an unblocked state.

7. The method for checking the validity of cross-clock domain synchronization according to claim 5, characterized in that, The output includes the synchronization validity detection result for at least one node in the set of nodes to be detected, including: In response to a query for a node to be detected in the set of nodes to be detected, one or more status flags corresponding to the node to be detected are output. If any of the one or more status flags are in an unblocked state, then the detection result indicating that the node to be detected has a risk of being out of sync is output. If all one or more status flags are in a blocked state or a synchronization maintained state, then the detection result indicating that the node to be detected does not have a risk of desynchronization is output.

8. The method for checking the validity of cross-clock domain synchronization according to claim 3, characterized in that, If the output pin signal of the current node under test is directly connected to the input signal pin of the subsequent logic device, then the status flag of the current node under test is assigned to the input signal pin so that the input signal pin and the output pin signal of the current node under test have the same status flag.

9. An electronic device, characterized in that, include: processor; Memory for storing processor-executable instructions, wherein the processor-executable instructions, when executed by the processor, perform the cross-clock domain synchronization validity check method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the cross-clock domain synchronization validity check method according to any one of claims 1 to 8.

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