An esd conducted emission method and system based on device shot noise modeling

Abstract

The application provides an ESD conduction emission method and system based on device shot noise modeling. The method comprises the following steps: constructing a frequency domain impedance model of a power distribution network based on packaging data of a target chip; converting an extracted device shot noise power spectrum density into an equivalent noise source; inputting the equivalent noise source into the frequency domain impedance model of the power distribution network and performing transient simulation to output a predicted transient simulation result; and realizing ESD conduction emission based on the transient simulation result. The application takes the shot noise power spectrum density of an ESD avalanche breakdown process as a physical driving source of electromagnetic conduction emission, realizes the mapping relationship between device-level noise characteristics and system-level conduction emission response, avoids inefficient full-wave electromagnetic simulation, and has simple simulation process and high stability. The application can predict the electromagnetic emission trend of a chip under an ESD event in a chip design stage, and can select a scheme by comparing the shot noise characteristics of different ESD devices.

Description

Technical Field

[0001] This application relates to the field of electromagnetic emission modeling for integrated circuits, specifically to an ESD conducted emission method and system based on device shot noise modeling. Background Technology

[0002] Electrostatic discharge (ESD), as a ubiquitous and transiently energy-intensive source of interference, poses a dual threat to the electromagnetic compatibility (EMC) of highly integrated system-in-package (SiP / SoC) and high-speed chips. ESD pulses introduce high-amplitude voltage / current pulses on the nanosecond to tens of nanosecond scale, accompanied by strong electric fields, avalanche breakdown, and localized thermal effects. This can directly lead to device malfunction or permanent damage, or it can couple broadband energy into power and signal networks through parasitic coupling paths, resulting in significant conducted emission (CE). In heterogeneous integration environments such as SiP, complex packaging, wiring, and multi-port interfaces make coupling paths and resonant modes more diverse and unpredictable, further amplifying the ESC problems caused by ESD.

[0003] Currently, research and analysis paradigms for electromagnetic interference caused by electrostatic discharge (ESD) mainly focus on two levels. The first type of method emphasizes system-level electromagnetic field coupling simulation. These methods rely on full-wave electromagnetic field algorithms, such as the Finite-Difference Time-Domain (FDTD) method or the Partial Element Equivalent Circuit (PEEC) method, to calculate the coupling noise of the spatial electromagnetic field generated by the ESD pulse to internal sensitive signal lines by accurately modeling printed circuit boards, package structures, cables, etc. While these methods have some value in analyzing the coupling mechanisms of known systems, they consume enormous computational resources, have long simulation cycles, and heavily rely on a complete model of the system structure. More importantly, they essentially treat ESD interference as a purely external excitation source, focusing on how the external field couples into the system, without delving into the internal workings of the chip, especially the new noise generated by the changes in the semiconductor physical characteristics of the ESD protection device itself after triggering conduction. This black-box approach ignores the potential role of the ESD device as an internal noise source, transforming it from a protective element. The second type of method relies on statistical and a posteriori analysis of experimental data. By comparing conducted and radiated emissions before and after chip failure following ESD testing (such as IEC 61000-4-2) or electrical fast transient pulse (EFT) testing (such as IEC 62215-3), the correlation between ESD events and increased EMI levels can be empirically established. However, by the time a problem is discovered, the chip design is already fixed, making modifications extremely costly. Furthermore, purely experimental methods struggle to reveal the underlying physical mechanisms and cannot answer the fundamental question of why one ESD structure is superior to another, leaving design optimization without theoretical guidance.

[0004] Furthermore, the transient time during ESD events is only tens of nanoseconds, while standard conducted emission tests are typically measured using second-level integration or quasi-peak detection methods. This cross-timescale energy transfer and system response mechanism lacks effective theoretical support. Existing methods cannot explain why short-duration ESD events can generate significant signals in long-duration CE measurements. Therefore, there is an urgent need for a novel modeling and prediction method that starts from the device physical layer and can analyze how inherent noise energy under ESD excitation couples through the chip power network to form conducted emissions. This method would be crucial for assessing potential EMI risks and guiding the design of protection circuits during the chip design phase. Summary of the Invention

[0005] In view of the problem that in the past, when problems were discovered in practical applications, the chip design was often already fixed and the cost of modification was extremely high, this application provides an ESD conducted emission method based on device shot noise modeling.

[0006] The first aspect of this application provides an ESD conducted emission method based on device shot noise modeling, the method comprising: A frequency domain impedance model of the power distribution network is constructed based on the packaging data of the target chip. The extracted device shot noise power spectral density is converted into an equivalent noise source. The equivalent noise source is then input into the power distribution network model and transient simulation is performed. The predicted transient simulation results are then output. Based on the transient simulation results, ESD conducted emission is achieved.

[0007] Optionally, constructing the power distribution network model based on the target chip's packaging data includes: Obtain the target chip's package structure data, pin definition data, and stack-up information; Parasitic parameters are generated by extracting package structure data, pin definition data, and stack-up information through electromagnetic simulation. A frequency domain impedance model from the internal power solder joints to the external power supply pins of the target chip is established based on parasitic parameters. The frequency domain impedance model is verified, and the parameters of the frequency domain impedance model are corrected.

[0008] Optionally, the verification of the frequency domain impedance model and the correction of the frequency domain impedance model parameters include: Based on a dedicated test PCB board, a vector network analyzer is used to measure the parameters of the chip pins and generate measurement results. The measurement results are compared with the simulation results of the frequency domain impedance model to generate comparison results; The parameters of the frequency domain impedance model are corrected based on the comparison results.

[0009] Optionally, the extracted device shot noise power spectral density includes: In the TCAD simulation platform, the physical structure of the ESD device is constructed and meshed. Apply a bias voltage to the ESD device to trigger it into an avalanche breakdown state; In the triggered state, a shot noise physical model is introduced, specifying the observation node; The power spectrum of shot noise was extracted using the noise analysis function of the simulation tool.

[0010] Optionally, the physical structure for constructing the ESD device includes: Based on the size structure and doping requirements of the target process, determine the physical parameters of the device; Build the three-dimensional physical structure of the device in the simulation platform; Mesh refinement is performed in the high-field region of the PN junction to optimize simulation accuracy.

[0011] Optionally, converting the extracted device shot noise power spectral density into an equivalent noise source includes: The power spectrum of shot noise is transformed into the time domain using mathematical tools to obtain the time-domain noise waveform; The time-domain noise waveform is encapsulated into a standard format file to form an equivalent noise current source; The characteristics of the equivalent noise current source are verified to ensure that they are consistent with the power spectrum of shot noise.

[0012] Optionally, the step of inputting the equivalent noise source into the power distribution network model and performing transient simulation, and outputting the predicted transient simulation results, includes: Import the equivalent noise source and power distribution network model into the circuit simulation environment; Construct a system-level noise coupling simulation circuit that includes a load network; Configure the simulation parameters of the ICEM-CE modeling framework and start the transient simulation; Collect noise voltage response data during the simulation process.

[0013] Optionally, the method further includes: Frequency domain transformation is performed on the noise voltage response data acquired in the simulation. The noise voltage amplitude at different frequencies is extracted to form the conducted emission spectrum; Organize the conducted emission spectrum into a horizontal conducted emission curve and clarify the relationship between the frequency and amplitude of the curve.

[0014] Optionally, the implementation of ESD conducted emission based on the transient simulation results includes: Repeat the simulation steps by changing the shot noise power spectrum of different types of ESD devices; By comparing multiple sets of conducted emission level curves, the correlation between ESD device type and conducted emission level is analyzed. Based on the correlation analysis results, the ESD conduction emission of the target chip was completed.

[0015] A second aspect of this application provides an ESD conducted emission system based on device shot noise modeling, the system comprising: The model building module is used to build a frequency domain impedance model of the power distribution network based on the packaging data of the target chip. The prediction module is used to convert the extracted device shot noise power spectral density into an equivalent noise source, input the equivalent noise source into the power distribution network model and perform transient simulation, and output the predicted transient simulation results. The transmission module is used to realize ESD conducted transmission based on the transient simulation results.

[0016] As can be seen from the above technical solution, this application realizes the mapping relationship between device-level noise characteristics and system-level conducted emission response by using the shot noise power spectral density of the ESD avalanche breakdown process as the physical driving source of electromagnetic conducted emission. This method avoids inefficient full-wave electromagnetic simulation, and the simulation process is simple and highly stable. It can predict the electromagnetic emission trend of the chip under ESD events during the chip design stage, and select the appropriate solution by comparing the shot noise characteristics of different ESD devices. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating an ESD conducted emission method based on device shot noise modeling in an embodiment of this application.

[0019] Figure 2(a) is a schematic diagram of the SiP control chip packaging structure of this application.

[0020] Figure 2(b) is a schematic diagram of the logical and physical layout structure of the internal functional modules of the chip in this application.

[0021] Figure 3 This is a schematic diagram of the impedance testing platform structure built in this application.

[0022] Figure 4(a) is a schematic diagram of the equivalent circuit model structure of the package-level PDN built in ADS in this application.

[0023] Figure 4(b) is a linear graph comparing the simulation and experimental results of this application.

[0024] Figure 5 This is a schematic diagram of the equivalent model structure of PCB vias and copper traces constructed in this application.

[0025] Figure 6 This is a data comparison and verification diagram of an embodiment of this application.

[0026] Figure 7 This is a schematic diagram of the frequency domain impedance model of this application.

[0027] Figure 8(a) is a schematic diagram of the GGNMOS structure of the basic structure of this application.

[0028] Figure 8(b) is a schematic diagram of the GGNMOS structure with multiple emitters in this application.

[0029] Figure 8(c) is a schematic diagram of the GGNMOS structure with extended drain structure of this application.

[0030] Figure 9 This is a schematic diagram of an ESD conducted emission system based on device shot noise modeling in an embodiment of this application.

[0031] Reference numerals: 1: Frame; 2: Cover plate; 3: Chip; 4: Passive device; 5: Substrate; 6: Kovar lead; 7: Metal heat sink; 8: Gold wire; 9: Ceramic insulator. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] This application focuses on a system-in-package (SoC) control chip in a CFP36 package. This chip integrates FPGA, LDO, ADC, and DAC modules internally, and has multiple power supply pins and signal interfaces externally. The design phase requires assessment of the conducted emission risk caused by ESD events to provide a basis for selecting an ESD protection solution. The overall flow of the ESD conducted emission method based on device shot noise modeling in this application is as follows: Figure 1As shown, the process sequentially executes the following steps: constructing the frequency domain impedance model of the power distribution network, extracting the power spectral density of device shot noise, converting the equivalent noise source, performing system-level transient simulation, processing simulation results, and implementing ESD conducted emissions. These steps are closely linked, forming a complete analysis chain from the device physical layer to system-level electromagnetic emissions. The specific implementation process is as follows: S101, Construct a frequency domain impedance model of the power distribution network based on the packaging data of the target chip; S102, the extracted device shot noise power spectral density is converted into an equivalent noise source, the equivalent noise source is input into the power distribution network model and transient simulation is performed, and the predicted transient simulation results are output. S103, based on the transient simulation results, realize ESD conducted emission.

[0034] It should be noted that the target chip in this application is a CFP36 packaged SiP control chip, whose package structure is shown in Figure 2(a). It includes components such as a frame 1, a cover plate 2, a chip 3, passive devices 4, a substrate 5, Kovar leads 6, a metal heat sink 7, gold wires 8, and ceramic insulators 9. First, the complete package structure data of the target chip is obtained through chip design documents and packaging process drawings, including substrate size, number of stacked layers, characteristics of dielectric materials of each layer, width and thickness of metal wiring, length and diameter of gold wire bonding, and geometric structural parameters such as the arrangement of Kovar leads. At the same time, the pin definition data of the chip is obtained to clarify the functional type of each pin, distinguish between power supply pins, signal pins, and ground pins, and record the connection relationship between each power supply pin and the internal power network of the chip. In addition, the stacked layer information of the chip package is obtained, including but not limited to the dielectric constant, permeability, and thickness of each stacked layer, as well as the layout of each layer of metal wiring, and the position and size of vias. Figure 2(b) is the logic and physical layout diagram of the internal functional modules of the chip. In this diagram, the FPGA acts as the system hub, responsible for scheduling all modules. The low dropout linear regulator (LDO) is used to convert the input voltage into the stable voltage required by the module. It should be noted that the analog-to-digital converter (ADC) is responsible for receiving analog signals and converting them into digital signals for FPGA processing. The digital-to-analog converter (DAC) converts the digital signals processed by the FPGA into analog signals for output. The analog circuit area is a dedicated analog signal processing area for Analog. The interface communication uses the RS422 differential communication interface commonly used in industry, corresponding to the external pin VS510. The input signals on the left enter the PIN pin and are connected to the internal system. The power rails VSS, VDD1, and VDD2 clearly divide the power supply network of different areas.

[0035] The aforementioned package structure data, pin definition data, and stack-up information form the basis for constructing the power distribution network model. It is necessary to ensure the integrity and accuracy of the data. For subtle structural parameters that are not explicitly stated in the design document, reasonable supplementation should be made in conjunction with industry-standard packaging process specifications to ensure that the model construction can fit the actual physical structure of the chip. This application does not impose any restrictions on this.

[0036] It should be noted that the transient time during ESD is only tens of nanoseconds, while standard conducted emission tests are usually measured using second-level integration or quasi-peak detection methods, which cannot explain the significant signals generated by short-term ESD events in long-term CE measurements. Therefore, there is an urgent need for a novel modeling and prediction method that starts from the device physical layer and can analyze how the inherent noise energy under ESD excitation is coupled through the chip power network to form conducted emissions, so as to assess potential EMI risks and guide the design of protection circuits during the chip design stage. To analyze the above process, this application uses a method combining transmission line theory and chain noise modeling to explain the formation mechanism of chip electromagnetic emissions caused by electrostatic discharge, while meeting the following conditions. Under the condition that the size of the ESD device is... Much smaller than the wavelength of the highest noise frequency When there is no phase difference, the ESD plasma channel can be equivalent to a Hertzian dipole, and its transient behavior can be described by the transmission line equations: ,

[0037] in, and Let x represent the voltage and current at position x along the line, respectively. and Given the impedance and admittance matrices per unit length, a chain noise analysis method is introduced to describe the transformation of noise from the transmission line to the chip port. This transforms a noisy network containing complex internal noise sources into an equivalent noise-free two-port network, with two external equivalent noise sources added to its input: a series noise voltage source. and a parallel noise current source Based on the Y parameter, the spectral density of the equivalent input noise voltage source The calculation formula is:

[0038] in, This represents the noise current spectral density at the output port in the admittance representation. Given the positive transfer admittance in the Y matrix, the equivalent noise resistance of the noise voltage source is calculated using the following formula:

[0039] in, It is Boltzmann's constant. It is the standard noise temperature.

[0040] The formula for calculating relevant admittance is:

[0041] in, It is related to electrical conductance. It is a related inductance.

[0042] The spectral density of the equivalent input noise current source is:

[0043] The equivalent noise conductance is expressed as:

[0044] in, This represents the noise current spectral density at the input port in admittance representation. To express the cross-correlation spectral density between the input and output current noise sources in the admittance representation, we can see from the formula for calculating the spectral density of the equivalent input noise current source that, for a noise network, introducing... , , Three parameters are used to reflect its noise characteristics. Among them, This reflects the correlation between the source impedance and the network input impedance, affecting noise transmission. and This reflects the inherent noise level of the network itself. Substituting the equivalent noise resistance and equivalent noise conductance from the formula into the spectral density of the equivalent input noise current source, we can obtain:

[0045] Spectral density of equivalent input noise current source It is a noise voltage source Noise current source Coupling admittance with the line The associated function. By comparing the transmission line model and the two-port noise model, a major theoretical equivalence is proposed: the response of ESD induced on the line can be represented. and These are respectively equivalent to the input noise sources of a two-port network. and Based on this, the main relation is derived:

[0046] One end of this formula represents the macroscopic response of ESD field coupling. and The other end is the spectral density of the equivalent input noise current source of the driver chip's internal circuitry. .

[0047] Inside the chip, ESD protection devices such as diodes, GGNMOS, or SCRs enter avalanche ionization or parasitic transistor triggering states under high electric fields. During an avalanche, random collisional ionization of charge carriers generates shot noise, the power spectral density of which can be approximated as: Where q is the electron charge, Here, M represents the injected current, and M is the avalanche multiplication factor. At the chip system level, the transient electromagnetic field generated by an ESD event couples equivalent noise voltage and current onto the chip's power supply network and interconnects. Theoretical analysis shows that this coupling response can be equivalently represented as the excitation source of the chip's internal noise two-port network. The strong shot noise generated by the ESD device at the moment of conduction is the most significant physical component of this equivalent excitation source. The enhancement of shot noise Si directly leads to an increase in the intensity of the internal equivalent noise source. This noise then propagates through the chip's power distribution network, and the resonant characteristics of the PDN selectively amplify noise in specific frequency bands, ultimately manifesting as conducted electromagnetic emission at the chip ports.

[0048] In summary, shot noise is the primary form of noise in ESD devices. The stronger the shot noise, the greater the electromagnetic emission generated through the internal noise transmission network after it couples into the chip. Therefore, characterizing shot noise is crucial for evaluating the electromagnetic emission level caused by ESD-induced noise coupling into the chip.

[0049] In one embodiment achievable under this application, constructing the power distribution network model based on the packaging data of the target chip includes: S201, Obtain the target chip's package structure data, pin definition data, and stack-up information; S202 extracts package structure data, pin definition data and stack-up information through electromagnetic simulation to generate parasitic parameters; S203, establishes a frequency domain impedance model from the internal power solder joints of the target chip to the external power supply pins based on parasitic parameters; S204 verifies the frequency domain impedance model and corrects the parameters of the frequency domain impedance model.

[0050] It should be noted that, based on the acquired packaging structure data, pin definition data and stack-up information, a professional electromagnetic simulation tool is used to build a three-dimensional electromagnetic model of the chip package. This application uses the ADS electromagnetic simulation module to restore the packaging structure and power distribution network of the target chip according to the actual size, material and layout parameters, including power wiring, ground wiring, gold wire bonding structure, pin connection structure and so on on the substrate.

[0051] In the electromagnetic simulation environment, the simulation frequency range is set to DC-1GHz. This frequency range covers the main frequency bands of conducted emissions caused by ESD events and meets the conventional frequency range requirements for chip electromagnetic compatibility testing. Using the field-circuit coupling analysis function of the electromagnetic simulation tool, the built three-dimensional electromagnetic model is simulated in the frequency domain to extract the parasitic parameters of the power distribution network from the internal power solder joints to the external power supply pins, including parasitic resistance, parasitic inductance, parasitic capacitance, distributed resistance and inductance of metal wiring, distributed capacitance of dielectric materials, parasitic inductance of gold wire bonding, parasitic resistance and inductance of vias, and parasitic capacitance between pins and the substrate.

[0052] The extraction of parasitic parameters covers all critical paths of the power distribution network, including the connection paths between each VDD1, VDD2 power supply pin and the VSS ground pin, and the connection paths between the power solder joints of each functional module inside the chip and the external power supply pins. The extracted parasitic parameters are output in the form of a parameter list and a distributed parameter network, providing data support for the subsequent establishment of the frequency domain impedance model.

[0053] Based on the extraction of parasitic parameters, a frequency domain impedance model of the power distribution network of the target chip is constructed in the circuit simulation environment. This model is divided into two parts: a package-level PDN model and a board-level PDN model, which are finally integrated to form a complete frequency domain impedance model.

[0054] It should be noted that this application uses the extracted parasitic parameters of the packaging structure as a basis and adopts a combination of lumped parameters and distributed parameters to build an equivalent circuit model of the package-level PDN in ADS, as shown in Figure 4(a). This model uses passive R, L, and C components to simulate the parasitic characteristics of the packaging structure, fully characterizing the impedance characteristics from the internal power solder joints of the chip to the package pins. The input ports of the model correspond to the power solder joints of each functional module inside the chip, and the output ports correspond to the external power supply pins of the chip. For structures with obvious distributed characteristics, such as gold wire bonding and Kovar leads, a transmission line model is used to simulate their impedance characteristics; for short-distance metal wiring on the substrate, lumped parameters R, L, and C are used to simulate their parasitic characteristics. Subsequently, the component parameters in the model are iteratively adjusted to match the simulated impedance curve with the measured results. It is required that the simulation and measured results have good consistency within the calibrated frequency band, as shown in Figure 4(b), to verify the accuracy of the package-level PDN model.

[0055] It should be noted that this application imports the actual PCB layout into the electromagnetic simulation tool of ADS, and constructs an equivalent model of the PCB vias and copper traces according to the actual layer stack-up order and process parameter settings. Figure 5 The impedance characteristics were extracted through simulation and compared with data directly extracted from the layout for verification. Figure 6 In the range of 10³Hz to 10 9Within a wide frequency range of Hz, the simulation curves of Z11, Z12, Z21, and Z22 almost completely overlap with the layout-extracted curves. The impedance amplitude of both curves maintains a high degree of consistency with the frequency variation trend, and the numerical deviations at each frequency point are within the extremely small range acceptable for engineering applications. The above comparison results fully demonstrate that the via and copper trace equivalent model constructed based on the actual PCB layout in this application can accurately reproduce the real impedance characteristics of the PCB transmission link. The fidelity and accuracy of the model have been effectively verified. This model can replace the complex physical layout and be directly used for subsequent engineering applications such as ESD conducted emission simulation and power distribution network analysis, greatly improving efficiency and feasibility while ensuring simulation accuracy.

[0056] It should be noted that this application electrically connects the package-level PDN model and the board-level PDN model in the circuit simulation environment. The output ports of the package-level PDN model correspond one-to-one with the input ports of the board-level PDN model, realizing the complete power distribution network modeling from the internal power solder joints of the chip to the external power supply / grounding interface of the PCB, forming the final frequency domain impedance model. A complete topology example is shown below. Figure 7 This model can output the impedance characteristics between any two points in the power distribution network within the DC-1GHz frequency range, providing a network foundation for subsequent noise source injection and transient simulation.

[0057] In one embodiment that can be implemented in this application, the verification of the frequency domain impedance model and the correction of the frequency domain impedance model parameters include: S301, based on a dedicated test PCB board, uses a vector network analyzer to measure the parameters of the chip pins and generate measurement results; S302, compare the measurement results with the simulation results of the frequency domain impedance model to generate comparison results; S303, based on the comparison results, corrects the parameters of the frequency domain impedance model.

[0058] To ensure the accuracy and fidelity of the frequency domain impedance model, it is necessary to verify the model by comparing actual measurement results with simulation results, and then correct the model parameters based on the comparison results. The specific implementation process is as follows: Based on the pin definitions and package dimensions of the target chip, a dedicated impedance testing PCB board is designed and fabricated, such as... Figure 3As shown, the test board adopts a star-shaped microstrip line array structure. Each microstrip line branch has a pad at its end that matches the chip pins for soldering the SiP chip under test. The star structure effectively reduces crosstalk between microstrip line branches, ensuring the accuracy of measurement results. A calibration port is reserved on the test board for TRL calibration, eliminating parasitic errors inherent in the test system itself. The SiP chip under test is soldered onto a dedicated test PCB board, and an impedance testing platform is built. This platform uses a vector network analyzer as its core, and the test port of the vector network analyzer is connected to the calibration port of the test PCB board and the chip pins via RF cables. First, the test system is calibrated using TRL. After calibration, the S-parameters of the target VDD1-VSS and VDD2-VSS power supply pins of the chip are measured. The measurement frequency range is consistent with the DC-1GHz electromagnetic simulation frequency range. The measured S-parameters are converted into impedance parameters to generate the actual measured impedance results, including the impedance values ​​between each power supply pin and ground pin at different frequencies.

[0059] The frequency domain impedance model is simulated within the same frequency range to obtain the simulated impedance results. The simulated impedance curve and the actual measured impedance curve are plotted, and the trends and numerical differences between the two curves are compared to generate a comparison result. If the simulated curve and the measured curve show consistent trends across the entire frequency range, and the numerical deviation is within a preset allowable deviation range (for example, the preset allowable deviation range in this application is ≤10%), then the frequency domain impedance model is deemed to meet the requirements. If the numerical deviation in some frequency segments exceeds the preset allowable range, or if there are significant differences in the curve trends, then the model parameters need to be corrected. Subsequently, for the frequency segments where the simulation results and measurement results deviate, the causes of the numerical deviations are analyzed, mainly including inaccurate extraction of parasitic parameters, parameter settings for some structures in the model not matching reality, and failure to consider minor deviations in packaging and processing techniques. Based on the analysis results, relevant parameters in the frequency domain impedance model are adjusted. These relevant parameters include, but are not limited to, fine-tuning the parasitic resistance and inductance values ​​of metal wiring, correcting the parasitic inductance parameters of gold wire bonding, and adjusting the parasitic capacitance values ​​of the dielectric material. After each parameter adjustment, the simulation is repeated and compared with the measurement results. This process is iterated until the deviation between the simulation curve and the measurement curve is within the allowable range. This completes the parameter correction of the frequency domain impedance model and yields the final, accurate frequency domain impedance model of the power distribution network.

[0060] In embodiments achievable under this application, the extracted device shot noise power spectral density includes: S401, in the TCAD simulation platform, construct the physical structure of the ESD device and perform mesh generation; S402 applies a bias voltage to the ESD device, causing it to enter the avalanche breakdown trigger state; S403 introduces a shot noise physical model in the triggered state and specifies the observation node; S404 uses the noise analysis function of simulation tools to extract the power spectrum of shot noise.

[0061] It should be noted that the ESD protection device selected in this embodiment is a GGNMOS device that operates based on the avalanche breakdown principle.

[0062] It should be noted that shot noise in ESD protection devices is generated during their avalanche breakdown operation. Therefore, a suitable bias voltage needs to be applied to the device in TCAD simulation to trigger the avalanche breakdown state. First, in the TCAD simulation platform, the cathode of the ESD device is grounded, and a DC scanning bias voltage is applied to the anode. The scanning range is set according to the avalanche breakdown voltage range of the target ESD device. For example, in this embodiment, the scanning range is 0~10V, and the scanning step size is set to 0.1V to ensure accurate capture of the device's state change from forward conduction to avalanche breakdown. Then, DC simulation is started to obtain the current-voltage characteristic curve of the ESD device during the anode bias scanning process. The avalanche breakdown voltage of the device is determined by analyzing the current-voltage characteristic curve. When the bias voltage increases to a certain value, the current of the device suddenly increases sharply. This bias voltage value is the avalanche breakdown voltage. For example, in this embodiment, the avalanche breakdown voltage of the GGNMOS device is about 5.0V, the avalanche breakdown voltage of the diode is about 6.0V, and the avalanche breakdown voltage of the SCR device is about 9.0V. Finally, fix the anode bias at the avalanche breakdown voltage value, such as 5.0V for GGNMOS devices, keep the bias stable, start transient simulation, so that the internal electric field and carrier movement of the device reach a stable state, and ensure that the device enters and maintains the avalanche breakdown trigger state.

[0063] It should be noted that after the ESD device is stably in an avalanche breakdown triggered state, a shot noise physical model is introduced into the TCAD simulation platform, and noise observation nodes are specified to prepare for the extraction of shot noise power spectral density. For example, in the embodiments of this application, two shot noise physical models are introduced: the FlickerGRNoise model and the MonopolarGRNoise model. The FlickerGRNoise model is used to characterize the shot noise characteristics in the low-frequency range, and the MonopolarGRNoise model is used to characterize the shot noise characteristics in the mid-to-high frequency range. The combination of the two models can cover the shot noise characteristics in the frequency range related to conducted emissions caused by ESD events. In the noise simulation settings of the TCAD simulation platform, the above two shot noise physical models are enabled, and the relevant parameters of the models are set to match the device characteristics of the target process, including carrier concentration, collisional ionization coefficient, and noise figure. Subsequently, noise observation nodes were designated. Shot noise originates in the avalanche breakdown region of the ESD device, and its noise signal is mainly transmitted outward through the anode and cathode. Therefore, the anode and cathode of the device were designated as noise observation nodes. The shot noise power spectral density was then extracted by detecting the noise signals from the anode and cathode. Simultaneously, the frequency range for noise observation was set to be consistent with the frequency range of subsequent system-level simulations, ensuring that the extracted noise data can be directly used for subsequent equivalent noise source conversion.

[0064] It should be noted that after completing the introduction of the shot noise physical model and specifying the observation nodes, the noise analysis function of the TCAD simulation platform is activated to extract the shot noise power spectral density of the ESD device under avalanche breakdown triggered state. For example, the noise frequency domain simulation mode is selected in the TCAD simulation platform, and the simulation frequency step is set to 1MHz to ensure that the extracted power spectral density curve has sufficient resolution to clearly reflect the changes in shot noise intensity at different frequencies. Subsequently, the noise signal of the noise observation node is analyzed using the NoisePlot noise analysis function of the simulation platform to extract the shot noise power spectral density Si(f). This parameter characterizes the power intensity of shot noise at different frequencies, with units of A² / Hz. The simulation results are output in the form of a data list and curves. The horizontal axis of the shot noise power spectral density curve represents frequency, and the vertical axis represents the shot noise power spectral density value, which can intuitively reflect the trend of shot noise intensity changing with frequency. Finally, the validity of the extracted shot noise power spectral density data is verified by checking whether the curve conforms to the inherent characteristics of shot noise. For example, the power spectral density in the mid-to-high frequency band remains basically constant, while the power spectral density in the low frequency band increases as the frequency decreases. If the curve trend conforms to this characteristic and there are no obvious abrupt changes or distortions, the extracted shot noise power spectral density is considered valid. If there are any abnormalities, the parameter settings of the shot noise physical model and the stability of the device's operating state need to be checked again. After correction, the noise extraction is repeated until valid shot noise power spectral density data is obtained.

[0065] In this step, for three different types of ESD protection devices—GGNMOS, diodes, and SCRs—the shot noise power spectral density under avalanche breakdown state is extracted according to the above process. This provides multiple sets of noise data for subsequent equivalent noise source conversion, facilitating the comparison of the impact of different ESD devices on chip conducted emissions.

[0066] In one embodiment achievable under this application, the physical structure for constructing the ESD device includes: S501, based on the size structure and doping requirements of the target process, determine the physical parameters of the device; S502, builds the three-dimensional physical structure of the device in the simulation platform; S503 performs mesh refinement in the high-field region of the PN junction to optimize simulation accuracy.

[0067] It should be noted that the physical structure of the ESD device in this embodiment is constructed using the semiconductor TCAD simulation platform for physical modeling and simulation. First, based on the size structure and doping requirements of the target chip's manufacturing process, for example, the manufacturing process used in this application is the IMECAS 18nm FD-SOI process, the various physical parameters of the ESD protection device are determined, as shown in Figure 8. These include the device's substrate material, doping concentration, the size, position, and doping concentration of each P+, N+, PW, and NW region, the gate length and width, oxide layer thickness, and the size and position of the anode and cathode, among other key parameters. Figure 8(a) shows a single-finger, basic GGNMOS, which is the most basic unit for ESD protection; Figure 8(b) shows a multi-emitter GGNMOS. Compared to device 1 in Figure 8(a), the multi-emitter GGNMOS with a multi-emitter structure has an increased number of N+ emitter fingers in the source region, more source contact points, and a synchronously expanded gate coverage area, ensuring consistent gate-source capacitance across multiple fingers. During ESD discharge, multiple fingers in the multi-emitter GGNMOS can conduct simultaneously, avoiding excessive current concentration in a single finger that could lead to local overheating and significantly improving the single-finger current carrying capacity. Figure 8(c) shows a GGNMOS with an extended drain structure, which focuses on optimizing the trigger voltage and secondary breakdown withstand capability. The drain region extends significantly towards the PW direction, increasing the contact area / distance between the drain and PW. The source maintains a single-finger or multi-finger design, and the gate covers the corresponding channel region. The extended drain GGNMOS is suitable for high-voltage I / O or protection scenarios with strict requirements on trigger voltage.

[0068] For example, taking a GGNMOS device as an example, the three-dimensional physical structure of the device is built in the TCAD simulation platform. The steps of substrate construction, doping region implantation, gate fabrication, and anode and cathode fabrication are completed sequentially. The physical properties of each part are strictly set according to the parameter requirements of the target process to ensure that the constructed physical structure is consistent with the actual manufactured ESD device. For other ESD protection devices such as diodes and SCRs, the corresponding three-dimensional physical structures are built in the TCAD simulation platform according to their respective structural characteristics and target process requirements, such as the PN junction structure of a diode and the four-layer PNPN structure of an SCR. This application does not impose any restrictions here.

[0069] Mesh generation of ESD devices is fundamental to TCAD simulations, affecting their accuracy and convergence. After constructing the 3D physical structure of the ESD device, the adaptive mesh generation function of the TCAD simulation platform is used to mesh the device. First, the basic size of the global mesh is set to ensure that the overall structure of the device can be effectively meshed. Then, the mesh is refined in the high-field region such as the PN junction. This region is the core area where avalanche breakdown occurs in ESD events and is also the main area for shot noise generation. Refining the mesh can accurately capture the carrier motion, electric field distribution, and noise characteristics in this region, effectively optimizing the simulation results.

[0070] The degree of mesh refinement is balanced between simulation accuracy requirements and computational resources. Excessive refinement will increase computation and prolong simulation time, while insufficient refinement will lead to insufficient simulation accuracy. For example, in this embodiment, the mesh size of the PN junction region is set to 1 / 10 to 1 / 5 of the global mesh size, which ensures both simulation accuracy and simulation efficiency. For other regions of the device, such as the part of the substrate far from the PN junction, the basic mesh size is used to reduce computational resource consumption while ensuring simulation accuracy. It should be noted that after the mesh is generated, the meshing results need to be checked to ensure that there are no mesh overlaps, mesh distortions, or other problems, so as to avoid affecting the convergence of subsequent simulations.

[0071] In one embodiment of this application, converting the extracted device shot noise power spectral density into an equivalent noise source includes: S601 uses mathematical tools to perform time-domain transformation on the power spectrum of shot noise to obtain the time-domain noise waveform; S602 encapsulates the time-domain noise waveform into a standard format file to form an equivalent noise current source; S603 verifies the characteristics of the equivalent noise current source to ensure that it is consistent with the power spectrum of shot noise.

[0072] It should be noted that the extracted shot noise power spectral density is converted into a time-domain equivalent noise source that can be injected into the power distribution network model, realizing the transformation from device noise characteristics to system simulation excitation source. The specific steps are time-domain conversion, standard format packaging, and equivalent noise source characteristic verification. For example, firstly, the extracted shot noise power spectral density data is organized into a standard frequency domain data format, including a frequency point sequence and the corresponding power spectral density value sequence, ensuring that the data is complete and free of outliers. The range and step size of the frequency point sequence are consistent with the previous simulation, for example, DC-1GHz with a step size of 1MHz. Subsequently, Matlab is selected as the mathematical tool. This invention utilizes the inverse Fourier transform function in its signal processing toolbox to perform an inverse Fourier transform on the power spectral density data of shot noise in the frequency domain. During the transformation process, zero-padding is performed on the frequency domain data to expand the number of frequency points, ensuring that the transformed time-domain waveform has sufficient time length and time resolution. Simultaneously, a time-domain sampling frequency is set; for example, the time-domain sampling frequency in this application is 2 GHz, which is twice the highest simulation frequency, satisfying the Nyquist sampling theorem and avoiding aliasing of the time-domain waveform. After completing the inverse Fourier transform, the time-domain noise waveform of the shot noise is obtained, which can intuitively reflect the time-domain variation characteristics of the shot noise, including the noise amplitude and fluctuation frequency.

[0073] To enable time-domain noise waveforms to be recognized and imported by circuit simulation tools, they need to be encapsulated into a standard format file supported by the circuit simulation tools to form an equivalent noise current source. The specific implementation process is as follows: For example, this embodiment uses MDIF (Multi-Data Interchange Format) as the standard file format. This format is a common data format supported by mainstream circuit simulation tools such as ADS, which can effectively store time-domain waveform data and support batch import and retrieval of multiple sets of data. Encapsulating time-domain noise waveform data: In Matlab, the obtained time-domain noise waveform data is converted to MDIF format. The file header, data identifier, data units, and other information are set according to the MDIF format specifications to ensure that the data in the file can be correctly parsed by the circuit simulation tool. For the time-domain noise waveforms of three different ESD devices—GGNMOS, diodes, and SCRs—each is encapsulated into an independent MDIF format file and clearly named to distinguish the equivalent noise current sources of different devices. Generating equivalent noise current sources: The encapsulated MDIF format file is the equivalent noise current source that can be directly imported into the circuit simulation environment. This noise source completely preserves the frequency and amplitude characteristics of the original shot noise power spectral density, accurately simulating the shot noise generated by ESD protection devices under avalanche breakdown conditions, providing an effective excitation source for subsequent injection of the power distribution network model.

[0074] To ensure the authenticity of the equivalent noise current source, its characteristics need to be verified to ensure that the converted equivalent noise source is consistent with the original shot noise power spectral density characteristics, without distortion or deviation. The specific implementation process is as follows: For example, the equivalent noise current source is converted back to the frequency domain: The packaged MDIF format equivalent noise current source is imported into Matlab, and its time-domain waveform is subjected to Fourier transform to convert it back to the power spectral density data in the frequency domain. Comparison with the original shot noise power spectral density: The power spectral density data converted back to the frequency domain is compared with the original extracted shot noise power spectral density data. A power spectral density curve is plotted, and the consistency of its frequency trend and amplitude is analyzed. If the power spectral density curve shows a completely consistent trend across the entire frequency range, and the amplitude deviation is within the preset allowable range, then the characteristics of the equivalent noise current source are determined to be consistent with the original shot noise power spectral density. If a deviation exists, the parameter settings of the inverse Fourier transform and the file packaging process need to be checked for problems. After correction, the conversion and packaging are repeated until the verification passes.

[0075] In one embodiment of this application, the step of inputting the equivalent noise source into a power distribution network model and performing transient simulation, and outputting the predicted transient simulation results, includes: S701, import the equivalent noise source and power distribution network model into the circuit simulation environment; S702, build a system-level noise coupling simulation circuit including a load network; S703, configure the simulation parameters of the ICEM-CE modeling framework and start the transient simulation; S704 collects noise voltage response data during the simulation process as transient simulation results.

[0076] It should be noted that this step in this application injects the equivalent noise source into the previously constructed power distribution network frequency domain impedance model, builds a system-level noise coupling simulation circuit, and obtains the chip's noise voltage response data through transient simulation. The specific implementation is divided into four sub-steps: simulation environment preparation, building the system-level noise coupling simulation circuit, configuring simulation parameters, starting transient simulation, and acquiring data. Specifically, ADS is selected as the circuit simulation environment. First, the basic preparation work for the simulation environment is completed, including: starting the ADS simulation software, creating a new simulation project, importing the previously constructed and verified power distribution network frequency domain impedance model into the simulation project, ensuring the integrity of the connection relationships of each port and device in the model; importing the verified equivalent noise current source into the simulation project, completing the loading of the noise source, and ensuring that the simulation project contains all the models and excitation source files required for subsequent simulations. In the ADS simulation project, with the power distribution network frequency domain impedance model as the core, a system-level noise coupling simulation circuit containing the equivalent noise source and load network is built to ensure that the circuit can accurately simulate the process of ESD device shot noise being coupled through the power distribution network to form conducted emissions. The specific implementation process is as follows: First, the output of the equivalent noise current source is connected to the internal power solder joint port of the power distribution network model. This connection method simulates the shot noise generated by the ESD protection device inside the chip being directly injected into the chip's power distribution network, consistent with the actual noise coupling path. For power distribution network models with multiple power supply pins, the noise source is connected to the main power supply paths, such as VDD1-VSS and VDD2-VSS, ensuring that the noise can propagate to the external power supply pins through the power distribution network. Subsequently, a standard conducted emission test load network is built on the external power supply pin port of the power distribution network model. For example, this application uses a 50Ω pure resistive load, matched with a 1 / 150Ω network model. This load network is consistent with the standard load in electromagnetic compatibility testing, ensuring that the simulation results directly correspond to the actual conducted emission test results. One end of the load network is connected to the external power supply pin of the power distribution network model, and the other end is grounded, forming a complete noise transmission and detection loop. Finally, necessary auxiliary modules are added to the simulation circuit, including signal detection probes, data acquisition modules, and grounding modules. The signal detection probes are set at both ends of the load network to detect the noise voltage response on the load. The data acquisition module is used to collect voltage and current data in real time during the simulation process. The grounding module uses a uniform ground plane to eliminate simulation errors caused by uneven grounding.

[0077] This implementation uses the ICEM-CE modeling framework for system-level transient simulation. This framework is specifically designed for electromagnetic compatibility simulation of integrated circuits and can accurately simulate the propagation and coupling characteristics of noise in power distribution networks. The specific simulation parameter configuration and simulation startup process are as follows: It should be noted that this application uses the ICEM-CE modeling framework in the ADS simulation environment and sets the core parameters of the framework, including: the simulation type is transient simulation; the simulation time is set according to the time length of the time-domain noise waveform, and in this embodiment, the simulation time is 1μs to ensure complete capture of the time-domain response of the noise; the simulation step size is set to 0.1ns to ensure the resolution of the time-domain simulation; for example, the simulation convergence conditions are set to voltage convergence accuracy of 1e-6V and current convergence accuracy of 1e-9A to ensure the accuracy of the simulation results. This application also sets the startup time of the equivalent noise current source to be synchronized with the simulation startup time to ensure that the noise source injects noise into the power distribution network model at the start of the simulation; the working state of the power distribution network model is set to a linear working state, which conforms to the power network characteristics when the chip is working normally, avoiding the influence of nonlinear characteristics on noise propagation. After completing all simulation parameter configurations, check the connection relationships and parameter settings of the simulation circuit to ensure they are correct. Once confirmed, start the transient simulation. During the simulation, the ICEM-CE modeling framework will simulate the propagation, reflection, and coupling process of the noise signal from the equivalent noise current source in the power distribution network, ultimately generating a noise voltage response on the standard load network.

[0078] During transient simulation, signal detection probes and data acquisition modules set at both ends of the load network are used to collect noise voltage response data on the load in real time. The specific implementation process is as follows: During the simulation process, the data acquisition module collects noise voltage values ​​at both ends of the load network in real time according to the set simulation step size, generating time-domain noise voltage response data that varies with time. This data records the complete change process of the noise voltage on the load during the simulation time, including characteristics such as voltage amplitude, rising edge, falling edge, and fluctuation frequency. Subsequently, the collected noise voltage time-domain response data is stored as a standard numerical data file, and preliminary preprocessing is performed on the data, including outlier removal and smoothing filtering, to eliminate the influence of small numerical fluctuations during the simulation process and ensure the validity of the data. After the simulation is completed, the preprocessed noise voltage time-domain response data is output as the predicted transient simulation result. This output reflects the noise voltage characteristics generated outside the chip by the shot noise of the ESD device after coupling through the power distribution network.

[0079] In this step, simulation circuits are built and transient simulations are performed for the equivalent noise current sources of three different ESD devices: GGNMOS, diode, and SCR, following the above process. Three sets of corresponding noise voltage time-domain response data are output to provide data support for subsequent comparison of the conducted emission characteristics of different ESD devices.

[0080] In one embodiment that can be implemented in this application, the method further includes: S801 performs frequency domain conversion on the noise voltage response data acquired in the simulation. S802 extracts the noise voltage amplitude at different frequencies to form the conducted emission spectrum; S803 organizes the conducted emission spectrum into a conducted emission horizontal curve, clarifying the correspondence between the frequency and amplitude of the curve.

[0081] It should be noted that the noise voltage response data collected in this application is time-domain data, which needs to be converted to frequency-domain data through frequency domain transformation in order to analyze the conducted emission intensity at different frequencies. Specifically, firstly, the noise voltage time-domain response data output from the transient simulation is organized into a standard time-domain data format, including the time series and the corresponding voltage series, ensuring that the data is complete and without missing data, and that the range of the time series is consistent with the simulation time. Subsequently, Matlab is again used as the mathematical tool, and the Fast Fourier Transform function in its signal processing toolbox is used to perform frequency domain transformation on the time-domain noise voltage response data. During the transformation process, windowing is applied to the time-domain data, and a Hanning window is used to reduce spectral leakage and improve the accuracy of the frequency domain transformation. At the same time, the frequency range of the frequency domain transformation is set to be consistent with the previous simulation to ensure that the transformation result can cover the main frequency bands of ESD conducted emissions.

[0082] It should be noted that, based on frequency domain noise voltage data, the noise voltage amplitude at different frequencies is extracted. Specifically, the noise voltage amplitude corresponding to each frequency point is extracted from the frequency domain noise voltage data, ignoring phase characteristics, as conducted emission testing primarily focuses on the magnitude of the noise voltage. The frequency point sequence and the corresponding voltage amplitude sequence are then organized into a new dataset, which is the original conducted emission spectrum data of the chip. It should also be noted that this application converts the unit of the noise voltage amplitude to dBμV, commonly used in electromagnetic compatibility testing. The conversion formula is: dBμV = 20 × lg(V / V0), where V is the noise voltage amplitude, V0 is the reference voltage, and V0 = 1μV. This application plots the converted frequency point sequence and the dBμV voltage amplitude sequence as a curve, with the horizontal axis representing frequency (logarithmic scale) and the vertical axis representing noise voltage amplitude, forming the conducted emission spectrum of the chip. This spectrum reflects the conducted emission intensity distribution of the chip within the DC-1GHz frequency range; a higher voltage amplitude at a certain frequency indicates stronger ESD conducted emission at that frequency.

[0083] For example, to facilitate the analysis and application of conducted emission spectra, they are organized into standardized conducted emission level curves, clearly defining the frequency-amplitude correspondence of the curves. Specifically, the raw conducted emission spectrum data is first smoothed using a moving average method to eliminate minor fluctuations in the spectrum, making the curve smoother and more continuous, facilitating the observation of the overall trend of conducted emission intensity changes. Standardized conducted emission level curves are then plotted according to electromagnetic compatibility testing standards. Finally, the frequency-amplitude correspondence data of the conducted emission level curves are compiled into a standardized document, including data tables and curve images. This document represents the final conducted emission characteristic analysis result, reflecting the conducted emission level of the chip under ESD device shot noise excitation.

[0084] In one embodiment achievable under this application, realizing ESD conducted emissions based on the transient simulation results includes: S901, change the shot noise power spectrum of different types of ESD devices and repeat the simulation steps; S902, by comparing multiple sets of conducted emission level curves, the correlation between ESD device type and conducted emission level is analyzed; S903, based on the correlation analysis results, completes the ESD conduction emission of the target chip.

[0085] It should be noted that this application analyzes the correlation between ESD device type and conducted emission level. Combining the shot noise power spectral density characteristics of different ESD devices, the correlation between these characteristics and conducted emission level is analyzed. The results show that the higher the shot noise power spectral density of an ESD device, the higher its corresponding chip system-level conducted emission level. That is, shot noise is a factor affecting chip ESD conducted emission; the stronger the shot noise, the stronger the conducted emission formed through power distribution network coupling. Furthermore, different ESD devices have inherent differences in the generation mechanism and intensity of shot noise under avalanche breakdown conditions, leading to varying degrees of influence on chip conducted emission.

[0086] Based on the correlation analysis results between ESD device type and conducted emission level, and combined with the electromagnetic compatibility design requirements and ESD protection performance requirements of the target chip, the optimal ESD protection scheme is selected for the target chip. Finally, the ESD conducted emission optimization and evaluation of the target chip is completed, realizing the ESD conducted emission method of this invention. The specific implementation process is as follows: For example, the target chip is a SiP control chip used in a measurement and control system, which has high requirements for electromagnetic compatibility performance. Its ESD conducted emission level needs to be controlled below a preset threshold. Simultaneously, the chip must have sufficient ESD protection capabilities to withstand ESD impacts as specified in the IEC 61000-4-2 standard. To select the optimal ESD protection scheme, based on correlation analysis results, the GGNMOS device has the lowest shot noise power spectral density and corresponding lowest conducted emission level. Furthermore, the GGNMOS device meets the ESD protection performance requirements of the target chip. Therefore, the GGNMOS device is selected as the ESD protection device for the target chip, and it is determined to be the optimal ESD protection scheme. The ESD conducted emission optimization and evaluation of the target chip are completed. The selected GGNMOS device is applied to the ESD protection design of the target chip. Based on the method of this invention, its conducted emission level is predicted, confirming that it can meet the electromagnetic compatibility design requirements of the chip. Simultaneously, through the method of this invention, the conducted emission characteristics of the target chip under ESD events are evaluated, clarifying the distribution of the chip's conducted emission level and key influencing factors, providing a theoretical basis and data support for the subsequent electromagnetic compatibility optimization design of the chip.

[0087] Through the above steps, this invention realizes a complete process from device shot noise modeling to system-level ESD conducted emission prediction and optimization, successfully selects the optimal ESD protection scheme for the target chip, effectively reduces the ESD conducted emission risk of the target chip, and improves the electromagnetic compatibility performance and reliability of the target chip.

[0088] The second aspect of this application proposes an ESD conducted emission system based on device shot noise modeling, such as... Figure 9 As shown, the system includes: Model building module 1001 is used to build a frequency domain impedance model of the power distribution network based on the packaging data of the target chip. The prediction module 1002 is used to convert the extracted device shot noise power spectral density into an equivalent noise source, input the equivalent noise source into the power distribution network model and perform transient simulation, and output the predicted transient simulation results. The transmission module 1003 is used to realize ESD conducted transmission based on the transient simulation results.

[0089] It should be noted that the specific embodiments of this application only take a CFP36 packaged SiP control chip as an example. In practical applications, the methods and systems of this application can be adapted to integrated circuit chips with different packaging forms, different processes, and different functions. Only by adjusting the relevant simulation parameters, device models, and test standards according to the specific packaging data, process requirements, and ESD protection requirements of the chip, effective ESD conducted emission prediction and optimization can be achieved, all of which fall within the protection scope of this invention. Furthermore, the simulation tools and mathematical tools used in this invention are only exemplary selections. Those skilled in the art can choose other functionally equivalent tools according to actual needs. As long as the technical steps of this invention can be implemented, they do not depart from the concept and protection scope of this invention.

Claims

1. An ESD conducted emission method based on device shot noise modeling, characterized in that, The method includes: A frequency domain impedance model of the power distribution network is constructed based on the packaging data of the target chip. The extracted device shot noise power spectral density is converted into an equivalent noise source. The equivalent noise source is then input into the frequency domain impedance model of the power distribution network and transient simulation is performed. The predicted transient simulation results are then output. Based on the transient simulation results, ESD conducted emission is achieved.

2. The ESD conducted emission method based on device shot noise modeling according to claim 1, characterized in that, The construction of the power distribution network model based on the packaging data of the target chip includes: Obtain the target chip's package structure data, pin definition data, and stack-up information; Parasitic parameters are generated by extracting package structure data, pin definition data, and stack-up information through electromagnetic simulation. A frequency domain impedance model from the internal power solder joints to the external power supply pins of the target chip is established based on parasitic parameters. The frequency domain impedance model is verified, and the parameters of the frequency domain impedance model are corrected.

3. The ESD conducted emission method based on device shot noise modeling according to claim 2, characterized in that, The verification of the frequency domain impedance model and the correction of its parameters include: Based on a dedicated test PCB board, a vector network analyzer is used to measure the parameters of the chip pins and generate measurement results. The measurement results are compared with the simulation results of the frequency domain impedance model to generate comparison results; The parameters of the frequency domain impedance model are corrected based on the comparison results.

4. The ESD conducted emission method based on device shot noise modeling according to claim 1, characterized in that, The extracted device shot noise power spectral density includes: In the TCAD simulation platform, the physical structure of the ESD device is constructed and meshed. Apply a bias voltage to the ESD device to trigger it into an avalanche breakdown state; In the triggered state, a shot noise physical model is introduced, specifying the observation node; The power spectrum of shot noise was extracted using the noise analysis function of the simulation tool.

5. The ESD conducted emission method based on device shot noise modeling according to claim 4, characterized in that, The physical structure for constructing the ESD device includes: Based on the size structure and doping requirements of the target process, determine the physical parameters of the device; Build the three-dimensional physical structure of the device in the simulation platform; Mesh refinement is performed in the high-field region of the PN junction to optimize simulation accuracy.

6. The ESD conducted emission method based on device shot noise modeling according to claim 1, characterized in that, The step of converting the extracted device shot noise power spectral density into an equivalent noise source includes: The power spectrum of shot noise is transformed into the time domain using mathematical tools to obtain the time-domain noise waveform; The time-domain noise waveform is encapsulated into a standard format file to form an equivalent noise current source; The characteristics of the equivalent noise current source are verified to ensure that they are consistent with the power spectrum of shot noise.

7. The ESD conducted emission method based on device shot noise modeling according to claim 1, characterized in that, The step of inputting the equivalent noise source into the power distribution network model and performing transient simulation, and outputting the predicted transient simulation results includes: Import the equivalent noise source and power distribution network model into the circuit simulation environment; Construct a system-level noise coupling simulation circuit that includes a load network; Configure the simulation parameters of the ICEM-CE modeling framework and start the transient simulation; The noise voltage response data collected during the simulation process is used as the instantaneous simulation result.

8. The ESD conducted emission method based on device shot noise modeling according to claim 7, characterized in that, The method further includes: Frequency domain transformation is performed on the noise voltage response data acquired in the simulation. The noise voltage amplitude at different frequencies is extracted to form the conducted emission spectrum; Organize the conducted emission spectrum into a horizontal conducted emission curve and clarify the relationship between the frequency and amplitude of the curve.

9. The ESD conducted emission method based on device shot noise modeling according to claim 1, characterized in that, The implementation of ESD conducted emission based on the transient simulation results includes: Repeat the simulation steps by changing the shot noise power spectrum of different types of ESD devices; By comparing multiple sets of conducted emission level curves, the correlation between ESD device type and conducted emission level is analyzed. Based on the correlation analysis results, the ESD conduction emission of the target chip was completed.

10. An ESD conducted emission system based on device shot noise modeling, characterized in that, The system includes: The model building module is used to build a frequency domain impedance model of the power distribution network based on the packaging data of the target chip. The prediction module is used to convert the extracted device shot noise power spectral density into an equivalent noise source, input the equivalent noise source into the power distribution network model and perform transient simulation, and output the predicted transient simulation results. The transmission module is used to realize ESD conducted transmission based on the transient simulation results.

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