Cross-layer evaluation method, device and equipment of chip self-heating effect, and storage medium

Abstract

The application discloses a cross-layer evaluation method, device and equipment for a chip self-heating effect and a storage medium, and relates to the technical field of chip design. The method comprises the following steps: constructing a multi-order thermal equivalent model according to a three-dimensional self-heating simulation framework and a preset extraction strategy; constructing a thermal resistance matrix according to the multi-order thermal equivalent model; obtaining an extended self-heating database according to the thermal resistance matrix; and drawing a self-heating chip layout distribution according to the extended self-heating database, so as to perform cross-layer evaluation on the chip self-heating effect.

Description

Technical Field

[0001] This application relates to the technical field of chip design, and in particular to a method, apparatus, device and storage medium for cross-layer evaluation of chip self-heating effect. Background Technology

[0002] As chip manufacturing processes enter the nanoscale era, device integration has increased dramatically. Dennard scaling failures have led to a sharp increase in power density, making thermal issues increasingly prominent. In particular, the self-heating effect—the accumulation of heat generated by channel current during device operation causing significant internal temperature rise—severely impacts circuit performance and reliability. Advanced processes, such as FDSOI (Fully Depleted Silicon On Insulator) using low thermal conductivity materials, the fin structure of fin field-effect transistors introducing thermal confinement, and GAA (Gate All Around) construction, which traps heat within the transistor channel, further exacerbate the self-heating effect. This not only affects the reliability of BTI (Bias Temperature Instability), HCI (Hot Carrier Injection), and TDDB (Time Dependent Dielectric Breakdown), but also slows down transistor speed, causes timing violations, and results in significant performance losses.

[0003] However, current commercial digital EDA tools do not consider self-heating effects in chip design. To ensure reliability, circuit designers have to add conservative safety margins, assuming that each transistor experiences the highest expected self-heating-induced degradation. This approach ignores how transistors actually operate in CMOS circuits, leading to suboptimal circuit designs. While some progress has been made in device-level self-heating research, it typically employs lumped RC models, neglecting inter-device interactions and suffering from insufficient model accuracy. Furthermore, research on the effects of self-heating at the circuit level is still in its early stages; existing studies either only consider coarse-grained standard cell modules or are limited to small circuit cells, lacking comprehensiveness and accuracy.

[0004] Therefore, how to accurately assess the self-heating effect of chips is a problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, device, and storage medium for cross-layer evaluation of chip self-heating effect, aiming to solve the technical problem of accurately evaluating chip self-heating effect.

[0006] To achieve the above objectives, this application proposes a cross-layer evaluation method for chip self-heating effect, the method comprising:

[0007] A multi-stage thermal equivalent model is constructed based on a three-dimensional self-heating simulation framework and a preset extraction strategy.

[0008] Construct the thermal resistance matrix based on the multi-order thermal equivalent model;

[0009] An extended self-heating database is obtained based on the thermal resistance matrix;

[0010] The self-heating chip layout is plotted based on the extended self-heating database to perform cross-layer evaluation of the chip self-heating effect.

[0011] In one embodiment, the step of constructing a multi-order thermal equivalent model based on a three-dimensional self-heating simulation framework and a preset extraction strategy includes:

[0012] Based on the aforementioned multi-order thermal equivalent model, the multi-order cooling response function and each order thermal time constant of the current device are obtained.

[0013] Based on the cooling response function and the thermal time constants of each order, the self-heating temperature rise data corresponding to different cycles are obtained.

[0014] In one embodiment, the step of constructing the thermal resistance matrix based on the multi-order thermal equivalent model includes:

[0015] Thermal resistance data were extracted based on the multi-order thermal equivalent model.

[0016] Obtain the three-dimensional thermal simulation profile, lattice temperature distribution, geometry, and thermal properties of the device material;

[0017] The relationship between heat dissipation path and thermal resistance is obtained by analyzing the thermal resistance data, the three-dimensional thermal simulation profile, the lattice temperature distribution, the geometric structure, and the thermal properties of the device material.

[0018] The self-thermal resistance and the interactive thermal resistance are obtained based on the correspondence between the heat dissipation path and the thermal resistance.

[0019] A thermal resistance matrix is ​​constructed based on the self-thermal resistance and the interactive thermal resistance.

[0020] In one embodiment, the step of obtaining the self-thermal resistance and the cross-thermal resistance based on the correspondence between the heat dissipation path and the thermal resistance includes:

[0021] Obtain its own thermal resistance, and add fitting parameters to the thermal resistance of the order corresponding to the heat dissipation path that is adjacent to the heat dissipation path according to the correspondence between the heat dissipation path and the thermal resistance.

[0022] The fitting parameters are obtained based on preset simulations or experiments, and the interactive thermal resistance is obtained based on the fitting parameters.

[0023] In one embodiment, the step of obtaining the extended self-heating database based on the thermal resistance matrix includes:

[0024] Obtain the conversion time and load of the input signal;

[0025] The node power consumption is obtained based on the preset circuit simulation strategy, the conversion time, and the load.

[0026] A self-heating database is constructed based on the node power consumption and the thermal resistance matrix;

[0027] A differential delay is constructed based on the switching of multiple input signals, and the self-heating database is expanded based on the differential delay to obtain an extended self-heating database.

[0028] In one embodiment, the step of expanding the self-heating database based on the difference delay to obtain an expanded self-heating database includes:

[0029] The correlation function for multiple inputs is obtained based on the difference delay, and the correlation function includes a power-time correlation function and a thermal resistance-time correlation function.

[0030] Based on the correlation function, an analytical expression for the self-heating temperature rise with respect to the differential delay is obtained;

[0031] The self-heating database is expanded based on the analytical expression to obtain an extended self-heating database.

[0032] In one embodiment, the step of drawing a self-heating chip layout distribution based on the extended self-heating database to perform a cross-layer evaluation of the chip self-heating effect includes:

[0033] The circuit global information is obtained based on the preset auxiliary tools, and the self-heating temperature of each unit in the global circuit is obtained by applying the extended self-heating database.

[0034] The self-heating chip layout is plotted based on the circuit layout information and the self-heating temperature to perform cross-layer evaluation of the chip self-heating effect.

[0035] Furthermore, to achieve the above objectives, this application also proposes a cross-layer evaluation device for chip self-heating effect, the device comprising:

[0036] The model building module is used to construct multi-order thermal equivalent models based on the three-dimensional self-heating simulation framework and preset extraction strategies.

[0037] The thermal resistance analysis module is used to construct the thermal resistance matrix based on the multi-order thermal equivalent model.

[0038] The self-heating mapping module is used to obtain an extended self-heating database based on the thermal resistance matrix.

[0039] The self-heating assessment module is used to draw the self-heating chip layout distribution based on the extended self-heating database in order to perform cross-layer assessment of the chip self-heating effect.

[0040] In addition, to achieve the above objectives, this application also proposes a cross-layer evaluation device for chip self-heating effect, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the cross-layer evaluation method for chip self-heating effect as described above.

[0041] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the cross-layer evaluation method for chip self-heating effect as described above.

[0042] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the cross-layer evaluation method for chip self-heating effect as described above.

[0043] This application provides a cross-layer evaluation method for chip self-heating effect. The method includes: constructing a multi-order thermal equivalent model based on a three-dimensional self-heating simulation framework and a preset extraction strategy; constructing a thermal resistance matrix based on the multi-order thermal equivalent model; obtaining an extended self-heating database based on the thermal resistance matrix; and drawing the self-heating chip layout distribution based on the extended self-heating database to perform cross-layer evaluation of the chip self-heating effect. In summary, this application achieves cross-layer and accurate evaluation of chip self-heating effect through steps such as constructing a three-dimensional self-heating simulation framework, extracting a multi-order thermal equivalent model, studying the heat dissipation path and interactive thermal resistance within standard cells, establishing a self-heating temperature rise mapping based on transformation and load, and extending the self-heating lookup table under multiple input conditions. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1A flowchart illustrating the first embodiment of the cross-layer evaluation method for the chip self-heating effect of this application;

[0047] Figure 2 A flowchart illustrating the second embodiment of the cross-layer evaluation method for chip self-heating effect in this application;

[0048] Figure 3 This is a schematic diagram of the heat dissipation path and thermal interference structure of the cross-layer evaluation method for the chip self-heating effect of this application.

[0049] Figure 4 A flowchart illustrating the third embodiment of the cross-layer evaluation method for chip self-heating effect in this application;

[0050] Figure 5 This diagram illustrates the varying inputs and reference inputs under multiple input conditions in the cross-layer evaluation method for the chip self-heating effect of this application.

[0051] Figure 6 This is a schematic diagram of the overall framework of the cross-layer evaluation method for the chip self-heating effect of this application;

[0052] Figure 7 This is a schematic diagram of the module structure of the cross-layer evaluation device for chip self-heating effect according to an embodiment of this application;

[0053] Figure 8 This is a schematic diagram of the device structure of the hardware operating environment involved in the cross-layer evaluation method of chip self-heating effect in the embodiments of this application.

[0054] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0055] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0056] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0057] The main solution of this application embodiment is: to construct a multi-level thermal equivalent model based on a three-dimensional self-heating simulation framework and a preset extraction strategy; to construct a thermal resistance matrix based on the multi-level thermal equivalent model; to obtain an extended self-heating database based on the thermal resistance matrix; and to draw the self-heating chip layout distribution based on the extended self-heating database in order to perform cross-layer evaluation of the chip self-heating effect.

[0058] As chip manufacturing processes enter the nanoscale era, device integration density has increased dramatically. Denard scaling failures have led to a sharp increase in power density, making thermal issues increasingly prominent. In particular, the self-heating effect—the accumulation of heat generated by channel current during device operation causing significant internal temperature rise—severely impacts circuit performance and reliability. In advanced processes, such as FDSOI technology using low thermal conductivity materials, the fin structure of fin field-effect transistors introducing thermal confinement, and GAA construction trapping heat within the transistor channel, further exacerbating the self-heating effect. This not only affects the reliability of BTI, HCI, and TDDB but also leads to transistor speed reduction, timing violations, and significant performance losses.

[0059] However, current commercial digital EDA tools do not consider self-heating effects in chip design. To ensure reliability, circuit designers have to add conservative safety margins, assuming that each transistor experiences the highest expected self-heating-induced degradation. This approach ignores how transistors actually operate in CMOS circuits, leading to suboptimal circuit designs. While some progress has been made in device-level self-heating research, it typically employs lumped RC models, neglecting inter-device interactions and suffering from insufficient model accuracy. Furthermore, research on the effects of self-heating at the circuit level is still in its early stages; existing studies either only consider coarse-grained standard cell modules or are limited to small circuit cells, lacking comprehensiveness and accuracy. Therefore, accurately assessing chip self-heating effects is a pressing issue that needs to be addressed.

[0060] This application achieves cross-layer, accurate evaluation of chip self-heating effect through steps such as constructing a three-dimensional self-heating simulation framework, extracting multi-order thermal equivalent RC models, studying heat dissipation paths and interactive thermal resistances within standard cells, establishing a self-heating temperature rise mapping based on conversion and load, and expanding the self-heating lookup table under multiple input conditions.

[0061] It should be noted that the executing entity in this embodiment can be a cross-layer evaluation system for chip self-heating effect, or a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device capable of realizing the aforementioned cross-layer evaluation function for chip self-heating effect. This embodiment is not specifically limited in this regard. The following uses a cross-layer evaluation system for chip self-heating effect as an example to describe this embodiment and the following embodiments.

[0062] Based on this, embodiments of this application provide a cross-layer evaluation method for chip self-heating effect, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the cross-layer evaluation method for the chip self-heating effect of this application.

[0063] In this embodiment, the cross-layer evaluation method for the chip self-heating effect includes steps S10 to S40:

[0064] Step S10: Construct a multi-stage thermal equivalent model based on the three-dimensional self-heating simulation framework and the preset extraction strategy.

[0065] It should be noted that in this step, the system processes the thermal transient response signal obtained based on the three-dimensional self-heating simulation framework to construct a multi-order thermal equivalent model. Specifically, this step involves multiple stages such as data preprocessing, numerical differentiation, deconvolution, and time constant spectrum extraction, ultimately yielding a multi-order thermal equivalent model that can accurately reproduce the self-heating behavior of the device. By considering multiple heat propagation paths and complex material systems within the device, the model also uses a multi-order thermal equivalent approach to describe the thermal transient response during the self-heating process in greater detail.

[0066] Additionally, it should be noted that the three-dimensional self-heating simulation framework refers to a simulation environment capable of simulating the self-heating effect of a device in three-dimensional space. It considers various factors such as the device's geometry, material properties, and operating environment. Meanwhile, the deconvolution algorithm is a mathematical method used to extract useful information, such as the thermal time constant spectrum, from complex thermal transient response signals, thereby constructing a more accurate equivalent circuit model.

[0067] In one feasible implementation, after step S10, steps A10 to A20 are further included:

[0068] Step A10: Based on the multi-order thermal equivalent model, obtain the multi-order cooling response function and the thermal time constant of each order of the current device.

[0069] It should be noted that in this step, the system performs multi-order thermal equivalent model simulation analysis on the target device based on the constructed three-dimensional self-heating simulation model. This simulation framework can accurately simulate the thermal transient response of the device at different heating times, including the generation, propagation, and dissipation of heat. The thermal transient response model of the device has the characteristic of stage superposition, so different devices require different complete cooling times, which can be first-order, second-order, third-order, or other multi-order response functions. This embodiment does not impose any limitations on this comparison. Assuming that the cooling response function of one of the devices is second-order, its corresponding first-order and second-order cooling response functions are shown in Equations 1 and 2:

[0070] ΔT(t)=K1·exp(-t / τ1)(Formula 1)

[0071] ΔT(t)=ΔP·R th1 ·exp(-t / τ1)+K2·R th2 ·exp(-t / τ2)(Formula 2)

[0072] Where ΔT(t) is the thermal transient response signal, K1 and K2 represent the amplitude coefficients of the first and second order cooling responses, respectively, τ1 and τ2 represent the first and second order thermal time constants, respectively, and R... th1 With R th2 These represent the thermal resistances of the first-order and second-order devices, respectively. This cooling response function describes the temperature change of the device over time after heating. Furthermore, based on the principle of electrothermal analogy, the system can extract the thermal time constants for each order from the cooling response function. These constants reflect the different paths and speeds of heat propagation within the device.

[0073] Additionally, it should be noted that the system determines whether to activate the multi-stage thermal equivalent model based on the length of the heating and cooling times. Specifically, it will only be activated when the heating or cooling time is short (e.g., during high-frequency operation, when the device undergoes an incomplete heating or cooling process within a short period). When both heating and cooling times are long, the system does not need to use the multi-stage thermal equivalent model for thermal transient self-heating temperature rise analysis.

[0074] Step A20: Analyze and process the cooling response function and the thermal time constants of each order to obtain the self-heating temperature rise data corresponding to different cycles.

[0075] It should be noted that after obtaining the cooling response function and thermal time constants for each order, the system uses these parameters to analyze the self-heating temperature rise of the device under different cycles. Specifically, the system calculates the heat accumulation of the device in each cycle based on the heating time and cooling response function, thus obtaining the self-heating temperature rise data corresponding to different cycles. Furthermore, it should be noted that the self-heating temperature rise data describes the temperature increase of the device due to the self-heating effect under specific operating conditions. This data is crucial for evaluating the reliability and performance of the device. By analyzing and comparing the self-heating temperature rise data under different cycles, the system can determine the thermal characteristics of the device under different conditions and provide data support for subsequent circuit design and optimization.

[0076] Understandably, due to the short pulse turn-off time during high-frequency operation, the device will experience incomplete heating and cooling processes during dynamic operation, lacking sufficient time to completely dissipate the heat generated during the pulse on-phase. Therefore, the system can extract the thermal time constants of each order in the model to conduct further transient analysis on the incomplete heat dissipation within a cycle. Through the cyclic accumulation of residual heat, it stabilizes at the same level after multiple pulse cycles, allowing the device to reach its corresponding peak self-heating temperature, thereby extracting the self-heating temperature rise data corresponding to different cycles.

[0077] Step S20: Construct the thermal resistance matrix based on the multi-order thermal equivalent model.

[0078] It should be noted that in this step, the system constructs a thermal resistance matrix based on a multi-order thermal equivalent model to describe the thermal crosstalk and interactions between multiple devices within a standard cell. Specifically, this includes: extracting the cross-sectional view of the device from its 3D thermal simulation to display the lattice temperature distribution at different thermal transient times; then analyzing the thermal impact by combining the overall device geometry and the thermal conductivity and thermal capacity characteristics of each component; finally, obtaining the heat dissipation paths corresponding to each thermal process through the device's self-heating mechanism and mapping these paths in the multi-order equivalent model. Based on this, the system further determines the device's self-thermal resistance and interactive thermal resistance based on the thermal crosstalk and interactions between the device and its neighbors. This results in a thermal resistance matrix that includes the self-thermal resistance without interaction effects and the interactive thermal resistance between the heater and other nodes.

[0079] Additionally, it should be noted that the thermal resistance matrix is ​​a two-dimensional array, with diagonal elements representing the thermal resistance of the device itself and off-diagonal elements representing the thermal resistance between two nodes. Understandably, constructing the thermal resistance matrix is ​​crucial for cross-layer evaluation, extending device-level self-heating effects to the standard cell level, and providing a foundation for subsequent expansion of the self-heating database and chip layout design.

[0080] Step S30: Obtain the extended self-heating database based on the thermal resistance matrix.

[0081] The key to obtaining the self-heating database lies in establishing the mapping relationship between the input signal conversion time and load capacitance and the self-heating temperature rise. Specifically, for each device in the standard unit, under different input conversion times and output load capacitances, the system obtains its node power consumption through circuit simulation. Based on the thermal resistance matrix and node power consumption, it obtains temperature rise data, and then establishes an index of the temperature rise relationship based on the indices of the input conversion time and output load capacitance, storing it in the self-heating lookup table of the self-heating database. Based on the differential delay, the correlation functions of power, thermal resistance, and time under multiple inputs are obtained; based on the correlation functions, an analytical expression for the self-heating temperature rise with respect to the differential delay is obtained; and based on the analytical expression, the self-heating lookup table is expanded to obtain an extended self-heating lookup table.

[0082] Additionally, it should be noted that the self-heating lookup table is a mapping table of self-heating temperature rise based on input transition time and output load capacitance. It records the self-heating temperature rise of transistors or standard cells under different input signal transition times and load conditions. This simplifies the complex process of evaluating self-heating effects into a simple lookup operation.

[0083] By expanding the self-heating lookup table, accurate assessment of self-heating effects under multi-input conditions can be achieved, providing strong support for circuit design and optimization.

[0084] Step S40: Draw the self-heating chip layout distribution according to the extended self-heating database to perform cross-layer evaluation of the chip self-heating effect.

[0085] It should be noted that in this step, by integrating the extended self-heating database built in the previous steps and using this information to draw the self-heating chip layout, the distribution of the self-heating effect on the chip can be visually displayed. Specifically, the system imports the extended self-heating database into dedicated chip design software. This software is used to analyze the overall chip layout, obtain global circuit information, the connection relationships of each unit, and the characteristic information of each standard unit. Furthermore, the software can obtain information from the self-heating database. By mapping the characteristic information to the self-heating database, the self-heating temperature of each unit globally can be calculated. This temperature information can then be mapped onto the chip layout.

[0086] In one feasible implementation, step S40 specifically includes:

[0087] Step S401: Obtain global circuit information based on preset auxiliary tools, and apply the extended self-heating database to obtain the self-heating temperature of each unit in the global circuit.

[0088] It should be noted that in this step, the system utilizes pre-set auxiliary tools (such as the STA tool, or a similar tool) to parse the global information of the circuit and applies an extended self-heating database to obtain the self-heating temperature of each cell within the global range. Specifically, the system uses the STA tool to read files such as the chip's design netlist and process library, which contain the logic connection information of the chip circuits and the timing characteristics of standard cells. Next, the system imports the information from the extended self-heating database into the software. Then, the software calculates the self-heating temperature of each cell under different conditions based on the global timing information of the circuit and the information from the extended self-heating database. This temperature information will be used for subsequent self-heating chip layout drawing.

[0089] Step S402: Draw the self-heating chip layout distribution according to the circuit layout information and the self-heating temperature to perform cross-layer evaluation of the chip self-heating effect.

[0090] It's important to note that in this step, the system uses specialized drawing software to create a chip layout based on the circuit layout information. Specifically, the system marks the self-heating temperature information of each unit calculated in the previous step on the layout using colors or numbers. The intensity of the color or number indicates the temperature level, thus visually displaying the distribution of the self-heating effect within the chip. Understandably, by combining the self-heating temperature rise data with the circuit layout information, potential areas with temperature problems are identified. This provides crucial reference for subsequent circuit design and optimization.

[0091] Additionally, it's important to note that the self-heating chip layout is a graphical representation that visually illustrates the self-heating temperature rise of each device on the chip. This layout helps researchers quickly identify potential areas with temperature issues, thereby improving the reliability and performance of chip designs.

[0092] This embodiment provides a cross-layer evaluation method for chip self-heating effect. The method includes: constructing a multi-order thermal equivalent model based on a three-dimensional self-heating simulation framework and a preset extraction strategy; constructing a thermal resistance matrix based on the multi-order thermal equivalent model; obtaining an extended self-heating database based on the thermal resistance matrix; and drawing the self-heating chip layout distribution based on the extended self-heating database to perform cross-layer evaluation of the chip self-heating effect. In summary, this embodiment achieves cross-layer and accurate evaluation of the chip self-heating effect by constructing a three-dimensional self-heating simulation framework, extracting a multi-order thermal equivalent model, studying the heat dissipation path and interactive thermal resistance within standard cells, establishing a self-heating temperature rise mapping based on transformation and load, and extending the self-heating lookup table under multiple input conditions.

[0093] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in Embodiment 1 above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 , Figure 2 This is a flowchart illustrating the second embodiment of the cross-layer evaluation method for chip self-heating effect in this application. Step S20 specifically includes:

[0094] Step S201: Extract thermal resistance data based on the multi-order thermal equivalent model.

[0095] It should be noted that the thermal resistance data refers to the thermal resistance data of each unit node within the device. In this step, the system uses a constructed three-dimensional self-heating simulation platform to simulate the self-heating effect of the target device. Through simulation, the thermal transient response curves of the device under different operating conditions can be obtained. Subsequently, these thermal transient response curves are processed using a Bayesian deconvolution algorithm to extract the thermal time constant spectrum. Based on these thermal time constant spectra, a multi-order thermal equivalent RC model can be constructed. Finally, the required thermal resistance data, including the values ​​of each order of thermal resistance and the connection relationships between them, are extracted from this model.

[0096] Step S202: Obtain the three-dimensional thermal simulation profile, lattice temperature distribution, geometric structure, and thermal properties of the device material.

[0097] It should be noted that a 3D thermal simulation profile refers to a cross-sectional view obtained by creating a 3D model of a device using TCAD simulation software or other thermal simulation tools and simulating its thermal behavior during operation. This profile can display the temperature distribution at different locations within the device, which helps in analyzing the impact of self-heating effects on device performance. Lattice temperature distribution refers to the temperature distribution corresponding to the average kinetic energy of the lattice atoms within the device, reflecting the device's thermal behavior at the microscale. The device's geometry refers to its physical shape, size, and internal structure; the thermal properties of the device material refer to the thermal conductivity and thermal capacity of the materials in different parts of the device.

[0098] Step S203: Based on the thermal resistance data, the three-dimensional thermal simulation profile, the lattice temperature distribution, the geometric structure, and the thermal properties of the device material, the corresponding relationship between heat dissipation path and thermal resistance is obtained through analysis.

[0099] It should be noted that, as Figure 3 As shown in (a), in this step, the system performs simulation experiments based on the three-dimensional thermal simulation profiles and lattice temperature distribution of the device under different thermal transient times, combined with the overall geometry of the device (such as physical shape, size, and internal structure) and the thermal properties of each part of the material (such as thermal conductivity and thermal capacity). Through simulation analysis, the propagation path of heat inside the device can be determined, thereby realizing the mapping of heat dissipation path and thermal resistance relationship in a multi-order equivalent model.

[0100] Step S204: Obtain the self-thermal resistance and the cross-thermal resistance according to the correspondence between the heat dissipation path and the thermal resistance.

[0101] It should be noted that, based on the correspondence between heat dissipation paths and thermal resistances, the system can directly obtain the thermal resistance of the devices themselves, i.e., their intrinsic thermal resistance. The intrinsic thermal resistance reflects the heat transfer characteristics of the device without considering thermal crosstalk. Next, due to thermal crosstalk and interaction between devices during the heating process, the cross-sectional thermal resistance between devices needs to be considered. Cross-sectional thermal resistance refers to the thermal resistance between adjacent devices in a multi-device system that affects each other through heat conduction or radiation; it reflects the degree of mutual thermal influence between devices.

[0102] In one feasible implementation, step S204 specifically includes:

[0103] Step B10: Obtain its own thermal resistance, and add fitting parameters to the thermal resistance of the order corresponding to the heat dissipation path that is adjacent to the influence, according to the correspondence between the heat dissipation path and the thermal resistance.

[0104] It should be noted that in this step, the system obtains the thermal resistance of a node when it has no interaction with other nodes, i.e., its own thermal resistance, through simulation or experimentation. Simultaneously, the system identifies heat dissipation paths that influence neighboring nodes based on the correspondence between heat dissipation paths and thermal resistances. The correspondence between heat dissipation paths and thermal resistances refers to the fact that within the device, each path of heat propagation from the heat source to the surrounding environment has its corresponding thermal resistance. These paths and their corresponding thermal resistances collectively determine the heat propagation efficiency and distribution. To account for the influence of neighboring nodes on the target node's thermal resistance, i.e., thermal crosstalk, fitting parameters need to be added to the thermal resistance of the order corresponding to the heat dissipation paths of neighboring influences.

[0105] Step B20: Obtain the fitting parameters based on the preset simulation or experiment, and obtain the interactive thermal resistance based on the fitting parameters.

[0106] It should be noted that this step is achieved by fitting simulation or experimental results of the thermal transient response. Specifically, the fitting parameters include distance correlation. The system adjusts the values ​​of the fitting parameters based on the heat propagation in the simulation results, so that the updated cross-sectional thermal resistance can more accurately reflect the heat propagation characteristics between devices. By adjusting the fitting parameters, the system can obtain the updated cross-sectional thermal resistance, thereby more accurately describing the heat propagation from the heating device to its neighboring devices.

[0107] Step S205: Construct a thermal resistance matrix based on the self-thermal resistance and the interactive thermal resistance.

[0108] It should be noted that in this step, the system constructs a thermal resistance matrix based on its own thermal resistance and the interactive thermal resistance. Specifically, as shown below... Figure 3As shown in (b), each cell contains multiple devices and corresponds to a multi-heat source system. Assuming that heat transfer can be divided into individual heaters dissipating heat crosstalk to other heaters each time, the final temperature of a specific node 1 is its own temperature ΔT. S1 Add the temperature ΔT of each heater at that node n1 The sum is shown in Formula 3:

[0109]

[0110] like Figure 3 As shown in (b) above, since the thermal resistance matrix is ​​obtained by linear superposition, specifically as shown in Equation 4:

[0111]

[0112] Where R represents the thermal resistance of the corresponding device in the diagram, and P represents the heating power of the corresponding device. It should also be noted that when considering a single heat source, the thermal resistance network can be simplified to a diagonal matrix, meaning each heat source is only related to itself and has no interaction with other heat sources. However, when multiple heat sources exist, thermal crosstalk and interactions occur between them. In this case, the thermal resistance network is no longer a diagonal matrix but extends to a dense matrix. A dense matrix indicates that each heat source is not only related to itself but also has thermal interactions with other heat sources. Furthermore, the thermal resistance matrix consists of two parts: one is the (self-thermal resistance) thermal resistance without interaction effects, i.e., the thermal resistance corresponding to the heat generated by the heat source itself; the other is the (interaction thermal resistance) interaction thermal resistance between the heater and other nodes, i.e., the thermal resistance generated between heat sources due to thermal crosstalk. These two parts of thermal resistance together determine the characteristics of the thermal resistance network, thus affecting the heat transfer and distribution between heat sources.

[0113] Understandably, by considering the power consumption of each node, i.e. the heat generated by each heat source, the self-heating temperature rise of each node can be calculated using the thermal resistance matrix. Since the thermal resistance matrix takes into account the interactive thermal resistance between heat sources, the calculated self-heating temperature rise distribution can more accurately reflect the actual heat transfer and distribution.

[0114] In this embodiment, by analyzing the comprehensive self-heating effect based on the geometric material properties, the fitted interactive thermal resistance parameters are extracted, and a thermal resistance matrix of mutual heating superposition is constructed. This solves the problem of inaccurate evaluation of thermal interference in the heat dissipation path and improves the accuracy of the self-heating temperature rise distribution effect of each device node in the evaluation standard unit.

[0115] Based on the first and second embodiments of this application, in the third embodiment of this application, the content that is the same as or similar to that in embodiments one and two above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 4 , Figure 4This is a flowchart illustrating the third embodiment of the cross-layer evaluation method for chip self-heating effect in this application. Step S30 specifically includes:

[0116] Step S301: Obtain the conversion time and load of the input signal.

[0117] It is important to note that the input signal transition time and load are crucial factors affecting the self-heating effect of the circuit. Different transition times and loads cause changes in the current and power distribution within the circuit, thus influencing the temperature distribution during self-heating. Therefore, accurately obtaining these parameters is essential for subsequent evaluation of the self-heating effect. Furthermore, it should be clarified that the input signal refers to the signal at each input port of the circuit, the transition time of the input signal refers to the time required for the signal to change from one state to another, and the load refers to the circuit's load capacity, i.e., the value of the load capacitance that the circuit needs to drive during operation.

[0118] Step S302: Obtain node power consumption based on preset circuit simulation strategy, the conversion time, and the load.

[0119] It should be noted that in this step, the system utilizes a preset circuit simulation strategy, which can be based on SPICE or other circuit simulation software, to perform simulation analysis on the circuit. During the simulation, the system performs simulation calculations based on preset circuit models, input signal transition times, load, and other parameters to obtain the power consumption data of each node in the circuit. Furthermore, it should be noted that node power consumption refers to the power consumed by each node in the circuit during operation; it is one of the important indicators for evaluating the self-heating effect of the circuit.

[0120] Understandably, when a transistor is in the on-state and current flows, heat is generated in the conduction channel between the source and drain due to the Joule effect. Input signal state transitions and the charging and discharging of the load capacitor are both accompanied by current flow. The magnitude of the transistor's self-heating temperature largely depends on the capacitance required to charge it. The larger the output capacitance, the more current needs to flow through the transistor to charge it. Therefore, the current flow timeframe is extended, giving the transistor more time to build up its self-heating temperature. Thus, for a fixed-parameter thermal resistance matrix, the self-heating temperature rise is affected by power.

[0121] Step S303: Construct a self-heating database based on the node power consumption and the thermal resistance matrix.

[0122] It should be noted that in this step, the system calculates the self-heating temperature data of each node in the circuit based on parameters such as node power consumption and thermal resistance matrix, and stores this data in the self-heating database. This allows the system to establish an index based on the relationship between power and temperature rise, using input transition time and output load capacitance. When it is necessary to determine the temperature rise attribute of a unit instance in the circuit, the value is inserted from the corresponding lookup table in the self-heating database based on the transition and load displayed for that unit instance.

[0123] Step S304: Construct a differential delay based on the switching of multiple input signals, and expand the self-heating database based on the differential delay to obtain an extended self-heating database.

[0124] It should be noted that in this step, the system constructs the differential delay between the various input ports in the circuit based on the switching of multiple input signals. Differential delay refers to the time difference between the arrival times of signals at different input ports, reflecting the differences in signal propagation speed and path within the circuit. The input conversion signal refers to the signal changes at each input port in the circuit, which can be displayed through waveform graphs or data tables in simulation analysis. Specifically, for example... Figure 5 As shown, in order to accurately simulate the effect of simultaneous input transformation, it is assumed that the difference between the positions of the changing input B and the reference input A is t. diff Since power and thermal resistance are functions of arrival time in the case of multiple inputs, this correlation function can be obtained and substituted into the self-heating temperature rise T. multi Regarding t diff The parsing expression T multi =P(t) diff ) / R th (t diff This allows for the expansion of the lookup table, and consequently, the expansion of the self-heating database.

[0125] In one feasible implementation, step S304 specifically includes:

[0126] Step C10: Obtain the correlation function for multiple inputs based on the difference delay, the correlation function including the correlation function of power versus time and the correlation function of thermal resistance versus time.

[0127] It should be noted that the thermal resistance network in the circuit changes as the input signal switches. This is especially true when multiple input signals switch simultaneously, as the heat propagation path and heat dissipation efficiency within the thermal resistance network are affected. Therefore, it is necessary to analyze the relationship between thermal resistance and time to accurately describe this change. Understandably, the correlation function is a mathematical expression describing the relationship between power, thermal resistance, and time during multiple input signal switching. To obtain these correlation functions, a difference delay t needs to be defined. diffThis refers to the difference between the switching times of different input signals. Therefore, the power-time correlation function is P(t). diff The relationship between thermal resistance and time is R. th (t diff ).

[0128] Step C20: Obtain the analytical expression for the self-heating temperature rise with respect to the differential delay based on the correlation function.

[0129] It should be noted that the analytical expression for self-heating temperature rise with respect to differential delay is a mathematical expression describing the relationship between the self-heating effect and differential delay in a circuit during multi-input signal switching. This expression can be obtained by substituting the correlation function into the thermal resistance formula. Specifically, the system establishes a thermal equation based on the thermal resistance network and power distribution in the circuit. The correlation function is then substituted into the thermal resistance formula to consider the influence of differential delay on the self-heating effect during multi-input signal switching. This leads to the analytical expression for self-heating temperature rise with respect to differential delay. This expression describes the self-heating temperature rise of nodes in the circuit under multi-input conditions with different differential delays, i.e., T. multi =P(t) diff ) / R th (t diff (Multi represents multiple inputs, not individual nodes).

[0130] Step C30: Expand the self-heating database according to the parsing expression to obtain an extended self-heating database.

[0131] It should be noted that the extended self-heating database is a database containing information on the self-heating effect in circuits during multi-input signal switching. This database can be constructed by applying analytical expressions to different circuits and input signals. Appropriate circuit models and input signal waveforms are selected based on the circuit and input signal conditions to be evaluated. Using the analytical expression for self-heating temperature rise with respect to differential delay, the self-heating effect at each node in the circuit under different differential delays is calculated. The calculation results are stored in the self-heating database to achieve its expansion.

[0132] In this embodiment, the self-heating lookup table is expanded by considering the differential delay during multi-input signal switching, enabling it to reflect the self-heating temperature rise of each node in the circuit under multi-input conditions. This allows for a more accurate assessment of the circuit's self-heating effect under multi-input conditions, providing a more reliable basis for circuit design and optimization.

[0133] like Figure 6As shown in the figure, this is a schematic diagram of the overall framework of the cross-layer evaluation method for chip self-heating effect in this application. It should be noted that the Transistor SHE Model refers to the crystal-level self-heating effect model, Cell netlists refer to standard cell netlists, which describe the connection relationships between standard cells, including their electrical connections and signal transmission paths. Net netlists refer to circuit netlists, and Placement refers to the placement process. In circuit design, placement is the process of placing circuit components (such as standard cells, transistors, etc.) on the chip according to certain rules. This process needs to consider multiple factors such as electrical connections between components, signal transmission paths, and thermal management. SHE library refers to the Self-Heating Effect Library, i.e., the self-heating lookup table. SHE SDF refers to the standard delay of the self-heating effect. SHE Heat Map refers to the heat map of the self-heating effect, used to visualize the temperature distribution in various regions of the circuit. In the evaluation of the self-heating effect, the heat map can help designers intuitively understand the hot spots, temperature gradients, and other information in the circuit, thereby guiding circuit design and optimization.

[0134] This application also provides a cross-layer evaluation device for chip self-heating effect; please refer to [reference needed]. Figure 7 The cross-layer evaluation device for the chip self-heating effect includes:

[0135] Model building module 10 is used to build a multi-level thermal equivalent model based on the three-dimensional self-heating simulation framework and preset extraction strategy;

[0136] Thermal resistance analysis module 20 is used to construct a thermal resistance matrix based on the multi-order thermal equivalent model;

[0137] Self-heating mapping module 30 is used to obtain an extended self-heating database based on the thermal resistance matrix;

[0138] The self-heating assessment module 40 is used to draw the self-heating chip layout distribution according to the extended self-heating database in order to perform cross-layer assessment of the chip self-heating effect.

[0139] The cross-layer evaluation apparatus for chip self-heating effect provided in this application employs the cross-layer evaluation method for chip self-heating effect in the above embodiments, and can solve the technical problem of accurately evaluating chip self-heating effect. Compared with the prior art, the beneficial effects of the cross-layer evaluation apparatus for chip self-heating effect provided in this application are the same as the beneficial effects of the cross-layer evaluation method for chip self-heating effect provided in the above embodiments, and other technical features in the cross-layer evaluation apparatus for chip self-heating effect are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0140] In one embodiment, the model building module 10 is further configured to obtain the multi-order cooling response function and each order thermal time constant of the current device based on the multi-order thermal equivalent model; and to analyze and process the cooling response function and each order thermal time constant to obtain the self-heating temperature rise data corresponding to different periods.

[0141] In one embodiment, the thermal resistance analysis module 20 is further configured to extract thermal resistance data based on the multi-order thermal equivalent model; acquire the three-dimensional thermal simulation profile, lattice temperature distribution, geometric structure, and thermal properties of the device material; analyze the thermal resistance data, the three-dimensional thermal simulation profile, the lattice temperature distribution, the geometric structure, and the thermal properties of the device material to obtain the correspondence between heat dissipation path and thermal resistance; obtain the self-thermal resistance and interactive thermal resistance based on the correspondence between heat dissipation path and thermal resistance; and construct a thermal resistance matrix based on the self-thermal resistance and the interactive thermal resistance.

[0142] In one embodiment, the thermal resistance analysis module 20 is further configured to obtain its own thermal resistance, and add fitting parameters to the thermal resistance of the order corresponding to the heat dissipation path of the adjacent influence according to the correspondence between the heat dissipation path and the thermal resistance; obtain the fitting parameters according to the preset simulation or experiment, and obtain the interaction thermal resistance according to the fitting parameters.

[0143] In one embodiment, the self-heating mapping module 30 is further configured to acquire the conversion time and load of the input signal; obtain the node power consumption based on a preset circuit simulation strategy, the conversion time and the load; construct a self-heating database according to the node power consumption and the thermal resistance matrix; construct a differential delay according to the switching of multiple input signals, and expand the self-heating database according to the differential delay to obtain an extended self-heating database.

[0144] In one embodiment, the self-heating mapping module 30 is further configured to obtain a correlation function for multiple inputs based on the differential delay, the correlation function including a correlation function of power versus time and a correlation function of thermal resistance versus time; obtain an analytical expression for the self-heating temperature rise with respect to the differential delay based on the correlation function; and expand the self-heating database based on the analytical expression to obtain an extended self-heating database.

[0145] In one embodiment, the self-heating evaluation module 40 is further configured to acquire global circuit information based on a preset auxiliary tool, and apply the extended self-heating database to obtain the self-heating temperature of each unit in the global circuit; and draw the self-heating chip layout distribution according to the circuit layout information and the self-heating temperature to perform cross-layer evaluation of the chip self-heating effect.

[0146] This application provides a cross-layer evaluation device for chip self-heating effect. The cross-layer evaluation device for chip self-heating effect includes: at least one processor; and a memory communicatively connected to at least one processor; wherein the memory stores instructions executable by at least one processor, and the instructions are executed by at least one processor to enable at least one processor to perform the cross-layer evaluation method for chip self-heating effect in the above embodiment 1.

[0147] The following is for reference. Figure 8 This document illustrates a schematic diagram of a cross-layer evaluation device suitable for implementing the chip self-heating effect in the embodiments of this application. The cross-layer evaluation device for the chip self-heating effect in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 8 The cross-layer evaluation device for chip self-heating effect shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0148] like Figure 8As shown, the cross-layer evaluation device for chip self-heating effect may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the cross-layer evaluation device for chip self-heating effect. The processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the cross-layer evaluation device for chip self-heating effects to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a cross-layer evaluation device for chip self-heating effects with various systems, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0149] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0150] The cross-layer evaluation device for chip self-heating effect provided in this application, employing the cross-layer evaluation method for chip self-heating effect in the above embodiments, can solve the technical problem of accurately evaluating chip self-heating effect. Compared with the prior art, the beneficial effects of the cross-layer evaluation device for chip self-heating effect provided in this application are the same as those of the cross-layer evaluation method for chip self-heating effect provided in the above embodiments, and other technical features in this cross-layer evaluation device for chip self-heating effect are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0151] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0152] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0153] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the cross-layer evaluation method for chip self-heating effect in the above embodiments.

[0154] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0155] The aforementioned computer-readable storage medium may be included in a cross-layer evaluation device for chip self-heating effect; or it may exist independently and not be assembled into a cross-layer evaluation device for chip self-heating effect.

[0156] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by a cross-layer evaluation device for chip self-heating effect, the cross-layer evaluation device for chip self-heating effect performs the following: constructs a multi-level thermal equivalent model based on a three-dimensional self-heating simulation framework and a preset extraction strategy; constructs a thermal resistance matrix based on the multi-level thermal equivalent model; obtains an extended self-heating database based on the thermal resistance matrix; and draws a self-heating chip layout distribution based on the extended self-heating database to perform a cross-layer evaluation of chip self-heating effect.

[0157] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0158] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0159] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0160] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described cross-layer evaluation method for chip self-heating effect, thereby solving the technical problem of accurately evaluating chip self-heating effect. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the cross-layer evaluation method for chip self-heating effect provided in the above embodiments, and will not be repeated here.

[0161] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the cross-layer evaluation method for chip self-heating effect as described above.

[0162] The computer program product provided in this application can solve the technical problem of accurately evaluating the chip self-heating effect. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the cross-layer evaluation method for chip self-heating effect provided in the above embodiments, and will not be repeated here.

[0163] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for cross-layer evaluation of chip self-heating effect, characterized in that, The method includes: A multi-stage thermal equivalent model is constructed based on a three-dimensional self-heating simulation framework and a preset extraction strategy. Construct the thermal resistance matrix based on the multi-order thermal equivalent model; An extended self-heating database is obtained based on the thermal resistance matrix; The self-heating chip layout is plotted based on the extended self-heating database to perform cross-layer evaluation of the chip self-heating effect.

2. The method as described in claim 1, characterized in that, Following the step of constructing a multi-order thermal equivalent model based on the three-dimensional self-heating simulation framework and a preset extraction strategy, the method further includes: Based on the aforementioned multi-order thermal equivalent model, the multi-order cooling response function and each order thermal time constant of the current device are obtained. Based on the cooling response function and the thermal time constants of each order, the self-heating temperature rise data corresponding to different cycles are obtained.

3. The method as described in claim 1, characterized in that, The step of constructing the thermal resistance matrix based on the multi-order thermal equivalent model includes: Thermal resistance data were extracted based on the multi-order thermal equivalent model. Obtain the three-dimensional thermal simulation profile, lattice temperature distribution, geometry, and thermal properties of the device material; The relationship between heat dissipation path and thermal resistance is obtained by analyzing the thermal resistance data, the three-dimensional thermal simulation profile, the lattice temperature distribution, the geometric structure, and the thermal properties of the device material. The self-thermal resistance and the interactive thermal resistance are obtained based on the correspondence between the heat dissipation path and the thermal resistance. A thermal resistance matrix is ​​constructed based on the self-thermal resistance and the interactive thermal resistance.

4. The method as described in claim 3, characterized in that, The step of obtaining the self-thermal resistance and the cross-thermal resistance based on the correspondence between the heat dissipation path and the thermal resistance includes: Obtain its own thermal resistance, and add fitting parameters to the thermal resistance of the order corresponding to the heat dissipation path that is adjacent to the heat dissipation path according to the correspondence between the heat dissipation path and the thermal resistance. The fitting parameters are obtained based on preset simulations or experiments, and the interactive thermal resistance is obtained based on the fitting parameters.

5. The method as described in claim 1, characterized in that, The step of obtaining the extended self-heating database based on the thermal resistance matrix includes: Obtain the conversion time and load of the input signal; The node power consumption is obtained based on the preset circuit simulation strategy, the conversion time, and the load. A self-heating database is constructed based on the node power consumption and the thermal resistance matrix; A differential delay is constructed based on the switching of multiple input signals, and the self-heating database is expanded based on the differential delay to obtain an extended self-heating database.

6. The method as described in claim 5, characterized in that, The step of expanding the self-heating database based on the difference in delay to obtain an expanded self-heating database includes: The correlation function for multiple inputs is obtained based on the difference delay, and the correlation function includes a power-time correlation function and a thermal resistance-time correlation function. Based on the correlation function, an analytical expression for the self-heating temperature rise with respect to the differential delay is obtained; The self-heating database is expanded based on the analytical expression to obtain an extended self-heating database.

7. The method as described in claim 1, characterized in that, The step of drawing the self-heating chip layout distribution based on the extended self-heating database to perform cross-layer evaluation of the chip self-heating effect includes: The circuit global information is obtained based on the preset auxiliary tools, and the self-heating temperature of each unit in the global circuit is obtained by applying the extended self-heating database. The self-heating chip layout is plotted based on the circuit layout information and the self-heating temperature to perform cross-layer evaluation of the chip self-heating effect.

8. A cross-layer evaluation device for chip self-heating effect, characterized in that, The device includes: The model building module is used to construct multi-order thermal equivalent models based on the three-dimensional self-heating simulation framework and preset extraction strategies. The thermal resistance analysis module is used to construct the thermal resistance matrix based on the multi-order thermal equivalent model. The self-heating mapping module is used to obtain an extended self-heating database based on the thermal resistance matrix. The self-heating assessment module is used to draw the self-heating chip layout distribution based on the extended self-heating database in order to perform cross-layer assessment of the chip self-heating effect.

9. A cross-layer evaluation device for chip self-heating effect, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the cross-layer evaluation method for the chip self-heating effect as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the cross-layer evaluation method for the chip self-heating effect as described in any one of claims 1 to 7.

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