Circuit board layout design method, electronic device, and readable storage medium

Abstract

The application discloses a layout design method of a circuit board, an electronic device and a readable storage medium, and comprises the following steps: modeling the effective device occupation area by establishing a packaging special layer model to model the occupation area of devices and the distance between devices in each layout layer of the circuit board; determining the effective layout area of the circuit board in combination with the layout structure information of the circuit board, and calculating a layout compactness index for quantitatively representing the layout compactness degree based on the effective device occupation area and the effective layout area; under the condition of a preset physical size constraint, constructing a reverse calculation model of the physical size of the circuit board by using the layout compactness index, and then solving at least one physical size parameter of the circuit board that meets the layout compactness requirement, so as to realize the reverse calculation of the physical size of the circuit board, quickly and accurately obtain the size requirement of the circuit board in the layout design stage, reduce the artificial design cost, and improve the efficiency and reliability of the layout design of the circuit board.

Description

Technical Field

[0001] This application relates to the field of circuit board design technology, and in particular to a circuit board layout design method, electronic device, and readable storage medium. Background Technology

[0002] With the continuous updates and iterations of mobile communication terminals, terminal products are trending towards larger capacity batteries, ultra-thin bodies, and lower costs. To adapt to these trends, motherboard sizes are constantly shrinking, and circuit designs are exhibiting high-density layouts, making it increasingly difficult to balance cost, size, and product quality.

[0003] In existing technologies, printed circuit board (PCB) layout design primarily relies on engineers' experience. After the PCB layout is completed, space utilization assessments and design reviews are needed to evaluate the design's effectiveness. If the assessment results do not meet expectations, the layout scheme must be repeatedly modified. This experience-based design and review method suffers from drawbacks such as long cycles and low efficiency. When design changes or new functions are added, it is difficult to quickly and accurately obtain the required PCB dimensions. This not only increases labor costs but also extends the design cycle. Summary of the Invention

[0004] This application provides a circuit board layout design method, an electronic device, and a readable storage medium, which can realize the reverse calculation of the physical dimensions of the circuit board, and can quickly and accurately obtain the circuit board size requirements during the layout design stage, reduce manual design costs, and improve the efficiency and reliability of circuit board layout design.

[0005] One technical solution adopted in this application is: providing a layout design method for a circuit board, the layout design method for the circuit board comprising: Based on the dedicated packaging layer model, the area occupied by the devices and the spacing between devices in each layout layer of the circuit board is obtained, and the effective device area is obtained. Based on the layout structure information of the circuit board, the effective layout area of ​​the circuit board is determined, and the layout compactness index is calculated according to the effective device area and the effective layout area. Based on preset physical size constraints, at least one physical size parameter of the circuit board is calculated in reverse using the layout compactness index.

[0006] Another technical solution adopted in this application is: providing an electronic device, the electronic device comprising: Memory, used to store executable program code; A processor is configured to call and run the executable program code from the memory, causing the electronic device to perform the circuit board layout design method as described in any of the preceding descriptions.

[0007] Another technical solution adopted in this application is: providing a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the circuit board layout design method described in any of the above claims.

[0008] This application provides a circuit board layout design method, which includes: Based on the dedicated packaging layer model, the area occupied by devices and device spacing in each layout layer of the circuit board is obtained to obtain the effective device area. Based on the layout structure information of the circuit board, the effective layout area of ​​the circuit board is determined, and the layout compactness index is calculated according to the effective device area and the effective layout area. Based on the preset physical size constraints, at least one physical size parameter of the circuit board is calculated in reverse using the layout compactness index.

[0009] This application establishes a dedicated packaging layer model to model the area occupied by devices and their spacing in each layout layer of the circuit board, obtaining the effective device area. Combined with the circuit board's layout structure information, the effective layout area of ​​the circuit board is determined, and a layout compactness index is calculated based on the effective device area and the effective layout area to quantify the compactness of the layout. Under preset physical size constraints, a reverse calculation model of the circuit board's physical dimensions is constructed using the layout compactness index, thereby solving for at least one physical size parameter of the circuit board that meets the layout compactness requirements. By quantitatively analyzing the device layout area and available layout area, reverse calculation of the circuit board's physical dimensions is achieved. This enables rapid and accurate determination of circuit board size requirements during the layout design stage, reducing manual design costs and improving the efficiency and reliability of circuit board layout design. Attached Figure Description

[0010] Figure 1 This is a flowchart illustrating the first embodiment of the circuit board layout design method of this application; Figure 2 This is a flowchart illustrating the second embodiment of the circuit board layout design method of this application; Figure 3 This is a schematic diagram of the packaging-specific layer model of the circuit board layout design method of this application; Figure 4 This is a schematic diagram of the circuit board layout area composition according to the circuit board layout design method of this application; Figure 5 This is an exemplary structural block diagram of an electronic device using the circuit board layout design method of this application; Figure 6 This is an exemplary structural block diagram of a computer-readable storage medium for the layout design method of the circuit board of this application. Detailed Implementation

[0011] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0012] In some embodiments, please refer to Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the circuit board layout design method of this application. It should be noted that if substantially the same result is achieved, the method of this application is not necessarily identical. Figure 1 The illustrated process sequence is limited. For example... Figure 1 As shown, the layout design method of the circuit board includes: S101, based on the dedicated packaging layer model, obtains the area occupied by devices and device spacing in each layout layer of the circuit board, and obtains the effective device area.

[0013] The circuit board can be a structural carrier used to support electronic devices and realize electrical connections and spatial layout, and can have a regular or irregular shape. This embodiment does not limit the specific material, number of layers, or application scenario of the circuit board. For example, the circuit board can be a printed circuit board (PCB), including single-layer, double-layer, or multi-layer boards; flexible circuit boards, rigid-flex circuit boards; chip packaging substrates, system-in-package carrier boards; and other planar or non-planar carrier structures used for the installation and layout of electronic devices.

[0014] In this context, a placement layer can be a logical or physical layer on a circuit board used to carry and arrange electronic devices. A placement layer can be an actual physical placement layer, such as a top, bottom, or intermediate device layer; a logically defined device placement layer, which can be used to describe the projection relationship of devices on the carrier surface; or a virtual or mapping layer used for placement analysis and calculation. Multiple placement layers can be independent of each other or merged during area calculation. This embodiment does not limit the specific number or implementation form of placement layers.

[0015] Among them, the dedicated packaging layer model can characterize the area modeling model of the space occupied by electronic devices in the layout layer on the circuit board, that is, reflect the comprehensive space resource occupation of electronic devices in the layout layer. It can be used to calculate the area occupied by devices in different electronic device carriers or different layout schemes, thereby avoiding repeated parsing of packaging rules and improving the consistency, accuracy and efficiency of area calculation.

[0016] The dedicated package layer model can be pre-built and stored, or dynamically generated or adjusted during layout analysis. The dedicated package layer model can be used to describe at least one of the following: the package outline of the device; the projected boundary of the device; the minimum safety clearance required between the device and adjacent devices; and the safety distance between the device and the edge of the circuit board. In different embodiments, the dedicated package layer model can be implemented in different forms, such as an area model based on geometric contours; a pixel- or grid-based occupancy model; a contour model based on polygon or curve fitting; or a normalized model generated based on parametric rules.

[0017] By applying the dedicated packaging layer model to each layout layer of the circuit board, device entities and their corresponding space-occupying areas can be identified in different layout layers, and the occupied area formed by the device body and the spacing between devices can be statistically analyzed. Then, the occupied areas in each layout layer are summarized to obtain the effective device occupied area that reflects the actual space utilization of the devices. Thus, the traditional experience-based problem of device layout space occupancy can be transformed into an objective calculation process based on the model and area data.

[0018] S102, based on the layout structure information of the circuit board, determine the effective layout area of ​​the circuit board, and calculate the layout compactness index according to the effective device area and the effective layout area.

[0019] The layout structure information can be a set of data describing the spatial structural features of the circuit board. The layout structure information can be at least one of the following: the outer contour of the circuit board; cutout areas, opening areas, or avoidance areas on the board; and areas where components are prohibited from being placed.

[0020] The effective layout area refers to the area within the overall space of the circuit board that is actually available for device placement. It can be used to reflect the upper limit of the layout capacity that the circuit board can provide at the physical structure level.

[0021] The layout compactness index is used to quantitatively characterize the degree of compactness of devices within the effective layout area of ​​the circuit board. This index is obtained by calculating the ratio of the effective device area to the effective layout area, reflecting the utilization level of the effective space after deducting invalid and non-device-related areas. In different embodiments, the layout compactness index may correspond to parameters used in traditional designs to evaluate layout efficiency or space utilization. However, this application avoids interference from double-sided layouts, shielded areas, and invalid areas by clearly defining the calculation methods for the effective device area and the effective layout area, thus giving the index a clear physical upper limit and stable quantitative characteristics. In different embodiments, the layout compactness index can be characterized as an area ratio; a normalized proportional parameter; or a modified or weighted layout evaluation parameter.

[0022] By unifying the measurement of device occupancy with available layout space, that is, by correlating the effective layout area with the effective device occupancy area, a layout compactness index is obtained to quantify the density of device layout. This provides an objective basis for layout evaluation and avoids evaluation bias caused by subjective experience differences.

[0023] S103, based on preset physical size constraints, at least one physical size parameter of the circuit board is calculated in reverse using the layout compactness index.

[0024] Physical dimension constraints can be used to limit the range of physical dimensions of the circuit board. These constraints may include, but are not limited to, at least one preset value for the length or width parameter of the circuit board; the maximum or minimum allowable external dimensions of the circuit board; and dimensional limitations from product structure, housing, or system integration.

[0025] Physical dimension parameters are parameters used to describe the actual external dimensions of a circuit board. These parameters can include the length of the circuit board; the width of the circuit board; and the combination of external dimensions determined by the length and width.

[0026] Based on the aforementioned layout compactness index, a calculation relationship can be established between the device's occupied area, the effective layout area, and the physical dimensions of the circuit board. Under the condition of satisfying physical dimension constraints, at least one physical dimension parameter of the circuit board can be solved, such as the length or width parameter. Therefore, a design method that uses the layout compactness index to reverse-engineer the physical dimensions of the circuit board allows designers to quickly determine the required physical dimension range in the early stages of layout, thereby reducing trial and error and improving design efficiency.

[0027] This embodiment establishes a dedicated packaging layer model to model the area occupied by devices and their spacing in each layout layer of the circuit board, obtaining the effective device area. Combined with the circuit board's layout structure information, the effective layout area of ​​the circuit board is determined. Based on the effective device area and the effective layout area, a layout compactness index is calculated to quantify the compactness of the layout. Under preset physical size constraints, a reverse calculation model of the circuit board's physical dimensions is constructed using the layout compactness index, thereby solving for at least one physical size parameter of the circuit board that meets the layout compactness requirements. By quantitatively analyzing the device layout area and available layout area, reverse calculation of the circuit board's physical dimensions is achieved. This enables rapid and accurate determination of circuit board size requirements during the layout design stage, reducing manual design costs and improving the efficiency and reliability of circuit board layout design.

[0028] Please see Figure 2 , Figure 2This is a flowchart illustrating a second embodiment of the circuit board layout design method of this application. The method includes the following steps: S201, invoke the pre-established dedicated packaging layer model and apply the dedicated packaging layer model to each of the layout layers of the circuit board to identify device entities and their corresponding occupied areas in each of the layout layers.

[0029] Here, a device entity can be an electronic device object on a circuit board that actually participates in the implementation of functions. Device entities can include, but are not limited to, integrated circuit devices, discrete devices, connectors, shielding components, and other functional units with package outlines that occupy layout space. It is used to transform abstract device labels or netlist information into spatial entities that can be used for area calculation.

[0030] The occupied area refers to the spatial region formed by the device entity and its spacing, reflecting the actual space occupied by the device in the layout. The occupied area includes not only the projected range of the device body but also, but also, including but not limited to, the peripheral area extended to meet device spacing rules; and space reserved to meet assembly or manufacturing requirements. In different embodiments, the occupied area can be represented by polygons, curved surfaces, grids, or sets of pixels.

[0031] Please see Figure 3 , Figure 3 This is a schematic diagram of the dedicated package layer model for the circuit board layout design method of this application. By calling a pre-established dedicated package layer model, this model is applied as an identification rule to each layout layer of the circuit board. Graphical objects in different layout layers are parsed and classified, thereby automatically identifying device entities in the layout data and determining the occupied area of ​​each device entity in the corresponding layout layer. This enables standardized identification of device entities and their occupancy relationships in multi-layer layouts, reducing the risk of inconsistencies caused by manual parsing or single-layer processing.

[0032] In some embodiments, the steps of constructing the dedicated packaging layer model include: acquiring packaging rule information of multiple sample circuit boards, wherein the packaging rule information includes at least one of device packaging shape parameters, packaging layer correspondence, and device spacing rules; based on the packaging rule information, performing packaging layer mapping processing on the devices in the layout of the multiple sample circuit boards, mapping the packaging shape of each device to the corresponding dedicated packaging layer; and in the dedicated packaging layer, expanding and superimposing the occupied area of ​​each device according to the packaging shape and the corresponding device spacing rules to generate the dedicated packaging layer model.

[0033] The packaging rule information may include one or more of the following: device package outline parameters, package layer correspondences, and device spacing rules. These can be used to describe the geometric dimensions of the device in the layout; package layer correspondences indicate how the device is mapped in different placement or process layers; and device spacing rules define the minimum safe distance that should be maintained between devices and between devices and other structures.

[0034] Package layer mapping is used to map the device package outlines scattered in different functional layers, process layers or display layers in the original layout to a preset package-specific layer, which can shield the differences between different layout file formats and different layer definition methods.

[0035] Expansion processing can extend the actual usable area of ​​a device based on its package outline and using device spacing rules. Overlay processing can summarize and uniformly model the expanded usable areas of multiple devices in the presence of multiple devices.

[0036] S202, statistical analysis is performed on the area formed by the occupied area in each of the layout layers to obtain the total area of ​​the device layout.

[0037] The total device layout area can be the sum of the areas of all occupied areas in each layout layer, reflecting the overall scale of device placement on the circuit board. The total device layout area may include, but is not limited to: the cumulative area of ​​all device-occupied areas in a single layout layer; or the total area of ​​device-occupied areas across multiple layout layers. Statistical analysis may include summarizing the area of ​​a single layer, cumulatively superimposing the areas across layers, or synthesizing areas according to preset rules.

[0038] S203, based on the total area of ​​the device layout, identify and deduct the area corresponding to the shielding pad area to obtain the effective device occupied area.

[0039] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the circuit board layout area composition according to the circuit board layout design method of this application. The effective device occupied area can be used to characterize the sum of the effective occupied areas of devices and device spacing in each layout layer after excluding non-functional occupied areas such as shielding pads. It is obtained by modeling and calculating the area of ​​the device entities in each layout layer of the circuit board, and excluding areas that should not be included in the effective device occupied area during the calculation process.

[0040] Please continue reading for more details. Figure 4The shielding pad area refers to the pads or covering areas on a circuit board that are set to meet electromagnetic shielding, structural fixation, or reliability requirements. Although this area is located within the layout layer, it is not part of the occupied area formed by the device body and its necessary spacing. Therefore, when calculating the effective device occupied area, the area corresponding to the shielding pad area is identified and deducted.

[0041] S204, based on the layout structure information, obtain the outer contour of the circuit board, and determine the total layout area of ​​the circuit board based on the outer contour.

[0042] Please continue reading for more details. Figure 4 The total layout area can be defined as the area corresponding to the overall spatial range defined by the circuit board's outline. The total layout area characterizes the maximum spatial range within which the circuit board can be analyzed at the physical structural level. By analyzing the circuit board's layout structure information, its outline data is obtained, such as the geometric outline defined by boundary lines, outline layers, or mechanical definition information. The total layout area of ​​the circuit board can be determined by calculating the area enclosed by this outline.

[0043] S205, subtract the area of ​​the hollowed-out area on the board and the area of ​​the non-layoutable area from the total layout area to obtain the effective layout area.

[0044] Please continue reading for more details. Figure 4 Effective layout area is used to characterize the area of ​​the circuit board that can actually be used for device placement after deducting the cut-out areas and non-layout areas on the board.

[0045] Specifically, invalid areas that are not suitable for device placement include, but are not limited to, cut-out areas and non-placeable areas. Cut-out areas refer to physical missing areas on the circuit board due to structural design, functional openings, or assembly requirements. Non-placeable areas refer to areas that, although not physically cut out, do not allow device placement due to structural avoidance, electrical isolation, process limitations, or reliability requirements, such as high-voltage isolation areas, structural avoidance areas, or interface reserved areas.

[0046] Both cutout areas and non-deployable areas are technically invalid layout areas of the circuit board, used to jointly define the effective space range available for device placement on the circuit board.

[0047] S206, the ratio of the area occupied by the effective device to the area of ​​the effective layout is calculated to obtain the layout compactness index used to quantify the compactness of the circuit board layout.

[0048] By calculating the ratio of the effective device area to the effective layout area, a layout compactness index is obtained to describe the degree of device occupancy. The utilization level of available layout space by devices can be quantified in the form of a ratio, and the space utilization is transformed into a comparable and analyzable parameter form.

[0049] In one specific embodiment, the layout compactness index BR is defined as the ratio of the effective device area to the effective layout area, and its calculation relationship is as follows: BR = PDA / ALA; Wherein, PDA represents the effective device area; ALA represents the effective layout area.

[0050] S207, Based on preset physical size constraints and the layout structure information, analyze the effective layout area and physical size area of ​​the sample circuit board to determine the available layout area ratio that matches the layout structure of the circuit board in the physical size reverse calculation model.

[0051] In this context, a sample circuit board refers to an existing design instance used for analyzing and fitting layout characteristics. Sample circuit boards can be historical product designs; proven feasible reference layout schemes; or existing designs with a form similar to the physical dimensions of a reverse-engineered model circuit board.

[0052] The available layout area ratio is the ratio of the effective layout area to the physical area of ​​the circuit board. It characterizes the proportion of area available for device placement given the circuit board's external dimensions. This parameter is typically derived from historical design experience, statistical analysis of sample circuit boards, or an empirical constant fitted to a specific circuit board shape. In the reverse calculation of physical size parameters, the area requirement derived from the effective layout area is adjusted using the available layout area ratio, thereby converting the theoretical calculation results into size requirements that better reflect the actual circuit board geometry and engineering conditions.

[0053] Under physical size constraints, and combined with the layout structure information of the sample circuit board, the correspondence between its effective layout area and physical size area is analyzed and processed. The physical size area is transformed into the ratio of effective layout area. The available layout area ratio that matches the circuit board layout structure of the physical size reverse calculation model can be determined as a correction parameter in subsequent reverse calculation.

[0054] In one specific embodiment, a correspondence is established between the effective layout area and the actual physical size of the circuit board, introducing the available layout area ratio PR, which is defined as the ratio of the effective layout area to the physical size area of ​​the circuit board. The calculation relationship is as follows: PR = ALA / (L × W); Where L represents the length parameter of the circuit board; W represents the width parameter of the circuit board; and L×W represents the actual physical size area of ​​the circuit board.

[0055] In some embodiments, the step of determining the physical size constraints may include: obtaining design constraint information of the circuit board and selecting the length parameter and / or width parameter of the circuit board as physical size constraint parameters from the design constraint information; or obtaining the outline constraint information of the circuit board and determining the maximum allowable outline size range of the circuit board based on the outline constraint information; wherein the physical size constraint parameters or the maximum outline size range are used to limit the reverse calculation process of the physical size parameters.

[0056] As an exemplary implementation, the design constraint information of the circuit board is obtained. This design constraint information can originate from the circuit board's structural design requirements, overall assembly requirements, process design specifications, or system-level design rules of the electronic device. It may include, but is not limited to, the circuit board's allowable length range, width range, safety distance requirements from components to the board edge, board edge shape restrictions, and assembly tolerance requirements with adjacent structural components. Then, the circuit board's length and / or width parameters are selected from this information as physical dimensional constraint parameters for reverse calculation.

[0057] As another exemplary implementation, the outline constraint information of the circuit board is obtained. The outline constraint information can reflect the spatial boundary of the circuit board in the overall structure, such as the maximum allowable area defined by the terminal shell structure, functional module occupancy, or assembly cavity size. Based on the outline constraint information, the maximum allowable external dimension range of the circuit board can be determined. This maximum external dimension range is used to define the combined value range of the circuit board's length and width.

[0058] In both methods—selecting physical dimension constraint parameters based on design constraint information and determining the maximum external dimension range based on external contour constraint information—physical dimension constraints are used as boundary conditions or limitations input into the physical dimension reverse calculation model during the reverse calculation of physical dimension parameters. This prevents the reverse calculation results from exceeding the limits allowed by the actual design or structure. Consequently, the physical dimension reverse derivation process based on layout compactness indicators possesses both quantitative calculation capabilities and conforms to real-world engineering application scenarios, thereby improving the feasibility and reliability of circuit board size planning results.

[0059] S208, using the effective device area, the layout compactness index, and the available layout area ratio, construct a reverse calculation model of the physical dimensions of the circuit board.

[0060] As an example, the effective device area, layout compactness index, and available layout area ratio are combined as construction parameters of the physical size inverse calculation model to establish the physical size inverse calculation model of the circuit board, realizing the mapping from layout information to physical size parameters.

[0061] In some embodiments, S208 may include: determining the effective layout area requirement value of the circuit board based on the effective device occupied area and the layout compactness index; performing a conversion process on the effective layout area requirement value according to the available layout area ratio to obtain the corresponding circuit board geometric area requirement value; converting the circuit board geometric area requirement value into a solution expression for the length and width of the circuit board, and using at least one physical dimension parameter of the circuit board as a solution physical dimension inverse calculation model parameter for the physical dimension inverse calculation model.

[0062] As an example, by correlating the effective component area with the layout compactness index, the minimum effective layout area required by the circuit board under the layout compactness level of the physical dimension reverse calculation model can be derived in reverse, i.e., the effective layout area requirement value. Then, by correcting the effective layout area requirement value with the available layout area ratio, the area requirement based on layout space can be converted into a geometric area requirement that conforms to the actual physical structure conditions, thereby improving the engineering applicability of the reverse calculation results. Then, by combining physical dimension constraints, at least one parameter of the circuit board's length and width can be set as a known quantity or constraint variable, thereby constructing a solution relationship for another dimension parameter. At least one physical dimension parameter of the circuit board is used as the solution physical dimension reverse calculation model parameter to complete the reverse calculation of the circuit board's physical dimensions.

[0063] In one example implementation, when the preset width parameter of the electronic device carrier is W, the physical dimension reverse calculation model can be expressed as follows: L = PDA / BR / PR / W; Where L represents the length parameter of the circuit board; W represents the width parameter of the circuit board; PDA represents the effective device area occupied; BR represents the layout compactness index; and PR represents the available layout area ratio.

[0064] For scenarios involving new components or changes in layout area, the same reverse calculation model can be used to recalculate the physical dimensions of the circuit board. During this process, the available layout area ratio PR can be a ratio statistically obtained from the actual design, or a correction value close to the original ratio can be derived based on the new layout requirements to ensure the rationality and engineering feasibility of the reverse calculation results.

[0065] Through the above definitions and reverse calculation algorithms, this invention can not only quickly calculate the layout compactness index under the premise of accurately knowing the device layout requirements, but also reverse deduce the actual length and width characteristics required by the circuit board without completing the complete layout design, providing a quantitative basis for circuit board size decision-making.

[0066] S209, Based on the physical dimension reverse calculation model, at least one physical dimension parameter of the circuit board is obtained.

[0067] As an example, by calling a pre-established dedicated packaging layer model and applying it to each layout layer of the circuit board, the device entities and their corresponding occupied areas within each layout layer are automatically identified and their areas are statistically analyzed. Simultaneously, the area corresponding to the shield pad is identified and deducted from the statistical results, thus obtaining the effective device area that reflects the actual device placement requirements. This stage of processing avoids including non-functional areas such as test pads and shield pads in the device area calculation, significantly improving the accuracy and consistency of device area statistics and providing a reliable data foundation for subsequent layout compactness calculations.

[0068] In some embodiments, S209 may include: obtaining the design rules of the circuit board, the design rules including at least one of minimum component spacing rules, component-to-board edge safety distance rules, and prohibited placement area rules; using the design rules as layout rule constraints and inputting them into the physical dimension reverse calculation model to constrain the feasible solution range of the physical dimension parameters; and outputting the physical dimension parameters that satisfy the layout compactness index through the physical dimension reverse calculation model.

[0069] The design rules can be used as engineering specifications to constrain the layout and size planning of circuit board components. They may include, but are not limited to, at least one of the following: minimum component spacing rules, safe distance rules from components to board edges, and prohibited placement area rules. These rules are used to improve the actual manufacturability and placementability of the physical size parameters obtained by reverse calculation.

[0070] Among them, the minimum device spacing rule can be used to limit the minimum safe distance between adjacent devices; the device to board edge safe distance rule can be used to avoid reliability or assembly problems caused by devices being too close to the board edge; the prohibited placement area rule can be used to identify areas on the circuit board where device placement is not allowed, such as structural avoidance areas, interface opening areas, or high voltage isolation areas.

[0071] By parameterizing design rules and integrating them into the reverse computation model, the range of physical dimension parameters can be limited during the model solving process, thus constraining the feasible solution range for these parameters. Simultaneously, by using the physical dimension reverse computation model to satisfy the layout rule constraints and layout compactness indices, the output physical dimension parameters can reflect both the compactness of the device layout and the engineering boundaries defined by the design rules, thereby improving the usability and reliability of the reverse computation results in practical design scenarios. Thus, the layout compactness metric can be organically combined with specific design rules, transforming the reverse computation process of circuit board physical dimensions from purely theoretical calculations into a practical calculation process that conforms to engineering constraints.

[0072] In this embodiment, by analyzing the relationship between the effective layout area and the physical size area of ​​a sample circuit board under physical size constraints, the available layout area ratio that matches the circuit board layout structure of the physical size inverse calculation model is determined. Combined with the effective component area and layout compactness index, a physical size inverse calculation model is constructed to obtain at least one physical size parameter of the circuit board. In other words, by establishing a calculable mapping relationship between the layout results and physical size parameters, the reverse calculation from component layout requirements to circuit board physical dimensions is achieved. This allows for rapid size evaluation conclusions in the early stages of design, reducing repeated trial and error and manual experience-based judgment, and shortening the design cycle.

[0073] Please see Figure 5 , Figure 5 This is an exemplary structural block diagram of an electronic device using the circuit board layout design method of this application. For example... Figure 5 As shown, the electronic device 500 of this application may include a processor 501 and a memory 502, wherein the processor 501 and the memory 502 communicate via a bus. The memory 502 stores program instructions for circuit board layout estimation. When the program instructions are executed by the processor 501, the processor performs the aforementioned related method steps to implement a circuit board layout design method in the above embodiments.

[0074] Please see Figure 6 , Figure 6 This is an exemplary structural block diagram of a computer-readable storage medium for the layout design method of the circuit board of this application. (See diagram below.) Figure 6 As shown, the computer-readable storage medium 600 stores a computer program 601. When the computer program 601 is run by a processor on a computer, it causes the computer to perform the aforementioned related method steps to implement a circuit board layout design method in the above embodiments.

[0075] The above solution establishes a dedicated packaging layer model to model the area occupied by devices and their spacing in each layout layer of the circuit board, obtaining the effective device area. Combined with the circuit board's layout structure information, the effective layout area is determined, and a layout compactness index is calculated based on the effective device area and the effective layout area to quantify the compactness of the layout. Under preset physical size constraints, a reverse calculation model of the circuit board's physical dimensions is constructed using the layout compactness index, thereby solving for at least one physical size parameter of the circuit board that meets the layout compactness requirements. By quantitatively analyzing the device layout area and available layout area, reverse calculation of the circuit board's physical dimensions is achieved. This enables rapid and accurate determination of circuit board size requirements during the layout design stage, reducing manual design costs and improving the efficiency and reliability of circuit board layout design.

[0076] In the several embodiments provided in this application, it should be understood that the disclosed methods, electronic devices, and storage media can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0078] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0079] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the circuit board layout design method described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A circuit board layout design method, characterized in that, The layout design method for the circuit board includes: Based on the dedicated packaging layer model, the area occupied by the devices and the spacing between devices in each layout layer of the circuit board is obtained, and the effective device area is obtained. Based on the layout structure information of the circuit board, the effective layout area of ​​the circuit board is determined, and the layout compactness index is calculated according to the effective device area and the effective layout area. Based on preset physical size constraints, at least one physical size parameter of the circuit board is calculated in reverse using the layout compactness index.

2. The method according to claim 1, characterized in that, The step of using the layout compactness index to calculate at least one physical dimension parameter of the circuit board includes: Based on the layout structure information, the effective layout area and physical size area of ​​the sample circuit board are analyzed to determine the available layout area ratio that matches the layout structure information of the circuit board. Using the effective device area, the layout compactness index, and the available layout area ratio, a reverse calculation model of the physical dimensions of the circuit board is constructed; Based on the physical dimension reverse calculation model, at least one physical dimension parameter of the circuit board is obtained.

3. The method according to claim 2, characterized in that, The step of constructing a reverse physical dimension calculation model for the circuit board using the effective device area, the layout compactness index, and the available layout area ratio includes: Based on the effective component area and the layout compactness index, the effective layout area requirement of the circuit board is determined; Based on the available layout area ratio, the effective layout area requirement value is converted to obtain the corresponding circuit board geometric area requirement value. The required geometric area of ​​the circuit board is converted into a solution expression for the length and width of the circuit board, and at least one physical dimension parameter of the circuit board is used as the solution physical dimension inverse calculation model parameter.

4. The method according to claim 2, characterized in that, Based on the physical dimension reverse calculation model, at least one physical dimension parameter of the circuit board is obtained, including: Obtain the design rules for the circuit board, which include at least one of the following: minimum component spacing rules, safe distance rules from component to board edge rules, and prohibited placement area rules; The design rules are used as layout rule constraints and input into the physical dimension reverse calculation model to constrain the feasible solution range of the physical dimension parameters. The physical dimension parameters that satisfy the layout compactness index are output through the physical dimension reverse calculation model.

5. The method according to any one of claims 1 to 4, characterized in that, The steps for determining the physical dimensional constraints include: Obtain the design constraint information of the circuit board, and select the length and / or width parameters of the circuit board from the design constraint information as physical dimension constraint parameters; or Obtain the outline constraint information of the circuit board, and determine the maximum allowable outline size range of the circuit board based on the outline constraint information; The physical dimension constraint parameter or the maximum external dimension range is used to limit the reverse calculation process of the physical dimension parameter.

6. The method according to claim 1, characterized in that, The method based on the dedicated packaging layer model obtains the occupied area of ​​devices and their spacing in each layout layer of the circuit board, thus obtaining the effective device occupied area, including: The pre-established dedicated packaging layer model is invoked and applied to each of the layout layers of the circuit board to identify device entities and their corresponding occupied areas in each of the layout layers. Statistical analysis is performed on the area formed by the occupied region in each of the layout layers to obtain the total area of ​​the device layout; Based on the total area of ​​the device layout, the area corresponding to the shielding pad area is identified and deducted to obtain the effective device occupied area.

7. The method according to claim 1, characterized in that, Based on the layout structure information of the circuit board, the effective layout area of ​​the circuit board is determined, and a layout compactness index is calculated based on the effective component area and the effective layout area, including: Based on the layout structure information, the outer contour of the circuit board is obtained, and the total layout area of ​​the circuit board is determined based on the outer contour. The effective layout area is obtained by subtracting the area of ​​the hollowed-out area on the board and the area of ​​the non-layoutable area from the total layout area; The ratio of the area occupied by the effective devices to the area of ​​the effective layout is calculated to obtain the layout compactness index, which is used to quantitatively characterize the compactness of the circuit board layout.

8. The method according to claim 1, characterized in that, The steps for constructing the dedicated encapsulation layer model include: Obtain packaging rule information for multiple sample circuit boards, wherein the packaging rule information includes at least one of device packaging shape parameters, packaging layer correspondence, and device spacing rules; Based on the packaging rule information, the devices in the multiple sample circuit board layouts are mapped to the corresponding packaging-specific layer. In the dedicated packaging layer, the occupied areas of each device are expanded and superimposed according to the package shape and the corresponding device spacing rules to generate the dedicated packaging layer model.

9. An electronic device, characterized in that, The electronic device includes: Memory, used to store executable program code; A processor is configured to call and run the executable program code from the memory, causing the electronic device to perform the circuit board layout design method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the circuit board layout design method as described in any one of claims 1 to 8.

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