Layout generation method of printed circuit board and electronic device

Abstract

The application relates to the technical field of electronic design automation, and discloses a layout generation method of a printed circuit board and an electronic device. The method comprises the following steps: acquiring a first mapping relationship between a center deviation index and a component movement weight, a second mapping relationship between an area occupancy rate of the printed circuit board and an area occupancy rate of a component, and a third mapping relationship between a total movement distance and a target center coordinate of the component on the printed circuit board; under the constraint of a constraint condition, performing minimum processing on the center deviation index based on the first mapping relationship, maximum processing on the area occupancy rate of the printed circuit board based on the second mapping relationship, and minimum processing on the total movement distance based on the third mapping relationship, to obtain a target layout of the printed circuit board. The target layout is characterized by target center coordinates of all components. Through the method, a printed circuit board layout with good layout effect can be generated, and the generation efficiency of the printed circuit board layout is improved.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, specifically to a method for generating the layout of printed circuit boards and an electronic device. Background Technology

[0002] As the core carrier of electronic components, the layout of printed circuit boards (PCBs) directly affects the electrical performance, production yield, and manufacturing cost of products.

[0003] Currently, the layout of printed circuit boards (PCBs) is typically generated using automated placement tools, starting from a single objective such as PCB area occupancy or total wiring length. However, this approach focuses on a single objective, making it difficult to achieve global optimization in the generated layout. Moreover, it usually requires significant manpower for secondary manual debugging and correction, which not only significantly increases the development cycle but also fails to meet the refined design requirements of high-performance electronic products. Summary of the Invention

[0004] This application provides a layout generation method and electronic device for printed circuit boards to solve the problems of poor automatic layout effect and reliance on manual adjustment in related technologies.

[0005] In a first aspect, this application provides a layout generation method for a printed circuit board (PCB). The PCB includes multiple layout areas, each used to place components. The method includes: obtaining a first mapping relationship between a center deviation index and a component movement weight, a second mapping relationship between the PCB area occupancy rate and the component area occupancy rate, and a third mapping relationship between the total movement distance and the target center coordinates of the component on the PCB; under constraints, minimizing the center deviation index based on the first mapping relationship, maximizing the PCB area occupancy rate based on the second mapping relationship, and maximizing the PCB area occupancy rate based on the third mapping relationship. The total movement distance is minimized by the radiation relationship to obtain the target layout of the printed circuit board. The target layout is characterized based on the target center coordinates of each component. Among them, the center deviation index is used to characterize the deviation between the target center coordinates of the component and the center coordinates of the layout area where the component is located, and the total movement distance is used to characterize the movement distance of the component from the initial center coordinates to the target center coordinates on the printed circuit board. The constraints are configured as follows: the layout area where the component is located is unique, the component is within its own layout area, there is no collision between components and between the component and the obstacle point, and the arrangement priority between components meets the preset arrangement priority.

[0006] Secondly, this application provides a layout generation apparatus for a printed circuit board (PCB). The PCB includes multiple layout areas, each for placing components. The apparatus includes: an acquisition module, configured to acquire a first mapping relationship between a center deviation index and a component movement weight, a second mapping relationship between the PCB area occupancy rate and the component area occupancy rate, and a third mapping relationship between the total movement distance and the target center coordinates of the component on the PCB; and a generation module, configured to, under constraints, minimize the center deviation index based on the first mapping relationship and maximize the PCB area occupancy rate based on the second mapping relationship. The target layout of the printed circuit board is obtained by minimizing the total movement distance based on the third mapping relationship. The target layout is characterized by the target center coordinates of each component. The center deviation index is used to characterize the deviation between the target center coordinates of the component and the center coordinates of the layout area where the component is located. The total movement distance is used to characterize the movement distance of the component from the initial center coordinates to the target center coordinates on the printed circuit board. The constraints are configured as follows: the layout area where the component is located is unique; the component is within its layout area; there is no collision between components and between the component and the obstacle point; and the arrangement priority between components meets the preset arrangement priority.

[0007] Thirdly, this application provides an electronic device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the printed circuit board layout generation method of the first aspect or any corresponding embodiment described above.

[0008] Fourthly, this application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the printed circuit board layout generation method of the first aspect or any corresponding embodiment described above.

[0009] Fifthly, this application provides a computer program product, including computer instructions for causing a computer to execute the printed circuit board layout generation method of the first aspect or any corresponding embodiment described above.

[0010] The printed circuit board (PCB) layout generation method provided in this application, under the constraints of the conditions, minimizes the center deviation index based on the first mapping relationship, which can constrain the tightness between components in the final generated target layout to be relatively high. Maximizes the area utilization of the PCB based on the second mapping relationship, which can constrain the arrangement of components in the final generated target layout to be more regular and compact, making full use of the PCB space, reducing invalid blank areas, and effectively reducing the overall size of the PCB. Minimizes the total movement distance based on the third mapping relationship, which can constrain the target center coordinates of the components in the final generated target layout to be close to the preset initial center coordinates, reducing the offset of the component layout position, and avoiding the surge in wiring length, increased layout conflicts, and deterioration of electrical performance caused by large-scale movement. In this way, a target layout of the PCB with better layout effect can be generated. Compared with the scheme of generating PCB layout through a single target, this application can directly generate a PCB layout with better layout effect through multiple targets without the need for manual secondary adjustment, which can improve the generation efficiency of PCB layout. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this application, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of a first method for generating a layout of a printed circuit board according to an embodiment of this application. Figure 2 This is a schematic diagram of a second process for generating a layout of a printed circuit board according to an embodiment of this application; Figure 3 This is a collision detection schematic diagram provided according to an embodiment of this application; Figure 4 This is an overall schematic diagram of the printed circuit board layout generation method provided in the embodiments of this application; Figure 5 This is a flowchart of generating a target layout using a particle swarm optimization algorithm according to an embodiment of this application; Figure 6 This is a schematic diagram of the layout area on a printed circuit board according to an embodiment of this application; Figure 7 This is a flowchart of placing components in a first layout area and a second layout area according to an embodiment of this application; Figure 8This is a structural block diagram of a printed circuit board layout generation apparatus according to an embodiment of this application; Figure 9 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] It is understood that before using the technical solutions disclosed in the various embodiments of this application, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this application in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0015] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0016] In the context of rapid iteration in the electronic equipment industry, the layout of printed circuit boards (PCBs) directly affects the electrical performance, production yield, and manufacturing cost of products, as the core carrier of electronic components.

[0017] Currently, printed circuit board (PCB) layout largely relies on engineers' historical experience. Specifically, engineers divide the PCB into multiple layout areas based on circuit function, with each area corresponding to a functional module. They then adjust the positions of each component within its respective area, such as by adjusting the coordinates of the component's center point. This adjustment process requires repeatedly balancing multiple dimensions, including heat dissipation, wiring, and electromagnetic compatibility. The pre-layout of a medium-to-large PCB often requires a 2-5 day adjustment cycle, which is extremely inefficient. Furthermore, the layout quality is highly dependent on the engineer's skill level, easily leading to wasted space, unreasonable placement of critical components, and other problems, thus extending product development cycles and increasing trial-and-error costs.

[0018] To address these issues, related technologies propose using automated placement tools to generate PCB layouts, starting from single objectives such as PCB area occupancy and total wiring length. However, this approach focuses on a single objective, making it difficult to achieve global optimization in the generated layout. Furthermore, it typically requires significant manpower for secondary manual debugging and correction, significantly increasing the development cycle and failing to meet the refined design requirements of high-performance electronic products.

[0019] In addition, some heuristic algorithms, such as those using deep learning to generate printed circuit board layouts, are also inefficient because they have many parameters and the computation is time-consuming.

[0020] In view of this, this application converts the arrangement order of components into a spatial and temporal relationship based on the earliest and latest arrangement priorities of each component. It simultaneously satisfies the requirements of maximizing the area utilization of the printed circuit board (PCB), minimizing the allocated component movement weights, and minimizing the component movement distance within each layout area. A multi-objective optimization algorithm is used to optimize the initial center coordinates of each component, resulting in a PCB layout characterized by the target center coordinates of each component. Compared to generating a PCB layout through a single objective, this application can directly generate a PCB layout with superior layout performance through multiple objectives, eliminating the need for manual secondary adjustments and improving the efficiency of PCB layout generation.

[0021] According to an embodiment of this application, a method for generating the layout of a printed circuit board is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0022] Additionally, it should be noted that the printed circuit board mentioned in this application includes multiple layout areas, and each layout area is used to place components. The printed circuit boards discussed in this application are mostly rectangular in shape. The multiple layout areas on this printed circuit board can be pre-divided manually according to the circuit function, and the pre-divided layout areas are also rectangular in shape. Each layout area can correspond to a functional module. For example, if a printed circuit board can include three local areas, namely a first layout area, a second layout area, and a third layout area, the first layout area can correspond to a power module, the second layout area can correspond to a communication module, and the third layout area can correspond to a storage module. Each layout area can hold one or more components; however, each component can only be placed in one layout area. Components in different layout areas do not interfere with each other, and once the position of a component is determined, it cannot be moved again within the priority rules.

[0023] This embodiment provides a method for generating the layout of a printed circuit board, which can be used in electronic devices. Figure 1 This is a flowchart of a printed circuit board layout generation method according to an embodiment of this application, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain the first mapping relationship between the center deviation index and the component movement weight, the second mapping relationship between the area occupancy rate of the printed circuit board and the area occupancy rate of the component, and the third mapping relationship between the total movement distance and the target center coordinates of the component on the printed circuit board.

[0024] Among them, the center deviation index is used to characterize the deviation between the target center coordinates of the component and the center coordinates of the layout area where the component is located, and the total movement distance is used to characterize the movement distance of the component from the initial center coordinates to the target center coordinates on the printed circuit board.

[0025] The target center coordinates of the component here can be the coordinates of the component's center point on the entire printed circuit board within the final target layout. Correspondingly, the target center coordinates of the component can be the parameter to be solved in this application. Before optimizing the solution for the component's target center coordinates, the component has an initial center coordinate on the entire printed circuit board. By starting from the initial center coordinates and gradually moving the component multiple times within its layout area, the target center coordinates of the component on the entire printed circuit board can be obtained. It should be understood that the initial center coordinates of the component on the printed circuit board can be manually preset or can be the initial center point coordinates of the component generated during iterative solving using a multi-objective optimization algorithm.

[0026] Furthermore, the layout area where a component is located can be any layout area to which the component belongs and within which it can continuously move. The center coordinates of the layout area where the component is located can be the coordinates of the center point of that layout area on the entire printed circuit board. It should be noted that when the layout areas of the printed circuit board are pre-defined, the center coordinates of each layout area will not change as the component moves. In other words, in this application, the center coordinates of each layout area are known parameters, and the center coordinates of each layout area can be pre-stored in a database.

[0027] Furthermore, the center deviation index can effectively reflect the density of components within the target layout of the final printed circuit board. That is, the smaller the center deviation index, the higher the density of components in the target layout, and the higher the area utilization rate of the entire printed circuit board. Conversely, the larger the center deviation index, the lower the density of components in the target layout, and the lower the area utilization rate of the entire printed circuit board.

[0028] The component area occupancy rate here can be used to characterize the ratio between the area occupied by the component in its layout area and the area of ​​the layout area. Moreover, the printed circuit board area utilization rate can be the sum of the area occupancy rates of all components.

[0029] The total movement distance here can include the movement distance of the component along both the X-axis and Y-axis of the printed circuit board. The total movement distance reflects the amount of movement a component makes from its initial center coordinates to its target center coordinates within the final layout of the printed circuit board. A smaller total movement distance means smaller movement for each individual component, resulting in target center coordinates closer to the component's initial center coordinates. This reduces the probability of collisions between components and between components and obstacles, while also shortening component wiring lengths and improving electrical performance.

[0030] Step S102: Under the constraints of the constraints, the target layout of the printed circuit board is obtained by minimizing the center deviation index based on the first mapping relationship, maximizing the area occupancy rate of the printed circuit board based on the second mapping relationship, and minimizing the total moving distance based on the third mapping relationship.

[0031] The target layout is characterized based on the target center coordinates of each component.

[0032] The constraints are configured as follows: the component is located in a unique layout area; the component is located within its own layout area; there is no collision between components or between components and obstacle points; and the arrangement priority between components meets the preset arrangement priority.

[0033] Obstacles here can be locations or areas on the printed circuit board where components are not allowed to be placed, traces are prohibited, or where spatial constraints on the layout are imposed. As a specific example, obstacles can be, but are not limited to, edges of the printed circuit board, mounting holes, screw holes, positioning holes, etc.

[0034] The preset placement priority between components can be manually defined. By preset placement priority, the layout generation method of this application can be restricted to prioritize placing the highest priority components, such as critical components, high-value components, or special function components. This ensures that the highest priority components occupy the optimal layout resources on the printed circuit board, such as being close to core areas like signal interfaces, power inputs, heat dissipation channels, and high-speed signal links. This avoids the global optimization logic of the automatic placement algorithm causing the highest priority components to be squeezed into non-ideal positions, thereby affecting the electrical performance, heat dissipation efficiency, or structural assembly feasibility of the printed circuit board.

[0035] The printed circuit board (PCB) layout generation method provided in this embodiment, under the constraints of the constraints, minimizes the center deviation index based on the first mapping relationship, which can constrain the tightness between components in the final generated target layout to be relatively high. Maximizes the area utilization of the PCB based on the second mapping relationship, which can constrain the arrangement of components in the final generated target layout to be more regular and compact, making full use of the PCB space, reducing invalid blank areas, and effectively reducing the overall size of the PCB. Minimizes the total movement distance based on the third mapping relationship, which can constrain the target center coordinates of the components in the final generated target layout to be close to the preset initial center coordinates, reducing the offset of the component layout position, avoiding a surge in wiring length, increased layout conflicts, and deterioration of electrical performance due to large-scale movement. In this way, a target layout of the PCB with better layout effect can be generated. Compared with generating the PCB layout through a single target, this application can directly generate a PCB layout with better layout effect through multiple targets without manual secondary adjustment, which can improve the generation efficiency of the PCB layout.

[0036] This embodiment provides a method for generating the layout of a printed circuit board, which can be used in electronic devices. Figure 2 This is a flowchart of a printed circuit board layout generation method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps: Step S201: Obtain the first mapping relationship between the center deviation index and the component movement weight, the second mapping relationship between the area occupancy rate of the printed circuit board and the area occupancy rate of the component, and the third mapping relationship between the total movement distance and the target center coordinates of the component on the printed circuit board.

[0037] Specifically, step S201 includes: Step S2011: Obtain the first mapping relationship between the center deviation index and the component movement weight, wherein the first mapping relationship is: ;in, Used to indicate deviation from the center. Used to represent the weight of component movement Used to represent the weight of a component's movement along the X-axis. Used to represent the weight of component movement on the Y-axis Used to represent the first correction factor. Used to represent the weight of the k-th component in the u-th layout region. Used to represent the u-th layout region on the printed circuit board. X Center coordinates along the axis Used to represent the u-th layout region on the printed circuit board. Y Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. X Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. Y The center coordinates along the axis, where K represents the total number of components and U represents the total number of layout areas.

[0038] Here and These coordinates can be used together to represent the coordinates of the center point of the u-th layout area on the entire printed circuit board, which is also the center coordinate of the layout area where the component shown above is located.

[0039] Here and These coordinates can be used together to represent the coordinates of the center point of the k-th component on the entire printed circuit board. In the scenario of the first iteration, and These can be used together to represent the initial center coordinates of the k-th component shown above, in the scenario of the last iteration. and These can be used together to represent the target center coordinates of the k-th component shown above. In the scenario of intermediate iteration rounds, and These can be used together to represent the center coordinates of the k-th component shown above, obtained after its movement.

[0040] Furthermore, as mentioned earlier, the total number of layout areas U and the total number of components K are both pre-set manually and stored in the database mentioned above. Moreover, the placement area and orientation of each type of component, such as transistors, MOSFETs, diodes, Zener diodes, thyristors, resistors, capacitors, and inductors, can also be pre-set and stored in the database.

[0041] in addition, This is used to represent the weight of the k-th component within the u-th layout region, where... When =1, it means that the k-th component is located within the u-th layout region. When =0, it means that the k-th component is not located in the u-th layout area.

[0042] in addition, , as well as All values ​​can be customized in advance according to the actual situation, and this application does not impose any specific restrictions on them.

[0043] A first mapping relationship is constructed by the deviation between the center point coordinates of the component and the center point coordinates of the component itself. Subsequently, the deviation between the center point coordinates of the component and the center point coordinates of the component itself is minimized based on the first mapping relationship. This can further improve the compactness of each component in the final target layout, thereby effectively improving the space utilization of the printed circuit board and reducing the overall size of the printed circuit board.

[0044] Step S2012: Obtain the second mapping relationship between the area occupancy rate of the printed circuit board and the area occupancy rate of the components, wherein the second mapping relationship is: ;in, Used to indicate area occupancy rate Used to represent the u-th layout region on the printed circuit board. X Minimum boundary coordinates in the axial direction Used to represent the u-th layout region on the printed circuit board. Y Minimum boundary coordinates in the axial direction Used to represent the u-th layout region on the printed circuit board. X Maximum boundary coordinates in the axis direction Used to represent the u-th layout region on the printed circuit board. Y Maximum boundary coordinates in the axis direction Used to represent the u-th layout region on the printed circuit board. XTotal number of grid cells along the axis Used to represent the u-th layout region on the printed circuit board. Y Total number of grid cells along the axis Used to represent the second correction factor. Used to indicate the preset grid size for dividing a printed circuit board into grids. Used to represent grid state variables, in A value of 1 indicates that the k-th component occupies the grid represented by cx and cy. A value of 0 indicates that the k-th component does not occupy the grid represented by cx and cy.

[0045] To maximize the area utilization of printed circuit boards, in some cases, pre-defined division dimensions, such as 1mm, can be used. The printed circuit board is divided into multiple grids using a 1mm grid. The area occupancy rate of a component within its designated area can be represented by the ratio of the total number of grids occupied by that component to the total number of grids in that area. This area occupancy rate of all components is then used to determine the overall area utilization rate of the printed circuit board, which in turn allows us to assess the rationality of the utilization of each area.

[0046] Furthermore, as mentioned above, for ease of processing, this application can simplify all components into rectangles, while some irregularly shaped components can be adjusted using a second correction factor, thereby accurately determining the utilization of the entire printed circuit board. It should be understood that the second correction factor... The specific values ​​can be customized in advance according to the actual situation, and this application does not impose specific limitations on them.

[0047] In addition, through , , as well as These can collectively characterize the position of the u-th layout region within the entire printed circuit board. In some cases, and This can be the coordinates of the bottom-left corner of the u-th layout region (where left can be used as a reference direction when the viewer is facing the screen). Correspondingly, and It can be the coordinates of the top right corner of the u-th layout area.

[0048] Additionally, it should be noted that, This can be used to represent the ratio between the total number of grids occupied by the k-th component and the total number of grids in the u-th layout region itself. However, cx and cy can be the same or different. For example, starting from the bottom left corner of the u-th layout region, cx=1 and cy=1 represent the first grid adjacent to the bottom left corner, cx=1 and cy=2 can be the second grid along the Y-axis of the printed circuit board, and so on.

[0049] By constructing a second constraint relationship through the area occupancy rate of components and the area occupancy rate of printed circuit boards (PCBs), and then maximizing the area occupancy rate of PCBs based on the second constraint relationship, the space utilization rate of PCBs can be further improved, the invalid blank areas in the layout process can be reduced, the component arrangement can be made more regular and compact, and the overall size of PCBs can be reduced, thereby improving the integration and space utilization rate of PCBs.

[0050] Step S2013: Obtain the third mapping relationship between the total moving distance and the target center coordinates of the component on the printed circuit board, wherein the third mapping relationship is: ,in, Used to represent the total distance traveled. Used to represent the weight of the k-th component in the u-th layout region. Used to represent the u-th layout region on the printed circuit board. X Center coordinates along the axis Used to represent the u-th layout region on the printed circuit board. Y Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. X Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. Y The center coordinates along the axis, where K represents the total number of components and U represents the total number of layout areas. Please refer to the previous text for details.

[0051] A third constraint relationship is constructed by summing the movement distance of the component in the X-axis direction and the movement distance of the component in the Y-axis direction of the layout area, and the total movement distance. Subsequently, the total movement distance is minimized based on the third constraint relationship, which can make the target center coordinates of the finally generated component as close as possible to the initial center coordinates of the component. This can further reduce the probability of collisions between components and between components and obstacle points, and also shorten the wiring length of the components, thereby improving electrical performance.

[0052] Step S202: Under the constraints of the constraints, the target layout of the printed circuit board is obtained by minimizing the center deviation index based on the first mapping relationship, maximizing the area occupancy rate of the printed circuit board based on the second mapping relationship, and minimizing the total moving distance based on the third mapping relationship.

[0053] In one alternative implementation, based on This ensures that the components are placed within their designated layout area; among which, Used to represent the weight of the k-th component in the u-th layout region. Used to represent the u-th layout region on the printed circuit board. X Minimum boundary coordinates in the axial direction Used to represent the u-th layout region on the printed circuit board. Y Minimum boundary coordinates in the axial direction Used to represent the u-th layout region on the printed circuit board. X Maximum boundary coordinates in the axis direction Used to represent the u-th layout region on the printed circuit board. Y Maximum boundary coordinates in the axis direction Used to indicate the k-th component on the printed circuit board. X Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. Y Center coordinates along the axis Used to represent the length of the k-th component Used to represent the width of the k-th component.

[0054] pass The minimum boundary coordinates of the k-th component along the entire X-axis of the printed circuit board can be calculated; through The maximum boundary coordinates of the k-th component along the X-axis of the entire printed circuit board can be calculated.

[0055] If the minimum boundary coordinate of the u-th layout region along the entire X-axis of the printed circuit board is less than or equal to the minimum boundary coordinate of the k-th component along the entire X-axis of the printed circuit board, then the condition is satisfied. Furthermore, the maximum boundary coordinate of the u-th layout region along the entire X-axis of the printed circuit board is greater than or equal to the maximum boundary coordinate of the k-th component along the entire X-axis of the printed circuit board, i.e., it satisfies... Therefore, we can conclude that the k-th component will not exceed the u-th layout area in the X-axis direction. The same applies in the Y-axis direction, so we will not repeat the explanation.

[0056] The above formula can cleverly restrict the movement of each component within its layout area, further ensuring that components in different layout areas do not affect each other, and also reducing the possibility of different components going out of bounds, spatial interference, or layout conflicts due to layout optimization iteration.

[0057] In one alternative implementation, based on This prevents collisions between components; among them, Used to represent the center coordinates of the k1th component along the X-axis of the printed circuit board. Used to represent the center coordinates of the k1th component along the Y-axis of the printed circuit board. Used to represent the length of the k1th component. Used to represent the width of the k1th component; Used to indicate the earliest placement priority of the k1th component. Used to indicate the latest placement priority of the k1th component. Used to represent the collision detection state quantity between the k1th component and the k2th component; in 1 is used to indicate that the k1-th component and the k2-th component collide. A value of 0 indicates that the k1th and k2th components did not collide, which meets the requirements of this application.

[0058] in, Used to represent the center coordinates of the k2th component along the X-axis of the printed circuit board. Used to represent the center coordinates of the k2th component along the Y-axis of the printed circuit board. Used to represent the length of the k2th component. Used to represent the width of the k2th component. Used to represent the gap between the k1th component and the k2th component. Used to indicate the earliest placement priority of the k2th component. Used to indicate the latest placement priority of the k2th component.

[0059] in, Used to indicate on printed circuit boards X The amount of overlap in the axial direction. Used to indicate on printed circuit boards Y The amount of overlap in the axial direction. Used to indicate the amount of overlap in arrangement priority.

[0060] As a specific example, such as Figure 3 As shown, through The final right boundary of the k1th component can be obtained through... The final left boundary of the k1th component can be obtained. Similarly, through... The final right boundary of the k2th component can be obtained, and through... The final left boundary of the k2-th component can be obtained. If the minimum right boundary between the k1-th and k2-th components is still greater than the maximum left boundary between them, it indicates that the k1-th and k2-th components collide in the X-axis direction of the printed circuit board. The same logic applies to the Y-axis direction and the arrangement priority, so it will not be repeated.

[0061] By performing collision detection on the k1th and k2th components from three dimensions—X-axis direction, Y-axis direction, and arrangement priority—it is possible to accurately determine whether the k1th and k2th components actually collide in the actual layout, thereby further improving the feasibility of the final generated target layout.

[0062] In one alternative implementation, based on This prevents collisions between components and obstacles; among them, This is used to represent the minimum boundary coordinates of the b-th obstacle point along the X-axis of the printed circuit board. This is used to represent the minimum boundary coordinates of the b-th obstacle point in the Y-axis direction of the printed circuit board. This is used to represent the maximum boundary coordinates of the b-th obstacle point along the X-axis of the printed circuit board. This is used to represent the maximum boundary coordinates of the b-th obstacle point along the Y-axis of the printed circuit board. Used to represent the collision detection state quantity between the k-th component and the b-th obstacle point, in =1 is used to indicate that the k-th component collides with the b-th obstacle point. =0 indicates that the k-th component and the b-th obstacle did not collide. The collision detection principle here is similar to the collision detection principle between components shown earlier, and will not be repeated here.

[0063] Furthermore, when the obstacle point is rectangular, the minimum boundary coordinates of the b-th obstacle point in the X-axis and Y-axis directions of the entire printed circuit board can be the coordinates of the lower left corner of the b-th obstacle point. Similarly, the maximum boundary coordinates of the b-th obstacle point in the X-axis and Y-axis directions of the entire printed circuit board can be the coordinates of the upper right corner of the b-th obstacle point.

[0064] Of course, when the obstacle point is not rectangular, such as circular, elliptical, or hexagonal shapes, we can first determine the smallest rectangular frame that surrounds the obstacle point, then use the coordinates of the lower left corner of the smallest rectangular frame as the minimum boundary coordinates of the b-th obstacle point in the X and Y axes of the entire printed circuit board, and use the coordinates of the upper right corner of the smallest rectangular frame as the maximum boundary coordinates of the b-th obstacle point in the X and Y axes of the entire printed circuit board.

[0065] By performing collision detection on the k-th component and the b-th obstacle point from both the X-axis and Y-axis directions, it is possible to accurately determine whether the k-th component and the b-th obstacle point actually collide in the actual layout, thereby further improving the feasibility of the final generated target layout.

[0066] In addition, it should be noted that, under the constraints, in the process of minimizing the center deviation index based on the first mapping relationship, maximizing the area occupancy of the printed circuit board based on the second mapping relationship, and minimizing the total movement distance based on the third mapping relationship, not only can the target center coordinates of each component be obtained, but also the corner coordinates of each component can be obtained. Thus, by using the target center coordinates and corner coordinates of the components, the position of the components on the entire printed circuit board can be further determined, and the target center coordinates and corner coordinates of the components can also be used to characterize the final target layout of the printed circuit board.

[0067] In one alternative implementation, based on This ensures that the arrangement priority between components meets the preset arrangement priority; among which... Used to indicate the arrangement priority of the k1th component. This is used to indicate the arrangement priority of the k2-th component, and the preset arrangement priority corresponding to the k1-th component and the k2-th component is... Higher than , This is used to represent the priority coefficient when the k1th component and the k2th component are arranged in the uth layout area.

[0068] If, during the component placement process, the k2-th component is placed first, then the placement priority of the k1-th component is lower than that of the k2-th component. However, the preset placement priority for the k1-th and k2-th components should be that the placement priority of the k1-th component is higher than that of the k2-th component. =0. Conversely, if the k1th component is placed first, then the placement priority of the k1th component is lower than that of the k2th component, and the preset placement priority corresponding to the k1th and k2th components should be that the placement priority of the k1th component is lower than that of the k2th component. =1.

[0069] By applying this constraint, the highest priority components, such as critical components, high-value components, or special-function components, can be prioritized for placement. This ensures that the highest priority components occupy the optimal layout resources on the printed circuit board, such as being close to core areas like signal interfaces, power inputs, heat dissipation channels, and high-speed signal links. This avoids the global optimization logic of the automatic placement algorithm causing the highest priority components to be squeezed into non-ideal positions, which could affect the electrical performance, heat dissipation efficiency, or structural assembly feasibility of the printed circuit board.

[0070] In one alternative implementation, based on This ensures that the layout area of ​​each component is unique; among which, Used to represent the weight of the k-th component in the u-th layout area.

[0071] As shown above, when the k-th component is located within the u-th layout region, then If the k-th component is not located within the u-th layout area, then Here, k can be considered a constant and u a variable, with u taking values ​​from 1 to U. If the k-th component is located in only one of the U layout regions, then multiple The summation result is 1, which indicates that the component is located in only one layout area.

[0072] For example, a printed circuit board has three layout areas: the first layout area, the second layout area, and the third layout area. If a target component is located in the first layout area, then its corresponding area is... Since the target component is not located in the second or third layout area, its corresponding location is... Therefore, it is ultimately satisfied. Therefore, the constraint that the layout area where the target component is located is unique is satisfied.

[0073] By forcibly constraining each component to be assigned to only one layout area, the situation of duplicate component layout and lack of effective layout position can be fundamentally avoided, which can further ensure the feasibility of the final generated target layout.

[0074] Specifically, step S202 includes: Step S2021: Using a multi-objective optimization algorithm, under the constraints of the constraints, the target layout is obtained by minimizing the center deviation index based on the first mapping relationship, maximizing the area occupancy of the printed circuit board based on the second mapping relationship, and minimizing the total moving distance based on the third mapping relationship.

[0075] like Figure 4 As shown, with the objectives of minimizing the center deviation index, maximizing the area occupancy of the printed circuit board, and minimizing the total movement distance, under the constraints, the system calls the data stored in the database, such as the number and type of components, the preset arrangement priority between components, the number of layout areas, the functional modules corresponding to the layout areas, the center and corner coordinates of the layout areas, the number of obstacle points, the center and corner coordinates of the obstacle points, and the placement direction of the components. The system then executes a multi-objective optimization algorithm to calculate the position allocation of the components. For example, the multi-objective optimization algorithm calculates the target center coordinates of the components, and finally outputs the target layout of the printed circuit board that meets the optimization objectives and constraints.

[0076] In some cases, multi-objective optimization algorithms can be, but are not limited to, multi-objective particle swarm optimization, improved non-dominated sorting genetic algorithm (FS-NSGAII), improved multi-objective gray wolf optimization algorithm (FS-MOGWO), or multi-objective ant colony optimization, etc. The appropriate multi-objective optimization algorithm can be flexibly selected according to actual needs.

[0077] To facilitate understanding of the specific implementation process of this scheme, this application uses a multi-objective particle swarm optimization algorithm as an example to introduce the overall process of solving the target layout. Figure 5 As shown, it includes steps S501 to S511.

[0078] Step S501: Import data from the database and initialize algorithm parameters. Algorithm parameters may include the total number of individuals, the maximum number of iterations, the inertia weight range (minimum and maximum inertia weight), the global weight of each individual, the grid division of the printed circuit board, and the maximum number of non-dominated solutions.

[0079] Step S502: Introduce a normal distribution random number generation function to generate initial individuals.

[0080] First, the encoding method for each individual component in this application is real number encoding, meaning that a component is represented by the center point coordinates of its center point along the X-axis and Y-axis of the printed circuit board. Therefore, the encoding length for each component is 2. For example, if the total number of components involved in this layout is 5, then the encoding length for each individual component is 2. 5 = 10.

[0081] Secondly, to generate high-quality initialization individuals, the center point coordinates of each component along the X-axis and Y-axis of the printed circuit board can be generated using a normal distribution random number generation function. As a specific example, the normal distribution random number generation function can further include a first generation function and a second generation function. Based on this, 30% of the initialization individuals can be generated using the first generation function and 70% using the second generation function, thus ensuring a high degree of randomness in the generation of initialization individuals.

[0082] Wherein, for the first generating function, the coordinates of the center point of each component in each initialized individual along the X-axis of the printed circuit board can be expressed as: ,in, The initial center coordinates of the generated components along the X-axis are used to represent the coordinates of the generated components. `nr` represents the normally distributed random number generation function. Used to indicate the position of a component's movement. This is used to represent the length of the printed circuit board. For the first generation function, the method for generating the center point coordinates of each component in each initialized individual along the Y-axis is similar to the method for generating the center point coordinates along the X-axis, and will not be repeated here.

[0083] Specifically, for the second generation function, the coordinates of the center point of each component in the X-axis direction in each initialized individual can be expressed as follows: ,in, Used to represent the coordinates of the lower left corner point along the X-axis of the printed circuit board. This is used to represent the coordinates of the upper right corner point in the X-axis direction of the printed circuit board. The second generation function generates the center point coordinates of each component in the Y-axis direction for each initialized individual in the same way as the aforementioned generation method for the center point coordinates in the X-axis direction, and will not be repeated here.

[0084] Step S503: Under the constraints of the constraints, the target individual is obtained by updating each initial individual using the position optimization algorithm.

[0085] Step S504: Using the target individual, calculate the center deviation index, the area utilization rate of the printed circuit board, and the total moving distance. At the same time, select the Pareto optimal solution set based on the calculated center deviation index, the area utilization rate of the printed circuit board, and the total moving distance.

[0086] Step S505: Determine whether the preset conditions are met; if the preset conditions are met, proceed to step S506; if the preset conditions are not met, proceed to steps S507 to S511. The preset conditions can be that the current iteration count has reached the maximum iteration count. Of course, the preset conditions can also be other preset conditions, such as the current Pareto optimal solution set having converged, the current performance index having met the preset performance index, etc., and this application does not specifically limit them in this regard.

[0087] Step S506: Output the Pareto optimal solution set. Additionally, if the number of individuals in the Pareto optimal solution set exceeds the maximum number of non-dominated solutions, redundant individuals can be removed using crowding density.

[0088] Step S507: Select the current best individual from the Pareto optimal solution set.

[0089] Step S508, update the adaptive inertia weights. Specifically, this can be achieved through... The adaptive inertia weights are updated, where, Used to represent the current adaptive inertia weights after the update. Used to represent minimum inertia weight, Used to represent the maximum inertia weight, Used to indicate the maximum number of iterations Used to indicate the number of previous iterations.

[0090] Step S509: Update the speed and position of the optimal individual to obtain the updated individual.

[0091] Specifically, the center point coordinates of the optimal individual in the X-axis direction of the printed circuit board and the center point coordinates of the optimal individual in the Y-axis direction of the printed circuit board can be updated respectively.

[0092] As a concrete example, it can be seen that... Update the coordinates of the center point of the optimal individual along the X-axis of the printed circuit board, where, Used to represent the updated center point coordinates of the optimal individual in the X-axis direction of the printed circuit board. This is used to represent the current coordinates of the center point of the optimal individual along the X-axis of the printed circuit board. Used to represent the optimal weight of an individual. Used to represent the globally optimal weight. and Used to represent independent random numbers (i.e., random weight coefficients) that are uniformly distributed within the interval [0,1]. This is used to represent the existing optimal center point coordinates of the optimal individual in the X-axis direction.

[0093] It should be understood that the center point coordinates of the optimal individual in the Y-axis direction of the printed circuit board are similar to those described above, and will not be repeated here.

[0094] Step S510: Under the constraints of the constraints, the position optimization algorithm is used to update the individual to obtain the target individual for the new iteration round.

[0095] Step S511: Using the target individuals of the new iteration round, calculate the center deviation index, the area utilization rate of the printed circuit board, and the total moving distance. At the same time, based on the calculated center deviation index, the area utilization rate of the printed circuit board, and the total moving distance, select the Pareto optimal solution set, update the Pareto optimal solution set, and return to step S505.

[0096] Furthermore, the location optimization algorithm mentioned above can be specifically described as follows: Step 1: Import all current components, the initial center coordinates of the components, the pre-set arrangement priority between components, the obstacles on the printed circuit board, and the center and corner coordinates of the obstacles, the gaps between components, etc.

[0097] Step 2: Taking two layout areas (first layout area and second layout area) as an example, first operate on the first layout area, read all the components that should belong to, i.e. should be placed in the first layout area, and update the initial center coordinates of each component belonging to the first layout area in sequence according to the pre-set arrangement priority to obtain the target center coordinates of each component.

[0098] Taking whether a collision occurs between a component and an obstacle as an example, this specifically includes: Based on the initial center coordinates of the current component, determine whether the current component has collided with the obstacle point.

[0099] If the current component collides with an obstacle point in the X-axis direction of the printed circuit board, then according to the constraints, the current component is moved in the X-axis direction of the printed circuit board with a set granularity until the current component does not collide with the obstacle point in the X-axis direction of the printed circuit board. If the center point coordinates of the current component that does not collide cannot be found in the X-axis direction, then penalty coefficients are accumulated on the center deviation index, the area utilization rate of the printed circuit board, and the total movement distance.

[0100] If the current component collides with an obstacle point along the Y-axis of the printed circuit board, it moves along the Y-axis of the printed circuit board at a set granularity (i.e., grid number) according to the constraints, until the current component does not collide with an obstacle point or a component with a determined center point coordinate along the X-axis of the printed circuit board. The set of determined center point coordinates is then updated. If, at the end of the movement, a collision still occurs with an obstacle point or a component with a determined center point coordinate, a penalty coefficient is continuously added to the center deviation index, the area utilization rate of the printed circuit board, and the total movement distance.

[0101] It should be understood that the specific process of whether a collision occurs between components is described in the previous text, and will not be repeated here.

[0102] Step 3: If there are still components that have not been placed in the first layout area, continue to place them according to the steps described above.

[0103] As a specific example, such as Figure 6 As shown, the printed circuit board includes a first layout area, a second layout area, and a third layout area. Figure 7 As shown, taking the first layout area and the second layout area as examples, the flowchart of the layout generation method of the printed circuit board is introduced, including steps S701 to S718.

[0104] Step S701: Import data from the database and initialize algorithm parameters. Algorithm parameters may include the total number of individuals, maximum number of iterations, inertia weight range (minimum and maximum inertia weight), global weight of each individual, grid division of the printed circuit board, and maximum number of non-dominated solutions.

[0105] Step S702: Read the components belonging to the first layout area according to the preset layout priority.

[0106] Step S703: Read the information of obstacle points in the printed circuit board.

[0107] Step S704: Determine whether there are any components that are not arranged in the first layout area but should belong to the first layout area. If not, proceed to step S705; if yes, proceed to steps S706 to S710.

[0108] Step S705: Output the target center coordinates of each component belonging to the first layout area.

[0109] Step S706: Process the first component with the highest current arrangement priority.

[0110] Step S707: Determine whether the first component with the highest current placement priority collides with other components already placed in the first layout area, and whether the first component with the highest current sorting priority collides with an obstacle point. If no collision occurs, proceed to step S710; if a collision occurs, proceed to steps S708 and S709.

[0111] Step S708: Determine whether the first component with the highest current placement priority collides in the X-axis direction, i.e., whether the constraint rules in the X-axis direction are satisfied. If not, move the first component with the highest current placement priority in the X-axis direction until the constraint rules are satisfied. If the constraint rules in the X-axis direction are satisfied, proceed to step S709.

[0112] Step S709: Determine whether the first component with the highest current placement priority collides in the Y-axis direction, i.e. whether the constraint rules in the Y-axis direction are satisfied. If not, move the first component with the highest current placement priority in the Y-axis direction, such as moving it in the Y-axis direction according to the initial center coordinates, until the constraint rules in the Y-axis direction are satisfied.

[0113] Step S710: Remove the first component with the highest placement priority from the component set corresponding to the first layout area, update the component set with the determined center point coordinates, and return to step S704.

[0114] For details on steps S711 to S718, please refer to steps S702 to S710, which will not be repeated here.

[0115] The printed circuit board layout generation method provided in this embodiment utilizes a multi-objective optimization algorithm. It minimizes the center deviation index based on the first mapping relationship, maximizes the area utilization of the printed circuit board based on the second mapping relationship, and minimizes the total moving distance based on the third mapping relationship. This can quickly converge to the target layout of the printed circuit board with better layout effect and improve the generation efficiency of the target layout of the printed circuit board.

[0116] This embodiment also provides a layout generation apparatus for printed circuit boards, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0117] This embodiment provides a layout generation device for printed circuit boards, such as... Figure 8 As shown, it includes: The acquisition module 801 is used to acquire the first mapping relationship between the center deviation index and the component movement weight, the second mapping relationship between the area occupancy rate of the printed circuit board and the area occupancy rate of the component, and the third mapping relationship between the total movement distance and the target center coordinates of the component on the printed circuit board. The center deviation index is used to characterize the deviation between the target center coordinates of the component and the center coordinates of the layout area where the component is located, and the total movement distance is used to characterize the movement distance of the component from the initial center coordinates to the target center coordinates on the printed circuit board. The generation module 802 is used to minimize the center deviation index based on the first mapping relationship, maximize the area occupancy of the printed circuit board based on the second mapping relationship, and minimize the total movement distance based on the third mapping relationship under the constraints of the constraints, to obtain the target layout of the printed circuit board. The target layout is characterized based on the target center coordinates of each component. The constraints are configured as follows: the layout area of ​​the component is unique, the component is within its layout area, there is no collision between components and between components and obstacle points, and the arrangement priority between components meets the preset arrangement priority.

[0118] In one optional implementation, the first mapping relationship is: ;in, Used to indicate deviation from the center. Used to represent the weight of component movement Used to represent the weight of a component's movement along the X-axis. Used to represent the weight of component movement on the Y-axis Used to represent the first correction factor. Used to represent the weight of the k-th component in the u-th layout region. Used to represent the u-th layout region on the printed circuit board. X Center coordinates along the axis Used to represent the u-th layout region on the printed circuit board. Y Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. X Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. Y The center coordinates along the axis, where K represents the total number of components and U represents the total number of layout areas.

[0119] In one optional implementation, the second mapping relationship is: ;in, Used to indicate area occupancy rate Used to represent the u-th layout region on the printed circuit board.X Minimum boundary coordinates in the axial direction Used to represent the u-th layout region on the printed circuit board. Y Minimum boundary coordinates in the axial direction Used to represent the u-th layout region on the printed circuit board. X Maximum boundary coordinates in the axis direction Used to represent the u-th layout region on the printed circuit board. Y Maximum boundary coordinates in the axis direction Used to represent the u-th layout region on the printed circuit board. X Total number of grid cells along the axis Used to represent the u-th layout region on the printed circuit board. Y Total number of grid cells along the axis Used to represent the second correction factor. Used to indicate the preset grid size for dividing a printed circuit board into grids. Used to represent grid state variables, in When the value is 1, it means that the k-th component occupies the grid represented by cx and cy.

[0120] In one alternative implementation, the third mapping relationship is: ,in, Used to represent the total distance traveled. Used to represent the weight of the k-th component in the u-th layout region. Used to represent the u-th layout region on the printed circuit board. X Center coordinates along the axis Used to represent the u-th layout region on the printed circuit board. Y Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. X Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. Y The center coordinates along the axis, where K represents the total number of components and U represents the total number of layout areas.

[0121] In one alternative implementation, the components are located within their respective layout areas, including: based on This ensures that the components are placed within their designated layout area; among which, Used to represent the weight of the k-th component in the u-th layout region. Used to represent the u-th layout region on the printed circuit board. X Minimum boundary coordinates in the axial direction Used to represent the u-th layout region on the printed circuit board.Y Minimum boundary coordinates in the axial direction Used to represent the u-th layout region on the printed circuit board. X Maximum boundary coordinates in the axis direction Used to represent the u-th layout region on the printed circuit board. Y Maximum boundary coordinates in the axis direction Used to indicate the k-th component on the printed circuit board. X Center coordinates along the axis Used to indicate the k-th component on the printed circuit board. Y Center coordinates along the axis Used to represent the length of the k-th component Used to represent the width of the k-th component.

[0122] In one optional implementation, no collisions occur between components or between components and obstacle points, including: based on This prevents collisions between components; among them, Used to represent the center coordinates of the k1th component along the X-axis of the printed circuit board. Used to represent the center coordinates of the k1th component along the Y-axis of the printed circuit board. Used to represent the length of the k1th component. Used to represent the width of the k1th component; Used to indicate the earliest placement priority of the k1th component. Used to indicate the latest placement priority of the k1th component. 1 is used to indicate that the k1-th component and the k2-th component collide; where, Used to represent the center coordinates of the k2th component along the X-axis of the printed circuit board. Used to represent the center coordinates of the k2th component along the Y-axis of the printed circuit board. Used to represent the length of the k2th component. Used to represent the width of the k2th component. Used to represent the gap between the k1th component and the k2th component. Used to indicate the earliest placement priority of the k2th component. This is used to indicate the latest placement priority of the k2-th component; where... Used to indicate on printed circuit boards X The amount of overlap in the axial direction. Used to indicate on printed circuit boards Y The amount of overlap in the axial direction. Used to indicate the amount of overlap in arrangement priority; based on This prevents collisions between components and obstacles; among them, This is used to represent the minimum boundary coordinates of the b-th obstacle point along the X-axis of the printed circuit board. This is used to represent the minimum boundary coordinates of the b-th obstacle point in the Y-axis direction of the printed circuit board. This is used to represent the maximum boundary coordinates of the b-th obstacle point along the X-axis of the printed circuit board. This is used to represent the maximum boundary coordinates of the b-th obstacle point along the Y-axis of the printed circuit board. =1 is used to indicate that the k-th component collides with the b-th obstacle.

[0123] In one optional implementation, the arrangement priority between components satisfies a preset rule, including: based on This ensures that the arrangement priority between components meets the preset arrangement priority; among which... Used to indicate the arrangement priority of the k1th component. This is used to indicate the arrangement priority of the k2-th component, and the preset arrangement priority corresponding to the k1-th component and the k2-th component is... Higher than , This is used to represent the priority coefficient when the k1th component and the k2th component are arranged in the uth layout area.

[0124] In one alternative implementation, the layout area where the component is located uniquely includes: based on This ensures that the layout area of ​​each component is unique, among which... Used to represent the weight of the k-th component in the u-th layout area.

[0125] In an alternative implementation, the generation module is further configured to utilize a multi-objective optimization algorithm to minimize the center deviation index based on a first mapping relationship, maximize the area occupancy of the printed circuit board based on a second mapping relationship, and minimize the total movement distance based on a third mapping relationship, under the constraints of the constraints, to obtain the target layout.

[0126] The printed circuit board layout generation apparatus provided in this application embodiment can execute the printed circuit board layout generation method provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects of the method. Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0127] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0128] The following is a detailed reference. Figure 9This diagram illustrates a suitable structural schematic for implementing the electronic device described in the embodiments of this application. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 901, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 902 or a program loaded from memory 908 into random access memory (RAM) 903. The RAM 903 also stores various programs and data required for the operation of the electronic device. The processor 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0129] Typically, the following devices can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909. Communication device 909 allows electronic devices to exchange data via wireless or wired communication with other devices. Although Figure 9 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0130] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 909, or installed from a memory 908, or installed from a ROM 902. When the computer program is executed by the processor 901, it performs the functions defined in the printed circuit board layout generation method of embodiments of this application.

[0131] Figure 9 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0132] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the printed circuit board layout generation method shown in the above embodiments is implemented.

[0133] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0134] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for generating the layout of a printed circuit board, characterized in that, The printed circuit board includes multiple layout areas, each layout area being used to place components, and the method includes: Obtain the first mapping relationship between the center deviation index and the component movement weight, the second mapping relationship between the area occupancy rate of the printed circuit board and the area occupancy rate of the component, and the third mapping relationship between the total movement distance and the target center coordinates of the component on the printed circuit board. Under the constraints, the target layout of the printed circuit board is obtained by minimizing the center deviation index based on the first mapping relationship, maximizing the area occupancy of the printed circuit board based on the second mapping relationship, and minimizing the total movement distance based on the third mapping relationship. The target layout is characterized based on the target center coordinates of each component. The center deviation index is used to characterize the deviation between the target center coordinates of the component and the center coordinates of the layout area where the component is located, and the total movement distance is used to characterize the movement distance of the component from the initial center coordinates to the target center coordinates on the printed circuit board. The constraints are configured such that the layout area of ​​the component is unique, the component is within its layout area, there is no collision between the components and between the component and the obstacle point, and the arrangement priority between the components meets the preset arrangement priority.

2. The method according to claim 1, characterized in that, The first mapping relationship is: ； in, Used to represent the center deviation index. Used to represent the movement weight of the component Used to represent the movement weight of the component on the X-axis Used to represent the movement weight of the component on the Y-axis Used to represent the first correction factor. Used to represent the weight of the k-th component in the u-th layout region. Used to indicate the uth layout region on the printed circuit board X Center coordinates along the axis Used to indicate the uth layout region on the printed circuit board Y Center coordinates along the axis This is used to indicate that the kth component is on the printed circuit board. X Center coordinates along the axis This is used to indicate that the kth component is on the printed circuit board. Y The center coordinates along the axis, K represents the total number of the components, and U represents the total number of the layout areas.

3. The method according to claim 1, characterized in that, The second mapping relationship is: ； in, Used to represent the area occupancy rate. Used to indicate the uth layout region on the printed circuit board X Minimum boundary coordinates in the axial direction Used to indicate the uth layout region on the printed circuit board Y Minimum boundary coordinates in the axial direction Used to indicate the uth layout region on the printed circuit board X Maximum boundary coordinates in the axis direction Used to indicate the uth layout region on the printed circuit board Y Maximum boundary coordinates in the axis direction Used to indicate the uth layout region on the printed circuit board X Total number of grid cells along the axis Used to indicate the uth layout region on the printed circuit board Y Total number of grid cells along the axis Used to represent the second correction factor. The preset grid size is used to represent the grid division of the printed circuit board. Used to represent grid state variables, in A value of 1 indicates that the k-th component occupies the grid represented by cx and cy.

4. The method according to claim 1, characterized in that, The third mapping relationship is as follows: ； in, Used to represent the total distance traveled. Used to represent the weight of the k-th component in the u-th layout region. Used to indicate the uth layout region on the printed circuit board X Center coordinates along the axis Used to indicate the uth layout region on the printed circuit board Y Center coordinates along the axis This is used to indicate that the kth component is on the printed circuit board. X Center coordinates along the axis This is used to indicate that the kth component is on the printed circuit board. Y The center coordinates along the axis, K represents the total number of the components, and U represents the total number of the layout areas.

5. The method according to any one of claims 1 to 4, characterized in that, The components are located within their respective layout areas, including: based on This places the component within its layout area; in, Used to represent the weight of the k-th component in the u-th layout region. Used to indicate the uth layout region on the printed circuit board X Minimum boundary coordinates in the axial direction Used to indicate the uth layout region on the printed circuit board Y Minimum boundary coordinates in the axial direction Used to indicate the uth layout region on the printed circuit board X Maximum boundary coordinates in the axis direction Used to indicate the uth layout region on the printed circuit board Y Maximum boundary coordinates in the axis direction This is used to indicate that the kth component is on the printed circuit board. X Center coordinates along the axis This is used to indicate that the kth component is on the printed circuit board. Y Center coordinates along the axis Used to indicate the length of the k-th component. Used to indicate the width of the kth component.

6. The method according to any one of claims 1 to 4, characterized in that, No collisions occur between the components or between the components and the obstacle points, including: based on This prevents collisions between the components; in, This is used to represent the center coordinates of the k1th component along the X-axis of the printed circuit board. This is used to represent the center coordinates of the k1th component in the Y-axis direction of the printed circuit board. Used to indicate the length of the k1th component. Used to indicate the width of the k1th component; Used to indicate the earliest arrangement priority of the k1th component. Used to indicate the latest arrangement priority of the k1th component. 1 is used to indicate that the k1th component and the k2th component collide; in, This is used to represent the center coordinates of the k2th component along the X-axis of the printed circuit board. This is used to represent the center coordinates of the k2th component along the Y-axis of the printed circuit board. Used to indicate the length of the k2th component. Used to indicate the width of the k2th component, Used to indicate the gap between the k1th component and the k2th component. Used to indicate the earliest arrangement priority of the k2th component. Used to indicate the latest arrangement priority of the k2th component; in, Used to indicate on the printed circuit board X The amount of overlap in the axial direction, Used to indicate on the printed circuit board Y The amount of overlap in the axial direction, Used to indicate the amount of overlap in arrangement priority; based on This ensures that the components do not collide with the obstacle points; in, This is used to represent the minimum boundary coordinates of the b-th obstacle point in the X-axis direction of the printed circuit board. This is used to represent the minimum boundary coordinates of the b-th obstacle point in the Y-axis direction of the printed circuit board. This is used to represent the maximum boundary coordinates of the b-th obstacle point in the X-axis direction of the printed circuit board. This is used to represent the maximum boundary coordinates of the b-th obstacle point in the Y-axis direction of the printed circuit board. =1 is used to indicate that the k-th component collides with the b-th obstacle point.

7. The method according to any one of claims 1 to 4, characterized in that, The arrangement priority between the components meets preset rules, including: based on This ensures that the arrangement priority between the components meets the preset arrangement priority. in, Used to indicate the arrangement priority of the k1th component. This is used to indicate the arrangement priority of the k2th component, and the preset arrangement priority corresponding to the k1th component and the k2th component is... Higher than , This is used to represent the priority coefficient when the k1th component and the k2th component are arranged in the uth layout area.

8. The method according to any one of claims 1 to 4, characterized in that, The unique layout area where the component is located includes: based on This ensures that the layout area of ​​the component is unique; in, This is used to represent the weight of the k-th component in the u-th layout region.

9. The method according to claim 1, characterized in that, Under the constraints of the conditions, the process of minimizing the center deviation index based on the first mapping relationship, maximizing the area occupancy rate based on the second mapping relationship, and minimizing the total movement distance based on the third mapping relationship to obtain the target layout of the printed circuit board includes: Using a multi-objective optimization algorithm, under the constraints of the given conditions, the target layout is obtained by minimizing the center deviation index based on the first mapping relationship, maximizing the area occupancy of the printed circuit board based on the second mapping relationship, and minimizing the total movement distance based on the third mapping relationship.

10. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the printed circuit board layout generation method according to any one of claims 1 to 9.

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