A chip double-sided wiring method based on double-sided copy source points

Abstract

The application discloses a chip double-sided wiring method based on double-sided copy source points, and relates to chip wiring technology; the chip wiring network source points are copied into double-sided copies, namely, front-side copies and back-side copies, double-sided copies and cross-face via edges are introduced at Steiner points, a unified cost function is used to model the front-side edges, the back-side edges and the cross-face via edges, a double-sided perception Steiner graph based on the copy source points is constructed, and thus the chip double-sided wiring is naturally modeled and efficiently solved in the same process. The technical scheme provided by the application can be used as an independent double-sided wiring engine, or can be embedded into a larger EDA optimization process, such as a unit type distribution and wiring joint optimization, pin redistribution, layer resource collaborative optimization and the like, to provide an efficient double-sided wiring solution for chip back-end design.

Description

Technical Field

[0001] This invention relates to chip wiring technology, and more particularly to a novel double-sided wiring method based on double-sided replication source points of a chip. Background Technology

[0002] With advancements in back-side chip manufacturing processes, the accessible locations of standard cell pins are no longer limited to one side of the chip. For the same net, the driver and load terminals may be located on the front-side (FS) or back-side (BS) routing layer, respectively. Furthermore, nets can also establish connectivity between the front and back sides of the signal transmission unit (STC).

[0003] In existing technologies, many routing methods are still based on the traditional two-dimensional global routing framework. Typically, a topology tree is first determined on a two-dimensional plane, and then layer-switching or cross-plane behavior is determined locally in subsequent stages. This type of method has certain applicability in single-sided routing problems, but it has obvious limitations in double-sided routing scenarios, including the following aspects.

[0004] First, source point modeling is insufficient. Existing methods typically assume that the source point is fixed on one side of the chip, failing to fully describe the actual routing capability of the driver in a double-sided structure, thus limiting the search space.

[0005] Second, the coupling method between topology and face type is unreasonable. If the face type is fixed in advance during the 2D topology generation stage, it will constrain subsequent searches too early; if the face type is determined entirely in the post-processing stage, it will be difficult to obtain globally optimal results.

[0006] Third, the cross-face switching modeling is coarse. The current method cannot jointly support bi-face source points and STC cross-face behavior as explicit edge resources in the wiring diagram model, making it difficult to accurately optimize the via usage location and quantity.

[0007] Fourth. Fragmented cost system. Front-side routing, back-side routing, and cross-plane vias are often evaluated separately, lacking a unified cost function, resulting in a lack of consistent optimization criteria for path selection. Summary of the Invention

[0008] To overcome the shortcomings of the prior art, this invention provides a novel bi-sided routing method based on the source point of chip double-sided replication. By replicating the source point of the chip routing network into a front-side copy and a back-side copy, and introducing double-sided copies and cross-sided via edges at the Steiner point, a unified cost function is used to perform consistent modeling of the front-side edge / back-side edge / cross-sided via edge, thereby naturally modeling and efficiently solving the chip double-sided routing problem in the same process.

[0009] For convenience, the present invention defines the following terms:

[0010] EDA: Electronic Design Automation;

[0011] FS: Front-Side routing layer;

[0012] BS: Back-Side wiring layer;

[0013] DSR: Double-Sided Routing.

[0014] Steiner Tree: A minimum-cost tree structure for connecting multiple Steiner point terminal pins;

[0015] Steiner Point: A non-terminal branch node introduced in a Steiner tree to optimize connections;

[0016] Via: A vertical channel used to establish electrical connections between different wiring layers on the same side of a chip.

[0017] STC: Signal Transfer Cell, used to establish signal connectivity between the front and back sides of a wiring harness;

[0018] Pattern Routing: A method for extracting the optimal routing tree based on a predefined graph pattern.

[0019] The core of this invention includes: designing a source point replication mechanism: replicating the source point into a front copy and a back copy, and explicitly representing the two-sided reachability of the driver end through zero-cost connecting edges; designing a Steiner point two-sided replication mechanism: establishing front copies and back copies of Steiner points in the two-dimensional Steiner tree, and connecting them through cross-face via edges to support cross-face switching at branch positions; establishing a two-stage modeling mechanism of two-dimensional skeleton and two-sided expansion: first generating a two-dimensional Steiner topology skeleton, and then expanding it into a two-sided sensing graph structure, thereby decoupling planar topology determination from face selection; designing a unified two-sided cost function: using the same cost function to uniformly model front edges, back edges, and cross-face via edges, thereby considering line length, congestion, and cross-face cost in a unified optimization framework. The minimum cost tree is extracted from the expanded two-sided graph structure, and redundant Steiner leaf nodes are pruned to obtain the final two-sided sensing routing topology. Then, a two-sided routing tree is obtained through two-sided sensing pattern routing and layer allocation algorithms.

[0020] The technical solution provided by this invention is:

[0021] A chip bi-sided routing method based on double-sided source point replication is proposed. This method replicates the chip routing network source point into front and back copies, introduces double-sided copies and cross-sided via edges at Steiner points, and employs a unified cost function to consistently model front / back / cross-sided via edges. This allows for natural modeling and efficient solution of chip bi-sided routing within the same process. The method includes:

[0022] Step 1: Determine the pin locations of the wire mesh.

[0023] Based on the current cell type allocation results, determine the source point and each sink point of the network, as well as their actual access nodes on the double-sided three-dimensional wiring mesh.

[0024] Step 2: Generate a two-dimensional Steiner topology skeleton.

[0025] The source and sink terminals obtained in step 1 are projected onto a two-dimensional plane, and a two-dimensional Steiner tree is constructed. This two-dimensional Steiner tree is used to determine the planar branch topology of the network and candidate Steiner points. In this step, only the shared planar connection skeleton is determined, and it is not predetermined whether each edge is on the front or back side, thus avoiding premature constraints on bidirectional path selection.

[0026] Step 3: Construct a two-sided sensing Steiner graph based on the source point of replication.

[0027] The two-dimensional Steiner tree generated in step 2 is extended onto a double-sided wiring mesh to form a double-sided sensing Steiner graph. The extension includes at least:

[0028] 1. Generate a front copy o^F and a back copy o^B for the source node.

[0029] 2. Set a zero-cost connection edge between o^F and o^B to indicate that the driver can initiate routing from either the front or back side.

[0030] 3. For each Steiner point s, generate a front copy s^F and a back copy s^B.

[0031] 4. Set a cross-plane via edge between s^F and s^B to indicate that the wiring tree can switch between planes at this Steiner point.

[0032] 5. Copy each planar edge in the 2D Steiner tree to the front and back sides respectively to form the corresponding front and back edges.

[0033] 6. Connect each sink point only to the terminal on one side determined by the current cell type assignment.

[0034] Through the above steps, the two-dimensional planar skeleton can be transformed into a two-sided graph structure that explicitly includes the ability to initiate two-sided graphs at the source point, the ability to switch between surfaces at the Steiner point, and the constraint of surface-specific graphs at the sink point.

[0035] Step 4: Perform double-sided sensing mode wiring.

[0036] The minimum-cost face-aware Steiner tree of the network is extracted from the two-sided sensing Steiner graph generated in step 3. In the k-th iteration, the cost of edge e of network n can be represented as c_e, which applies uniformly to front edges, back edges, and cross-face via edges. During routing, the unified cost function automatically determines whether the network should remain connected on a single face or introduce cross-face switching at one or more Steiner points to obtain a lower total cost. The operation to obtain the minimum-cost tree is the minimum spanning tree algorithm, in which Steiner points are also considered vertices. After obtaining the minimum-cost tree, a pruning operation is performed on the resulting tree structure, deleting redundant Steiner leaf nodes that are neither source nor sink pins, to obtain the final two-sided sensing Steiner tree. Then, two-sided sensing mode routing is performed on the Steiner tree to obtain a two-sided routing tree.

[0037] Step 5: Perform double-sided layer assignment.

[0038] Each edge of the surface-aware routing tree obtained in step 4 is mapped onto the actual metal layer, including front-side routing resources, back-side routing resources, and cross-surface via resources, thereby determining the actual resource usage of each routing segment and updating the current routing requirements accordingly. Layer allocation for double-sided chips is set based on the location of nodes in the routing tree. For a given edge in the routing tree, if the endpoints of the edge are on the same side of the chip, STC will not be used; if the endpoints of the edge are on different sides of the chip, STC will be used.

[0039] In practice, the connection edges between the source points are not limited to absolute zero cost; they can also be set to a sufficiently small cost, as long as they can express the two-sided reachability priority.

[0040] The cross-face via edge can be set not only at the Steiner point, but also extended to other positions that allow switching, depending on the process rules and mesh structure.

[0041] Two-dimensional skeleton generation methods are not limited to a single Steiner tree algorithm; they can also be replaced by other heuristic or exact algorithms capable of generating planar shared topologies.

[0042] Compared with the prior art, the beneficial effects of the present invention are:

[0043] This invention provides a novel bifacial routing method based on bifacial source point replication. By replicating the source point and setting zero-cost connection edges, it fully expresses the bifacial reachability of the driver in a bifacial routing environment, expanding the searchable path space. By introducing bifacial copies and cross-face via edges at the Steiner point, cross-face behavior is elevated from post-processing patching to native decision-making in the graph model, improving path optimization quality. Through a two-stage process of "2D skeleton + bifacial expansion," it improves bifacial path search capability while maintaining topology stability. By unifying the cost function, it performs consistent optimization of front, back, and cross-face via resources, avoiding inconsistencies between multiple cost systems. By pruning redundant leaf nodes, it obtains a more compact routing tree structure, reducing invalid resource occupation. It significantly reduces runtime in the later stages of bifacial routing and layer allocation iterations, improving the overall efficiency of the joint optimization framework. The technical solution provided by this invention can be applied to the global routing stage in integrated circuit physical design and EDA tools, and is particularly suitable for advanced process nodes that support bifacial routing. This method can be used as a standalone double-sided routing engine, or it can be embedded in larger-scale EDA optimization processes such as cell type allocation and routing joint optimization, pin reallocation, and layer resource collaborative optimization, providing an efficient double-sided routing solution for chip back-end design. Attached Figure Description

[0044] Figure 1 The flowchart illustrates the double-sided wiring method based on double-sided chip replication source points provided by this invention.

[0045] Figure 2 This is a schematic diagram of a two-dimensional Steiner tree skeleton constructed based on the pins of a two-dimensional terminal net.

[0046] Figure 3 This is a schematic diagram of the double-sided sensing Steiner graph extension when the lateral edge cost w(S1,S2)=3 in a two-dimensional Steiner tree.

[0047] Figure 4 This is a schematic diagram of the minimum cost tree pruning result when the horizontal edge cost w(S1,S2)=3 in a two-dimensional Steiner tree.

[0048] Figure 5 This is a schematic diagram of the double-sided sensing Steiner graph extension when the lateral edge cost w(S1,S2)=30 in a two-dimensional Steiner tree.

[0049] Figure 6 This is a schematic diagram of the minimum cost tree pruning result when the horizontal edge cost w(S1,S2)=30 in a two-dimensional Steiner tree. Detailed Implementation

[0050] The present invention will be further described below with reference to the accompanying drawings and embodiments, but the scope of the invention is not limited in any way.

[0051] This invention proposes a double-sided routing method based on source point replication. By replicating the source point into a front copy and a back copy, introducing double-sided copies and cross-sided via edges at the Steiner point, and using a unified cost function to perform consistent modeling of the front edge / back edge / cross-sided via edge, the double-sided routing problem can be naturally modeled and efficiently solved in the same process.

[0052] This invention addresses the network to be routed by first solving the 3D network routing problem as a 2D problem to obtain a rough plan, and then mapping it to 3D. The double-sided routing method based on source point replication executes the following steps sequentially: First, based on the current cell type allocation results, the actual access nodes of the network source points and sink points on the double-sided 3D routing mesh are determined; then, the source points and sink points are projected onto a 2D plane to construct a Steiner topology skeleton; next, the 2D skeleton is expanded into a double-sided sensing Steiner graph containing replicated source points, double-sided copies of Steiner points, and cross-face via edges; subsequently, uniform-cost pattern routing is performed on this graph to extract the minimum-cost double-sided sensing routing tree; finally, the routing tree is mapped to actual physical resources.

[0053] The following is an example of double-sided wiring for a single network chip; the complete process is as follows: Figure 1 As shown, it includes the following steps:

[0054] Step 1: Determine the chip wireline pin locations.

[0055] Based on the current cell type allocation results of the chip, the source points and sink terminals of the network, as well as their actual access nodes on the double-sided 3D routing mesh, are determined and used as chip net pins. For each sink instance v of network n, if the currently selected cell type t*(v) exposes the sink pin at mesh node u, then node u is used as the valid terminal (i.e., net pin) of that sink. The source point retains its double-sided reachability on both the front and back sides so that subsequent routing searches can be initiated from either side.

[0056] Step 2: Generate a two-dimensional Steiner topology skeleton.

[0057] Ignoring the differences between the front and back sides, project the source and sink terminals determined in step 1 onto a two-dimensional plane and construct a two-dimensional Steiner tree. For example... Figure 2 As shown, this two-dimensional Steiner tree is used to determine the planar branch topology and candidate Steiner points of the network. In this step, only the shared planar connection skeleton is determined, and it is not predetermined whether each edge of the Steiner tree is on the front or back side, thus avoiding premature constraints on bidirectional path selection.

[0058] Step 3: Construct a two-sided sensing Steiner graph based on the source point of replication.

[0059] The two-dimensional Steiner tree generated in step 2 is extended onto a double-sided wiring mesh to form a double-sided sensing Steiner graph. For example... Figure 3 As shown, the extension includes at least:

[0060] 1. Generate a front copy o^F and a back copy o^B for the source node.

[0061] 2. Set a connection edge (e.g., zero cost) between o^F and o^B to indicate that the driver can initiate routing from either the front or back side.

[0062] 3. For each Steiner point s, generate a front copy s^F and a back copy s^B.

[0063] 4. Set a cross-plane via edge between s^F and s^B to indicate that the wiring tree can switch between planes at this Steiner point.

[0064] 5. Copy each planar edge in the 2D Steiner tree to the front and back sides respectively to form the corresponding front and back edges.

[0065] 6. Connect each sink point only to the terminal on one side determined by the current cell type assignment.

[0066] Through the above steps, the two-dimensional planar skeleton can be transformed into a two-sided graph structure that explicitly includes source point bi-face initiation capability, Steiner point cross-face switching capability, and sink point connection constraints, such as... Figure 3 and Figure 5 As shown.

[0067] Step 4: Perform double-sided sensing mode wiring.

[0068] Extract the minimum-cost surface-aware Steiner tree from the two-sided sensing Steiner graph generated in step 3, as follows: Figure 4 As shown. In the k-th iteration, the cost of edge e in network n can be represented as c_e, which applies uniformly to front edges, back edges, and cross-face via edges. During routing, the unified cost function automatically determines whether the network should remain connected on a single face or introduce cross-face switching at one or more Steiner points to obtain a lower total cost. The operation to obtain the minimum cost tree uses the minimum spanning tree algorithm, in which Steiner points are also considered vertices. After obtaining the minimum cost tree, a pruning operation is performed on the resulting tree structure, deleting redundant Steiner leaf nodes that are neither source nor sink pins, such as... Figure 6As shown, the final minimum-cost two-sided sensing Steiner tree is obtained. Next, two-sided sensing pattern routing is performed on the Steiner tree to obtain a two-sided routing tree.

[0069] Step 5: Perform double-sided layer assignment.

[0070] Each edge of the double-sided sensing routing tree obtained in step 4 is mapped onto the actual metal layer, including front-side routing resources, back-side routing resources, and cross-sided via resources, thereby determining the actual resource usage of each routing segment and updating the current routing requirements accordingly. Double-sided layer allocation sets the layer allocation range based on the location of nodes in the routing tree. For a given edge in the routing tree, if the endpoints of the edge are on the same side of the chip, STC will not be used; if the endpoints of the edge are on different sides of the chip, STC will be used.

[0071] When extracting the minimum cost tree on the extended two-sided graph structure, the connection edge between the front copy and the back copy generated by copying the source point is not limited to absolute zero cost, but can also be set to a sufficiently small cost, as long as it can express the two-sided reachability priority.

[0072] The cross-face via edge can be set not only at the Steiner point, but also extended to other positions (non-Steiner point) that allow switching, depending on the process rules and mesh structure.

[0073] Step 2 is not limited to a single Steiner tree algorithm; other heuristic or exact algorithms capable of generating planar shared topologies can also be used.

[0074] This invention's method can be used not only for simple double-sided routing but also embedded in joint optimization tasks such as cell type allocation, pin reallocation, and layer resource collaborative optimization. It can be applied to the global routing stage in integrated circuit physical design and EDA tools, and is particularly suitable for advanced process nodes that support double-sided routing. This method can be used as a standalone double-sided routing engine or embedded in larger-scale EDA optimization flows such as cell type allocation and routing joint optimization, pin reallocation, and layer resource collaborative optimization, providing an efficient double-sided routing solution for chip back-end design.

[0075] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A chip double-sided wiring method based on double-sided replication source points, characterized in that, By replicating the chip routing network source point into double-sided copies (front and back), and introducing double-sided copies and cross-sided via edges at the Steiner point, a unified cost function is used to consistently model the front, back, and cross-sided via edges. This allows for natural modeling and efficient solution of double-sided chip routing within the same process; including: Step 1: Determine the pin locations of the net: Based on the current cell type allocation results, determine the source point and each sink point of the net and their actual access nodes on the double-sided three-dimensional wiring mesh; Step 2: Generate a two-dimensional Steiner tree topology skeleton to determine the planar branch topology and candidate Steiner points of the network; Step 3: Construct a two-sided sensing Steiner graph based on the copied source point. Extend the two-dimensional Steiner tree generated in Step 2 onto the two-sided wiring mesh to form a two-sided sensing Steiner graph. The two-sided sensing Steiner graph is a two-sided graph structure that explicitly includes the two-sided initiation capability of the source point, the cross-face switching capability of the Steiner point, and the face constraint of the sink point. The extension includes: 31) Generate a front copy and a back copy of the source node; 32) Set a connection edge between the front copy and the back copy generated by the source point, indicating that the driver can initiate routing from either the front or the back side; 33) Generate a front copy and a back copy for each Steiner point; 34) Set a cross-face via edge between the front copy and the back copy generated at the Steiner point, indicating that the wiring tree can switch between faces at this Steiner point; 35) Copy each planar edge in the two-dimensional Steiner tree to the front and back sides respectively to form the corresponding front edge and back edge; 36) Connect each sink point only to the terminal on one side determined by the current cell type assignment; Step 4: Extract the minimum cost surface-aware Steiner tree from the generated two-sided sensing Steiner graph and prune redundant non-pin endpoints; then perform two-sided sensing mode routing on the Steiner tree to obtain a two-sided routing tree. Step 5: Perform double-sided layer assignment, including: Map each edge of the face-aware routing tree obtained in step four onto the actual metal layer, including front routing resources, back routing resources, and cross-face via resources, determine the actual resource usage of each routing segment, and update the current routing requirements; double-sided layer allocation sets the layer allocation range according to the location of the nodes on the routing tree.

2. The chip double-sided wiring method based on double-sided replication source points as described in claim 1, characterized in that, Step 2 involves projecting the source and sink terminals obtained in Step 1 onto a two-dimensional plane to construct a two-dimensional Steiner tree. Only the shared planar connection skeleton is determined, without pre-determining whether each edge is on the front or back side.

3. The chip double-sided wiring method based on double-sided replication source points as described in claim 1, characterized in that, In step 32), the connection edges between the front copy and the back copy generated by copying the source point are made with absolute zero cost; Or set the cost to be small enough that it can express the priority of both sides being reachable.

4. The chip double-sided wiring method based on double-sided replication source points as described in claim 1, characterized in that, In step 34), the cross-face via edge is set at the Steiner point, or extended to other locations where switching is permitted according to process rules and mesh structure.

5. The chip double-sided wiring method based on double-sided replication source points as described in claim 1, characterized in that, When performing mode routing in step four, the network automatically determines the way to achieve a lower total cost based on the unified cost function, including: completing connectivity on a single surface or introducing cross-surface switching at one or more Steiner points; and treating Steiner points as vertices.

6. The chip double-sided wiring method based on double-sided replication source points as described in claim 5, characterized in that, After obtaining the minimum cost tree, a pruning operation is performed on the resulting minimum cost tree structure to delete redundant Steiner leaf nodes that are neither source nor sink pins, thus obtaining a two-sided sensing wiring tree.

7. The chip double-sided wiring method based on double-sided replication source points as described in claim 1, characterized in that, In double-sided layer assignment, for an edge on the wiring tree, if the endpoints of the edge are on the same side of the chip, the signal transmission unit (STC) is not used; if the endpoints of the edge are on different sides of the chip, the signal transmission unit (STC) is used.

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