Clock dividing apparatus, method and electronic device based on multi-mode frequency divider

Abstract

The application discloses a clock frequency division device based on a multi-mode frequency divider, which comprises a cascade circuit module and a mode control module. The cascade circuit module comprises one or more multi-mode frequency dividers and is used for outputting a target frequency division clock. The multi-mode frequency dividers are arranged in series. The clock input end of a later-stage multi-mode frequency divider is connected with the clock output end of an earlier-stage multi-mode frequency divider. The first-stage multi-mode frequency divider is connected with an original input clock. The mode control module is connected with the frequency division mode switching ports of each multi-mode frequency divider. The mode control module generates frequency division control signals of the multi-mode frequency dividers according to a frequency division signal. The frequency division control signals of different multi-mode frequency dividers are independent of each other. The application further discloses a clock frequency division method based on the multi-mode frequency divider and electronic equipment. Compared with the prior art, the application realizes specific fractional frequency division by dynamically switching the enable sequence of the frequency division control signals. Meanwhile, the application expands the frequency division ratio range that can be realized by using the series multi-mode frequency divider structure, avoids the quantization noise problem and realizes power consumption management.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a clock division device, method and electronic device based on a multi-mode divider. Background Technology

[0002] Modern integrated circuit design places stringent requirements on clock systems, particularly in terms of timing accuracy and power consumption. The performance of frequency divider circuits directly determines the timing stability, power consumption, and performance of the entire system. In particular, fractional frequency division technology is crucial for achieving flexible clock frequency configuration and is an essential technology for high-performance SoCs (System-on-Chip).

[0003] Clock divider circuits are core modules in modern digital and mixed-signal systems, widely used in frequency synthesis, clock generation, and data synchronization. Early clock divider techniques were integer dividers, based on a simple counter structure using cascaded D flip-flops that only supported division ratios to powers of 2. While simple, this approach suffered from low frequency resolution, complex clock tree structures, and poor flexibility, making it unsuitable for high-frequency applications and failing to meet the multi-frequency requirements of modern SoCs. Existing fractional divider techniques (such as dual-mode prescalers combined with Δ-Σ modulators) inevitably introduce high-frequency quantization noise. Even after noise shaping, this leads to output clock jitter (more severe in processes below 28nm, and almost unusable in processes below 16nm), resulting in clock timing violations. Furthermore, the modulator itself consumes additional power, increasing dynamic power consumption. Moreover, existing techniques often implement fractional dividers using standard cells, failing to overcome timing accumulation errors. For example, the slight differences in trace length, parasitic parameters, and cell positions in the four paths used to generate a four-phase clock can be amplified by process variations, causing a significant phase deviation of 90 degrees.

[0004] To address the aforementioned problems, this invention discloses a clock frequency divider device, method, and electronic device. Summary of the Invention

[0005] The purpose of this invention is to provide a clock division device, method, and electronic device based on cascaded multi-mode dividers, so as to avoid the problems of high-frequency quantization noise and additional power consumption caused by the application of Δ-Σ modulators in existing fractional division technology.

[0006] To achieve the above objectives, this invention discloses a clock division device based on a multi-mode divider, comprising a cascaded circuit module and a mode control module. The cascaded circuit module includes one or more multi-mode dividers for outputting a target divided clock. Multiple multi-mode dividers are connected in series, such that the clock input of a subsequent multi-mode divider is connected to the clock output of the preceding multi-mode divider, and the clock input of the first-stage multi-mode divider is connected to the original input clock. The mode control module is connected to the division mode switching port of each multi-mode divider. It generates a division control signal for the multi-mode divider based on an externally input division signal containing the final division ratio information. The division control signals of different multi-mode dividers are independent of each other. The mode control module sends the division control signal to the corresponding division mode switching port of the multi-mode divider according to a preset timing sequence, causing the multi-mode divider to switch to the corresponding division ratio based on the division control signal, so that the frequency ratio of the original input clock to the target divided clock is the final division ratio. The preset timing of the frequency division control signal transmission corresponds to the period of the original input clock.

[0007] Preferably, the cascaded circuit module uses the clock signal output from the clock output terminal of the last stage of the multi-mode divider as the target divided clock output; or, the multi-mode divider has multiple components, and the cascaded circuit module further includes a target clock output section connected to the clock output terminal of each stage of the multi-mode divider, and selects the clock signal output from the clock output terminal of one of the multi-mode dividers as the target divided clock according to a selection control signal, thereby accurately selecting the clock signal with the required division ratio and bypassing the other clock signals. The mode control module also generates a selection control signal based on the division signal, the division control signal being the division control signal of the multi-mode divider corresponding to the selection control signal, the selection control signal corresponding to the multi-mode divider selected by the selection control signal and all the preceding multi-mode dividers of this stage, the division control signal being multiple independent division control signals, each of the division control signals controlling the dynamic switching of the division mode of the corresponding multi-mode divider.

[0008] Preferably, the mode control module also receives the original input clock, and the cascaded circuit module and the mode control module receive an externally input synchronization signal. Based on the synchronization signal, the generated signals are made to be in the same timing and phase as the original input clock, so as to prevent phase shift of the signals and cause signal timing disorder.

[0009] Preferably, the mode control module includes a mode switching unit and a decision control unit. The mode switching unit is connected to the frequency division mode switching port of each stage of the multi-mode divider. One end of the decision control unit is connected to the frequency division signal, and the other end is connected to the mode switching unit. The decision control unit generates a corresponding clock selection strategy based on the final frequency division ratio information of the frequency division signal and sends the clock selection strategy to the mode switching unit. The mode switching unit determines the multi-mode divider corresponding to the selection control signal based on the clock selection strategy and generates a frequency division control signal corresponding to the multi-mode divider.

[0010] Preferably, the clock division device based on the multi-mode divider further includes a multiplexer and a four-phase delay circuit. One end of the four-phase delay circuit is connected to the target divided clock and delays the target divided clock in four different phases to generate four-phase clocks with four different phases. The multiplexer has several input ports, one of which is connected to the target divided clock, and the other four input ports are connected to the four-phase clocks. The multiplexer selects one or more clock signals from the input signals of the several input ports as the target clock signal to obtain a clock signal with the best phase quality that meets the application requirements.

[0011] Specifically, the mode control module also generates a corresponding clock selection strategy based on the frequency division signal and sends the clock selection strategy to the control terminal of the multiplexer. The multiplexer selects one or more clock outputs from the input signals of several input ports as the target clock signal based on the clock selection strategy.

[0012] This invention also discloses a clock division method based on a multi-mode divider, comprising: A cascaded circuit module is configured, comprising one or more multi-mode dividers for outputting a target frequency-divided clock. Multiple multi-mode dividers are connected in series, such that the clock input of the subsequent multi-mode divider is connected to the clock output of the preceding multi-mode divider, and the clock input of the first multi-mode divider is connected to the original input clock. An externally input frequency division signal is obtained, the frequency division signal containing the final frequency division ratio information. A frequency division control signal for the multi-mode frequency divider is generated based on the frequency division signal. The frequency division control signal is sent to the frequency division mode switching port of the corresponding multi-mode frequency divider according to a preset timing sequence. The frequency division control signals of different multi-mode frequency dividers are independent of each other.

[0013] Preferably, the cascaded circuit module uses the clock signal output from the clock output terminal of the last stage of the multi-mode divider as the target divided clock output; or, the multi-mode divider has multiple components, and the cascaded circuit module further includes a target clock output section, which is connected to the clock output terminal of each stage of the multi-mode divider, and selects the clock signal output from the clock output terminal of one of the multi-mode dividers as the target divided clock output according to a selection control signal.

[0014] Specifically, generating the frequency division control signal of the multi-mode frequency divider based on the frequency division signal includes: generating a selection control signal and a frequency division control signal based on the externally input frequency division signal, wherein the frequency division control signal is the frequency division control signal of the multi-mode frequency divider corresponding to the selection control signal, and the selection control signal corresponds to the multi-mode frequency divider selected by the selection control signal and all the preceding multi-mode frequency dividers of the multi-mode frequency divider at this stage.

[0015] Preferably, the clock division method based on a multi-mode divider further includes: making the generated signals consistent with the timing and phase of the original input clock based on the externally input synchronization signal and the original input clock.

[0016] The present invention also discloses an electronic device, including a cascaded circuit module, a computer program, a storage medium, and an actuator. The cascaded circuit module includes one or more multi-mode dividers for outputting a target frequency-divided clock. Multiple multi-mode dividers are connected in series so that the clock input terminal of the subsequent multi-mode divider is connected to the clock output terminal of the preceding multi-mode divider. The first-stage multi-mode divider is connected to the original input clock. The computer program is stored in the storage medium. The actuator is electrically connected to the cascaded circuit module and executes the computer program to implement the clock division method based on multi-mode dividers described above.

[0017] Compared to existing technologies, this invention dynamically switches the enable sequence of the frequency division control signal to control the dynamic switching of the division ratio of a single-stage multi-mode frequency divider, enabling it to form an average division ratio in the time domain to achieve specific fractional division. Simultaneously, the series multi-mode frequency divider structure expands the range of possible division ratios, improving the flexibility of the division ratio. It allows for flexible output of multiple clock frequency signals from a single hardware circuit, avoiding the quantization noise injection problem inherent in Δ-Σ modulators. Furthermore, the frequency division mode switching process does not require reconfiguration of the PLL loop; the division ratio switching is completed simply by modifying the enable sequence of the frequency division control signal, achieving real-time power management and overcoming the technical bottleneck of not supporting dynamic frequency adjustment. This provides a clock division solution with both high flexibility and high performance for high-speed SerDes, mobile SoCs, and 5G communication systems. On the other hand, standard cell library designs often fail to meet the requirements of high-performance clock circuits. This invention employs a fully custom circuit design, allowing for precise drive control through optimization methods such as adjusting the transistor width-to-length ratio (W / L). It also supports physical-level timing optimization (such as clock line length matching and node capacitance minimization) to improve overall circuit performance. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the clock divider device in Example 1.

[0019] Figure 2 This is a schematic diagram of the series multimode divider in Example 1.

[0020] Figure 3 This is a schematic diagram of a further clock divider device structure for Embodiment 1.

[0021] Figure 4 This is a schematic diagram of the clock divider device in Example 2.

[0022] Figure 5 This is a schematic diagram of the series multimode divider in Example 2.

[0023] Figure 6 This is a schematic diagram of a further clock divider device structure in Example 2. Detailed Implementation

[0024] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0025] Example 1: refer to Figure 1 , Figure 2This embodiment provides a clock division device based on a multi-mode divider, including a cascaded circuit module 10 and a mode control module 20. The cascaded circuit module 10 includes one or more multi-mode dividers for outputting a target divided clock 101. The multiple multi-mode dividers are connected in series so that the clock input terminal 1 of the subsequent multi-mode divider is connected to the clock output terminal 2 of the previous multi-mode divider, and the clock input terminal 1 of the first multi-mode divider is connected to the original input clock 01.

[0026] The mode control module 20 is connected to the division mode switching port 3 of each stage of the multi-mode frequency divider. Based on the externally input division signal 02 containing the final division ratio information, it generates a division control signal 201 for the multi-mode frequency divider. The division control signals 201 of different multi-mode frequency dividers are independent of each other. The mode control module 20 sends the division control signal 201 to the corresponding division mode switching port 3 of the multi-mode frequency divider according to a preset timing sequence, so that the multi-mode frequency divider switches to the corresponding division ratio according to the division control signal 201, so that the frequency ratio of the original input clock 01 to the target divided clock 101 is the final division ratio. The preset timing sequence of the division control signal 201 corresponds to the period of the original input clock.

[0027] In this embodiment, the multi-mode divider is a 2 / 3 multi-mode divider. Of course, this invention does not limit the type of multi-mode divider; it depends on the specific application scenario. In other embodiments, the multi-mode divider can also be an 8 / 9 multi-mode divider, a 16 / 17 multi-mode divider, a 2 / 3 / 4 multi-mode divider, etc. In this embodiment, each stage of the 2 / 3 multi-mode divider controls its division mode switching through one division control signal 201. In other embodiments, a 2 / 3 / 4 multi-mode divider can also be used. In this case, each stage of the 2 / 3 / 4 multi-mode divider needs to control its division mode switching through two division control signals. Other types of multi-mode dividers follow the same principle.

[0028] In this embodiment, the frequency division control signal 201 controls the dynamic switching of the frequency division mode of the single-stage 2 / 3 multi-mode frequency divider by dynamically switching the enable sequence, so as to form an average frequency division ratio in the time domain to achieve fractional frequency division.

[0029] Specifically, the frequency division control signal 201 is a signal that controls the current division ratio of the multi-mode frequency divider. For example, when the current input is from 0 to 2 / 3 of the multi-mode frequency divider's frequency division mode switching port 3, the 2 / 3 multi-mode frequency divider operates in 2-division mode. When the current input is from 1 to 2 / 3 of the multi-mode frequency divider's frequency division mode switching port 3, the 2 / 3 multi-mode frequency divider operates in 3-division mode. When the frequency division control signal 201 is output sequentially to the 2 / 3 multi-mode frequency divider's frequency division mode switching port 3 according to the timing sequence, a series of 0 and 1 bit enable sequences will be formed. This allows the mode control module 20 to control the corresponding multi-mode frequency divider to operate at a fixed division ratio (e.g., 2-division or 3-division) or to switch between multiple division ratios at a certain period (e.g., switching between 2-division and 3-division at a period corresponding to the frequency of the original input clock).

[0030] In this embodiment, in the enable sequence of the frequency division control signal 201, bit 0 controls the 2 / 3 multimode frequency divider to be in divide-2 mode, and bit 1 controls the 2 / 3 multimode frequency divider to be in divide-3 mode. For example, when the frequency division control signal 201 with the enable sequence [0,1,0,1,0,1…] is input to the frequency division mode switching port 3 of the 2 / 3 multimode frequency divider at the frequency of the original input clock, the 2 / 3 multimode frequency divider will work in a mode of uniformly alternating divide-2 and divide-3, ultimately achieving an average division ratio of (2+3) / 2=2.5.

[0031] Preferably, the mode control module 20 also receives the original input clock 01, and the cascaded circuit module 10 and the mode control module 20 receive the externally input synchronization signal 03. Based on the synchronization signal 03, the generated signals are made to be in the same timing and phase as the original input clock 01, so as to prevent the signals from shifting phase and causing signal timing disorder.

[0032] refer to Figure 3The mode control module 20 includes a mode switching unit 21 and a decision control unit 22. The mode switching unit 21 is connected to the frequency division mode switching port 3 of each stage of the multi-mode frequency divider. One end of the decision control unit 22 is connected to the frequency division signal 02, and the other end is connected to the mode switching unit 21. It generates a corresponding clock selection strategy 203 based on the final frequency division ratio information of the frequency division signal 02. For example, the clock selection strategy 203 includes the frequency division mode selected by each multi-mode frequency divider, that is, it determines the frequency division mode selected by each multi-mode frequency divider based on the required final frequency division ratio information. When the multi-mode frequency divider is a 2 / 3 multi-mode frequency divider, the frequency division modes include a fixed 2-frequency division working mode, a fixed 3-frequency division working mode, and a 2-frequency division and 3-frequency division switching working mode based on the original input clock frequency. The decision control unit 22 sends the clock selection strategy 203 to the mode switching unit 21, and the mode switching unit 21 determines the frequency division control signal 201 of the multi-mode frequency divider based on the clock selection strategy 203.

[0033] refer to Figure 1 , Figure 3 The clock division device based on the multi-mode divider further includes a multiplexer 30 and a four-phase delay circuit 40. One end of the four-phase delay circuit 40 is connected to the target divided clock 101 and performs four phase delays on the target divided clock 101 to generate four different phase four-phase clocks. The multiplexer 30 has several input ports, one of which is connected to the target divided clock 101, and the other four input ports are connected to the four-phase clocks. The multiplexer 30 selects one or more clock signals from the input signals of the several input ports and outputs them as the target clock signal 301 to obtain a clock signal with the best phase quality that meets the application requirements.

[0034] The four-phase clock is a clock group composed of clock signals with the same frequency but four different phases. In this embodiment, the four-phase clock is a standard four-phase clock, that is, the four different phases are 0°, 90°, 180°, and 270°, and the four-phase clock has the same frequency as the target frequency divider clock 101. Of course, this embodiment does not specifically limit the four different phases of the four-phase clock; the specific phase values ​​should depend on the actual application scenario.

[0035] Specifically, the clock selection strategy 203 also includes a phase selection command for the clock that needs to be output. The mode control module 20 sends the phase selection command of the clock selection strategy 203 to the control terminal of the multiplexer 30. The multiplexer 30 selects one or more clock signals from the input signals of several input ports according to the phase selection command and outputs them as the target clock signal 301.

[0036] The specific steps of the clock division method based on a multi-mode divider, completed by the mode control module 20 in conjunction with the cascaded circuit module 10 according to the present invention, are described below: 1. Obtain an externally input frequency division signal 02, wherein the frequency division signal 02 contains the final frequency division ratio information.

[0037] 2. Generate the frequency division control signal 201 of the multi-mode frequency divider based on the frequency division signal 02.

[0038] 3. The frequency division control signal 201 is sent to the frequency division mode switching port 3 of each of the multi-mode frequency dividers according to a preset timing sequence. The frequency division control signals 201 of different multi-mode frequency dividers are independent of each other. Each multi-mode frequency divider switches the corresponding division ratio according to the frequency division control signal 201 input to its frequency division mode switching port 3, thereby converting the original input clock 01 into the required target frequency divided clock 101, and outputting it from the clock output terminal 2 of the last stage multi-mode frequency divider. At this time, the frequency ratio of the original input clock 01 to the target frequency divided clock 101 is the final frequency division ratio.

[0039] The mode control module 20 also ensures that the generated signals (including various frequency division control signals, phase selection commands, etc.) are in the same timing and phase aligned with the original input clock 01 based on the externally input synchronization signal 03 and the original input clock 01.

[0040] This embodiment also discloses an electronic device, including a cascaded circuit module 10 and a mode control module 20. The mode control module 20 includes a computer program, a storage medium, and an actuator. The cascaded circuit module 10 is as described above. The computer program is Verilog code and is stored in the storage medium. The actuator is electrically connected to the cascaded circuit module 10 and executes the computer program to implement the clock division method based on a multi-mode divider described above.

[0041] Using a 2 / 3 multimode divider with a single stage as an example, the working process for achieving a 2.33 frequency division is described: The mode control module 20 generates a frequency division control signal 201 to control the 2 / 3 multimode divider based on the externally input frequency division signal 02 containing the final frequency division ratio information. The enable sequence of the frequency division control signal 201 is [0,0,1,0,0,1…]. The frequency division control signal 201 is sent to the frequency division mode switching port 3 of the multimode divider according to a preset timing sequence. By controlling the dynamic switching between the 2-frequency division mode and the 3-frequency division mode, it forms a (2) frequency division ratio in the time domain. The average division ratio of (2+3) / 3 = 2.33 is used to achieve fractional division. The divided clock signal is output as the target divided clock 101. Of course, the enable sequence of the division control signal 201 can also be [0,1,0,0,1,0…], as long as it is ensured that the average division ratio formed by the division ratio switching behavior controlled by the enable sequence in the time domain is the target fractional division ratio. This invention does not impose any special restrictions on this.

[0042] Using a 2 / 3 multimode divider with a single stage as an example, the working process for achieving a 2.67 frequency division is described: The mode control module 20 generates a frequency division control signal 201 to control the 2 / 3 multimode divider based on the externally input frequency division signal 02 containing the final frequency division ratio information. The enable sequence of the frequency division control signal 201 is [0,1,1,0,1,1…]. The frequency division control signal 201 is sent to the frequency division mode switching port 3 of the multimode divider according to a preset timing sequence. By controlling the dynamic switching between the 2-frequency division mode and the 3-frequency division mode, it forms a (2+3) pattern in the time domain. 2) The average division ratio is 2.67 (2 / 3), which is used to achieve fractional division. The divided clock signal is output as the target divided clock 101. Of course, the enable sequence of the division control signal 201 can also be [1,0,1,1,0,1…], as long as it is ensured that the average division ratio formed by the division ratio switching behavior controlled by the enable sequence in the time domain is the target fractional division ratio. This invention does not impose any special restrictions on this.

[0043] Example 2: Unlike Example 1, in this example, the reference... Figure 5 The multi-mode frequency divider has multiple components, and the cascaded circuit module 10 further includes a target clock output section 11. The target clock output section 11 is connected to the clock output terminal 2 of each stage of the multi-mode frequency divider, and selects the clock signal output from the clock output terminal 2 of one of the multi-mode frequency dividers as the target frequency division clock 101 according to a selection control signal 202, thereby accurately selecting the multi-mode frequency divider that needs to be divided, and bypassing the clock signals output by the other multi-mode frequency dividers.

[0044] The target clock output section 11 is a bypass switching circuit, which can be a switching circuit or a multiplexer, etc.

[0045] refer to Figure 4The mode control module 20 generates a selection control signal 202 and a frequency division control signal 201 based on the frequency division signal 02. The selection control signal 202 is sent to the control terminal of the target clock output unit 11 to control the multi-mode frequency divider corresponding to the output target frequency division clock 101. The frequency division control signal 201 is the frequency division control signal 201 of the multi-mode frequency divider corresponding to the selection control signal 202. The selection control signal 202 corresponds to the multi-mode frequency divider selected by the selection control signal 202 and all the preceding multi-mode frequency dividers of this stage. The frequency division control signal 201 consists of multiple independent frequency division control signals 201, and each frequency division control signal 201 controls the dynamic switching of the division ratio of the corresponding multi-mode frequency divider.

[0046] If there are n multi-mode frequency dividers, the target clock output unit 11 can select the clock signal output from the clock output terminal 2 of the i-th multi-mode frequency divider as the target frequency division clock 101, where i = 1, 2, 3...n, and n is greater than or equal to 2. The frequency division control signal 201 generated by the mode control module 20 is the frequency division control signal 201 of the 1st to the i-th multi-mode frequency divider.

[0047] It should be noted that when multiple multi-mode frequency dividers do not need to be used, but only a few multi-mode frequency dividers in the preceding stage are used to achieve the target frequency division ratio, the frequency division control signal 201 is only input to the corresponding few multi-mode frequency dividers in the preceding stage, and the subsequent multi-mode frequency dividers have no frequency division control signal 201 input and no corresponding frequency division signal output.

[0048] Preferably, the mode control module 20 also receives the original input clock 01, and the cascaded circuit module 10 and the mode control module 20 receive the externally input synchronization signal 03. Based on the synchronization signal 03, the generated signals are made to be in the same timing and phase as the original input clock 01, so as to prevent the signals from shifting phase and causing signal timing disorder.

[0049] refer to Figure 6The mode control module 20 includes a mode switching unit 21 and a decision control unit 22. One end of the decision control unit 22 is connected to the frequency division signal 02, and the other end is connected to the mode switching unit 21. It generates a corresponding clock selection strategy 203 based on the final frequency division ratio information of the frequency division signal 02. For example, the clock selection strategy 203 includes the frequency division mode selected by each multi-mode frequency divider. That is, the frequency division mode selected by each multi-mode frequency divider is determined based on the required final frequency division ratio information. When the multi-mode frequency divider is a 2 / 3 multi-mode frequency divider, the frequency division mode includes a fixed 2-frequency division working mode, a fixed 3-frequency division working mode, and a 2-frequency division and 3-frequency division switching working mode based on the frequency of the original input clock. The decision control unit 22 sends the clock selection strategy 203 to the mode switching unit 21. The mode switching unit 21 is connected to the frequency division mode switching port 3 of each stage of the multi-mode frequency divider and the control terminal of the target clock output unit 11. The mode switching unit 21 determines the frequency division control signal 201 of the multi-mode frequency divider according to the clock selection strategy 203, and determines the selection control signal 202 to be sent to the target clock output unit 11, so that while the selected i multi-mode frequency dividers work according to the corresponding frequency division mode, the target clock output unit 11 uses the clock signal output by the clock output terminal 2 of the i-th multi-mode frequency divider as the target frequency division clock 101 according to the selection control signal 202.

[0050] refer to Figure 4 , Figure 6 The clock division device based on the multi-mode divider further includes a multiplexer 30 and a four-phase delay circuit 40. One end of the four-phase delay circuit 40 is connected to the target divided clock 101 and performs four phase delays on the target divided clock 101 to generate four different phase four-phase clocks. The multiplexer 30 has several input ports, one of which is connected to the target divided clock 101, and the other four input ports are connected to the four-phase clocks. The multiplexer 30 selects one or more clock signals from the input signals of the several input ports and outputs them as the target clock signal 301 to obtain a clock signal with the best phase quality that meets the application requirements.

[0051] The four-phase clock is a clock group composed of clock signals with the same frequency but four different phases. In this embodiment, the four-phase clock is a standard four-phase clock, that is, the four different phases are 0°, 90°, 180°, and 270°, and the four-phase clock has the same frequency as the target frequency divider clock 101. Of course, this embodiment does not specifically limit the four different phases of the four-phase clock; the specific phase values ​​should depend on the actual application scenario.

[0052] Specifically, the clock selection strategy 203 also includes a phase selection command for the clock that needs to be output. The mode control module 20 sends the phase selection command of the clock selection strategy 203 to the control terminal of the multiplexer 30. The multiplexer 30 selects one or more clock signals from the input signals of several input ports according to the phase selection command and outputs them as the target clock signal 301.

[0053] The specific steps of the clock division method based on a multi-mode divider, completed by the mode control module 20 in conjunction with the cascaded circuit module 10 according to the present invention, are described below: 1. Obtain an externally input frequency division signal 02, wherein the frequency division signal 02 contains the final frequency division ratio information.

[0054] 2. Based on the frequency division signal 02, determine the frequency division operation required for the first i multi-mode frequency dividers and the frequency division mode of the first i multi-mode frequency dividers, thereby generating a selection control signal 202 corresponding to the i-th multi-mode frequency divider and a frequency division control signal 201 for the first i multi-mode frequency dividers.

[0055] 3. The frequency division control signal 201 is sent to the frequency division mode switching port 3 of the first i multi-mode frequency dividers according to a preset timing sequence, and the selection control signal 202 is sent to the control terminal of the target clock output unit 11. The frequency division control signals 201 of different multi-mode frequency dividers are independent of each other. The first i multi-mode frequency dividers switch the corresponding division ratio according to the frequency division control signal 201 input to their frequency division mode switching port 3. The target clock output unit 11 uses the clock signal output from the clock output terminal 2 of the i multi-mode frequency dividers as the target divided clock 101 according to the selection control signal 202, thereby converting the original input clock O1 into the required target divided clock 101, and outputting it from the clock output terminal 2 of the i-th multi-mode frequency divider. At this time, the frequency ratio of the original input clock O1 to the target divided clock 101 is the final division ratio.

[0056] Taking the multi-mode frequency divider as an example of a 2 / 3 multi-mode frequency divider, in the enable sequence of the frequency division control signal 201, bit 0 controls the 2 / 3 multi-mode frequency divider to be in 2-division mode, and bit 1 controls the 2 / 3 multi-mode frequency divider to be in 3-division mode.

[0057] In this invention, when a target frequency division clock 101 with a larger fractional division ratio is required, one or more 2 / 3 multi-mode frequency dividers are dynamically switched through the frequency division control signal 201 to obtain a smaller fractional division ratio. The remaining 2 / 3 multi-mode frequency dividers are fixed to divide by 2 or 3, so that the division ratios of all the 2 / 3 multi-mode frequency dividers are multiplied to obtain the target fractional division ratio.

[0058] The following describes the working process of implementing a 22.5 frequency divider: When a division ratio of 22.5 is required, the first three stages of 2 / 3 multimode dividers need to be configured among n 2 / 3 multimode dividers, where n is greater than or equal to 3. The mode control module 20 generates a division control signal 201 for controlling the first three stages of the 2 / 3 multimode dividers based on the externally input division signal 02 containing the final division ratio information. The division control signal 201 includes three independent division control signals, each corresponding to one of the first three stages of the 2 / 3 multimode dividers. The mode control module 20 sends the division control signal 201 to the division mode switching port 3 of the first three stages of the 2 / 3 multimode dividers according to a preset timing sequence. Subsequent 2 / 3 multimode dividers have no division control signal 201 input and no corresponding division signal output. The first stage 2 / 3 multimode divider is configured to achieve a 2.5 division ratio, the second stage 2 / 3 multimode divider is configured to achieve a 3 division ratio, and the third stage 2 / 3 multimode divider is configured to achieve a 3 division ratio. When the first-stage 2 / 3 multimode frequency divider achieves a 2.5 division ratio, the enable sequence of the division control signal 201 controlling this stage is [0,1,0,1…]. Through dynamic switching between the 2-division and 3-division modes, it achieves an average division ratio of (2+3) / 2 = 2.5 in the time domain. When the second-stage 2 / 3 multimode frequency divider achieves a 3-division ratio, the enable sequence of the division control signal 201 controlling this stage is [1,1,1,1…], keeping it fixed in the 3-division mode. When the third-stage 2 / 3 multimode frequency divider achieves a 3-division ratio, the enable sequence of the division control signal 201 controlling this stage is [1,1,1,1…], keeping it fixed in the 3-division mode, thus enabling the three-stage 2 / 3 multimode frequency dividers in series to achieve a 2.5 division ratio. 3 The target frequency division ratio is 22.5. The output frequency division signals of the above three-stage 2 / 3 multimode frequency dividers are all output to the target clock output section 11 in the cascaded circuit module 10. The target clock output section 11 selects the clock signal output from the clock output terminal 2 of the third-stage 2 / 3 multimode frequency divider as the target frequency division clock 101 output according to the selection control signal 202 corresponding to the 22.5 frequency division input by the mode control module 20.

[0059] It should be noted that in this embodiment, the mode control module 20 outputs the selection control signal 202 to the target clock output unit 11, so that the target clock output unit 11 can select the clock signal that achieves the target division ratio as the target divided clock 101 output, while prohibiting the output of other clock signals that do not have the target division ratio, effectively bypassing unnecessary clock signals. The target clock output unit 11 can be implemented by a bypass switching circuit, a multiplexer, etc., and the present invention does not impose any particular limitations on it.

[0060] Of course, this invention can also be used to achieve larger integer division ratios. Whether to achieve fractional or integer division ratios, it is only necessary to reasonably configure the number of series stages of the 2 / 3 multimode divider and the division ratio achieved by a single-stage 2 / 3 multimode divider within the division ratio range achievable by this invention.

[0061] It should be noted that this invention does not limit the multi-mode divider used to only 2 / 3 multi-mode dividers. Therefore, when a large target division ratio is required and a large number of stages are not necessary in the series multi-mode divider structure, it can also be achieved using series structures of other multi-mode dividers. For example, compared to a series structure of 2 / 3 multi-mode dividers, a series structure of 8 / 9 multi-mode dividers can achieve a larger division ratio with fewer stages. The specific multi-mode divider used should be determined based on the actual application scenario.

[0062] Compared with existing technologies, this invention controls the dynamic switching of the division ratio of a single-stage multi-mode frequency divider by dynamically switching the enable sequence of the division control signal 201, thereby achieving an average division ratio in the time domain to realize a specific fractional division. Simultaneously, the series multi-mode frequency divider structure expands the range of possible division ratios and improves the flexibility of the division ratio. Multiple clock frequency signals can be flexibly output with a single hardware circuit, avoiding the quantization noise injection problem inherent in Δ-Σ modulators. Furthermore, the division mode switching process does not require reconfiguration of the PLL loop; the division ratio switching can be completed simply by modifying the enable sequence of the division control signal 201, achieving real-time power management. This solves the technical bottleneck of not being able to support dynamic frequency adjustment, providing a clock division solution with both high flexibility and high performance for high-speed SerDes, mobile SoC, and 5G communication systems. On the other hand, standard cell library designs are difficult to meet the requirements of high-performance clock circuits. This invention adopts a fully custom circuit design. During the design process, optimization methods such as adjusting the transistor width-to-length ratio (W / L) can be used to achieve precise drive control. At the same time, it supports physical-level timing optimization (such as clock line length matching and node capacitance minimization) to improve the overall circuit performance.

[0063] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the scope of the present invention are still within the scope of the present invention.

Claims

1. A clock frequency divider based on a multi-mode frequency divider, characterized in that: Includes cascaded circuit modules and mode control modules; The cascaded circuit module includes one or more multi-mode dividers for outputting a target frequency-divided clock. The multiple multi-mode dividers are connected in series so that the clock input terminal of the subsequent multi-mode divider is connected to the clock output terminal of the preceding multi-mode divider, and the first multi-mode divider is connected to the original input clock. The mode control module is connected to the frequency division mode switching port of each stage of the multi-mode frequency divider. Based on the externally input frequency division signal containing the final frequency division ratio information, it generates the frequency division control signal of the multi-mode frequency divider. The frequency division control signals of different multi-mode frequency dividers are independent of each other. The mode control module sends the frequency division control signal to the frequency division mode switching port of the corresponding multi-mode frequency divider according to a preset timing sequence, so that the multi-mode frequency divider switches to the corresponding frequency division ratio according to the frequency division control signal, so that the frequency ratio of the original input clock to the target frequency division clock is the final frequency division ratio.

2. The clock divider based on a multi-mode divider as described in claim 1, characterized in that: The cascaded circuit module uses the clock signal output from the clock output terminal of the last stage multi-mode divider as the target frequency division clock output. or, The multi-mode frequency divider has multiple components, and the cascaded circuit module further includes a target clock output section. The target clock output section is connected to the clock output terminal of each stage of the multi-mode frequency divider, and selects the clock signal output by the clock output terminal of a multi-mode frequency divider as the target frequency divider according to a selection control signal. The mode control module also generates a selection control signal and a frequency division control signal based on the frequency division signal. The frequency division control signal is the frequency division control signal of the multi-mode frequency divider corresponding to the selection control signal. The selection control signal corresponds to the multi-mode frequency divider selected by the selection control signal and all the preceding multi-mode frequency dividers of this stage multi-mode frequency divider.

3. The clock frequency divider based on a multi-mode frequency divider as described in claim 1, characterized in that: The mode control module also receives the original input clock, and the cascaded circuit module and the mode control module receive an externally input synchronization signal. Based on the synchronization signal, the generated signals are made to be in the same timing and phase as the original input clock.

4. The clock divider based on a multi-mode divider as described in claim 1, characterized in that: The mode control module includes a mode switching unit and a decision control unit. The mode switching unit is connected to the frequency division mode switching port of each stage of the multi-mode frequency divider. One end of the decision control unit is connected to the frequency division signal, and the other end is connected to the mode switching unit. The decision control unit generates a corresponding clock selection strategy based on the final frequency division ratio information of the frequency division signal and sends the clock selection strategy to the mode switching unit. The mode switching unit determines the frequency division control signal corresponding to the multi-mode frequency divider based on the clock selection strategy.

5. The clock divider based on a multi-mode divider as described in claim 1, characterized in that: It also includes a multiplexer and a four-phase delay circuit. One end of the four-phase delay circuit is connected to the target frequency divider clock and delays the target frequency divider clock in four different phases to generate four-phase clocks with four different phases. The multiplexer has several input ports, one of which is connected to the target frequency divider clock and the other four input ports are connected to the four-phase clock. The multiplexer selects one or more clock signals from the input signals of the several input ports and outputs them as the target clock signal.

6. The clock divider based on a multi-mode divider as described in claim 5, characterized in that: The mode control module also generates a corresponding clock selection strategy based on the frequency division signal and sends the clock selection strategy to the control terminal of the multiplexer. The multiplexer selects one or more clock signals from the input signals of several input ports as the target clock signal based on the clock selection strategy.

7. A clock frequency division method based on a multi-mode frequency divider, characterized in that: include: A cascaded circuit module is configured, which includes one or more multi-mode dividers for outputting a target frequency-divided clock. The multiple multi-mode dividers are connected in series so that the clock input terminal of the subsequent multi-mode divider is connected to the clock output terminal of the previous multi-mode divider, and the first multi-mode divider is connected to the original input clock. An externally input frequency division signal is obtained, the frequency division signal containing the final frequency division ratio information. A frequency division control signal for the multi-mode frequency divider is generated based on the frequency division signal. The frequency division control signal is sent to the frequency division mode switching port of the corresponding multi-mode frequency divider according to a preset timing sequence. The frequency division control signals of different multi-mode frequency dividers are independent of each other.

8. The clock division method based on a multi-mode divider as described in claim 7, characterized in that: The cascaded circuit module uses the clock signal output from the clock output terminal of the last stage multi-mode divider as the target frequency division clock output; or... The multi-mode divider has multiple components, and the cascaded circuit module further includes a target clock output section. The target clock output section is connected to the clock output terminal of each stage of the multi-mode divider, and selects the clock signal output by the clock output terminal of one of the multi-mode dividers as the target divided clock output according to a selection control signal. Generating the frequency division control signal of the multi-mode frequency divider based on the frequency division signal includes: generating a selection control signal and a frequency division control signal based on the externally input frequency division signal, wherein the frequency division control signal is the frequency division control signal of the multi-mode frequency divider corresponding to the selection control signal, and the selection control signal corresponds to the multi-mode frequency divider selected by the selection control signal and all the preceding multi-mode frequency dividers of the multi-mode frequency divider at this stage.

9. The clock division method based on a multi-mode divider as described in claim 7, characterized in that: Furthermore, based on the externally input synchronization signal and the original input clock, the generated signals are made to be consistent with the timing and phase of the original input clock.

10. An electronic device, characterized in that: The device includes a cascaded circuit module, a computer program, a storage medium, and an actuator. The cascaded circuit module includes one or more multi-mode dividers for outputting a target frequency-divided clock. Multiple multi-mode dividers are connected in series so that the clock input of the subsequent multi-mode divider is connected to the clock output of the preceding multi-mode divider. The first-stage multi-mode divider is connected to the original input clock. The computer program is stored in the storage medium. The actuator is electrically connected to the cascaded circuit module and executes the computer program to implement the clock division method based on multi-mode dividers as described in claims 7-9.

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